Thomas Gleixner | 457c899 | 2019-05-19 13:08:55 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Dynamic DMA mapping support. |
| 4 | * |
Jan Beulich | 563aaf0 | 2007-02-05 18:51:25 -0800 | [diff] [blame] | 5 | * This implementation is a fallback for platforms that do not support |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * I/O TLBs (aka DMA address translation hardware). |
| 7 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> |
| 8 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> |
| 9 | * Copyright (C) 2000, 2003 Hewlett-Packard Co |
| 10 | * David Mosberger-Tang <davidm@hpl.hp.com> |
| 11 | * |
| 12 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. |
| 13 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid |
| 14 | * unnecessary i-cache flushing. |
John W. Linville | 569c8bf | 2005-09-29 14:45:24 -0700 | [diff] [blame] | 15 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
| 16 | * 05/09/10 linville Add support for syncing ranges, support syncing for |
| 17 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 18 | * 08/12/11 beckyb Add highmem support |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
Kees Cook | 7d63fb3 | 2018-07-10 16:22:22 -0700 | [diff] [blame] | 21 | #define pr_fmt(fmt) "software IO TLB: " fmt |
| 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/cache.h> |
Christoph Hellwig | ea8c64a | 2018-01-10 16:21:13 +0100 | [diff] [blame] | 24 | #include <linux/dma-direct.h> |
Christoph Hellwig | 9f4df96 | 2020-09-22 15:36:11 +0200 | [diff] [blame] | 25 | #include <linux/dma-map-ops.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include <linux/mm.h> |
Paul Gortmaker | 8bc3bcc | 2011-11-16 21:29:17 -0500 | [diff] [blame] | 27 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <linux/spinlock.h> |
| 29 | #include <linux/string.h> |
Ian Campbell | 0016fde | 2008-12-16 12:17:27 -0800 | [diff] [blame] | 30 | #include <linux/swiotlb.h> |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 31 | #include <linux/pfn.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <linux/types.h> |
| 33 | #include <linux/ctype.h> |
Jeremy Fitzhardinge | ef9b189 | 2008-12-16 12:17:33 -0800 | [diff] [blame] | 34 | #include <linux/highmem.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/gfp.h> |
Christoph Hellwig | 84be456 | 2015-05-01 12:46:15 +0200 | [diff] [blame] | 36 | #include <linux/scatterlist.h> |
Tom Lendacky | e9d1d2b | 2021-09-08 17:58:39 -0500 | [diff] [blame] | 37 | #include <linux/cc_platform.h> |
Christoph Hellwig | e7de6c7 | 2018-03-19 11:38:23 +0100 | [diff] [blame] | 38 | #include <linux/set_memory.h> |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 39 | #ifdef CONFIG_DEBUG_FS |
| 40 | #include <linux/debugfs.h> |
| 41 | #endif |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 42 | #ifdef CONFIG_DMA_RESTRICTED_POOL |
| 43 | #include <linux/io.h> |
| 44 | #include <linux/of.h> |
| 45 | #include <linux/of_fdt.h> |
| 46 | #include <linux/of_reserved_mem.h> |
| 47 | #include <linux/slab.h> |
| 48 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
| 50 | #include <asm/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | #include <asm/dma.h> |
| 52 | |
| 53 | #include <linux/init.h> |
Mike Rapoport | 57c8a66 | 2018-10-30 15:09:49 -0700 | [diff] [blame] | 54 | #include <linux/memblock.h> |
FUJITA Tomonori | a852250 | 2008-04-29 00:59:36 -0700 | [diff] [blame] | 55 | #include <linux/iommu-helper.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | |
Thierry Reding | ce5be5a | 2013-10-23 13:32:04 +0200 | [diff] [blame] | 57 | #define CREATE_TRACE_POINTS |
Zoltan Kiss | 2b2b614 | 2013-09-04 21:11:05 +0100 | [diff] [blame] | 58 | #include <trace/events/swiotlb.h> |
| 59 | |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 60 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
| 61 | |
| 62 | /* |
| 63 | * Minimum IO TLB size to bother booting with. Systems with mainly |
| 64 | * 64bit capable cards will only lightly use the swiotlb. If we can't |
| 65 | * allocate a contiguous 1MB, we're probably in trouble anyway. |
| 66 | */ |
| 67 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) |
| 68 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 69 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
| 70 | |
Geert Uytterhoeven | ae7871b | 2016-12-16 14:28:41 +0100 | [diff] [blame] | 71 | enum swiotlb_force swiotlb_force; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 73 | struct io_tlb_mem io_tlb_default_mem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
Konrad Rzeszutek Wilk | 7453c54 | 2016-12-20 10:02:02 -0500 | [diff] [blame] | 76 | * Max segment that we can provide which (if pages are contingous) will |
| 77 | * not be bounced (unless SWIOTLB_FORCE is set). |
| 78 | */ |
Andy Shevchenko | b51e627 | 2020-09-02 20:31:05 +0300 | [diff] [blame] | 79 | static unsigned int max_segment; |
Konrad Rzeszutek Wilk | 7453c54 | 2016-12-20 10:02:02 -0500 | [diff] [blame] | 80 | |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 81 | static unsigned long default_nslabs = IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT; |
| 82 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | static int __init |
| 84 | setup_io_tlb_npages(char *str) |
| 85 | { |
| 86 | if (isdigit(*str)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 88 | default_nslabs = |
| 89 | ALIGN(simple_strtoul(str, &str, 0), IO_TLB_SEGSIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | } |
| 91 | if (*str == ',') |
| 92 | ++str; |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 93 | if (!strcmp(str, "force")) |
Geert Uytterhoeven | ae7871b | 2016-12-16 14:28:41 +0100 | [diff] [blame] | 94 | swiotlb_force = SWIOTLB_FORCE; |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 95 | else if (!strcmp(str, "noforce")) |
Geert Uytterhoeven | fff5d99 | 2016-12-16 14:28:42 +0100 | [diff] [blame] | 96 | swiotlb_force = SWIOTLB_NO_FORCE; |
FUJITA Tomonori | b18485e | 2009-11-12 00:03:28 +0900 | [diff] [blame] | 97 | |
Yinghai Lu | c729de8 | 2013-04-15 22:23:45 -0700 | [diff] [blame] | 98 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | } |
Yinghai Lu | c729de8 | 2013-04-15 22:23:45 -0700 | [diff] [blame] | 100 | early_param("swiotlb", setup_io_tlb_npages); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | |
Konrad Rzeszutek Wilk | 7453c54 | 2016-12-20 10:02:02 -0500 | [diff] [blame] | 102 | unsigned int swiotlb_max_segment(void) |
| 103 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 104 | return io_tlb_default_mem.nslabs ? max_segment : 0; |
Konrad Rzeszutek Wilk | 7453c54 | 2016-12-20 10:02:02 -0500 | [diff] [blame] | 105 | } |
| 106 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); |
| 107 | |
| 108 | void swiotlb_set_max_segment(unsigned int val) |
| 109 | { |
| 110 | if (swiotlb_force == SWIOTLB_FORCE) |
| 111 | max_segment = 1; |
| 112 | else |
| 113 | max_segment = rounddown(val, PAGE_SIZE); |
| 114 | } |
| 115 | |
Yinghai Lu | c729de8 | 2013-04-15 22:23:45 -0700 | [diff] [blame] | 116 | unsigned long swiotlb_size_or_default(void) |
| 117 | { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 118 | return default_nslabs << IO_TLB_SHIFT; |
Yinghai Lu | c729de8 | 2013-04-15 22:23:45 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 121 | void __init swiotlb_adjust_size(unsigned long size) |
Ashish Kalra | e998879 | 2020-12-10 01:25:15 +0000 | [diff] [blame] | 122 | { |
Ashish Kalra | e998879 | 2020-12-10 01:25:15 +0000 | [diff] [blame] | 123 | /* |
| 124 | * If swiotlb parameter has not been specified, give a chance to |
| 125 | * architectures such as those supporting memory encryption to |
| 126 | * adjust/expand SWIOTLB size for their use. |
| 127 | */ |
Christoph Hellwig | dfc06b3 | 2021-04-29 08:28:59 +0200 | [diff] [blame] | 128 | if (default_nslabs != IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT) |
| 129 | return; |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 130 | size = ALIGN(size, IO_TLB_SIZE); |
| 131 | default_nslabs = ALIGN(size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE); |
| 132 | pr_info("SWIOTLB bounce buffer size adjusted to %luMB", size >> 20); |
Ashish Kalra | e998879 | 2020-12-10 01:25:15 +0000 | [diff] [blame] | 133 | } |
| 134 | |
FUJITA Tomonori | ad32e8c | 2009-11-10 19:46:19 +0900 | [diff] [blame] | 135 | void swiotlb_print_info(void) |
Ian Campbell | 2e5b2b8 | 2008-12-16 12:17:34 -0800 | [diff] [blame] | 136 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 137 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Ian Campbell | 2e5b2b8 | 2008-12-16 12:17:34 -0800 | [diff] [blame] | 138 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 139 | if (!mem->nslabs) { |
Kees Cook | 7d63fb3 | 2018-07-10 16:22:22 -0700 | [diff] [blame] | 140 | pr_warn("No low mem\n"); |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 141 | return; |
| 142 | } |
| 143 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 144 | pr_info("mapped [mem %pa-%pa] (%luMB)\n", &mem->start, &mem->end, |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 145 | (mem->nslabs << IO_TLB_SHIFT) >> 20); |
Ian Campbell | 2e5b2b8 | 2008-12-16 12:17:34 -0800 | [diff] [blame] | 146 | } |
| 147 | |
Christoph Hellwig | c7fbeca | 2021-02-04 10:11:20 +0100 | [diff] [blame] | 148 | static inline unsigned long io_tlb_offset(unsigned long val) |
| 149 | { |
| 150 | return val & (IO_TLB_SEGSIZE - 1); |
| 151 | } |
| 152 | |
Christoph Hellwig | c32a77fd | 2021-02-05 11:19:34 +0100 | [diff] [blame] | 153 | static inline unsigned long nr_slots(u64 val) |
| 154 | { |
| 155 | return DIV_ROUND_UP(val, IO_TLB_SIZE); |
| 156 | } |
| 157 | |
Tom Lendacky | c775320 | 2017-07-17 16:10:21 -0500 | [diff] [blame] | 158 | /* |
| 159 | * Early SWIOTLB allocation may be too early to allow an architecture to |
| 160 | * perform the desired operations. This function allows the architecture to |
| 161 | * call SWIOTLB when the operations are possible. It needs to be called |
| 162 | * before the SWIOTLB memory is used. |
| 163 | */ |
| 164 | void __init swiotlb_update_mem_attributes(void) |
| 165 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 166 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Tom Lendacky | c775320 | 2017-07-17 16:10:21 -0500 | [diff] [blame] | 167 | void *vaddr; |
| 168 | unsigned long bytes; |
| 169 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 170 | if (!mem->nslabs || mem->late_alloc) |
Tom Lendacky | c775320 | 2017-07-17 16:10:21 -0500 | [diff] [blame] | 171 | return; |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 172 | vaddr = phys_to_virt(mem->start); |
| 173 | bytes = PAGE_ALIGN(mem->nslabs << IO_TLB_SHIFT); |
Christoph Hellwig | e7de6c7 | 2018-03-19 11:38:23 +0100 | [diff] [blame] | 174 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
Tom Lendacky | c775320 | 2017-07-17 16:10:21 -0500 | [diff] [blame] | 175 | memset(vaddr, 0, bytes); |
Tom Lendacky | c775320 | 2017-07-17 16:10:21 -0500 | [diff] [blame] | 176 | } |
| 177 | |
Claire Chang | 0a65579 | 2021-06-19 11:40:32 +0800 | [diff] [blame] | 178 | static void swiotlb_init_io_tlb_mem(struct io_tlb_mem *mem, phys_addr_t start, |
| 179 | unsigned long nslabs, bool late_alloc) |
| 180 | { |
| 181 | void *vaddr = phys_to_virt(start); |
| 182 | unsigned long bytes = nslabs << IO_TLB_SHIFT, i; |
| 183 | |
| 184 | mem->nslabs = nslabs; |
| 185 | mem->start = start; |
| 186 | mem->end = mem->start + bytes; |
| 187 | mem->index = 0; |
| 188 | mem->late_alloc = late_alloc; |
Claire Chang | 903cd0f | 2021-06-24 23:55:20 +0800 | [diff] [blame] | 189 | |
| 190 | if (swiotlb_force == SWIOTLB_FORCE) |
| 191 | mem->force_bounce = true; |
| 192 | |
Claire Chang | 0a65579 | 2021-06-19 11:40:32 +0800 | [diff] [blame] | 193 | spin_lock_init(&mem->lock); |
| 194 | for (i = 0; i < mem->nslabs; i++) { |
| 195 | mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i); |
| 196 | mem->slots[i].orig_addr = INVALID_PHYS_ADDR; |
| 197 | mem->slots[i].alloc_size = 0; |
| 198 | } |
| 199 | memset(vaddr, 0, bytes); |
| 200 | } |
| 201 | |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 202 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 204 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Mike Rapoport | a0bf842 | 2019-03-11 23:30:26 -0700 | [diff] [blame] | 205 | size_t alloc_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 207 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
| 208 | return 0; |
| 209 | |
Christoph Hellwig | 5d0538b | 2021-03-01 08:44:31 +0100 | [diff] [blame] | 210 | /* protect against double initialization */ |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 211 | if (WARN_ON_ONCE(mem->nslabs)) |
Christoph Hellwig | 5d0538b | 2021-03-01 08:44:31 +0100 | [diff] [blame] | 212 | return -ENOMEM; |
| 213 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 214 | alloc_size = PAGE_ALIGN(array_size(sizeof(*mem->slots), nslabs)); |
| 215 | mem->slots = memblock_alloc(alloc_size, PAGE_SIZE); |
| 216 | if (!mem->slots) |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 217 | panic("%s: Failed to allocate %zu bytes align=0x%lx\n", |
| 218 | __func__, alloc_size, PAGE_SIZE); |
Claire Chang | 0a65579 | 2021-06-19 11:40:32 +0800 | [diff] [blame] | 219 | |
| 220 | swiotlb_init_io_tlb_mem(mem, __pa(tlb), nslabs, false); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | |
FUJITA Tomonori | ad32e8c | 2009-11-10 19:46:19 +0900 | [diff] [blame] | 222 | if (verbose) |
| 223 | swiotlb_print_info(); |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 224 | swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT); |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 225 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | } |
| 227 | |
FUJITA Tomonori | abbceff | 2010-05-10 15:15:12 -0400 | [diff] [blame] | 228 | /* |
| 229 | * Statically reserve bounce buffer space and initialize bounce buffer data |
| 230 | * structures for the software IO TLB used to implement the DMA API. |
| 231 | */ |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 232 | void __init |
| 233 | swiotlb_init(int verbose) |
FUJITA Tomonori | abbceff | 2010-05-10 15:15:12 -0400 | [diff] [blame] | 234 | { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 235 | size_t bytes = PAGE_ALIGN(default_nslabs << IO_TLB_SHIFT); |
| 236 | void *tlb; |
FUJITA Tomonori | abbceff | 2010-05-10 15:15:12 -0400 | [diff] [blame] | 237 | |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 238 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
| 239 | return; |
| 240 | |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 241 | /* Get IO TLB memory from the low pages */ |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 242 | tlb = memblock_alloc_low(bytes, PAGE_SIZE); |
| 243 | if (!tlb) |
| 244 | goto fail; |
| 245 | if (swiotlb_init_with_tbl(tlb, default_nslabs, verbose)) |
| 246 | goto fail_free_mem; |
| 247 | return; |
FUJITA Tomonori | abbceff | 2010-05-10 15:15:12 -0400 | [diff] [blame] | 248 | |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 249 | fail_free_mem: |
Mike Rapoport | 4421cca | 2021-11-05 13:43:22 -0700 | [diff] [blame] | 250 | memblock_free(tlb, bytes); |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 251 | fail: |
Kees Cook | 7d63fb3 | 2018-07-10 16:22:22 -0700 | [diff] [blame] | 252 | pr_warn("Cannot allocate buffer"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 255 | /* |
| 256 | * Systems with larger DMA zones (those that don't support ISA) can |
| 257 | * initialize the swiotlb later using the slab allocator if needed. |
| 258 | * This should be just like above, but with some error catching. |
| 259 | */ |
| 260 | int |
Jan Beulich | 563aaf0 | 2007-02-05 18:51:25 -0800 | [diff] [blame] | 261 | swiotlb_late_init_with_default_size(size_t default_size) |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 262 | { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 263 | unsigned long nslabs = |
| 264 | ALIGN(default_size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE); |
| 265 | unsigned long bytes; |
Alexander Duyck | ff7204a | 2012-10-15 10:19:28 -0700 | [diff] [blame] | 266 | unsigned char *vstart = NULL; |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 267 | unsigned int order; |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 268 | int rc = 0; |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 269 | |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 270 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
| 271 | return 0; |
| 272 | |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 273 | /* |
| 274 | * Get IO TLB memory from the low pages |
| 275 | */ |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 276 | order = get_order(nslabs << IO_TLB_SHIFT); |
| 277 | nslabs = SLABS_PER_PAGE << order; |
| 278 | bytes = nslabs << IO_TLB_SHIFT; |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 279 | |
| 280 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { |
Alexander Duyck | ff7204a | 2012-10-15 10:19:28 -0700 | [diff] [blame] | 281 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
| 282 | order); |
| 283 | if (vstart) |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 284 | break; |
| 285 | order--; |
| 286 | } |
| 287 | |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 288 | if (!vstart) |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 289 | return -ENOMEM; |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 290 | |
Jan Beulich | 563aaf0 | 2007-02-05 18:51:25 -0800 | [diff] [blame] | 291 | if (order != get_order(bytes)) { |
Kees Cook | 7d63fb3 | 2018-07-10 16:22:22 -0700 | [diff] [blame] | 292 | pr_warn("only able to allocate %ld MB\n", |
| 293 | (PAGE_SIZE << order) >> 20); |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 294 | nslabs = SLABS_PER_PAGE << order; |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 295 | } |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 296 | rc = swiotlb_late_init_with_tbl(vstart, nslabs); |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 297 | if (rc) |
Alexander Duyck | ff7204a | 2012-10-15 10:19:28 -0700 | [diff] [blame] | 298 | free_pages((unsigned long)vstart, order); |
Konrad Rzeszutek Wilk | 7453c54 | 2016-12-20 10:02:02 -0500 | [diff] [blame] | 299 | |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 300 | return rc; |
| 301 | } |
| 302 | |
| 303 | int |
| 304 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) |
| 305 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 306 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Claire Chang | 0a65579 | 2021-06-19 11:40:32 +0800 | [diff] [blame] | 307 | unsigned long bytes = nslabs << IO_TLB_SHIFT; |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 308 | |
Florian Fainelli | 2726bf3 | 2021-03-22 18:53:49 -0700 | [diff] [blame] | 309 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
| 310 | return 0; |
| 311 | |
Christoph Hellwig | 5d0538b | 2021-03-01 08:44:31 +0100 | [diff] [blame] | 312 | /* protect against double initialization */ |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 313 | if (WARN_ON_ONCE(mem->nslabs)) |
Christoph Hellwig | 5d0538b | 2021-03-01 08:44:31 +0100 | [diff] [blame] | 314 | return -ENOMEM; |
| 315 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 316 | mem->slots = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
| 317 | get_order(array_size(sizeof(*mem->slots), nslabs))); |
| 318 | if (!mem->slots) |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 319 | return -ENOMEM; |
Konrad Rzeszutek Wilk | 74838b7 | 2012-07-27 20:55:27 -0400 | [diff] [blame] | 320 | |
Christoph Hellwig | e7de6c7 | 2018-03-19 11:38:23 +0100 | [diff] [blame] | 321 | set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT); |
Claire Chang | 0a65579 | 2021-06-19 11:40:32 +0800 | [diff] [blame] | 322 | swiotlb_init_io_tlb_mem(mem, virt_to_phys(tlb), nslabs, true); |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 323 | |
FUJITA Tomonori | ad32e8c | 2009-11-10 19:46:19 +0900 | [diff] [blame] | 324 | swiotlb_print_info(); |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 325 | swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT); |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 326 | return 0; |
Alex Williamson | 0b9afed | 2005-09-06 11:20:49 -0600 | [diff] [blame] | 327 | } |
| 328 | |
Christoph Hellwig | 7f2c8bb | 2017-12-23 14:14:54 +0100 | [diff] [blame] | 329 | void __init swiotlb_exit(void) |
FUJITA Tomonori | 5740afd | 2009-11-10 19:46:18 +0900 | [diff] [blame] | 330 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 331 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Will Deacon | ad6c002 | 2021-07-20 14:38:26 +0100 | [diff] [blame] | 332 | unsigned long tbl_vaddr; |
| 333 | size_t tbl_size, slots_size; |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 334 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 335 | if (!mem->nslabs) |
FUJITA Tomonori | 5740afd | 2009-11-10 19:46:18 +0900 | [diff] [blame] | 336 | return; |
| 337 | |
Will Deacon | 1efd3fc | 2021-07-20 14:38:25 +0100 | [diff] [blame] | 338 | pr_info("tearing down default memory pool\n"); |
Will Deacon | ad6c002 | 2021-07-20 14:38:26 +0100 | [diff] [blame] | 339 | tbl_vaddr = (unsigned long)phys_to_virt(mem->start); |
| 340 | tbl_size = PAGE_ALIGN(mem->end - mem->start); |
| 341 | slots_size = PAGE_ALIGN(array_size(sizeof(*mem->slots), mem->nslabs)); |
| 342 | |
| 343 | set_memory_encrypted(tbl_vaddr, tbl_size >> PAGE_SHIFT); |
| 344 | if (mem->late_alloc) { |
| 345 | free_pages(tbl_vaddr, get_order(tbl_size)); |
| 346 | free_pages((unsigned long)mem->slots, get_order(slots_size)); |
| 347 | } else { |
| 348 | memblock_free_late(mem->start, tbl_size); |
| 349 | memblock_free_late(__pa(mem->slots), slots_size); |
| 350 | } |
| 351 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 352 | memset(mem, 0, sizeof(*mem)); |
FUJITA Tomonori | 5740afd | 2009-11-10 19:46:18 +0900 | [diff] [blame] | 353 | } |
| 354 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | /* |
Bumyong Lee | 5f89468 | 2021-05-10 18:10:04 +0900 | [diff] [blame] | 356 | * Return the offset into a iotlb slot required to keep the device happy. |
| 357 | */ |
| 358 | static unsigned int swiotlb_align_offset(struct device *dev, u64 addr) |
| 359 | { |
| 360 | return addr & dma_get_min_align_mask(dev) & (IO_TLB_SIZE - 1); |
| 361 | } |
| 362 | |
| 363 | /* |
Dongli Zhang | 6442ca2 | 2019-01-18 15:10:26 +0800 | [diff] [blame] | 364 | * Bounce: copy the swiotlb buffer from or back to the original dma location |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 365 | */ |
Christoph Hellwig | 2bdba62 | 2021-03-01 08:44:25 +0100 | [diff] [blame] | 366 | static void swiotlb_bounce(struct device *dev, phys_addr_t tlb_addr, size_t size, |
| 367 | enum dma_data_direction dir) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 368 | { |
Claire Chang | 69031f5 | 2021-06-19 11:40:34 +0800 | [diff] [blame] | 369 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 370 | int index = (tlb_addr - mem->start) >> IO_TLB_SHIFT; |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 371 | phys_addr_t orig_addr = mem->slots[index].orig_addr; |
| 372 | size_t alloc_size = mem->slots[index].alloc_size; |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 373 | unsigned long pfn = PFN_DOWN(orig_addr); |
| 374 | unsigned char *vaddr = phys_to_virt(tlb_addr); |
Dominique Martinet | 868c9dd | 2021-07-07 14:12:54 +0900 | [diff] [blame] | 375 | unsigned int tlb_offset, orig_addr_offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | |
Christoph Hellwig | 2bdba62 | 2021-03-01 08:44:25 +0100 | [diff] [blame] | 377 | if (orig_addr == INVALID_PHYS_ADDR) |
| 378 | return; |
| 379 | |
Dominique Martinet | 868c9dd | 2021-07-07 14:12:54 +0900 | [diff] [blame] | 380 | tlb_offset = tlb_addr & (IO_TLB_SIZE - 1); |
| 381 | orig_addr_offset = swiotlb_align_offset(dev, orig_addr); |
| 382 | if (tlb_offset < orig_addr_offset) { |
| 383 | dev_WARN_ONCE(dev, 1, |
| 384 | "Access before mapping start detected. orig offset %u, requested offset %u.\n", |
| 385 | orig_addr_offset, tlb_offset); |
| 386 | return; |
| 387 | } |
| 388 | |
| 389 | tlb_offset -= orig_addr_offset; |
| 390 | if (tlb_offset > alloc_size) { |
| 391 | dev_WARN_ONCE(dev, 1, |
| 392 | "Buffer overflow detected. Allocation size: %zu. Mapping size: %zu+%u.\n", |
| 393 | alloc_size, size, tlb_offset); |
| 394 | return; |
| 395 | } |
Bumyong Lee | 5f89468 | 2021-05-10 18:10:04 +0900 | [diff] [blame] | 396 | |
| 397 | orig_addr += tlb_offset; |
| 398 | alloc_size -= tlb_offset; |
| 399 | |
Christoph Hellwig | 2bdba62 | 2021-03-01 08:44:25 +0100 | [diff] [blame] | 400 | if (size > alloc_size) { |
| 401 | dev_WARN_ONCE(dev, 1, |
| 402 | "Buffer overflow detected. Allocation size: %zu. Mapping size: %zu.\n", |
| 403 | alloc_size, size); |
| 404 | size = alloc_size; |
| 405 | } |
| 406 | |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 407 | if (PageHighMem(pfn_to_page(pfn))) { |
| 408 | /* The buffer does not have a mapping. Map it in and copy */ |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 409 | unsigned int offset = orig_addr & ~PAGE_MASK; |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 410 | char *buffer; |
| 411 | unsigned int sz = 0; |
| 412 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 414 | while (size) { |
Becky Bruce | 67131ad | 2009-04-08 09:09:16 -0500 | [diff] [blame] | 415 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 417 | local_irq_save(flags); |
Cong Wang | c3eede8 | 2011-11-25 23:14:39 +0800 | [diff] [blame] | 418 | buffer = kmap_atomic(pfn_to_page(pfn)); |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 419 | if (dir == DMA_TO_DEVICE) |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 420 | memcpy(vaddr, buffer + offset, sz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | else |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 422 | memcpy(buffer + offset, vaddr, sz); |
Cong Wang | c3eede8 | 2011-11-25 23:14:39 +0800 | [diff] [blame] | 423 | kunmap_atomic(buffer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | local_irq_restore(flags); |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 425 | |
| 426 | size -= sz; |
| 427 | pfn++; |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 428 | vaddr += sz; |
Becky Bruce | fb05a37 | 2008-12-22 10:26:09 -0800 | [diff] [blame] | 429 | offset = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | } |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 431 | } else if (dir == DMA_TO_DEVICE) { |
| 432 | memcpy(vaddr, phys_to_virt(orig_addr), size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | } else { |
Alexander Duyck | af51a9f | 2012-10-15 10:19:55 -0700 | [diff] [blame] | 434 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | } |
| 436 | } |
| 437 | |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 438 | #define slot_addr(start, idx) ((start) + ((idx) << IO_TLB_SHIFT)) |
| 439 | |
| 440 | /* |
| 441 | * Carefully handle integer overflow which can occur when boundary_mask == ~0UL. |
| 442 | */ |
| 443 | static inline unsigned long get_max_slots(unsigned long boundary_mask) |
| 444 | { |
| 445 | if (boundary_mask == ~0UL) |
| 446 | return 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); |
| 447 | return nr_slots(boundary_mask + 1); |
| 448 | } |
| 449 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 450 | static unsigned int wrap_index(struct io_tlb_mem *mem, unsigned int index) |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 451 | { |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 452 | if (index >= mem->nslabs) |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 453 | return 0; |
| 454 | return index; |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * Find a suitable number of IO TLB entries size that will fit this request and |
| 459 | * allocate a buffer from that IO TLB pool. |
| 460 | */ |
Claire Chang | 36f7b2f | 2021-06-24 23:55:21 +0800 | [diff] [blame] | 461 | static int swiotlb_find_slots(struct device *dev, phys_addr_t orig_addr, |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 462 | size_t alloc_size, unsigned int alloc_align_mask) |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 463 | { |
Claire Chang | 69031f5 | 2021-06-19 11:40:34 +0800 | [diff] [blame] | 464 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 465 | unsigned long boundary_mask = dma_get_seg_boundary(dev); |
| 466 | dma_addr_t tbl_dma_addr = |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 467 | phys_to_dma_unencrypted(dev, mem->start) & boundary_mask; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 468 | unsigned long max_slots = get_max_slots(boundary_mask); |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 469 | unsigned int iotlb_align_mask = |
| 470 | dma_get_min_align_mask(dev) & ~(IO_TLB_SIZE - 1); |
| 471 | unsigned int nslots = nr_slots(alloc_size), stride; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 472 | unsigned int index, wrap, count = 0, i; |
Claire Chang | 36f7b2f | 2021-06-24 23:55:21 +0800 | [diff] [blame] | 473 | unsigned int offset = swiotlb_align_offset(dev, orig_addr); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 474 | unsigned long flags; |
| 475 | |
| 476 | BUG_ON(!nslots); |
| 477 | |
| 478 | /* |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 479 | * For mappings with an alignment requirement don't bother looping to |
| 480 | * unaligned slots once we found an aligned one. For allocations of |
| 481 | * PAGE_SIZE or larger only look for page aligned allocations. |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 482 | */ |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 483 | stride = (iotlb_align_mask >> IO_TLB_SHIFT) + 1; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 484 | if (alloc_size >= PAGE_SIZE) |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 485 | stride = max(stride, stride << (PAGE_SHIFT - IO_TLB_SHIFT)); |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 486 | stride = max(stride, (alloc_align_mask >> IO_TLB_SHIFT) + 1); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 487 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 488 | spin_lock_irqsave(&mem->lock, flags); |
| 489 | if (unlikely(nslots > mem->nslabs - mem->used)) |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 490 | goto not_found; |
| 491 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 492 | index = wrap = wrap_index(mem, ALIGN(mem->index, stride)); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 493 | do { |
Claire Chang | f4111e3 | 2021-06-19 11:40:40 +0800 | [diff] [blame] | 494 | if (orig_addr && |
| 495 | (slot_addr(tbl_dma_addr, index) & iotlb_align_mask) != |
| 496 | (orig_addr & iotlb_align_mask)) { |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 497 | index = wrap_index(mem, index + 1); |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 498 | continue; |
| 499 | } |
| 500 | |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 501 | /* |
| 502 | * If we find a slot that indicates we have 'nslots' number of |
| 503 | * contiguous buffers, we allocate the buffers from that slot |
| 504 | * and mark the entries as '0' indicating unavailable. |
| 505 | */ |
| 506 | if (!iommu_is_span_boundary(index, nslots, |
| 507 | nr_slots(tbl_dma_addr), |
| 508 | max_slots)) { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 509 | if (mem->slots[index].list >= nslots) |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 510 | goto found; |
| 511 | } |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 512 | index = wrap_index(mem, index + stride); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 513 | } while (index != wrap); |
| 514 | |
| 515 | not_found: |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 516 | spin_unlock_irqrestore(&mem->lock, flags); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 517 | return -1; |
| 518 | |
| 519 | found: |
Claire Chang | 36f7b2f | 2021-06-24 23:55:21 +0800 | [diff] [blame] | 520 | for (i = index; i < index + nslots; i++) { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 521 | mem->slots[i].list = 0; |
Claire Chang | 36f7b2f | 2021-06-24 23:55:21 +0800 | [diff] [blame] | 522 | mem->slots[i].alloc_size = |
| 523 | alloc_size - (offset + ((i - index) << IO_TLB_SHIFT)); |
| 524 | } |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 525 | for (i = index - 1; |
| 526 | io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 && |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 527 | mem->slots[i].list; i--) |
| 528 | mem->slots[i].list = ++count; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 529 | |
| 530 | /* |
| 531 | * Update the indices to avoid searching in the next round. |
| 532 | */ |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 533 | if (index + nslots < mem->nslabs) |
| 534 | mem->index = index + nslots; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 535 | else |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 536 | mem->index = 0; |
| 537 | mem->used += nslots; |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 538 | |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 539 | spin_unlock_irqrestore(&mem->lock, flags); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 540 | return index; |
| 541 | } |
| 542 | |
| 543 | phys_addr_t swiotlb_tbl_map_single(struct device *dev, phys_addr_t orig_addr, |
Christoph Hellwig | fc0021a | 2020-10-23 08:33:09 +0200 | [diff] [blame] | 544 | size_t mapping_size, size_t alloc_size, |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 545 | unsigned int alloc_align_mask, enum dma_data_direction dir, |
| 546 | unsigned long attrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | { |
Claire Chang | 69031f5 | 2021-06-19 11:40:34 +0800 | [diff] [blame] | 548 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
Christoph Hellwig | 1f221a0 | 2021-02-22 14:39:44 -0500 | [diff] [blame] | 549 | unsigned int offset = swiotlb_align_offset(dev, orig_addr); |
Claire Chang | 95b079d | 2021-04-22 16:14:53 +0800 | [diff] [blame] | 550 | unsigned int i; |
| 551 | int index; |
Alexander Duyck | e05ed4d | 2012-10-15 10:19:39 -0700 | [diff] [blame] | 552 | phys_addr_t tlb_addr; |
FUJITA Tomonori | 681cc5c | 2008-02-04 22:28:16 -0800 | [diff] [blame] | 553 | |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 554 | if (!mem) |
Yinghai Lu | ac2cbab | 2013-01-24 12:20:16 -0800 | [diff] [blame] | 555 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); |
| 556 | |
Tom Lendacky | e9d1d2b | 2021-09-08 17:58:39 -0500 | [diff] [blame] | 557 | if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) |
Thiago Jung Bauermann | 47e5d8f | 2019-08-06 01:49:15 -0300 | [diff] [blame] | 558 | pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n"); |
Tom Lendacky | 648babb | 2017-07-17 16:10:22 -0500 | [diff] [blame] | 559 | |
Lu Baolu | 3fc1ca0 | 2019-09-06 14:14:48 +0800 | [diff] [blame] | 560 | if (mapping_size > alloc_size) { |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 561 | dev_warn_once(dev, "Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)", |
Lu Baolu | 3fc1ca0 | 2019-09-06 14:14:48 +0800 | [diff] [blame] | 562 | mapping_size, alloc_size); |
| 563 | return (phys_addr_t)DMA_MAPPING_ERROR; |
| 564 | } |
| 565 | |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 566 | index = swiotlb_find_slots(dev, orig_addr, |
| 567 | alloc_size + offset, alloc_align_mask); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 568 | if (index == -1) { |
| 569 | if (!(attrs & DMA_ATTR_NO_WARN)) |
| 570 | dev_warn_ratelimited(dev, |
| 571 | "swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n", |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 572 | alloc_size, mem->nslabs, mem->used); |
Christoph Hellwig | 26a7e09 | 2021-02-04 11:08:35 +0100 | [diff] [blame] | 573 | return (phys_addr_t)DMA_MAPPING_ERROR; |
| 574 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | |
| 576 | /* |
| 577 | * Save away the mapping from the original address to the DMA address. |
| 578 | * This is needed when we sync the memory. Then we sync the buffer if |
| 579 | * needed. |
| 580 | */ |
Claire Chang | 36f7b2f | 2021-06-24 23:55:21 +0800 | [diff] [blame] | 581 | for (i = 0; i < nr_slots(alloc_size + offset); i++) |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 582 | mem->slots[index + i].orig_addr = slot_addr(orig_addr, i); |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 583 | tlb_addr = slot_addr(mem->start, index) + offset; |
Alexander Duyck | 0443fa0 | 2016-11-02 07:13:02 -0400 | [diff] [blame] | 584 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
| 585 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) |
Christoph Hellwig | 2bdba62 | 2021-03-01 08:44:25 +0100 | [diff] [blame] | 586 | swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_TO_DEVICE); |
Alexander Duyck | e05ed4d | 2012-10-15 10:19:39 -0700 | [diff] [blame] | 587 | return tlb_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | } |
| 589 | |
Claire Chang | 7034787 | 2021-06-19 11:40:39 +0800 | [diff] [blame] | 590 | static void swiotlb_release_slots(struct device *dev, phys_addr_t tlb_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | { |
Claire Chang | 7034787 | 2021-06-19 11:40:39 +0800 | [diff] [blame] | 592 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | unsigned long flags; |
Claire Chang | 7034787 | 2021-06-19 11:40:39 +0800 | [diff] [blame] | 594 | unsigned int offset = swiotlb_align_offset(dev, tlb_addr); |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 595 | int index = (tlb_addr - offset - mem->start) >> IO_TLB_SHIFT; |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 596 | int nslots = nr_slots(mem->slots[index].alloc_size + offset); |
Christoph Hellwig | 2bdba62 | 2021-03-01 08:44:25 +0100 | [diff] [blame] | 597 | int count, i; |
Martin Radev | daf9514 | 2021-01-12 16:07:29 +0100 | [diff] [blame] | 598 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | * Return the buffer to the free list by setting the corresponding |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 601 | * entries to indicate the number of contiguous entries available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | * While returning the entries to the free list, we merge the entries |
| 603 | * with slots below and above the pool being returned. |
| 604 | */ |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 605 | spin_lock_irqsave(&mem->lock, flags); |
Christoph Hellwig | ca10d0f | 2021-02-04 10:13:40 +0100 | [diff] [blame] | 606 | if (index + nslots < ALIGN(index + 1, IO_TLB_SEGSIZE)) |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 607 | count = mem->slots[index + nslots].list; |
Christoph Hellwig | ca10d0f | 2021-02-04 10:13:40 +0100 | [diff] [blame] | 608 | else |
| 609 | count = 0; |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 610 | |
Christoph Hellwig | ca10d0f | 2021-02-04 10:13:40 +0100 | [diff] [blame] | 611 | /* |
| 612 | * Step 1: return the slots to the free list, merging the slots with |
| 613 | * superceeding slots |
| 614 | */ |
| 615 | for (i = index + nslots - 1; i >= index; i--) { |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 616 | mem->slots[i].list = ++count; |
| 617 | mem->slots[i].orig_addr = INVALID_PHYS_ADDR; |
| 618 | mem->slots[i].alloc_size = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | } |
Christoph Hellwig | ca10d0f | 2021-02-04 10:13:40 +0100 | [diff] [blame] | 620 | |
| 621 | /* |
| 622 | * Step 2: merge the returned slots with the preceding slots, if |
| 623 | * available (non zero) |
| 624 | */ |
| 625 | for (i = index - 1; |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 626 | io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 && mem->slots[i].list; |
Christoph Hellwig | ca10d0f | 2021-02-04 10:13:40 +0100 | [diff] [blame] | 627 | i--) |
Christoph Hellwig | 2d29960 | 2021-03-18 17:14:23 +0100 | [diff] [blame] | 628 | mem->slots[i].list = ++count; |
Claire Chang | 73f6209 | 2021-03-18 17:14:22 +0100 | [diff] [blame] | 629 | mem->used -= nslots; |
| 630 | spin_unlock_irqrestore(&mem->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | } |
| 632 | |
Claire Chang | 7034787 | 2021-06-19 11:40:39 +0800 | [diff] [blame] | 633 | /* |
| 634 | * tlb_addr is the physical address of the bounce buffer to unmap. |
| 635 | */ |
| 636 | void swiotlb_tbl_unmap_single(struct device *dev, phys_addr_t tlb_addr, |
| 637 | size_t mapping_size, enum dma_data_direction dir, |
| 638 | unsigned long attrs) |
| 639 | { |
| 640 | /* |
| 641 | * First, sync the memory before unmapping the entry |
| 642 | */ |
| 643 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
| 644 | (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) |
| 645 | swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_FROM_DEVICE); |
| 646 | |
| 647 | swiotlb_release_slots(dev, tlb_addr); |
| 648 | } |
| 649 | |
Christoph Hellwig | 80808d2 | 2021-03-01 08:44:26 +0100 | [diff] [blame] | 650 | void swiotlb_sync_single_for_device(struct device *dev, phys_addr_t tlb_addr, |
| 651 | size_t size, enum dma_data_direction dir) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | { |
Christoph Hellwig | 80808d2 | 2021-03-01 08:44:26 +0100 | [diff] [blame] | 653 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 654 | swiotlb_bounce(dev, tlb_addr, size, DMA_TO_DEVICE); |
| 655 | else |
| 656 | BUG_ON(dir != DMA_FROM_DEVICE); |
| 657 | } |
| 658 | |
| 659 | void swiotlb_sync_single_for_cpu(struct device *dev, phys_addr_t tlb_addr, |
| 660 | size_t size, enum dma_data_direction dir) |
| 661 | { |
| 662 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 663 | swiotlb_bounce(dev, tlb_addr, size, DMA_FROM_DEVICE); |
| 664 | else |
| 665 | BUG_ON(dir != DMA_TO_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | } |
| 667 | |
Christoph Hellwig | 55897af | 2018-12-03 11:43:54 +0100 | [diff] [blame] | 668 | /* |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 669 | * Create a swiotlb mapping for the buffer at @paddr, and in case of DMAing |
Christoph Hellwig | 55897af | 2018-12-03 11:43:54 +0100 | [diff] [blame] | 670 | * to the device copy the data into it as well. |
| 671 | */ |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 672 | dma_addr_t swiotlb_map(struct device *dev, phys_addr_t paddr, size_t size, |
| 673 | enum dma_data_direction dir, unsigned long attrs) |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 674 | { |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 675 | phys_addr_t swiotlb_addr; |
| 676 | dma_addr_t dma_addr; |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 677 | |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 678 | trace_swiotlb_bounced(dev, phys_to_dma(dev, paddr), size, |
| 679 | swiotlb_force); |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 680 | |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 681 | swiotlb_addr = swiotlb_tbl_map_single(dev, paddr, size, size, 0, dir, |
Christoph Hellwig | fc0021a | 2020-10-23 08:33:09 +0200 | [diff] [blame] | 682 | attrs); |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 683 | if (swiotlb_addr == (phys_addr_t)DMA_MAPPING_ERROR) |
| 684 | return DMA_MAPPING_ERROR; |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 685 | |
| 686 | /* Ensure that the address returned is DMA'ble */ |
Christoph Hellwig | 5ceda74 | 2020-08-17 17:34:03 +0200 | [diff] [blame] | 687 | dma_addr = phys_to_dma_unencrypted(dev, swiotlb_addr); |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 688 | if (unlikely(!dma_capable(dev, dma_addr, size, true))) { |
Christoph Hellwig | 2973073 | 2021-03-01 08:44:24 +0100 | [diff] [blame] | 689 | swiotlb_tbl_unmap_single(dev, swiotlb_addr, size, dir, |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 690 | attrs | DMA_ATTR_SKIP_CPU_SYNC); |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 691 | dev_WARN_ONCE(dev, 1, |
| 692 | "swiotlb addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", |
| 693 | &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); |
| 694 | return DMA_MAPPING_ERROR; |
Christoph Hellwig | c4dae36 | 2018-08-20 16:21:10 +0200 | [diff] [blame] | 695 | } |
| 696 | |
Christoph Hellwig | 4a47cba | 2020-02-03 14:44:38 +0100 | [diff] [blame] | 697 | if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
| 698 | arch_sync_dma_for_device(swiotlb_addr, size, dir); |
| 699 | return dma_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | } |
| 701 | |
Joerg Roedel | abe420b | 2019-02-07 12:59:13 +0100 | [diff] [blame] | 702 | size_t swiotlb_max_mapping_size(struct device *dev) |
| 703 | { |
Christoph Hellwig | b5d7ccb | 2021-02-05 11:18:40 +0100 | [diff] [blame] | 704 | return ((size_t)IO_TLB_SIZE) * IO_TLB_SEGSIZE; |
Joerg Roedel | abe420b | 2019-02-07 12:59:13 +0100 | [diff] [blame] | 705 | } |
Joerg Roedel | 492366f | 2019-02-07 12:59:14 +0100 | [diff] [blame] | 706 | |
Claire Chang | 6f2beb2 | 2021-06-19 11:40:36 +0800 | [diff] [blame] | 707 | bool is_swiotlb_active(struct device *dev) |
Joerg Roedel | 492366f | 2019-02-07 12:59:14 +0100 | [diff] [blame] | 708 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 709 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
| 710 | |
| 711 | return mem && mem->nslabs; |
Joerg Roedel | 492366f | 2019-02-07 12:59:14 +0100 | [diff] [blame] | 712 | } |
Christoph Hellwig | 2cbc277 | 2021-03-18 17:14:24 +0100 | [diff] [blame] | 713 | EXPORT_SYMBOL_GPL(is_swiotlb_active); |
Linus Torvalds | 45ba8d5 | 2019-03-10 12:47:57 -0700 | [diff] [blame] | 714 | |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 715 | #ifdef CONFIG_DEBUG_FS |
Claire Chang | 6e675a1 | 2021-06-19 11:40:33 +0800 | [diff] [blame] | 716 | static struct dentry *debugfs_dir; |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 717 | |
Claire Chang | 6e675a1 | 2021-06-19 11:40:33 +0800 | [diff] [blame] | 718 | static void swiotlb_create_debugfs_files(struct io_tlb_mem *mem) |
| 719 | { |
| 720 | debugfs_create_ulong("io_tlb_nslabs", 0400, mem->debugfs, &mem->nslabs); |
| 721 | debugfs_create_ulong("io_tlb_used", 0400, mem->debugfs, &mem->used); |
| 722 | } |
| 723 | |
| 724 | static int __init swiotlb_create_default_debugfs(void) |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 725 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 726 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 727 | |
Claire Chang | 6e675a1 | 2021-06-19 11:40:33 +0800 | [diff] [blame] | 728 | debugfs_dir = debugfs_create_dir("swiotlb", NULL); |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 729 | if (mem->nslabs) { |
Claire Chang | 6e675a1 | 2021-06-19 11:40:33 +0800 | [diff] [blame] | 730 | mem->debugfs = debugfs_dir; |
| 731 | swiotlb_create_debugfs_files(mem); |
| 732 | } |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 733 | return 0; |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 734 | } |
| 735 | |
Claire Chang | 6e675a1 | 2021-06-19 11:40:33 +0800 | [diff] [blame] | 736 | late_initcall(swiotlb_create_default_debugfs); |
Dongli Zhang | 71602fe | 2019-01-18 15:10:27 +0800 | [diff] [blame] | 737 | |
| 738 | #endif |
Claire Chang | f4111e3 | 2021-06-19 11:40:40 +0800 | [diff] [blame] | 739 | |
| 740 | #ifdef CONFIG_DMA_RESTRICTED_POOL |
Claire Chang | 09a4a79 | 2021-07-01 11:31:30 +0800 | [diff] [blame] | 741 | |
| 742 | #ifdef CONFIG_DEBUG_FS |
| 743 | static void rmem_swiotlb_debugfs_init(struct reserved_mem *rmem) |
| 744 | { |
| 745 | struct io_tlb_mem *mem = rmem->priv; |
| 746 | |
| 747 | mem->debugfs = debugfs_create_dir(rmem->name, debugfs_dir); |
| 748 | swiotlb_create_debugfs_files(mem); |
| 749 | } |
| 750 | #else |
| 751 | static void rmem_swiotlb_debugfs_init(struct reserved_mem *rmem) |
| 752 | { |
| 753 | } |
| 754 | #endif |
| 755 | |
Claire Chang | f4111e3 | 2021-06-19 11:40:40 +0800 | [diff] [blame] | 756 | struct page *swiotlb_alloc(struct device *dev, size_t size) |
| 757 | { |
| 758 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
| 759 | phys_addr_t tlb_addr; |
| 760 | int index; |
| 761 | |
| 762 | if (!mem) |
| 763 | return NULL; |
| 764 | |
David Stevens | e81e99b | 2021-09-29 11:32:59 +0900 | [diff] [blame] | 765 | index = swiotlb_find_slots(dev, 0, size, 0); |
Claire Chang | f4111e3 | 2021-06-19 11:40:40 +0800 | [diff] [blame] | 766 | if (index == -1) |
| 767 | return NULL; |
| 768 | |
| 769 | tlb_addr = slot_addr(mem->start, index); |
| 770 | |
| 771 | return pfn_to_page(PFN_DOWN(tlb_addr)); |
| 772 | } |
| 773 | |
| 774 | bool swiotlb_free(struct device *dev, struct page *page, size_t size) |
| 775 | { |
| 776 | phys_addr_t tlb_addr = page_to_phys(page); |
| 777 | |
| 778 | if (!is_swiotlb_buffer(dev, tlb_addr)) |
| 779 | return false; |
| 780 | |
| 781 | swiotlb_release_slots(dev, tlb_addr); |
| 782 | |
| 783 | return true; |
| 784 | } |
| 785 | |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 786 | static int rmem_swiotlb_device_init(struct reserved_mem *rmem, |
| 787 | struct device *dev) |
| 788 | { |
| 789 | struct io_tlb_mem *mem = rmem->priv; |
| 790 | unsigned long nslabs = rmem->size >> IO_TLB_SHIFT; |
| 791 | |
| 792 | /* |
| 793 | * Since multiple devices can share the same pool, the private data, |
| 794 | * io_tlb_mem struct, will be initialized by the first device attached |
| 795 | * to it. |
| 796 | */ |
| 797 | if (!mem) { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 798 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 799 | if (!mem) |
| 800 | return -ENOMEM; |
| 801 | |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 802 | mem->slots = kzalloc(array_size(sizeof(*mem->slots), nslabs), |
| 803 | GFP_KERNEL); |
| 804 | if (!mem->slots) { |
| 805 | kfree(mem); |
| 806 | return -ENOMEM; |
| 807 | } |
| 808 | |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 809 | set_memory_decrypted((unsigned long)phys_to_virt(rmem->base), |
| 810 | rmem->size >> PAGE_SHIFT); |
| 811 | swiotlb_init_io_tlb_mem(mem, rmem->base, nslabs, false); |
| 812 | mem->force_bounce = true; |
| 813 | mem->for_alloc = true; |
| 814 | |
| 815 | rmem->priv = mem; |
| 816 | |
Claire Chang | 09a4a79 | 2021-07-01 11:31:30 +0800 | [diff] [blame] | 817 | rmem_swiotlb_debugfs_init(rmem); |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | dev->dma_io_tlb_mem = mem; |
| 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | static void rmem_swiotlb_device_release(struct reserved_mem *rmem, |
| 826 | struct device *dev) |
| 827 | { |
Will Deacon | 463e862 | 2021-07-20 14:38:24 +0100 | [diff] [blame] | 828 | dev->dma_io_tlb_mem = &io_tlb_default_mem; |
Claire Chang | 0b84e4f | 2021-06-19 11:40:41 +0800 | [diff] [blame] | 829 | } |
| 830 | |
| 831 | static const struct reserved_mem_ops rmem_swiotlb_ops = { |
| 832 | .device_init = rmem_swiotlb_device_init, |
| 833 | .device_release = rmem_swiotlb_device_release, |
| 834 | }; |
| 835 | |
| 836 | static int __init rmem_swiotlb_setup(struct reserved_mem *rmem) |
| 837 | { |
| 838 | unsigned long node = rmem->fdt_node; |
| 839 | |
| 840 | if (of_get_flat_dt_prop(node, "reusable", NULL) || |
| 841 | of_get_flat_dt_prop(node, "linux,cma-default", NULL) || |
| 842 | of_get_flat_dt_prop(node, "linux,dma-default", NULL) || |
| 843 | of_get_flat_dt_prop(node, "no-map", NULL)) |
| 844 | return -EINVAL; |
| 845 | |
| 846 | if (PageHighMem(pfn_to_page(PHYS_PFN(rmem->base)))) { |
| 847 | pr_err("Restricted DMA pool must be accessible within the linear mapping."); |
| 848 | return -EINVAL; |
| 849 | } |
| 850 | |
| 851 | rmem->ops = &rmem_swiotlb_ops; |
| 852 | pr_info("Reserved memory: created restricted DMA pool at %pa, size %ld MiB\n", |
| 853 | &rmem->base, (unsigned long)rmem->size / SZ_1M); |
| 854 | return 0; |
| 855 | } |
| 856 | |
| 857 | RESERVEDMEM_OF_DECLARE(dma, "restricted-dma-pool", rmem_swiotlb_setup); |
Claire Chang | f4111e3 | 2021-06-19 11:40:40 +0800 | [diff] [blame] | 858 | #endif /* CONFIG_DMA_RESTRICTED_POOL */ |