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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / a305597850c96e2f2d349533cf3b514fa4b7b9f8 / . / arch / powerpc / kernel / head_32.h
blob: ba20bfabdf63b8dd9487da7a899476cedb9392ed [file] [log] [blame]
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __HEAD_32_H__
3#define __HEAD_32_H__
4
5#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6
7/*
8 * Exception entry code. This code runs with address translation
9 * turned off, i.e. using physical addresses.
10 * We assume sprg3 has the physical address of the current
11 * task's thread_struct.
12 */
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]13.macro EXCEPTION_PROLOG trapno name handle_dar_dsisr=0
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]14 EXCEPTION_PROLOG_0 handle_dar_dsisr=\handle_dar_dsisr
Christophe Leroy1f1c4d02019-12-21 08:32:23 +0000[diff] [blame]15 EXCEPTION_PROLOG_1
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]16 EXCEPTION_PROLOG_2 \trapno \name handle_dar_dsisr=\handle_dar_dsisr
Christophe Leroy1f1c4d02019-12-21 08:32:23 +0000[diff] [blame]17.endm
18
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]19.macro EXCEPTION_PROLOG_0 handle_dar_dsisr=0
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]20 mtspr SPRN_SPRG_SCRATCH0,r10
21 mtspr SPRN_SPRG_SCRATCH1,r11
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]22 mfspr r10, SPRN_SPRG_THREAD
23 .if \handle_dar_dsisr
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]24#ifdef CONFIG_40x
25 mfspr r11, SPRN_DEAR
26#else
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]27 mfspr r11, SPRN_DAR
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]28#endif
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]29 stw r11, DAR(r10)
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]30#ifdef CONFIG_40x
31 mfspr r11, SPRN_ESR
32#else
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]33 mfspr r11, SPRN_DSISR
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]34#endif
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]35 stw r11, DSISR(r10)
36 .endif
37 mfspr r11, SPRN_SRR0
38 stw r11, SRR0(r10)
Christophe Leroy5ae8fab2019-12-21 08:32:25 +0000[diff] [blame]39 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]40 stw r11, SRR1(r10)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]41 mfcr r10
Christophe Leroy5ae8fab2019-12-21 08:32:25 +0000[diff] [blame]42 andi. r11, r11, MSR_PR
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]43.endm
44
Christophe Leroy7aa8dd62021-03-12 12:50:22 +0000[diff] [blame]45.macro EXCEPTION_PROLOG_1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]46 mtspr SPRN_SPRG_SCRATCH2,r1
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]47 subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */
48 beq 1f
49 mfspr r1,SPRN_SPRG_THREAD
50 lwz r1,TASK_STACK-THREAD(r1)
51 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy6285f9c2020-11-25 07:10:51 +0000[diff] [blame]521:
Christophe Leroy7aa8dd62021-03-12 12:50:22 +0000[diff] [blame]53#ifdef CONFIG_VMAP_STACK
Christophe Leroy3642eb22021-02-08 07:17:40 +0000[diff] [blame]54 mtcrf 0x3f, r1
Christophe Leroy5b5e5bc2021-03-12 12:50:27 +0000[diff] [blame]55 bt 32 - THREAD_ALIGN_SHIFT, vmap_stack_overflow
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]56#endif
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]57.endm
58
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]59.macro EXCEPTION_PROLOG_2 trapno name handle_dar_dsisr=0
Christophe Leroy5b1c9a02021-03-12 12:50:23 +0000[diff] [blame]60#ifdef CONFIG_PPC_8xx
61 .if \handle_dar_dsisr
62 li r11, RPN_PATTERN
63 mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */
64 .endif
65#endif
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]66 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */
67 mtspr SPRN_SRR1, r11
68 lis r11, 1f@h
69 ori r11, r11, 1f@l
70 mtspr SPRN_SRR0, r11
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]71 mfspr r11, SPRN_SPRG_SCRATCH2
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]72 rfi
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]73
74 .text
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame]75\name\()_virt:
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]761:
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]77 stw r11,GPR1(r1)
78 stw r11,0(r1)
79 mr r11, r1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]80 stw r10,_CCR(r11) /* save registers */
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]81 stw r12,GPR12(r11)
82 stw r9,GPR9(r11)
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]83 mfspr r10,SPRN_SPRG_SCRATCH0
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]84 mfspr r12,SPRN_SPRG_SCRATCH1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]85 stw r10,GPR10(r11)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]86 stw r12,GPR11(r11)
87 mflr r10
88 stw r10,_LINK(r11)
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]89 mfspr r12, SPRN_SPRG_THREAD
90 tovirt(r12, r12)
91 .if \handle_dar_dsisr
92 lwz r10, DAR(r12)
93 stw r10, _DAR(r11)
94 lwz r10, DSISR(r12)
95 stw r10, _DSISR(r11)
96 .endif
97 lwz r9, SRR1(r12)
98 lwz r12, SRR0(r12)
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]99#ifdef CONFIG_40x
100 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
Christophe Leroye464d922021-03-12 12:50:20 +0000[diff] [blame]101#elif defined(CONFIG_PPC_8xx)
102 mtspr SPRN_EID, r2 /* Set MSR_RI */
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]103#else
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]104 li r10, MSR_KERNEL /* can take exceptions */
Christophe Leroy39bccfd2019-12-21 08:32:22 +0000[diff] [blame]105 mtmsr r10 /* (except for mach check in rtas) */
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]106#endif
Christophe Leroya3055972021-03-12 12:50:43 +0000[diff] [blame^]107 COMMON_EXCEPTION_PROLOG_END \trapno
108_ASM_NOKPROBE_SYMBOL(\name\()_virt)
109.endm
110
111.macro COMMON_EXCEPTION_PROLOG_END trapno
112 stw r0,GPR0(r1)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]113 lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
114 addi r10,r10,STACK_FRAME_REGS_MARKER@l
Christophe Leroya3055972021-03-12 12:50:43 +0000[diff] [blame^]115 stw r10,8(r1)
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]116 li r10, \trapno
Christophe Leroya3055972021-03-12 12:50:43 +0000[diff] [blame^]117 stw r10,_TRAP(r1)
118 SAVE_4GPRS(3, r1)
119 SAVE_2GPRS(7, r1)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]120.endm
121
Christophe Leroybce4c262021-03-12 12:50:39 +0000[diff] [blame]122.macro prepare_transfer_to_handler
123 bl prepare_transfer_to_handler
124.endm
125
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]126.macro SYSCALL_ENTRY trapno
Christophe Leroy9e270862020-01-31 11:34:54 +0000[diff] [blame]127 mfspr r9, SPRN_SRR1
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]128 mfspr r10, SPRN_SRR0
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]129 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL) /* can take exceptions */
130 lis r12, 1f@h
131 ori r12, r12, 1f@l
132 mtspr SPRN_SRR1, r11
133 mtspr SPRN_SRR0, r12
134 mfspr r12,SPRN_SPRG_THREAD
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]135 mr r11, r1
136 lwz r1,TASK_STACK-THREAD(r12)
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]137 tovirt(r12, r12)
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]138 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy76249dd2021-02-08 15:10:22 +0000[diff] [blame]139 rfi
1401:
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]141 stw r11,GPR1(r1)
142 stw r11,0(r1)
143 mr r11, r1
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]144 stw r10,_NIP(r11)
Christophe Leroy9e270862020-01-31 11:34:54 +0000[diff] [blame]145 mflr r10
146 stw r10, _LINK(r11)
Christophe Leroyc06f0af2020-01-31 11:34:55 +0000[diff] [blame]147 mfcr r10
148 rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */
149 stw r10,_CCR(r11) /* save registers */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]150#ifdef CONFIG_40x
151 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]152#endif
153 lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
154 stw r2,GPR2(r11)
155 addi r10,r10,STACK_FRAME_REGS_MARKER@l
156 stw r9,_MSR(r11)
Christophe Leroyfbcee2e2021-02-08 15:10:32 +0000[diff] [blame]157 li r2, \trapno
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]158 stw r10,8(r11)
159 stw r2,_TRAP(r11)
160 SAVE_GPR(0, r11)
161 SAVE_4GPRS(3, r11)
162 SAVE_2GPRS(7, r11)
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]163 addi r2,r12,-THREAD
Christophe Leroy76249dd2021-02-08 15:10:22 +0000[diff] [blame]164 b transfer_to_syscall /* jump to handler */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]165.endm
166
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]167/*
168 * Note: code which follows this uses cr0.eq (set if from kernel),
169 * r11, r12 (SRR0), and r9 (SRR1).
170 *
171 * Note2: once we have set r1 we are in a position to take exceptions
172 * again, and we could thus set MSR:RI at that point.
173 */
174
175/*
176 * Exception vectors.
177 */
178#ifdef CONFIG_PPC_BOOK3S
179#define START_EXCEPTION(n, label) \
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]180 __HEAD; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]181 . = n; \
182 DO_KVM n; \
183label:
184
185#else
186#define START_EXCEPTION(n, label) \
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]187 __HEAD; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]188 . = n; \
189label:
190
191#endif
192
Christophe Leroyacc142b2021-03-12 12:50:42 +0000[diff] [blame]193#define EXCEPTION(n, label, hdlr) \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]194 START_EXCEPTION(n, label) \
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]195 EXCEPTION_PROLOG n label; \
Christophe Leroy4c0104a2021-03-12 12:50:41 +0000[diff] [blame]196 prepare_transfer_to_handler; \
197 bl hdlr; \
198 b interrupt_return
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]199
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]200.macro vmap_stack_overflow_exception
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]201 __HEAD
Christophe Leroy5b5e5bc2021-03-12 12:50:27 +0000[diff] [blame]202vmap_stack_overflow:
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]203#ifdef CONFIG_SMP
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]204 mfspr r1, SPRN_SPRG_THREAD
205 lwz r1, TASK_CPU - THREAD(r1)
206 slwi r1, r1, 3
207 addis r1, r1, emergency_ctx@ha
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]208#else
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]209 lis r1, emergency_ctx@ha
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]210#endif
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]211 lwz r1, emergency_ctx@l(r1)
Christophe Leroya4719f52021-03-12 12:50:25 +0000[diff] [blame]212 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy719e7e22021-03-12 12:50:38 +0000[diff] [blame]213 EXCEPTION_PROLOG_2 0 vmap_stack_overflow
Christophe Leroy4c0104a2021-03-12 12:50:41 +0000[diff] [blame]214 prepare_transfer_to_handler
215 bl stack_overflow_exception
216 b interrupt_return
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]217.endm
218
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]219#endif /* __HEAD_32_H__ */