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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8f844c06f460687b028c675c3fa68f8e735aeb8c / . / arch / powerpc / kernel / head_32.h
blob: 160ebd573c37944c7b02d2d6897bcbb0b849cdcb [file] [log] [blame]
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __HEAD_32_H__
3#define __HEAD_32_H__
4
5#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6
7/*
8 * Exception entry code. This code runs with address translation
9 * turned off, i.e. using physical addresses.
10 * We assume sprg3 has the physical address of the current
11 * task's thread_struct.
12 */
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]13.macro EXCEPTION_PROLOG name handle_dar_dsisr=0
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]14 EXCEPTION_PROLOG_0 handle_dar_dsisr=\handle_dar_dsisr
Christophe Leroy1f1c4d02019-12-21 08:32:23 +0000[diff] [blame]15 EXCEPTION_PROLOG_1
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]16 EXCEPTION_PROLOG_2 \name handle_dar_dsisr=\handle_dar_dsisr
Christophe Leroy1f1c4d02019-12-21 08:32:23 +0000[diff] [blame]17.endm
18
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]19.macro EXCEPTION_PROLOG_0 handle_dar_dsisr=0
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]20 mtspr SPRN_SPRG_SCRATCH0,r10
21 mtspr SPRN_SPRG_SCRATCH1,r11
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]22 mfspr r10, SPRN_SPRG_THREAD
23 .if \handle_dar_dsisr
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]24#ifdef CONFIG_40x
25 mfspr r11, SPRN_DEAR
26#else
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]27 mfspr r11, SPRN_DAR
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]28#endif
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]29 stw r11, DAR(r10)
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]30#ifdef CONFIG_40x
31 mfspr r11, SPRN_ESR
32#else
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]33 mfspr r11, SPRN_DSISR
Christophe Leroy0512aad2021-03-12 12:50:16 +0000[diff] [blame]34#endif
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]35 stw r11, DSISR(r10)
36 .endif
37 mfspr r11, SPRN_SRR0
38 stw r11, SRR0(r10)
Christophe Leroy5ae8fab2019-12-21 08:32:25 +0000[diff] [blame]39 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]40 stw r11, SRR1(r10)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]41 mfcr r10
Christophe Leroy5ae8fab2019-12-21 08:32:25 +0000[diff] [blame]42 andi. r11, r11, MSR_PR
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]43.endm
44
Christophe Leroy7aa8dd62021-03-12 12:50:22 +0000[diff] [blame]45.macro EXCEPTION_PROLOG_1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]46 mtspr SPRN_SPRG_SCRATCH2,r1
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]47 subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */
48 beq 1f
49 mfspr r1,SPRN_SPRG_THREAD
50 lwz r1,TASK_STACK-THREAD(r1)
51 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy6285f9c2020-11-25 07:10:51 +0000[diff] [blame]521:
Christophe Leroy7aa8dd62021-03-12 12:50:22 +0000[diff] [blame]53#ifdef CONFIG_VMAP_STACK
Christophe Leroy3642eb22021-02-08 07:17:40 +0000[diff] [blame]54 mtcrf 0x3f, r1
Christophe Leroy5b5e5bc2021-03-12 12:50:27 +0000[diff] [blame]55 bt 32 - THREAD_ALIGN_SHIFT, vmap_stack_overflow
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]56#endif
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]57.endm
58
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]59.macro EXCEPTION_PROLOG_2 name handle_dar_dsisr=0
Christophe Leroy5b1c9a02021-03-12 12:50:23 +0000[diff] [blame]60#ifdef CONFIG_PPC_8xx
61 .if \handle_dar_dsisr
62 li r11, RPN_PATTERN
63 mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */
64 .endif
65#endif
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]66 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */
67 mtspr SPRN_SRR1, r11
68 lis r11, 1f@h
69 ori r11, r11, 1f@l
70 mtspr SPRN_SRR0, r11
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]71 mfspr r11, SPRN_SPRG_SCRATCH2
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]72 rfi
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]73
74 .text
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]75\name\()_virt:
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]761:
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]77 stw r11,GPR1(r1)
78 stw r11,0(r1)
79 mr r11, r1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]80 stw r10,_CCR(r11) /* save registers */
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]81 stw r12,GPR12(r11)
82 stw r9,GPR9(r11)
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]83 mfspr r10,SPRN_SPRG_SCRATCH0
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]84 mfspr r12,SPRN_SPRG_SCRATCH1
Christophe Leroyd2e00602020-11-25 07:10:53 +0000[diff] [blame]85 stw r10,GPR10(r11)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]86 stw r12,GPR11(r11)
87 mflr r10
88 stw r10,_LINK(r11)
Christophe Leroy02847482019-12-21 08:32:27 +0000[diff] [blame]89 mfspr r12, SPRN_SPRG_THREAD
90 tovirt(r12, r12)
91 .if \handle_dar_dsisr
92 lwz r10, DAR(r12)
93 stw r10, _DAR(r11)
94 lwz r10, DSISR(r12)
95 stw r10, _DSISR(r11)
96 .endif
97 lwz r9, SRR1(r12)
98 lwz r12, SRR0(r12)
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]99#ifdef CONFIG_40x
100 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
Christophe Leroye464d922021-03-12 12:50:20 +0000[diff] [blame]101#elif defined(CONFIG_PPC_8xx)
102 mtspr SPRN_EID, r2 /* Set MSR_RI */
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]103#else
Christophe Leroy9b6150f2021-03-12 12:50:24 +0000[diff] [blame]104 li r10, MSR_KERNEL /* can take exceptions */
Christophe Leroy39bccfd2019-12-21 08:32:22 +0000[diff] [blame]105 mtmsr r10 /* (except for mach check in rtas) */
Christophe Leroy90f204b2019-04-30 12:38:56 +0000[diff] [blame]106#endif
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]107 stw r0,GPR0(r11)
108 lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
109 addi r10,r10,STACK_FRAME_REGS_MARKER@l
110 stw r10,8(r11)
111 SAVE_4GPRS(3, r11)
112 SAVE_2GPRS(7, r11)
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]113_ASM_NOKPROBE_SYMBOL(\name\()_virt)
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]114.endm
115
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]116.macro SYSCALL_ENTRY trapno
Christophe Leroy9e270862020-01-31 11:34:54 +0000[diff] [blame]117 mfspr r9, SPRN_SRR1
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]118 mfspr r10, SPRN_SRR0
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]119 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL) /* can take exceptions */
120 lis r12, 1f@h
121 ori r12, r12, 1f@l
122 mtspr SPRN_SRR1, r11
123 mtspr SPRN_SRR0, r12
124 mfspr r12,SPRN_SPRG_THREAD
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]125 mr r11, r1
126 lwz r1,TASK_STACK-THREAD(r12)
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]127 tovirt(r12, r12)
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]128 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy76249dd2021-02-08 15:10:22 +0000[diff] [blame]129 rfi
1301:
Christophe Leroyd5c24392020-12-21 06:18:03 +0000[diff] [blame]131 stw r11,GPR1(r1)
132 stw r11,0(r1)
133 mr r11, r1
Christophe Leroy2c59e512021-02-08 15:10:23 +0000[diff] [blame]134 stw r10,_NIP(r11)
Christophe Leroy9e270862020-01-31 11:34:54 +0000[diff] [blame]135 mflr r10
136 stw r10, _LINK(r11)
Christophe Leroyc06f0af2020-01-31 11:34:55 +0000[diff] [blame]137 mfcr r10
138 rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */
139 stw r10,_CCR(r11) /* save registers */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]140#ifdef CONFIG_40x
141 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]142#endif
143 lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
144 stw r2,GPR2(r11)
145 addi r10,r10,STACK_FRAME_REGS_MARKER@l
146 stw r9,_MSR(r11)
Christophe Leroyfbcee2e2021-02-08 15:10:32 +0000[diff] [blame]147 li r2, \trapno
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]148 stw r10,8(r11)
149 stw r2,_TRAP(r11)
150 SAVE_GPR(0, r11)
151 SAVE_4GPRS(3, r11)
152 SAVE_2GPRS(7, r11)
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]153 addi r2,r12,-THREAD
Christophe Leroy76249dd2021-02-08 15:10:22 +0000[diff] [blame]154 b transfer_to_syscall /* jump to handler */
Christophe Leroyb86fb882019-04-30 12:39:02 +0000[diff] [blame]155.endm
156
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]157/*
158 * Note: code which follows this uses cr0.eq (set if from kernel),
159 * r11, r12 (SRR0), and r9 (SRR1).
160 *
161 * Note2: once we have set r1 we are in a position to take exceptions
162 * again, and we could thus set MSR:RI at that point.
163 */
164
165/*
166 * Exception vectors.
167 */
168#ifdef CONFIG_PPC_BOOK3S
169#define START_EXCEPTION(n, label) \
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]170 __HEAD; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]171 . = n; \
172 DO_KVM n; \
173label:
174
175#else
176#define START_EXCEPTION(n, label) \
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]177 __HEAD; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]178 . = n; \
179label:
180
181#endif
182
183#define EXCEPTION(n, label, hdlr, xfer) \
184 START_EXCEPTION(n, label) \
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]185 EXCEPTION_PROLOG label; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]186 addi r3,r1,STACK_FRAME_OVERHEAD; \
187 xfer(n, hdlr)
188
Christophe Leroy1ae99b42019-04-30 12:39:00 +0000[diff] [blame]189#define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]190 li r10,trap; \
191 stw r10,_TRAP(r11); \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]192 bl tfer; \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]193 .long hdlr; \
194 .long ret
195
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]196#define EXC_XFER_STD(n, hdlr) \
Christophe Leroy1ae99b42019-04-30 12:39:00 +0000[diff] [blame]197 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]198 ret_from_except_full)
199
200#define EXC_XFER_LITE(n, hdlr) \
Christophe Leroy1ae99b42019-04-30 12:39:00 +0000[diff] [blame]201 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]202 ret_from_except)
203
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]204.macro vmap_stack_overflow_exception
Christophe Leroydc13b882021-03-12 12:50:29 +0000[diff] [blame]205 __HEAD
Christophe Leroy5b5e5bc2021-03-12 12:50:27 +0000[diff] [blame]206vmap_stack_overflow:
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]207#ifdef CONFIG_SMP
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]208 mfspr r1, SPRN_SPRG_THREAD
209 lwz r1, TASK_CPU - THREAD(r1)
210 slwi r1, r1, 3
211 addis r1, r1, emergency_ctx@ha
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]212#else
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]213 lis r1, emergency_ctx@ha
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]214#endif
Christophe Leroyda7bb432020-09-07 13:42:10 +0000[diff] [blame]215 lwz r1, emergency_ctx@l(r1)
Christophe Leroya4719f52021-03-12 12:50:25 +0000[diff] [blame]216 addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
Christophe Leroy8f844c02021-03-12 12:50:30 +0000[diff] [blame^]217 EXCEPTION_PROLOG_2 vmap_stack_overflow
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]218 SAVE_NVGPRS(r11)
219 addi r3, r1, STACK_FRAME_OVERHEAD
220 EXC_XFER_STD(0, stack_overflow_exception)
Christophe Leroy3978eb72019-12-21 08:32:29 +0000[diff] [blame]221.endm
222
Christophe Leroy8a23fdec2019-04-30 12:38:50 +0000[diff] [blame]223#endif /* __HEAD_32_H__ */