blob: fdd6f9fda6f9fabcb03190acf587762220650c3e [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
David Brownell1abb0dc2006-06-25 05:48:17 -07002/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
Matthias Fuchsa2166852009-03-31 15:24:58 -07007 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
Bertrand Achardbc48b902013-04-29 16:19:26 -07008 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
David Brownell1abb0dc2006-06-25 05:48:17 -07009 */
10
Tin Huynh9c19b892016-11-30 09:57:31 +070011#include <linux/acpi.h>
David Brownell1abb0dc2006-06-25 05:48:17 -070012#include <linux/bcd.h>
Nishanth Menoneac72372015-06-23 11:15:12 -050013#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/module.h>
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -030016#include <linux/of_device.h>
Wolfram Sangeb86c302012-05-29 15:07:38 -070017#include <linux/rtc/ds1307.h>
Nishanth Menoneac72372015-06-23 11:15:12 -050018#include <linux/rtc.h>
19#include <linux/slab.h>
20#include <linux/string.h>
Akinobu Mita445c0202016-01-25 00:22:16 +090021#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
Akinobu Mita6c6ff142016-01-31 23:10:10 +090023#include <linux/clk-provider.h>
Heiner Kallweit11e58902017-03-10 18:52:34 +010024#include <linux/regmap.h>
Chris Packhamfd90d482020-03-30 15:55:00 +130025#include <linux/watchdog.h>
David Brownell1abb0dc2006-06-25 05:48:17 -070026
David Anders40ce9722012-03-23 15:02:37 -070027/*
28 * We can't determine type by probing, but if we expect pre-Linux code
David Brownell1abb0dc2006-06-25 05:48:17 -070029 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
David Brownell1abb0dc2006-06-25 05:48:17 -070032 */
33enum ds_type {
David Brownell045e0e82007-07-17 04:04:55 -070034 ds_1307,
Sean Nyekjaer300a7732017-06-08 12:36:54 +020035 ds_1308,
David Brownell045e0e82007-07-17 04:04:55 -070036 ds_1337,
37 ds_1338,
38 ds_1339,
39 ds_1340,
Nikita Yushchenko0759c882017-08-24 09:32:11 +030040 ds_1341,
Joakim Tjernlund33df2ee2009-06-17 16:26:08 -070041 ds_1388,
Wolfram Sang97f902b2009-06-17 16:26:10 -070042 ds_3231,
Stefan Agner8566f702017-03-23 16:54:57 -070043 m41t0,
David Brownell045e0e82007-07-17 04:04:55 -070044 m41t00,
Giulio Benetti7e580762018-05-16 23:08:40 +020045 m41t11,
Tomas Novotnyf4199f82014-12-10 15:53:57 -080046 mcp794xx,
Matthias Fuchsa2166852009-03-31 15:24:58 -070047 rx_8025,
Marek Vasutee0981b2017-06-18 22:55:28 +020048 rx_8130,
Wolfram Sang32d322b2012-03-23 15:02:36 -070049 last_ds_type /* always last */
David Anders40ce9722012-03-23 15:02:37 -070050 /* rs5c372 too? different address... */
David Brownell1abb0dc2006-06-25 05:48:17 -070051};
52
David Brownell1abb0dc2006-06-25 05:48:17 -070053/* RTC registers don't differ much, except for the century flag */
54#define DS1307_REG_SECS 0x00 /* 00-59 */
55# define DS1307_BIT_CH 0x80
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -070056# define DS1340_BIT_nEOSC 0x80
Tomas Novotnyf4199f82014-12-10 15:53:57 -080057# define MCP794XX_BIT_ST 0x80
David Brownell1abb0dc2006-06-25 05:48:17 -070058#define DS1307_REG_MIN 0x01 /* 00-59 */
Stefan Agner8566f702017-03-23 16:54:57 -070059# define M41T0_BIT_OF 0x80
David Brownell1abb0dc2006-06-25 05:48:17 -070060#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
David Brownellc065f352007-07-17 04:05:10 -070061# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
62# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
David Brownell1abb0dc2006-06-25 05:48:17 -070063# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
64# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
65#define DS1307_REG_WDAY 0x03 /* 01-07 */
Tomas Novotnyf4199f82014-12-10 15:53:57 -080066# define MCP794XX_BIT_VBATEN 0x08
David Brownell1abb0dc2006-06-25 05:48:17 -070067#define DS1307_REG_MDAY 0x04 /* 01-31 */
68#define DS1307_REG_MONTH 0x05 /* 01-12 */
69# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
70#define DS1307_REG_YEAR 0x06 /* 00-99 */
71
David Anders40ce9722012-03-23 15:02:37 -070072/*
73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
David Brownell045e0e82007-07-17 04:04:55 -070074 * start at 7, and they differ a LOT. Only control and status matter for
75 * basic RTC date and time functionality; be careful using them.
David Brownell1abb0dc2006-06-25 05:48:17 -070076 */
David Brownell045e0e82007-07-17 04:04:55 -070077#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
David Brownell1abb0dc2006-06-25 05:48:17 -070078# define DS1307_BIT_OUT 0x80
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -070079# define DS1338_BIT_OSF 0x20
David Brownell1abb0dc2006-06-25 05:48:17 -070080# define DS1307_BIT_SQWE 0x10
81# define DS1307_BIT_RS1 0x02
82# define DS1307_BIT_RS0 0x01
83#define DS1337_REG_CONTROL 0x0e
84# define DS1337_BIT_nEOSC 0x80
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -070085# define DS1339_BIT_BBSQI 0x20
Wolfram Sang97f902b2009-06-17 16:26:10 -070086# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
David Brownell1abb0dc2006-06-25 05:48:17 -070087# define DS1337_BIT_RS2 0x10
88# define DS1337_BIT_RS1 0x08
89# define DS1337_BIT_INTCN 0x04
90# define DS1337_BIT_A2IE 0x02
91# define DS1337_BIT_A1IE 0x01
David Brownell045e0e82007-07-17 04:04:55 -070092#define DS1340_REG_CONTROL 0x07
93# define DS1340_BIT_OUT 0x80
94# define DS1340_BIT_FT 0x40
95# define DS1340_BIT_CALIB_SIGN 0x20
96# define DS1340_M_CALIBRATION 0x1f
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -070097#define DS1340_REG_FLAG 0x09
98# define DS1340_BIT_OSF 0x80
David Brownell1abb0dc2006-06-25 05:48:17 -070099#define DS1337_REG_STATUS 0x0f
100# define DS1337_BIT_OSF 0x80
Akinobu Mita6c6ff142016-01-31 23:10:10 +0900101# define DS3231_BIT_EN32KHZ 0x08
David Brownell1abb0dc2006-06-25 05:48:17 -0700102# define DS1337_BIT_A2I 0x02
103# define DS1337_BIT_A1I 0x01
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -0700104#define DS1339_REG_ALARM1_SECS 0x07
Wolfram Sangeb86c302012-05-29 15:07:38 -0700105
106#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
David Brownell1abb0dc2006-06-25 05:48:17 -0700107
Matthias Fuchsa2166852009-03-31 15:24:58 -0700108#define RX8025_REG_CTRL1 0x0e
109# define RX8025_BIT_2412 0x20
110#define RX8025_REG_CTRL2 0x0f
111# define RX8025_BIT_PON 0x10
112# define RX8025_BIT_VDET 0x40
113# define RX8025_BIT_XST 0x20
David Brownell1abb0dc2006-06-25 05:48:17 -0700114
Uwe Kleine-König3ffd4a22019-01-25 15:35:56 +0100115#define RX8130_REG_ALARM_MIN 0x17
116#define RX8130_REG_ALARM_HOUR 0x18
117#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
118#define RX8130_REG_EXTENSION 0x1c
Uwe Kleine-König92cbf122019-01-25 15:35:54 +0100119#define RX8130_REG_EXTENSION_WADA BIT(3)
Uwe Kleine-König3ffd4a22019-01-25 15:35:56 +0100120#define RX8130_REG_FLAG 0x1d
121#define RX8130_REG_FLAG_VLF BIT(1)
Uwe Kleine-König92cbf122019-01-25 15:35:54 +0100122#define RX8130_REG_FLAG_AF BIT(3)
Uwe Kleine-König3ffd4a22019-01-25 15:35:56 +0100123#define RX8130_REG_CONTROL0 0x1e
Uwe Kleine-König92cbf122019-01-25 15:35:54 +0100124#define RX8130_REG_CONTROL0_AIE BIT(3)
125
126#define MCP794XX_REG_CONTROL 0x07
127# define MCP794XX_BIT_ALM0_EN 0x10
128# define MCP794XX_BIT_ALM1_EN 0x20
129#define MCP794XX_REG_ALARM0_BASE 0x0a
130#define MCP794XX_REG_ALARM0_CTRL 0x0d
131#define MCP794XX_REG_ALARM1_BASE 0x11
132#define MCP794XX_REG_ALARM1_CTRL 0x14
133# define MCP794XX_BIT_ALMX_IF BIT(3)
134# define MCP794XX_BIT_ALMX_C0 BIT(4)
135# define MCP794XX_BIT_ALMX_C1 BIT(5)
136# define MCP794XX_BIT_ALMX_C2 BIT(6)
137# define MCP794XX_BIT_ALMX_POL BIT(7)
138# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
139 MCP794XX_BIT_ALMX_C1 | \
140 MCP794XX_BIT_ALMX_C2)
141
Giulio Benetti79230ff2018-07-25 19:26:04 +0200142#define M41TXX_REG_CONTROL 0x07
143# define M41TXX_BIT_OUT BIT(7)
144# define M41TXX_BIT_FT BIT(6)
145# define M41TXX_BIT_CALIB_SIGN BIT(5)
146# define M41TXX_M_CALIBRATION GENMASK(4, 0)
147
Chris Packhamfd90d482020-03-30 15:55:00 +1300148#define DS1388_REG_WDOG_HUN_SECS 0x08
149#define DS1388_REG_WDOG_SECS 0x09
Chris Packhamdf11b322020-02-07 16:18:11 +1300150#define DS1388_REG_FLAG 0x0b
Chris Packhamfd90d482020-03-30 15:55:00 +1300151# define DS1388_BIT_WF BIT(6)
Chris Packhamdf11b322020-02-07 16:18:11 +1300152# define DS1388_BIT_OSF BIT(7)
Chris Packhamfd90d482020-03-30 15:55:00 +1300153#define DS1388_REG_CONTROL 0x0c
154# define DS1388_BIT_RST BIT(0)
155# define DS1388_BIT_WDE BIT(1)
Chris Packham59ed0122020-08-17 11:57:31 +1200156# define DS1388_BIT_nEOSC BIT(7)
Chris Packhamfd90d482020-03-30 15:55:00 +1300157
Giulio Benetti79230ff2018-07-25 19:26:04 +0200158/* negative offset step is -2.034ppm */
159#define M41TXX_NEG_OFFSET_STEP_PPB 2034
160/* positive offset step is +4.068ppm */
161#define M41TXX_POS_OFFSET_STEP_PPB 4068
162/* Min and max values supported with 'offset' interface by M41TXX */
163#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
164#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
165
David Brownell1abb0dc2006-06-25 05:48:17 -0700166struct ds1307 {
David Brownell1abb0dc2006-06-25 05:48:17 -0700167 enum ds_type type;
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -0700168 unsigned long flags;
169#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
170#define HAS_ALARM 1 /* bit 1 == irq claimed */
Heiner Kallweit11e58902017-03-10 18:52:34 +0100171 struct device *dev;
172 struct regmap *regmap;
173 const char *name;
David Brownell1abb0dc2006-06-25 05:48:17 -0700174 struct rtc_device *rtc;
Akinobu Mita6c6ff142016-01-31 23:10:10 +0900175#ifdef CONFIG_COMMON_CLK
176 struct clk_hw clks[2];
177#endif
David Brownell1abb0dc2006-06-25 05:48:17 -0700178};
179
David Brownell045e0e82007-07-17 04:04:55 -0700180struct chip_desc {
David Brownell045e0e82007-07-17 04:04:55 -0700181 unsigned alarm:1;
Austin Boyle9eab0a72012-03-23 15:02:38 -0700182 u16 nvram_offset;
183 u16 nvram_size;
Heiner Kallweite5531702017-07-12 07:49:47 +0200184 u8 offset; /* register's offset */
Heiner Kallweite48585d2017-06-05 17:57:33 +0200185 u8 century_reg;
186 u8 century_enable_bit;
187 u8 century_bit;
Heiner Kallweit0b6ee802017-07-12 07:49:22 +0200188 u8 bbsqi_bit;
Heiner Kallweit45947122017-07-12 07:49:41 +0200189 irq_handler_t irq_handler;
Heiner Kallweit1efb98b2017-07-12 07:49:44 +0200190 const struct rtc_class_ops *rtc_ops;
Wolfram Sangeb86c302012-05-29 15:07:38 -0700191 u16 trickle_charger_reg;
Alexandre Belloni57ec2d92017-09-04 22:46:04 +0200192 u8 (*do_trickle_setup)(struct ds1307 *, u32,
Heiner Kallweit11e58902017-03-10 18:52:34 +0100193 bool);
Bastian Krause1b5b6af2020-09-17 20:32:43 +0200194 /* Does the RTC require trickle-resistor-ohms to select the value of
195 * the resistor between Vcc and Vbackup?
196 */
197 bool requires_trickle_resistor;
Bastian Krause95a74cb2020-09-17 20:32:44 +0200198 /* Some RTC's batteries and supercaps were charged by default, others
199 * allow charging but were not configured previously to do so.
200 * Remember this behavior to stay backwards compatible.
201 */
202 bool charge_default;
David Brownell045e0e82007-07-17 04:04:55 -0700203};
204
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100205static const struct chip_desc chips[last_ds_type];
206
207static int ds1307_get_time(struct device *dev, struct rtc_time *t)
208{
209 struct ds1307 *ds1307 = dev_get_drvdata(dev);
210 int tmp, ret;
211 const struct chip_desc *chip = &chips[ds1307->type];
212 u8 regs[7];
213
Uwe Kleine-König501f9822019-01-25 15:35:57 +0100214 if (ds1307->type == rx_8130) {
215 unsigned int regflag;
216 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
217 if (ret) {
218 dev_err(dev, "%s error %d\n", "read", ret);
219 return ret;
220 }
221
222 if (regflag & RX8130_REG_FLAG_VLF) {
223 dev_warn_once(dev, "oscillator failed, set time!\n");
224 return -EINVAL;
225 }
226 }
227
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100228 /* read the RTC date and time registers all at once */
229 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
230 sizeof(regs));
231 if (ret) {
232 dev_err(dev, "%s error %d\n", "read", ret);
233 return ret;
234 }
235
236 dev_dbg(dev, "%s: %7ph\n", "read", regs);
237
238 /* if oscillator fail bit is set, no data can be trusted */
239 if (ds1307->type == m41t0 &&
240 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
241 dev_warn_once(dev, "oscillator failed, set time!\n");
242 return -EINVAL;
243 }
244
Alexandre Bellonib3a50162019-04-11 00:16:29 +0200245 tmp = regs[DS1307_REG_SECS];
246 switch (ds1307->type) {
247 case ds_1307:
248 case m41t0:
249 case m41t00:
250 case m41t11:
251 if (tmp & DS1307_BIT_CH)
252 return -EINVAL;
253 break;
254 case ds_1308:
255 case ds_1338:
256 if (tmp & DS1307_BIT_CH)
257 return -EINVAL;
258
259 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
260 if (ret)
261 return ret;
262 if (tmp & DS1338_BIT_OSF)
263 return -EINVAL;
264 break;
265 case ds_1340:
266 if (tmp & DS1340_BIT_nEOSC)
267 return -EINVAL;
268
269 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
270 if (ret)
271 return ret;
272 if (tmp & DS1340_BIT_OSF)
273 return -EINVAL;
274 break;
Chris Packhamdf11b322020-02-07 16:18:11 +1300275 case ds_1388:
276 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
277 if (ret)
278 return ret;
279 if (tmp & DS1388_BIT_OSF)
280 return -EINVAL;
281 break;
Alexandre Bellonib3a50162019-04-11 00:16:29 +0200282 case mcp794xx:
283 if (!(tmp & MCP794XX_BIT_ST))
284 return -EINVAL;
285
286 break;
287 default:
288 break;
289 }
290
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100291 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
292 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
293 tmp = regs[DS1307_REG_HOUR] & 0x3f;
294 t->tm_hour = bcd2bin(tmp);
295 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
296 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
297 tmp = regs[DS1307_REG_MONTH] & 0x1f;
298 t->tm_mon = bcd2bin(tmp) - 1;
299 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
300
301 if (regs[chip->century_reg] & chip->century_bit &&
302 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
303 t->tm_year += 100;
304
305 dev_dbg(dev, "%s secs=%d, mins=%d, "
306 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
307 "read", t->tm_sec, t->tm_min,
308 t->tm_hour, t->tm_mday,
309 t->tm_mon, t->tm_year, t->tm_wday);
310
311 return 0;
312}
313
314static int ds1307_set_time(struct device *dev, struct rtc_time *t)
315{
316 struct ds1307 *ds1307 = dev_get_drvdata(dev);
317 const struct chip_desc *chip = &chips[ds1307->type];
318 int result;
319 int tmp;
320 u8 regs[7];
321
322 dev_dbg(dev, "%s secs=%d, mins=%d, "
323 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
324 "write", t->tm_sec, t->tm_min,
325 t->tm_hour, t->tm_mday,
326 t->tm_mon, t->tm_year, t->tm_wday);
327
328 if (t->tm_year < 100)
329 return -EINVAL;
330
331#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
332 if (t->tm_year > (chip->century_bit ? 299 : 199))
333 return -EINVAL;
334#else
335 if (t->tm_year > 199)
336 return -EINVAL;
337#endif
338
339 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
340 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
341 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
342 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
343 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
344 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
345
346 /* assume 20YY not 19YY */
347 tmp = t->tm_year - 100;
348 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
349
350 if (chip->century_enable_bit)
351 regs[chip->century_reg] |= chip->century_enable_bit;
352 if (t->tm_year > 199 && chip->century_bit)
353 regs[chip->century_reg] |= chip->century_bit;
354
Alexandre Bellonib3a50162019-04-11 00:16:29 +0200355 switch (ds1307->type) {
356 case ds_1308:
357 case ds_1338:
358 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
359 DS1338_BIT_OSF, 0);
360 break;
361 case ds_1340:
362 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
363 DS1340_BIT_OSF, 0);
364 break;
Chris Packhamf471b052020-08-18 13:35:43 +1200365 case ds_1388:
366 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
367 DS1388_BIT_OSF, 0);
368 break;
Alexandre Bellonib3a50162019-04-11 00:16:29 +0200369 case mcp794xx:
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100370 /*
371 * these bits were cleared when preparing the date/time
372 * values and need to be set again before writing the
373 * regsfer out to the device.
374 */
375 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
376 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
Alexandre Bellonib3a50162019-04-11 00:16:29 +0200377 break;
378 default:
379 break;
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100380 }
381
382 dev_dbg(dev, "%s: %7ph\n", "write", regs);
383
384 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
385 sizeof(regs));
386 if (result) {
387 dev_err(dev, "%s error %d\n", "write", result);
388 return result;
389 }
Uwe Kleine-König501f9822019-01-25 15:35:57 +0100390
391 if (ds1307->type == rx_8130) {
392 /* clear Voltage Loss Flag as data is available now */
393 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
394 ~(u8)RX8130_REG_FLAG_VLF);
395 if (result) {
396 dev_err(dev, "%s error %d\n", "write", result);
397 return result;
398 }
399 }
400
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100401 return 0;
402}
403
404static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
405{
406 struct ds1307 *ds1307 = dev_get_drvdata(dev);
407 int ret;
408 u8 regs[9];
409
410 if (!test_bit(HAS_ALARM, &ds1307->flags))
411 return -EINVAL;
412
413 /* read all ALARM1, ALARM2, and status registers at once */
414 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
415 regs, sizeof(regs));
416 if (ret) {
417 dev_err(dev, "%s error %d\n", "alarm read", ret);
418 return ret;
419 }
420
421 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
422 &regs[0], &regs[4], &regs[7]);
423
424 /*
425 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
426 * and that all four fields are checked matches
427 */
428 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
429 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
430 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
431 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
432
433 /* ... and status */
434 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
435 t->pending = !!(regs[8] & DS1337_BIT_A1I);
436
437 dev_dbg(dev, "%s secs=%d, mins=%d, "
438 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
439 "alarm read", t->time.tm_sec, t->time.tm_min,
440 t->time.tm_hour, t->time.tm_mday,
441 t->enabled, t->pending);
442
443 return 0;
444}
445
446static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
447{
448 struct ds1307 *ds1307 = dev_get_drvdata(dev);
449 unsigned char regs[9];
450 u8 control, status;
451 int ret;
452
453 if (!test_bit(HAS_ALARM, &ds1307->flags))
454 return -EINVAL;
455
456 dev_dbg(dev, "%s secs=%d, mins=%d, "
457 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
458 "alarm set", t->time.tm_sec, t->time.tm_min,
459 t->time.tm_hour, t->time.tm_mday,
460 t->enabled, t->pending);
461
462 /* read current status of both alarms and the chip */
463 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
464 sizeof(regs));
465 if (ret) {
466 dev_err(dev, "%s error %d\n", "alarm write", ret);
467 return ret;
468 }
469 control = regs[7];
470 status = regs[8];
471
472 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
473 &regs[0], &regs[4], control, status);
474
475 /* set ALARM1, using 24 hour and day-of-month modes */
476 regs[0] = bin2bcd(t->time.tm_sec);
477 regs[1] = bin2bcd(t->time.tm_min);
478 regs[2] = bin2bcd(t->time.tm_hour);
479 regs[3] = bin2bcd(t->time.tm_mday);
480
481 /* set ALARM2 to non-garbage */
482 regs[4] = 0;
483 regs[5] = 0;
484 regs[6] = 0;
485
486 /* disable alarms */
487 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
488 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
489
490 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
491 sizeof(regs));
492 if (ret) {
493 dev_err(dev, "can't set alarm time\n");
494 return ret;
495 }
496
497 /* optionally enable ALARM1 */
498 if (t->enabled) {
499 dev_dbg(dev, "alarm IRQ armed\n");
500 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
501 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
502 }
503
504 return 0;
505}
506
507static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
508{
509 struct ds1307 *ds1307 = dev_get_drvdata(dev);
510
511 if (!test_bit(HAS_ALARM, &ds1307->flags))
512 return -ENOTTY;
513
514 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
515 DS1337_BIT_A1IE,
516 enabled ? DS1337_BIT_A1IE : 0);
517}
518
519static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
520{
521 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
522 DS1307_TRICKLE_CHARGER_NO_DIODE;
523
Bastian Krause462eb732020-09-17 20:32:42 +0200524 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
525
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100526 switch (ohms) {
527 case 250:
528 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
529 break;
530 case 2000:
531 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
532 break;
533 case 4000:
534 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
535 break;
536 default:
537 dev_warn(ds1307->dev,
538 "Unsupported ohm value %u in dt\n", ohms);
539 return 0;
540 }
541 return setup;
542}
543
544static irqreturn_t rx8130_irq(int irq, void *dev_id)
545{
546 struct ds1307 *ds1307 = dev_id;
547 struct mutex *lock = &ds1307->rtc->ops_lock;
548 u8 ctl[3];
549 int ret;
550
551 mutex_lock(lock);
552
553 /* Read control registers. */
554 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
555 sizeof(ctl));
556 if (ret < 0)
557 goto out;
558 if (!(ctl[1] & RX8130_REG_FLAG_AF))
559 goto out;
560 ctl[1] &= ~RX8130_REG_FLAG_AF;
561 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
562
563 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
564 sizeof(ctl));
565 if (ret < 0)
566 goto out;
567
568 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
569
570out:
571 mutex_unlock(lock);
572
573 return IRQ_HANDLED;
574}
575
576static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
577{
578 struct ds1307 *ds1307 = dev_get_drvdata(dev);
579 u8 ald[3], ctl[3];
580 int ret;
581
582 if (!test_bit(HAS_ALARM, &ds1307->flags))
583 return -EINVAL;
584
585 /* Read alarm registers. */
586 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
587 sizeof(ald));
588 if (ret < 0)
589 return ret;
590
591 /* Read control registers. */
592 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
593 sizeof(ctl));
594 if (ret < 0)
595 return ret;
596
597 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
598 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
599
600 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
601 t->time.tm_sec = -1;
602 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
603 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
604 t->time.tm_wday = -1;
605 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
606 t->time.tm_mon = -1;
607 t->time.tm_year = -1;
608 t->time.tm_yday = -1;
609 t->time.tm_isdst = -1;
610
611 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
612 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
613 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
614
615 return 0;
616}
617
618static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
619{
620 struct ds1307 *ds1307 = dev_get_drvdata(dev);
621 u8 ald[3], ctl[3];
622 int ret;
623
624 if (!test_bit(HAS_ALARM, &ds1307->flags))
625 return -EINVAL;
626
627 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
628 "enabled=%d pending=%d\n", __func__,
629 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
630 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
631 t->enabled, t->pending);
632
633 /* Read control registers. */
634 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
635 sizeof(ctl));
636 if (ret < 0)
637 return ret;
638
Uwe Kleine-König3f929ca2019-01-25 15:35:58 +0100639 ctl[0] &= RX8130_REG_EXTENSION_WADA;
640 ctl[1] &= ~RX8130_REG_FLAG_AF;
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100641 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
642
643 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
644 sizeof(ctl));
645 if (ret < 0)
646 return ret;
647
648 /* Hardware alarm precision is 1 minute! */
649 ald[0] = bin2bcd(t->time.tm_min);
650 ald[1] = bin2bcd(t->time.tm_hour);
651 ald[2] = bin2bcd(t->time.tm_mday);
652
653 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
654 sizeof(ald));
655 if (ret < 0)
656 return ret;
657
658 if (!t->enabled)
659 return 0;
660
661 ctl[2] |= RX8130_REG_CONTROL0_AIE;
662
Uwe Kleine-König3f929ca2019-01-25 15:35:58 +0100663 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
Uwe Kleine-Königd0e3f612019-01-25 15:35:55 +0100664}
665
666static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
667{
668 struct ds1307 *ds1307 = dev_get_drvdata(dev);
669 int ret, reg;
670
671 if (!test_bit(HAS_ALARM, &ds1307->flags))
672 return -EINVAL;
673
674 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
675 if (ret < 0)
676 return ret;
677
678 if (enabled)
679 reg |= RX8130_REG_CONTROL0_AIE;
680 else
681 reg &= ~RX8130_REG_CONTROL0_AIE;
682
683 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
684}
685
686static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
687{
688 struct ds1307 *ds1307 = dev_id;
689 struct mutex *lock = &ds1307->rtc->ops_lock;
690 int reg, ret;
691
692 mutex_lock(lock);
693
694 /* Check and clear alarm 0 interrupt flag. */
695 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
696 if (ret)
697 goto out;
698 if (!(reg & MCP794XX_BIT_ALMX_IF))
699 goto out;
700 reg &= ~MCP794XX_BIT_ALMX_IF;
701 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
702 if (ret)
703 goto out;
704
705 /* Disable alarm 0. */
706 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
707 MCP794XX_BIT_ALM0_EN, 0);
708 if (ret)
709 goto out;
710
711 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
712
713out:
714 mutex_unlock(lock);
715
716 return IRQ_HANDLED;
717}
718
719static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
720{
721 struct ds1307 *ds1307 = dev_get_drvdata(dev);
722 u8 regs[10];
723 int ret;
724
725 if (!test_bit(HAS_ALARM, &ds1307->flags))
726 return -EINVAL;
727
728 /* Read control and alarm 0 registers. */
729 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
730 sizeof(regs));
731 if (ret)
732 return ret;
733
734 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
735
736 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
737 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
738 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
739 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
740 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
741 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
742 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
743 t->time.tm_year = -1;
744 t->time.tm_yday = -1;
745 t->time.tm_isdst = -1;
746
747 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
748 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
749 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
750 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
751 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
752 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
753 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
754
755 return 0;
756}
757
758/*
759 * We may have a random RTC weekday, therefore calculate alarm weekday based
760 * on current weekday we read from the RTC timekeeping regs
761 */
762static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
763{
764 struct rtc_time tm_now;
765 int days_now, days_alarm, ret;
766
767 ret = ds1307_get_time(dev, &tm_now);
768 if (ret)
769 return ret;
770
771 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
772 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
773
774 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
775}
776
777static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
778{
779 struct ds1307 *ds1307 = dev_get_drvdata(dev);
780 unsigned char regs[10];
781 int wday, ret;
782
783 if (!test_bit(HAS_ALARM, &ds1307->flags))
784 return -EINVAL;
785
786 wday = mcp794xx_alm_weekday(dev, &t->time);
787 if (wday < 0)
788 return wday;
789
790 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
791 "enabled=%d pending=%d\n", __func__,
792 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
793 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
794 t->enabled, t->pending);
795
796 /* Read control and alarm 0 registers. */
797 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
798 sizeof(regs));
799 if (ret)
800 return ret;
801
802 /* Set alarm 0, using 24-hour and day-of-month modes. */
803 regs[3] = bin2bcd(t->time.tm_sec);
804 regs[4] = bin2bcd(t->time.tm_min);
805 regs[5] = bin2bcd(t->time.tm_hour);
806 regs[6] = wday;
807 regs[7] = bin2bcd(t->time.tm_mday);
808 regs[8] = bin2bcd(t->time.tm_mon + 1);
809
810 /* Clear the alarm 0 interrupt flag. */
811 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
812 /* Set alarm match: second, minute, hour, day, date, month. */
813 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
814 /* Disable interrupt. We will not enable until completely programmed */
815 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
816
817 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
818 sizeof(regs));
819 if (ret)
820 return ret;
821
822 if (!t->enabled)
823 return 0;
824 regs[0] |= MCP794XX_BIT_ALM0_EN;
825 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
826}
827
828static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
829{
830 struct ds1307 *ds1307 = dev_get_drvdata(dev);
831
832 if (!test_bit(HAS_ALARM, &ds1307->flags))
833 return -EINVAL;
834
835 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
836 MCP794XX_BIT_ALM0_EN,
837 enabled ? MCP794XX_BIT_ALM0_EN : 0);
838}
839
840static int m41txx_rtc_read_offset(struct device *dev, long *offset)
841{
842 struct ds1307 *ds1307 = dev_get_drvdata(dev);
843 unsigned int ctrl_reg;
844 u8 val;
845
846 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
847
848 val = ctrl_reg & M41TXX_M_CALIBRATION;
849
850 /* check if positive */
851 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
852 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
853 else
854 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
855
856 return 0;
857}
858
859static int m41txx_rtc_set_offset(struct device *dev, long offset)
860{
861 struct ds1307 *ds1307 = dev_get_drvdata(dev);
862 unsigned int ctrl_reg;
863
864 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
865 return -ERANGE;
866
867 if (offset >= 0) {
868 ctrl_reg = DIV_ROUND_CLOSEST(offset,
869 M41TXX_POS_OFFSET_STEP_PPB);
870 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
871 } else {
872 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
873 M41TXX_NEG_OFFSET_STEP_PPB);
874 }
875
876 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
877 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
878 ctrl_reg);
879}
Matti Vaittinen33b04b72014-10-13 15:52:48 -0700880
Chris Packhamfd90d482020-03-30 15:55:00 +1300881#ifdef CONFIG_WATCHDOG_CORE
882static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
883{
884 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
885 u8 regs[2];
886 int ret;
887
888 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
889 DS1388_BIT_WF, 0);
890 if (ret)
891 return ret;
892
893 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
894 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
895 if (ret)
896 return ret;
897
898 /*
899 * watchdog timeouts are measured in seconds. So ignore hundredths of
900 * seconds field.
901 */
902 regs[0] = 0;
903 regs[1] = bin2bcd(wdt_dev->timeout);
904
905 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
906 sizeof(regs));
907 if (ret)
908 return ret;
909
910 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
911 DS1388_BIT_WDE | DS1388_BIT_RST,
912 DS1388_BIT_WDE | DS1388_BIT_RST);
913}
914
915static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
916{
917 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
918
919 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
920 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
921}
922
923static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
924{
925 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
926 u8 regs[2];
927
928 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
929 sizeof(regs));
930}
931
932static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
933 unsigned int val)
934{
935 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
936 u8 regs[2];
937
938 wdt_dev->timeout = val;
939 regs[0] = 0;
940 regs[1] = bin2bcd(wdt_dev->timeout);
941
942 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
943 sizeof(regs));
944}
945#endif
946
Heiner Kallweit1efb98b2017-07-12 07:49:44 +0200947static const struct rtc_class_ops rx8130_rtc_ops = {
948 .read_time = ds1307_get_time,
949 .set_time = ds1307_set_time,
950 .read_alarm = rx8130_read_alarm,
951 .set_alarm = rx8130_set_alarm,
952 .alarm_irq_enable = rx8130_alarm_irq_enable,
953};
954
955static const struct rtc_class_ops mcp794xx_rtc_ops = {
956 .read_time = ds1307_get_time,
957 .set_time = ds1307_set_time,
958 .read_alarm = mcp794xx_read_alarm,
959 .set_alarm = mcp794xx_set_alarm,
960 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
961};
Matti Vaittinen33b04b72014-10-13 15:52:48 -0700962
Giulio Benetti79230ff2018-07-25 19:26:04 +0200963static const struct rtc_class_ops m41txx_rtc_ops = {
964 .read_time = ds1307_get_time,
965 .set_time = ds1307_set_time,
966 .read_alarm = ds1337_read_alarm,
967 .set_alarm = ds1337_set_alarm,
968 .alarm_irq_enable = ds1307_alarm_irq_enable,
969 .read_offset = m41txx_rtc_read_offset,
970 .set_offset = m41txx_rtc_set_offset,
971};
972
Heiner Kallweit7624df42017-07-12 07:49:33 +0200973static const struct chip_desc chips[last_ds_type] = {
Wolfram Sang32d322b2012-03-23 15:02:36 -0700974 [ds_1307] = {
Austin Boyle9eab0a72012-03-23 15:02:38 -0700975 .nvram_offset = 8,
976 .nvram_size = 56,
Wolfram Sang32d322b2012-03-23 15:02:36 -0700977 },
Sean Nyekjaer300a7732017-06-08 12:36:54 +0200978 [ds_1308] = {
979 .nvram_offset = 8,
980 .nvram_size = 56,
981 },
Wolfram Sang32d322b2012-03-23 15:02:36 -0700982 [ds_1337] = {
983 .alarm = 1,
Heiner Kallweite48585d2017-06-05 17:57:33 +0200984 .century_reg = DS1307_REG_MONTH,
985 .century_bit = DS1337_BIT_CENTURY,
Wolfram Sang32d322b2012-03-23 15:02:36 -0700986 },
987 [ds_1338] = {
Austin Boyle9eab0a72012-03-23 15:02:38 -0700988 .nvram_offset = 8,
989 .nvram_size = 56,
Wolfram Sang32d322b2012-03-23 15:02:36 -0700990 },
991 [ds_1339] = {
992 .alarm = 1,
Heiner Kallweite48585d2017-06-05 17:57:33 +0200993 .century_reg = DS1307_REG_MONTH,
994 .century_bit = DS1337_BIT_CENTURY,
Heiner Kallweit0b6ee802017-07-12 07:49:22 +0200995 .bbsqi_bit = DS1339_BIT_BBSQI,
Wolfram Sangeb86c302012-05-29 15:07:38 -0700996 .trickle_charger_reg = 0x10,
Matti Vaittinen33b04b72014-10-13 15:52:48 -0700997 .do_trickle_setup = &do_trickle_setup_ds1339,
Bastian Krause1b5b6af2020-09-17 20:32:43 +0200998 .requires_trickle_resistor = true,
Bastian Krause95a74cb2020-09-17 20:32:44 +0200999 .charge_default = true,
Wolfram Sangeb86c302012-05-29 15:07:38 -07001000 },
1001 [ds_1340] = {
Heiner Kallweite48585d2017-06-05 17:57:33 +02001002 .century_reg = DS1307_REG_HOUR,
1003 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1004 .century_bit = DS1340_BIT_CENTURY,
Andrea Greco51ed73eb2018-04-20 11:34:02 +02001005 .do_trickle_setup = &do_trickle_setup_ds1339,
Wolfram Sangeb86c302012-05-29 15:07:38 -07001006 .trickle_charger_reg = 0x08,
Bastian Krause1b5b6af2020-09-17 20:32:43 +02001007 .requires_trickle_resistor = true,
Bastian Krause95a74cb2020-09-17 20:32:44 +02001008 .charge_default = true,
Wolfram Sangeb86c302012-05-29 15:07:38 -07001009 },
Nikita Yushchenko0759c882017-08-24 09:32:11 +03001010 [ds_1341] = {
1011 .century_reg = DS1307_REG_MONTH,
1012 .century_bit = DS1337_BIT_CENTURY,
1013 },
Wolfram Sangeb86c302012-05-29 15:07:38 -07001014 [ds_1388] = {
Heiner Kallweite5531702017-07-12 07:49:47 +02001015 .offset = 1,
Wolfram Sangeb86c302012-05-29 15:07:38 -07001016 .trickle_charger_reg = 0x0a,
Wolfram Sang32d322b2012-03-23 15:02:36 -07001017 },
1018 [ds_3231] = {
1019 .alarm = 1,
Heiner Kallweite48585d2017-06-05 17:57:33 +02001020 .century_reg = DS1307_REG_MONTH,
1021 .century_bit = DS1337_BIT_CENTURY,
Heiner Kallweit0b6ee802017-07-12 07:49:22 +02001022 .bbsqi_bit = DS3231_BIT_BBSQW,
Wolfram Sang32d322b2012-03-23 15:02:36 -07001023 },
Marek Vasutee0981b2017-06-18 22:55:28 +02001024 [rx_8130] = {
1025 .alarm = 1,
1026 /* this is battery backed SRAM */
1027 .nvram_offset = 0x20,
1028 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
Heiner Kallweite5531702017-07-12 07:49:47 +02001029 .offset = 0x10,
Heiner Kallweit45947122017-07-12 07:49:41 +02001030 .irq_handler = rx8130_irq,
Heiner Kallweit1efb98b2017-07-12 07:49:44 +02001031 .rtc_ops = &rx8130_rtc_ops,
Marek Vasutee0981b2017-06-18 22:55:28 +02001032 },
Giulio Benetti79230ff2018-07-25 19:26:04 +02001033 [m41t0] = {
1034 .rtc_ops = &m41txx_rtc_ops,
1035 },
1036 [m41t00] = {
1037 .rtc_ops = &m41txx_rtc_ops,
1038 },
Giulio Benetti7e580762018-05-16 23:08:40 +02001039 [m41t11] = {
1040 /* this is battery backed SRAM */
1041 .nvram_offset = 8,
1042 .nvram_size = 56,
Giulio Benetti79230ff2018-07-25 19:26:04 +02001043 .rtc_ops = &m41txx_rtc_ops,
Giulio Benetti7e580762018-05-16 23:08:40 +02001044 },
Tomas Novotnyf4199f82014-12-10 15:53:57 -08001045 [mcp794xx] = {
Simon Guinot1d1945d2014-04-03 14:49:55 -07001046 .alarm = 1,
Austin Boyle9eab0a72012-03-23 15:02:38 -07001047 /* this is battery backed SRAM */
1048 .nvram_offset = 0x20,
1049 .nvram_size = 0x40,
Heiner Kallweit45947122017-07-12 07:49:41 +02001050 .irq_handler = mcp794xx_irq,
Heiner Kallweit1efb98b2017-07-12 07:49:44 +02001051 .rtc_ops = &mcp794xx_rtc_ops,
Austin Boyle9eab0a72012-03-23 15:02:38 -07001052 },
Wolfram Sang32d322b2012-03-23 15:02:36 -07001053};
David Brownell045e0e82007-07-17 04:04:55 -07001054
Jean Delvare3760f732008-04-29 23:11:40 +02001055static const struct i2c_device_id ds1307_id[] = {
1056 { "ds1307", ds_1307 },
Sean Nyekjaer300a7732017-06-08 12:36:54 +02001057 { "ds1308", ds_1308 },
Jean Delvare3760f732008-04-29 23:11:40 +02001058 { "ds1337", ds_1337 },
1059 { "ds1338", ds_1338 },
1060 { "ds1339", ds_1339 },
Joakim Tjernlund33df2ee2009-06-17 16:26:08 -07001061 { "ds1388", ds_1388 },
Jean Delvare3760f732008-04-29 23:11:40 +02001062 { "ds1340", ds_1340 },
Nikita Yushchenko0759c882017-08-24 09:32:11 +03001063 { "ds1341", ds_1341 },
Wolfram Sang97f902b2009-06-17 16:26:10 -07001064 { "ds3231", ds_3231 },
Stefan Agner8566f702017-03-23 16:54:57 -07001065 { "m41t0", m41t0 },
Jean Delvare3760f732008-04-29 23:11:40 +02001066 { "m41t00", m41t00 },
Giulio Benetti7e580762018-05-16 23:08:40 +02001067 { "m41t11", m41t11 },
Tomas Novotnyf4199f82014-12-10 15:53:57 -08001068 { "mcp7940x", mcp794xx },
1069 { "mcp7941x", mcp794xx },
Priyanka Jain31c17712011-06-27 16:18:04 -07001070 { "pt7c4338", ds_1307 },
Matthias Fuchsa2166852009-03-31 15:24:58 -07001071 { "rx8025", rx_8025 },
Alexandre Belloni78aaa062016-07-13 02:36:41 +02001072 { "isl12057", ds_1337 },
Marek Vasutee0981b2017-06-18 22:55:28 +02001073 { "rx8130", rx_8130 },
Jean Delvare3760f732008-04-29 23:11:40 +02001074 { }
1075};
1076MODULE_DEVICE_TABLE(i2c, ds1307_id);
David Brownell1abb0dc2006-06-25 05:48:17 -07001077
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001078#ifdef CONFIG_OF
1079static const struct of_device_id ds1307_of_match[] = {
1080 {
1081 .compatible = "dallas,ds1307",
1082 .data = (void *)ds_1307
1083 },
1084 {
Sean Nyekjaer300a7732017-06-08 12:36:54 +02001085 .compatible = "dallas,ds1308",
1086 .data = (void *)ds_1308
1087 },
1088 {
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001089 .compatible = "dallas,ds1337",
1090 .data = (void *)ds_1337
1091 },
1092 {
1093 .compatible = "dallas,ds1338",
1094 .data = (void *)ds_1338
1095 },
1096 {
1097 .compatible = "dallas,ds1339",
1098 .data = (void *)ds_1339
1099 },
1100 {
1101 .compatible = "dallas,ds1388",
1102 .data = (void *)ds_1388
1103 },
1104 {
1105 .compatible = "dallas,ds1340",
1106 .data = (void *)ds_1340
1107 },
1108 {
Nikita Yushchenko0759c882017-08-24 09:32:11 +03001109 .compatible = "dallas,ds1341",
1110 .data = (void *)ds_1341
1111 },
1112 {
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001113 .compatible = "maxim,ds3231",
1114 .data = (void *)ds_3231
1115 },
1116 {
Alexandre Bellonidb2f8142017-04-08 17:22:02 +02001117 .compatible = "st,m41t0",
Giulio Benetti146a5522018-05-16 23:08:39 +02001118 .data = (void *)m41t0
Alexandre Bellonidb2f8142017-04-08 17:22:02 +02001119 },
1120 {
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001121 .compatible = "st,m41t00",
1122 .data = (void *)m41t00
1123 },
1124 {
Giulio Benetti7e580762018-05-16 23:08:40 +02001125 .compatible = "st,m41t11",
1126 .data = (void *)m41t11
1127 },
1128 {
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001129 .compatible = "microchip,mcp7940x",
1130 .data = (void *)mcp794xx
1131 },
1132 {
1133 .compatible = "microchip,mcp7941x",
1134 .data = (void *)mcp794xx
1135 },
1136 {
1137 .compatible = "pericom,pt7c4338",
1138 .data = (void *)ds_1307
1139 },
1140 {
1141 .compatible = "epson,rx8025",
1142 .data = (void *)rx_8025
1143 },
1144 {
1145 .compatible = "isil,isl12057",
1146 .data = (void *)ds_1337
1147 },
Bastian Stender47dd4722017-10-17 14:46:07 +02001148 {
1149 .compatible = "epson,rx8130",
1150 .data = (void *)rx_8130
1151 },
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001152 { }
1153};
1154MODULE_DEVICE_TABLE(of, ds1307_of_match);
1155#endif
1156
Tin Huynh9c19b892016-11-30 09:57:31 +07001157#ifdef CONFIG_ACPI
1158static const struct acpi_device_id ds1307_acpi_ids[] = {
1159 { .id = "DS1307", .driver_data = ds_1307 },
Sean Nyekjaer300a7732017-06-08 12:36:54 +02001160 { .id = "DS1308", .driver_data = ds_1308 },
Tin Huynh9c19b892016-11-30 09:57:31 +07001161 { .id = "DS1337", .driver_data = ds_1337 },
1162 { .id = "DS1338", .driver_data = ds_1338 },
1163 { .id = "DS1339", .driver_data = ds_1339 },
1164 { .id = "DS1388", .driver_data = ds_1388 },
1165 { .id = "DS1340", .driver_data = ds_1340 },
Nikita Yushchenko0759c882017-08-24 09:32:11 +03001166 { .id = "DS1341", .driver_data = ds_1341 },
Tin Huynh9c19b892016-11-30 09:57:31 +07001167 { .id = "DS3231", .driver_data = ds_3231 },
Stefan Agner8566f702017-03-23 16:54:57 -07001168 { .id = "M41T0", .driver_data = m41t0 },
Tin Huynh9c19b892016-11-30 09:57:31 +07001169 { .id = "M41T00", .driver_data = m41t00 },
Giulio Benetti7e580762018-05-16 23:08:40 +02001170 { .id = "M41T11", .driver_data = m41t11 },
Tin Huynh9c19b892016-11-30 09:57:31 +07001171 { .id = "MCP7940X", .driver_data = mcp794xx },
1172 { .id = "MCP7941X", .driver_data = mcp794xx },
1173 { .id = "PT7C4338", .driver_data = ds_1307 },
1174 { .id = "RX8025", .driver_data = rx_8025 },
1175 { .id = "ISL12057", .driver_data = ds_1337 },
Bastian Stender47dd4722017-10-17 14:46:07 +02001176 { .id = "RX8130", .driver_data = rx_8130 },
Tin Huynh9c19b892016-11-30 09:57:31 +07001177 { }
1178};
1179MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1180#endif
1181
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001182/*
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001183 * The ds1337 and ds1339 both have two alarms, but we only use the first
1184 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1185 * signal; ds1339 chips have only one alarm signal.
1186 */
Felipe Balbi2fb07a12015-06-23 11:15:10 -05001187static irqreturn_t ds1307_irq(int irq, void *dev_id)
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001188{
Heiner Kallweit11e58902017-03-10 18:52:34 +01001189 struct ds1307 *ds1307 = dev_id;
Felipe Balbi2fb07a12015-06-23 11:15:10 -05001190 struct mutex *lock = &ds1307->rtc->ops_lock;
Heiner Kallweit078f3f62017-06-05 17:57:29 +02001191 int stat, ret;
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001192
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001193 mutex_lock(lock);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001194 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1195 if (ret)
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001196 goto out;
1197
1198 if (stat & DS1337_BIT_A1I) {
1199 stat &= ~DS1337_BIT_A1I;
Heiner Kallweit11e58902017-03-10 18:52:34 +01001200 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001201
Heiner Kallweit078f3f62017-06-05 17:57:29 +02001202 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1203 DS1337_BIT_A1IE, 0);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001204 if (ret)
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001205 goto out;
1206
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001207 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001208 }
1209
1210out:
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001211 mutex_unlock(lock);
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001212
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001213 return IRQ_HANDLED;
1214}
1215
1216/*----------------------------------------------------------------------*/
1217
David Brownellff8371a2006-09-30 23:28:17 -07001218static const struct rtc_class_ops ds13xx_rtc_ops = {
David Brownell1abb0dc2006-06-25 05:48:17 -07001219 .read_time = ds1307_get_time,
1220 .set_time = ds1307_set_time,
Jüri Reitel74d88eb2009-01-07 18:07:16 -08001221 .read_alarm = ds1337_read_alarm,
1222 .set_alarm = ds1337_set_alarm,
John Stultz16380c12011-02-02 17:02:41 -08001223 .alarm_irq_enable = ds1307_alarm_irq_enable,
David Brownell1abb0dc2006-06-25 05:48:17 -07001224};
1225
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001226static ssize_t frequency_test_store(struct device *dev,
1227 struct device_attribute *attr,
1228 const char *buf, size_t count)
Giulio Benettib41c23e2018-07-25 19:26:05 +02001229{
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001230 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
Giulio Benettib41c23e2018-07-25 19:26:05 +02001231 bool freq_test_en;
1232 int ret;
1233
1234 ret = kstrtobool(buf, &freq_test_en);
1235 if (ret) {
1236 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1237 return ret;
1238 }
1239
1240 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1241 freq_test_en ? M41TXX_BIT_FT : 0);
1242
1243 return count;
1244}
1245
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001246static ssize_t frequency_test_show(struct device *dev,
1247 struct device_attribute *attr,
1248 char *buf)
Giulio Benettib41c23e2018-07-25 19:26:05 +02001249{
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001250 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
Giulio Benettib41c23e2018-07-25 19:26:05 +02001251 unsigned int ctrl_reg;
1252
1253 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1254
1255 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1256 "off\n");
1257}
1258
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001259static DEVICE_ATTR_RW(frequency_test);
Giulio Benettib41c23e2018-07-25 19:26:05 +02001260
1261static struct attribute *rtc_freq_test_attrs[] = {
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001262 &dev_attr_frequency_test.attr,
Giulio Benettib41c23e2018-07-25 19:26:05 +02001263 NULL,
1264};
1265
1266static const struct attribute_group rtc_freq_test_attr_group = {
1267 .attrs = rtc_freq_test_attrs,
1268};
1269
Giulio Benettib41c23e2018-07-25 19:26:05 +02001270static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1271{
1272 int err;
1273
1274 switch (ds1307->type) {
1275 case m41t0:
1276 case m41t00:
1277 case m41t11:
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001278 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1279 if (err)
Giulio Benettib41c23e2018-07-25 19:26:05 +02001280 return err;
Giulio Benettib41c23e2018-07-25 19:26:05 +02001281 break;
1282 default:
1283 break;
1284 }
1285
1286 return 0;
1287}
1288
Simon Guinot1d1945d2014-04-03 14:49:55 -07001289/*----------------------------------------------------------------------*/
1290
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001291static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1292 size_t bytes)
David Brownell682d73f2007-11-14 16:58:32 -08001293{
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001294 struct ds1307 *ds1307 = priv;
Heiner Kallweit969fa072017-07-12 07:49:54 +02001295 const struct chip_desc *chip = &chips[ds1307->type];
David Brownell682d73f2007-11-14 16:58:32 -08001296
Heiner Kallweit969fa072017-07-12 07:49:54 +02001297 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001298 val, bytes);
David Brownell682d73f2007-11-14 16:58:32 -08001299}
1300
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001301static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1302 size_t bytes)
David Brownell682d73f2007-11-14 16:58:32 -08001303{
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001304 struct ds1307 *ds1307 = priv;
Heiner Kallweit969fa072017-07-12 07:49:54 +02001305 const struct chip_desc *chip = &chips[ds1307->type];
David Brownell682d73f2007-11-14 16:58:32 -08001306
Heiner Kallweit969fa072017-07-12 07:49:54 +02001307 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
Alexandre Belloniabc925f2017-07-06 11:42:07 +02001308 val, bytes);
David Brownell682d73f2007-11-14 16:58:32 -08001309}
1310
David Brownell682d73f2007-11-14 16:58:32 -08001311/*----------------------------------------------------------------------*/
1312
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001313static u8 ds1307_trickle_init(struct ds1307 *ds1307,
Heiner Kallweit7624df42017-07-12 07:49:33 +02001314 const struct chip_desc *chip)
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001315{
Alexandre Belloni57ec2d92017-09-04 22:46:04 +02001316 u32 ohms;
Bastian Krause95a74cb2020-09-17 20:32:44 +02001317 bool diode = chip->charge_default;
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001318
1319 if (!chip->do_trickle_setup)
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001320 return 0;
1321
Heiner Kallweit11e58902017-03-10 18:52:34 +01001322 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
Bastian Krause1b5b6af2020-09-17 20:32:43 +02001323 &ohms) && chip->requires_trickle_resistor)
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001324 return 0;
1325
Heiner Kallweit11e58902017-03-10 18:52:34 +01001326 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001327 diode = false;
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001328
1329 return chip->do_trickle_setup(ds1307, ohms, diode);
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001330}
1331
Akinobu Mita445c0202016-01-25 00:22:16 +09001332/*----------------------------------------------------------------------*/
1333
Heiner Kallweit6b583a62017-09-27 22:41:26 +02001334#if IS_REACHABLE(CONFIG_HWMON)
Akinobu Mita445c0202016-01-25 00:22:16 +09001335
1336/*
1337 * Temperature sensor support for ds3231 devices.
1338 */
1339
1340#define DS3231_REG_TEMPERATURE 0x11
1341
1342/*
1343 * A user-initiated temperature conversion is not started by this function,
1344 * so the temperature is updated once every 64 seconds.
1345 */
Zhuang Yuyao9a3dce62016-04-18 09:21:42 +09001346static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
Akinobu Mita445c0202016-01-25 00:22:16 +09001347{
1348 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1349 u8 temp_buf[2];
1350 s16 temp;
1351 int ret;
1352
Heiner Kallweit11e58902017-03-10 18:52:34 +01001353 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1354 temp_buf, sizeof(temp_buf));
1355 if (ret)
Akinobu Mita445c0202016-01-25 00:22:16 +09001356 return ret;
Akinobu Mita445c0202016-01-25 00:22:16 +09001357 /*
1358 * Temperature is represented as a 10-bit code with a resolution of
1359 * 0.25 degree celsius and encoded in two's complement format.
1360 */
1361 temp = (temp_buf[0] << 8) | temp_buf[1];
1362 temp >>= 6;
1363 *mC = temp * 250;
1364
1365 return 0;
1366}
1367
1368static ssize_t ds3231_hwmon_show_temp(struct device *dev,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001369 struct device_attribute *attr, char *buf)
Akinobu Mita445c0202016-01-25 00:22:16 +09001370{
1371 int ret;
Zhuang Yuyao9a3dce62016-04-18 09:21:42 +09001372 s32 temp;
Akinobu Mita445c0202016-01-25 00:22:16 +09001373
1374 ret = ds3231_hwmon_read_temp(dev, &temp);
1375 if (ret)
1376 return ret;
1377
1378 return sprintf(buf, "%d\n", temp);
1379}
Alexandre Bellonib4be2712017-09-04 22:46:08 +02001380static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001381 NULL, 0);
Akinobu Mita445c0202016-01-25 00:22:16 +09001382
1383static struct attribute *ds3231_hwmon_attrs[] = {
1384 &sensor_dev_attr_temp1_input.dev_attr.attr,
1385 NULL,
1386};
1387ATTRIBUTE_GROUPS(ds3231_hwmon);
1388
1389static void ds1307_hwmon_register(struct ds1307 *ds1307)
1390{
1391 struct device *dev;
1392
1393 if (ds1307->type != ds_3231)
1394 return;
1395
Heiner Kallweit11e58902017-03-10 18:52:34 +01001396 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001397 ds1307,
1398 ds3231_hwmon_groups);
Akinobu Mita445c0202016-01-25 00:22:16 +09001399 if (IS_ERR(dev)) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001400 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1401 PTR_ERR(dev));
Akinobu Mita445c0202016-01-25 00:22:16 +09001402 }
1403}
1404
1405#else
1406
1407static void ds1307_hwmon_register(struct ds1307 *ds1307)
1408{
1409}
1410
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001411#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1412
1413/*----------------------------------------------------------------------*/
1414
1415/*
1416 * Square-wave output support for DS3231
1417 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1418 */
1419#ifdef CONFIG_COMMON_CLK
1420
1421enum {
1422 DS3231_CLK_SQW = 0,
1423 DS3231_CLK_32KHZ,
1424};
1425
1426#define clk_sqw_to_ds1307(clk) \
1427 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1428#define clk_32khz_to_ds1307(clk) \
1429 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1430
1431static int ds3231_clk_sqw_rates[] = {
1432 1,
1433 1024,
1434 4096,
1435 8192,
1436};
1437
1438static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1439{
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001440 struct mutex *lock = &ds1307->rtc->ops_lock;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001441 int ret;
1442
1443 mutex_lock(lock);
Heiner Kallweit078f3f62017-06-05 17:57:29 +02001444 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1445 mask, value);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001446 mutex_unlock(lock);
1447
1448 return ret;
1449}
1450
1451static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1452 unsigned long parent_rate)
1453{
1454 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001455 int control, ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001456 int rate_sel = 0;
1457
Heiner Kallweit11e58902017-03-10 18:52:34 +01001458 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1459 if (ret)
1460 return ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001461 if (control & DS1337_BIT_RS1)
1462 rate_sel += 1;
1463 if (control & DS1337_BIT_RS2)
1464 rate_sel += 2;
1465
1466 return ds3231_clk_sqw_rates[rate_sel];
1467}
1468
1469static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001470 unsigned long *prate)
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001471{
1472 int i;
1473
1474 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1475 if (ds3231_clk_sqw_rates[i] <= rate)
1476 return ds3231_clk_sqw_rates[i];
1477 }
1478
1479 return 0;
1480}
1481
1482static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001483 unsigned long parent_rate)
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001484{
1485 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1486 int control = 0;
1487 int rate_sel;
1488
1489 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1490 rate_sel++) {
1491 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1492 break;
1493 }
1494
1495 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1496 return -EINVAL;
1497
1498 if (rate_sel & 1)
1499 control |= DS1337_BIT_RS1;
1500 if (rate_sel & 2)
1501 control |= DS1337_BIT_RS2;
1502
1503 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1504 control);
1505}
1506
1507static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1508{
1509 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1510
1511 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1512}
1513
1514static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1515{
1516 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1517
1518 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1519}
1520
1521static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1522{
1523 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001524 int control, ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001525
Heiner Kallweit11e58902017-03-10 18:52:34 +01001526 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1527 if (ret)
1528 return ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001529
1530 return !(control & DS1337_BIT_INTCN);
1531}
1532
1533static const struct clk_ops ds3231_clk_sqw_ops = {
1534 .prepare = ds3231_clk_sqw_prepare,
1535 .unprepare = ds3231_clk_sqw_unprepare,
1536 .is_prepared = ds3231_clk_sqw_is_prepared,
1537 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1538 .round_rate = ds3231_clk_sqw_round_rate,
1539 .set_rate = ds3231_clk_sqw_set_rate,
1540};
1541
1542static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001543 unsigned long parent_rate)
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001544{
1545 return 32768;
1546}
1547
1548static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1549{
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001550 struct mutex *lock = &ds1307->rtc->ops_lock;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001551 int ret;
1552
1553 mutex_lock(lock);
Heiner Kallweit078f3f62017-06-05 17:57:29 +02001554 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1555 DS3231_BIT_EN32KHZ,
1556 enable ? DS3231_BIT_EN32KHZ : 0);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001557 mutex_unlock(lock);
1558
1559 return ret;
1560}
1561
1562static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1563{
1564 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1565
1566 return ds3231_clk_32khz_control(ds1307, true);
1567}
1568
1569static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1570{
1571 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1572
1573 ds3231_clk_32khz_control(ds1307, false);
1574}
1575
1576static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1577{
1578 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001579 int status, ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001580
Heiner Kallweit11e58902017-03-10 18:52:34 +01001581 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1582 if (ret)
1583 return ret;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001584
1585 return !!(status & DS3231_BIT_EN32KHZ);
1586}
1587
1588static const struct clk_ops ds3231_clk_32khz_ops = {
1589 .prepare = ds3231_clk_32khz_prepare,
1590 .unprepare = ds3231_clk_32khz_unprepare,
1591 .is_prepared = ds3231_clk_32khz_is_prepared,
1592 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1593};
1594
1595static struct clk_init_data ds3231_clks_init[] = {
1596 [DS3231_CLK_SQW] = {
1597 .name = "ds3231_clk_sqw",
1598 .ops = &ds3231_clk_sqw_ops,
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001599 },
1600 [DS3231_CLK_32KHZ] = {
1601 .name = "ds3231_clk_32khz",
1602 .ops = &ds3231_clk_32khz_ops,
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001603 },
1604};
1605
1606static int ds3231_clks_register(struct ds1307 *ds1307)
1607{
Heiner Kallweit11e58902017-03-10 18:52:34 +01001608 struct device_node *node = ds1307->dev->of_node;
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001609 struct clk_onecell_data *onecell;
1610 int i;
1611
Heiner Kallweit11e58902017-03-10 18:52:34 +01001612 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001613 if (!onecell)
1614 return -ENOMEM;
1615
1616 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001617 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1618 sizeof(onecell->clks[0]), GFP_KERNEL);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001619 if (!onecell->clks)
1620 return -ENOMEM;
1621
1622 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1623 struct clk_init_data init = ds3231_clks_init[i];
1624
1625 /*
1626 * Interrupt signal due to alarm conditions and square-wave
1627 * output share same pin, so don't initialize both.
1628 */
1629 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1630 continue;
1631
1632 /* optional override of the clockname */
1633 of_property_read_string_index(node, "clock-output-names", i,
Alexandre Belloni4057a662017-09-04 22:46:06 +02001634 &init.name);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001635 ds1307->clks[i].init = &init;
1636
Heiner Kallweit11e58902017-03-10 18:52:34 +01001637 onecell->clks[i] = devm_clk_register(ds1307->dev,
1638 &ds1307->clks[i]);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001639 if (IS_ERR(onecell->clks[i]))
1640 return PTR_ERR(onecell->clks[i]);
1641 }
1642
1643 if (!node)
1644 return 0;
1645
1646 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1647
1648 return 0;
1649}
1650
1651static void ds1307_clks_register(struct ds1307 *ds1307)
1652{
1653 int ret;
1654
1655 if (ds1307->type != ds_3231)
1656 return;
1657
1658 ret = ds3231_clks_register(ds1307);
1659 if (ret) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001660 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1661 ret);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09001662 }
1663}
1664
1665#else
1666
1667static void ds1307_clks_register(struct ds1307 *ds1307)
1668{
1669}
1670
1671#endif /* CONFIG_COMMON_CLK */
Akinobu Mita445c0202016-01-25 00:22:16 +09001672
Chris Packhamfd90d482020-03-30 15:55:00 +13001673#ifdef CONFIG_WATCHDOG_CORE
1674static const struct watchdog_info ds1388_wdt_info = {
1675 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1676 .identity = "DS1388 watchdog",
1677};
1678
1679static const struct watchdog_ops ds1388_wdt_ops = {
1680 .owner = THIS_MODULE,
1681 .start = ds1388_wdt_start,
1682 .stop = ds1388_wdt_stop,
1683 .ping = ds1388_wdt_ping,
1684 .set_timeout = ds1388_wdt_set_timeout,
1685
1686};
1687
1688static void ds1307_wdt_register(struct ds1307 *ds1307)
1689{
1690 struct watchdog_device *wdt;
Chris Packham9bf13062020-07-27 15:46:14 +12001691 int err;
1692 int val;
Chris Packhamfd90d482020-03-30 15:55:00 +13001693
1694 if (ds1307->type != ds_1388)
1695 return;
1696
1697 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
Colin Ian King1821b792020-04-03 12:04:37 +01001698 if (!wdt)
1699 return;
Chris Packhamfd90d482020-03-30 15:55:00 +13001700
Chris Packham9bf13062020-07-27 15:46:14 +12001701 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1702 if (!err && val & DS1388_BIT_WF)
1703 wdt->bootstatus = WDIOF_CARDRESET;
1704
Chris Packhamfd90d482020-03-30 15:55:00 +13001705 wdt->info = &ds1388_wdt_info;
1706 wdt->ops = &ds1388_wdt_ops;
1707 wdt->timeout = 99;
1708 wdt->max_timeout = 99;
1709 wdt->min_timeout = 1;
1710
1711 watchdog_init_timeout(wdt, 0, ds1307->dev);
1712 watchdog_set_drvdata(wdt, ds1307);
1713 devm_watchdog_register_device(ds1307->dev, wdt);
1714}
1715#else
1716static void ds1307_wdt_register(struct ds1307 *ds1307)
1717{
1718}
1719#endif /* CONFIG_WATCHDOG_CORE */
1720
Heiner Kallweit11e58902017-03-10 18:52:34 +01001721static const struct regmap_config regmap_config = {
1722 .reg_bits = 8,
1723 .val_bits = 8,
Heiner Kallweit11e58902017-03-10 18:52:34 +01001724};
1725
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -08001726static int ds1307_probe(struct i2c_client *client,
1727 const struct i2c_device_id *id)
David Brownell1abb0dc2006-06-25 05:48:17 -07001728{
1729 struct ds1307 *ds1307;
1730 int err = -ENODEV;
Heiner Kallweit584ce302017-08-29 21:52:56 +02001731 int tmp;
Heiner Kallweit7624df42017-07-12 07:49:33 +02001732 const struct chip_desc *chip;
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001733 bool want_irq;
Michael Lange8bc2a402016-01-21 18:10:16 +01001734 bool ds1307_can_wakeup_device = false;
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001735 unsigned char regs[8];
Jingoo Han01ce8932013-11-12 15:10:41 -08001736 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001737 u8 trickle_charger_setup = 0;
David Brownell1abb0dc2006-06-25 05:48:17 -07001738
Jingoo Hanedca66d2013-07-03 15:07:05 -07001739 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
David Anders40ce9722012-03-23 15:02:37 -07001740 if (!ds1307)
David Brownellc065f352007-07-17 04:05:10 -07001741 return -ENOMEM;
David Brownell045e0e82007-07-17 04:04:55 -07001742
Heiner Kallweit11e58902017-03-10 18:52:34 +01001743 dev_set_drvdata(&client->dev, ds1307);
1744 ds1307->dev = &client->dev;
1745 ds1307->name = client->name;
Joakim Tjernlund33df2ee2009-06-17 16:26:08 -07001746
Heiner Kallweit11e58902017-03-10 18:52:34 +01001747 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1748 if (IS_ERR(ds1307->regmap)) {
1749 dev_err(ds1307->dev, "regmap allocation failed\n");
1750 return PTR_ERR(ds1307->regmap);
1751 }
1752
1753 i2c_set_clientdata(client, ds1307);
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03001754
1755 if (client->dev.of_node) {
1756 ds1307->type = (enum ds_type)
1757 of_device_get_match_data(&client->dev);
1758 chip = &chips[ds1307->type];
1759 } else if (id) {
Tin Huynh9c19b892016-11-30 09:57:31 +07001760 chip = &chips[id->driver_data];
1761 ds1307->type = id->driver_data;
1762 } else {
1763 const struct acpi_device_id *acpi_id;
Joakim Tjernlund33df2ee2009-06-17 16:26:08 -07001764
Tin Huynh9c19b892016-11-30 09:57:31 +07001765 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
Heiner Kallweit11e58902017-03-10 18:52:34 +01001766 ds1307->dev);
Tin Huynh9c19b892016-11-30 09:57:31 +07001767 if (!acpi_id)
1768 return -ENODEV;
1769 chip = &chips[acpi_id->driver_data];
1770 ds1307->type = acpi_id->driver_data;
1771 }
1772
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001773 want_irq = client->irq > 0 && chip->alarm;
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001774
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001775 if (!pdata)
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001776 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001777 else if (pdata->trickle_charger_setup)
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001778 trickle_charger_setup = pdata->trickle_charger_setup;
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001779
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001780 if (trickle_charger_setup && chip->trickle_charger_reg) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001781 dev_dbg(ds1307->dev,
1782 "writing trickle charger info 0x%x to 0x%x\n",
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001783 trickle_charger_setup, chip->trickle_charger_reg);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001784 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
Heiner Kallweitd8490fd2017-07-12 07:49:28 +02001785 trickle_charger_setup);
Matti Vaittinen33b04b72014-10-13 15:52:48 -07001786 }
Wolfram Sangeb86c302012-05-29 15:07:38 -07001787
Michael Lange8bc2a402016-01-21 18:10:16 +01001788#ifdef CONFIG_OF
1789/*
1790 * For devices with no IRQ directly connected to the SoC, the RTC chip
1791 * can be forced as a wakeup source by stating that explicitly in
1792 * the device's .dts file using the "wakeup-source" boolean property.
1793 * If the "wakeup-source" property is set, don't request an IRQ.
1794 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1795 * if supported by the RTC.
1796 */
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001797 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1798 "wakeup-source"))
Michael Lange8bc2a402016-01-21 18:10:16 +01001799 ds1307_can_wakeup_device = true;
Michael Lange8bc2a402016-01-21 18:10:16 +01001800#endif
1801
David Brownell045e0e82007-07-17 04:04:55 -07001802 switch (ds1307->type) {
1803 case ds_1337:
1804 case ds_1339:
Nikita Yushchenko0759c882017-08-24 09:32:11 +03001805 case ds_1341:
Wolfram Sang97f902b2009-06-17 16:26:10 -07001806 case ds_3231:
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -07001807 /* get registers that the "rtc" read below won't read... */
Heiner Kallweit11e58902017-03-10 18:52:34 +01001808 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001809 regs, 2);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001810 if (err) {
1811 dev_dbg(ds1307->dev, "read error %d\n", err);
Jingoo Hanedca66d2013-07-03 15:07:05 -07001812 goto exit;
David Brownell1abb0dc2006-06-25 05:48:17 -07001813 }
1814
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -07001815 /* oscillator off? turn it on, so clock can tick. */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001816 if (regs[0] & DS1337_BIT_nEOSC)
1817 regs[0] &= ~DS1337_BIT_nEOSC;
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001818
David Anders40ce9722012-03-23 15:02:37 -07001819 /*
Michael Lange8bc2a402016-01-21 18:10:16 +01001820 * Using IRQ or defined as wakeup-source?
1821 * Disable the square wave and both alarms.
Wolfram Sang97f902b2009-06-17 16:26:10 -07001822 * For some variants, be sure alarms can trigger when we're
1823 * running on Vbackup (BBSQI/BBSQW)
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001824 */
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001825 if (want_irq || ds1307_can_wakeup_device) {
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001826 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1827 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001828 }
1829
Heiner Kallweit11e58902017-03-10 18:52:34 +01001830 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001831 regs[0]);
Rodolfo Giomettibe5f59f2007-07-17 04:05:06 -07001832
1833 /* oscillator fault? clear flag, and warn */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001834 if (regs[1] & DS1337_BIT_OSF) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001835 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001836 regs[1] & ~DS1337_BIT_OSF);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001837 dev_warn(ds1307->dev, "SET TIME!\n");
David Brownell1abb0dc2006-06-25 05:48:17 -07001838 }
David Brownell045e0e82007-07-17 04:04:55 -07001839 break;
Matthias Fuchsa2166852009-03-31 15:24:58 -07001840
1841 case rx_8025:
Heiner Kallweit11e58902017-03-10 18:52:34 +01001842 err = regmap_bulk_read(ds1307->regmap,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001843 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001844 if (err) {
1845 dev_dbg(ds1307->dev, "read error %d\n", err);
Jingoo Hanedca66d2013-07-03 15:07:05 -07001846 goto exit;
Matthias Fuchsa2166852009-03-31 15:24:58 -07001847 }
1848
1849 /* oscillator off? turn it on, so clock can tick. */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001850 if (!(regs[1] & RX8025_BIT_XST)) {
1851 regs[1] |= RX8025_BIT_XST;
Heiner Kallweit11e58902017-03-10 18:52:34 +01001852 regmap_write(ds1307->regmap,
1853 RX8025_REG_CTRL2 << 4 | 0x08,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001854 regs[1]);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001855 dev_warn(ds1307->dev,
Matthias Fuchsa2166852009-03-31 15:24:58 -07001856 "oscillator stop detected - SET TIME!\n");
1857 }
1858
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001859 if (regs[1] & RX8025_BIT_PON) {
1860 regs[1] &= ~RX8025_BIT_PON;
Heiner Kallweit11e58902017-03-10 18:52:34 +01001861 regmap_write(ds1307->regmap,
1862 RX8025_REG_CTRL2 << 4 | 0x08,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001863 regs[1]);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001864 dev_warn(ds1307->dev, "power-on detected\n");
Matthias Fuchsa2166852009-03-31 15:24:58 -07001865 }
1866
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001867 if (regs[1] & RX8025_BIT_VDET) {
1868 regs[1] &= ~RX8025_BIT_VDET;
Heiner Kallweit11e58902017-03-10 18:52:34 +01001869 regmap_write(ds1307->regmap,
1870 RX8025_REG_CTRL2 << 4 | 0x08,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001871 regs[1]);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001872 dev_warn(ds1307->dev, "voltage drop detected\n");
Matthias Fuchsa2166852009-03-31 15:24:58 -07001873 }
1874
1875 /* make sure we are running in 24hour mode */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001876 if (!(regs[0] & RX8025_BIT_2412)) {
Matthias Fuchsa2166852009-03-31 15:24:58 -07001877 u8 hour;
1878
1879 /* switch to 24 hour mode */
Heiner Kallweit11e58902017-03-10 18:52:34 +01001880 regmap_write(ds1307->regmap,
1881 RX8025_REG_CTRL1 << 4 | 0x08,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001882 regs[0] | RX8025_BIT_2412);
Matthias Fuchsa2166852009-03-31 15:24:58 -07001883
Heiner Kallweit11e58902017-03-10 18:52:34 +01001884 err = regmap_bulk_read(ds1307->regmap,
1885 RX8025_REG_CTRL1 << 4 | 0x08,
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001886 regs, 2);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001887 if (err) {
1888 dev_dbg(ds1307->dev, "read error %d\n", err);
Jingoo Hanedca66d2013-07-03 15:07:05 -07001889 goto exit;
Matthias Fuchsa2166852009-03-31 15:24:58 -07001890 }
1891
1892 /* correct hour */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001893 hour = bcd2bin(regs[DS1307_REG_HOUR]);
Matthias Fuchsa2166852009-03-31 15:24:58 -07001894 if (hour == 12)
1895 hour = 0;
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001896 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
Matthias Fuchsa2166852009-03-31 15:24:58 -07001897 hour += 12;
1898
Heiner Kallweit11e58902017-03-10 18:52:34 +01001899 regmap_write(ds1307->regmap,
1900 DS1307_REG_HOUR << 4 | 0x08, hour);
Matthias Fuchsa2166852009-03-31 15:24:58 -07001901 }
1902 break;
Chris Packham59ed0122020-08-17 11:57:31 +12001903 case ds_1388:
1904 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1905 if (err) {
1906 dev_dbg(ds1307->dev, "read error %d\n", err);
1907 goto exit;
1908 }
1909
1910 /* oscillator off? turn it on, so clock can tick. */
1911 if (tmp & DS1388_BIT_nEOSC) {
1912 tmp &= ~DS1388_BIT_nEOSC;
1913 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1914 }
1915 break;
David Brownell045e0e82007-07-17 04:04:55 -07001916 default:
1917 break;
1918 }
David Brownell1abb0dc2006-06-25 05:48:17 -07001919
David Brownell1abb0dc2006-06-25 05:48:17 -07001920 /* read RTC registers */
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001921 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1922 sizeof(regs));
Heiner Kallweit11e58902017-03-10 18:52:34 +01001923 if (err) {
1924 dev_dbg(ds1307->dev, "read error %d\n", err);
Jingoo Hanedca66d2013-07-03 15:07:05 -07001925 goto exit;
David Brownell1abb0dc2006-06-25 05:48:17 -07001926 }
1927
Alexandre Bellonib3a50162019-04-11 00:16:29 +02001928 if (ds1307->type == mcp794xx &&
1929 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1930 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1931 regs[DS1307_REG_WDAY] |
1932 MCP794XX_BIT_VBATEN);
David Brownell1abb0dc2006-06-25 05:48:17 -07001933 }
David Brownell045e0e82007-07-17 04:04:55 -07001934
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001935 tmp = regs[DS1307_REG_HOUR];
David Brownellc065f352007-07-17 04:05:10 -07001936 switch (ds1307->type) {
1937 case ds_1340:
Stefan Agner8566f702017-03-23 16:54:57 -07001938 case m41t0:
David Brownellc065f352007-07-17 04:05:10 -07001939 case m41t00:
Giulio Benetti7e580762018-05-16 23:08:40 +02001940 case m41t11:
David Anders40ce9722012-03-23 15:02:37 -07001941 /*
1942 * NOTE: ignores century bits; fix before deploying
David Brownellc065f352007-07-17 04:05:10 -07001943 * systems that will run through year 2100.
1944 */
1945 break;
Matthias Fuchsa2166852009-03-31 15:24:58 -07001946 case rx_8025:
1947 break;
David Brownellc065f352007-07-17 04:05:10 -07001948 default:
1949 if (!(tmp & DS1307_BIT_12HR))
1950 break;
1951
David Anders40ce9722012-03-23 15:02:37 -07001952 /*
1953 * Be sure we're in 24 hour mode. Multi-master systems
David Brownellc065f352007-07-17 04:05:10 -07001954 * take note...
1955 */
Adrian Bunkfe20ba72008-10-18 20:28:41 -07001956 tmp = bcd2bin(tmp & 0x1f);
David Brownellc065f352007-07-17 04:05:10 -07001957 if (tmp == 12)
1958 tmp = 0;
Alexandre Belloni042fa8c2017-09-04 22:46:02 +02001959 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
David Brownellc065f352007-07-17 04:05:10 -07001960 tmp += 12;
Heiner Kallweite5531702017-07-12 07:49:47 +02001961 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
Heiner Kallweit11e58902017-03-10 18:52:34 +01001962 bin2bcd(tmp));
David Brownell1abb0dc2006-06-25 05:48:17 -07001963 }
1964
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001965 if (want_irq || ds1307_can_wakeup_device) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001966 device_set_wakeup_capable(ds1307->dev, true);
Simon Guinot3abb1ad2015-11-26 15:37:13 +01001967 set_bit(HAS_ALARM, &ds1307->flags);
1968 }
Alexandre Belloni69b119a2017-07-06 11:42:06 +02001969
1970 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
Alexandre Bellonie69c0562017-09-04 22:46:07 +02001971 if (IS_ERR(ds1307->rtc))
Alessandro Zummo4071ea22014-04-03 14:49:36 -07001972 return PTR_ERR(ds1307->rtc);
David Brownell1abb0dc2006-06-25 05:48:17 -07001973
Heiner Kallweit82e2d432017-07-12 07:49:37 +02001974 if (ds1307_can_wakeup_device && !want_irq) {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001975 dev_info(ds1307->dev,
1976 "'wakeup-source' is set, request for an IRQ is disabled!\n");
Michael Lange8bc2a402016-01-21 18:10:16 +01001977 /* We cannot support UIE mode if we do not have an IRQ line */
1978 ds1307->rtc->uie_unsupported = 1;
1979 }
1980
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001981 if (want_irq) {
Heiner Kallweit45947122017-07-12 07:49:41 +02001982 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1983 chip->irq_handler ?: ds1307_irq,
Nishanth Menonc5983192015-06-23 11:15:11 -05001984 IRQF_SHARED | IRQF_ONESHOT,
Alexandre Belloni4b9e2a02017-06-02 14:13:21 +02001985 ds1307->name, ds1307);
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001986 if (err) {
Alessandro Zummo4071ea22014-04-03 14:49:36 -07001987 client->irq = 0;
Heiner Kallweit11e58902017-03-10 18:52:34 +01001988 device_set_wakeup_capable(ds1307->dev, false);
Simon Guinot3abb1ad2015-11-26 15:37:13 +01001989 clear_bit(HAS_ALARM, &ds1307->flags);
Heiner Kallweit11e58902017-03-10 18:52:34 +01001990 dev_err(ds1307->dev, "unable to request IRQ!\n");
Alexandre Bellonie69c0562017-09-04 22:46:07 +02001991 } else {
Heiner Kallweit11e58902017-03-10 18:52:34 +01001992 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
Alexandre Bellonie69c0562017-09-04 22:46:07 +02001993 }
Rodolfo Giometticb49a5e2008-10-15 22:02:58 -07001994 }
1995
Alexandre Bellonie9fb7682018-02-12 23:47:22 +01001996 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02001997 err = ds1307_add_frequency_test(ds1307);
Alexandre Bellonie9fb7682018-02-12 23:47:22 +01001998 if (err)
1999 return err;
2000
Alexandre Belloni6a5f2a1f2018-09-20 16:35:26 +02002001 err = rtc_register_device(ds1307->rtc);
Giulio Benettib41c23e2018-07-25 19:26:05 +02002002 if (err)
2003 return err;
2004
Austin Boyle9eab0a72012-03-23 15:02:38 -07002005 if (chip->nvram_size) {
Alexandre Belloni409baf12018-02-12 23:47:23 +01002006 struct nvmem_config nvmem_cfg = {
2007 .name = "ds1307_nvram",
2008 .word_size = 1,
2009 .stride = 1,
2010 .size = chip->nvram_size,
2011 .reg_read = ds1307_nvram_read,
2012 .reg_write = ds1307_nvram_write,
2013 .priv = ds1307,
2014 };
Alessandro Zummo4071ea22014-04-03 14:49:36 -07002015
Alexandre Belloniabc925f2017-07-06 11:42:07 +02002016 ds1307->rtc->nvram_old_abi = true;
Alexandre Belloni409baf12018-02-12 23:47:23 +01002017 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
David Brownell682d73f2007-11-14 16:58:32 -08002018 }
2019
Akinobu Mita445c0202016-01-25 00:22:16 +09002020 ds1307_hwmon_register(ds1307);
Akinobu Mita6c6ff142016-01-31 23:10:10 +09002021 ds1307_clks_register(ds1307);
Chris Packhamfd90d482020-03-30 15:55:00 +13002022 ds1307_wdt_register(ds1307);
Akinobu Mita445c0202016-01-25 00:22:16 +09002023
David Brownell1abb0dc2006-06-25 05:48:17 -07002024 return 0;
2025
Jingoo Hanedca66d2013-07-03 15:07:05 -07002026exit:
David Brownell1abb0dc2006-06-25 05:48:17 -07002027 return err;
2028}
2029
David Brownell1abb0dc2006-06-25 05:48:17 -07002030static struct i2c_driver ds1307_driver = {
2031 .driver = {
David Brownellc065f352007-07-17 04:05:10 -07002032 .name = "rtc-ds1307",
Javier Martinez Canillas7ef6d2c2017-03-03 11:29:15 -03002033 .of_match_table = of_match_ptr(ds1307_of_match),
Tin Huynh9c19b892016-11-30 09:57:31 +07002034 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
David Brownell1abb0dc2006-06-25 05:48:17 -07002035 },
David Brownellc065f352007-07-17 04:05:10 -07002036 .probe = ds1307_probe,
Jean Delvare3760f732008-04-29 23:11:40 +02002037 .id_table = ds1307_id,
David Brownell1abb0dc2006-06-25 05:48:17 -07002038};
2039
Axel Lin0abc9202012-03-23 15:02:31 -07002040module_i2c_driver(ds1307_driver);
David Brownell1abb0dc2006-06-25 05:48:17 -07002041
2042MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2043MODULE_LICENSE("GPL");