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Thomas Gleixner4fa9c49f2019-05-29 07:18:05 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -07002/*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -07005
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7*******************************************************************************/
8
Rayagond Kokatanurbd4242d2012-08-22 21:28:18 +00009#ifndef __STMMAC_H__
10#define __STMMAC_H__
11
Giuseppe CAVALLARObfab27a2011-12-21 03:58:19 +000012#define STMMAC_RESOURCE_NAME "stmmaceth"
Alexandre TORGUE06bce7d2016-04-01 11:37:36 +020013#define DRV_MODULE_VERSION "Jan_2016"
Giuseppe CAVALLAROba1377ff2012-04-04 04:33:25 +000014
15#include <linux/clk.h>
Vincent Whitchurchd5a05e62020-11-20 16:02:08 +010016#include <linux/hrtimer.h>
Jose Abreu3cd1cfc2019-08-07 10:03:14 +020017#include <linux/if_vlan.h>
Giuseppe CAVALLAROee7946a2010-01-06 23:07:14 +000018#include <linux/stmmac.h>
Jose Abreueeef2f62019-06-11 17:18:46 +020019#include <linux/phylink.h>
Giuseppe CAVALLARO33d5e332012-06-07 19:25:07 +000020#include <linux/pci.h>
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070021#include "common.h"
Rayagond Kokatanur92ba6882013-03-26 04:43:11 +000022#include <linux/ptp_clock_kernel.h>
Artem Panfilovd6228b72019-01-20 19:05:15 +030023#include <linux/net_tstamp.h>
Chen-Yu Tsaic5e4ddb2014-01-17 21:24:41 +080024#include <linux/reset.h>
Jose Abreu2af61062019-07-09 10:03:00 +020025#include <net/page_pool.h>
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070026
Joachim Eastwoode56788c2015-05-20 20:03:07 +020027struct stmmac_resources {
28 void __iomem *addr;
29 const char *mac;
30 int wol_irq;
31 int lpi_irq;
32 int irq;
Ong Boon Leong8532f612021-03-26 01:39:14 +080033 int sfty_ce_irq;
34 int sfty_ue_irq;
35 int rx_irq[MTL_MAX_RX_QUEUES];
36 int tx_irq[MTL_MAX_TX_QUEUES];
Joachim Eastwoode56788c2015-05-20 20:03:07 +020037};
38
Ong Boon Leongbe8b38a2021-04-01 10:11:16 +080039enum stmmac_txbuf_type {
40 STMMAC_TXBUF_T_SKB,
41 STMMAC_TXBUF_T_XDP_TX,
Ong Boon Leong8b278a52021-04-01 10:11:17 +080042 STMMAC_TXBUF_T_XDP_NDO,
Ong Boon Leongbe8b38a2021-04-01 10:11:16 +080043};
44
Giuseppe CAVALLARO362b37b2014-08-27 11:27:00 +020045struct stmmac_tx_info {
46 dma_addr_t buf;
47 bool map_as_page;
Giuseppe Cavallaro553e2ab2016-02-29 14:27:31 +010048 unsigned len;
Giuseppe Cavallaro2a6d8e12016-02-29 14:27:32 +010049 bool last_segment;
Giuseppe Cavallaro96951362016-02-29 14:27:33 +010050 bool is_jumbo;
Ong Boon Leongbe8b38a2021-04-01 10:11:16 +080051 enum stmmac_txbuf_type buf_type;
Giuseppe CAVALLARO362b37b2014-08-27 11:27:00 +020052};
53
Jose Abreu579a25a2020-01-13 17:24:09 +010054#define STMMAC_TBS_AVAIL BIT(0)
55#define STMMAC_TBS_EN BIT(1)
56
Joao Pintoce736782017-04-06 09:49:10 +010057/* Frequently used values are kept adjacent for cache effect */
58struct stmmac_tx_queue {
Jose Abreu8fce3332018-09-17 09:22:56 +010059 u32 tx_count_frames;
Jose Abreu579a25a2020-01-13 17:24:09 +010060 int tbs;
Vincent Whitchurchd5a05e62020-11-20 16:02:08 +010061 struct hrtimer txtimer;
Joao Pintoce736782017-04-06 09:49:10 +010062 u32 queue_index;
63 struct stmmac_priv *priv_data;
64 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
Jose Abreu579a25a2020-01-13 17:24:09 +010065 struct dma_edesc *dma_entx;
Joao Pintoce736782017-04-06 09:49:10 +010066 struct dma_desc *dma_tx;
Ong Boon Leongbe8b38a2021-04-01 10:11:16 +080067 union {
68 struct sk_buff **tx_skbuff;
69 struct xdp_frame **xdpf;
70 };
Joao Pintoce736782017-04-06 09:49:10 +010071 struct stmmac_tx_info *tx_skbuff_dma;
72 unsigned int cur_tx;
73 unsigned int dirty_tx;
74 dma_addr_t dma_tx_phy;
75 u32 tx_tail_addr;
Niklas Cassel8d212a9e2018-02-19 18:11:09 +010076 u32 mss;
Joao Pintoce736782017-04-06 09:49:10 +010077};
78
Jose Abreu2af61062019-07-09 10:03:00 +020079struct stmmac_rx_buffer {
80 struct page *page;
81 dma_addr_t addr;
Ong Boon Leong5fabb012021-04-01 10:11:15 +080082 __u32 page_offset;
83 struct page *sec_page;
Jose Abreu67afd6d2019-08-17 20:54:43 +020084 dma_addr_t sec_addr;
Jose Abreu2af61062019-07-09 10:03:00 +020085};
86
Joao Pinto54139cf2017-04-06 09:49:09 +010087struct stmmac_rx_queue {
Jose Abreud429b662019-07-09 10:02:58 +020088 u32 rx_count_frames;
Joao Pinto54139cf2017-04-06 09:49:09 +010089 u32 queue_index;
Ong Boon Leongbe8b38a2021-04-01 10:11:16 +080090 struct xdp_rxq_info xdp_rxq;
Jose Abreu2af61062019-07-09 10:03:00 +020091 struct page_pool *page_pool;
92 struct stmmac_rx_buffer *buf_pool;
Joao Pinto54139cf2017-04-06 09:49:09 +010093 struct stmmac_priv *priv_data;
94 struct dma_extended_desc *dma_erx;
95 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
Joao Pinto54139cf2017-04-06 09:49:09 +010096 unsigned int cur_rx;
97 unsigned int dirty_rx;
98 u32 rx_zeroc_thresh;
99 dma_addr_t dma_rx_phy;
100 u32 rx_tail_addr;
Jose Abreuec222002019-08-17 20:54:41 +0200101 unsigned int state_saved;
102 struct {
103 struct sk_buff *skb;
104 unsigned int len;
105 unsigned int error;
106 } state;
Jose Abreu8fce3332018-09-17 09:22:56 +0100107};
108
109struct stmmac_channel {
Jose Abreu4ccb45852019-02-19 10:38:47 +0100110 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
111 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
Jose Abreu8fce3332018-09-17 09:22:56 +0100112 struct stmmac_priv *priv_data;
Jose Abreu021bd5e2019-12-18 11:24:44 +0100113 spinlock_t lock;
Jose Abreu8fce3332018-09-17 09:22:56 +0100114 u32 index;
Joao Pinto54139cf2017-04-06 09:49:09 +0100115};
116
Jose Abreu4dbbe8d2018-05-04 10:01:38 +0100117struct stmmac_tc_entry {
118 bool in_use;
119 bool in_hw;
120 bool is_last;
121 bool is_frag;
122 void *frag_ptr;
123 unsigned int table_pos;
124 u32 handle;
125 u32 prio;
126 struct {
127 u32 match_data;
128 u32 match_en;
129 u8 af:1;
130 u8 rf:1;
131 u8 im:1;
132 u8 nc:1;
133 u8 res1:4;
134 u8 frame_offset;
135 u8 ok_index;
136 u8 dma_ch_no;
137 u32 res2;
138 } __packed val;
139};
140
Jose Abreu9a8a02c2018-05-31 18:01:27 +0100141#define STMMAC_PPS_MAX 4
142struct stmmac_pps_cfg {
143 bool available;
144 struct timespec64 start;
145 struct timespec64 period;
146};
147
Jose Abreu76067452019-08-07 10:03:12 +0200148struct stmmac_rss {
149 int enable;
150 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
151 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
152};
153
Jose Abreu425eabd2019-09-04 15:16:56 +0200154#define STMMAC_FLOW_ACTION_DROP BIT(0)
155struct stmmac_flow_entry {
156 unsigned long cookie;
157 unsigned long action;
158 u8 ip_proto;
159 int in_use;
160 int idx;
161 int is_l4;
162};
163
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700164struct stmmac_priv {
165 /* Frequently used values are kept adjacent for cache effect */
Ong Boon Leongdb2f2842021-03-17 09:01:23 +0800166 u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
167 u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
168 u32 rx_coal_frames[MTL_MAX_TX_QUEUES];
Joao Pintoce736782017-04-06 09:49:10 +0100169
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700170 int tx_coalesce;
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000171 int hwts_tx_en;
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000172 bool tx_path_in_lpi_mode;
Alexandre TORGUEf748be52016-04-01 11:37:34 +0200173 bool tso;
Jose Abreu67afd6d2019-08-17 20:54:43 +0200174 int sph;
Ong Boon Leongd08d32d2021-04-01 10:11:13 +0800175 int sph_cap;
Jose Abreu8000ddc2019-08-17 20:54:47 +0200176 u32 sarc_type;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700177
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700178 unsigned int dma_buf_sz;
Giuseppe Cavallaro22ad3832016-02-29 14:27:41 +0100179 unsigned int rx_copybreak;
Ong Boon Leongdb2f2842021-03-17 09:01:23 +0800180 u32 rx_riwt[MTL_MAX_TX_QUEUES];
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000181 int hwts_rx_en;
LABBE Corentin5bacd772017-03-29 07:05:40 +0200182
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000183 void __iomem *ioaddr;
184 struct net_device *dev;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700185 struct device *device;
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000186 struct mac_device_info *hw;
Jose Abreu7cfde0a2018-06-15 16:17:27 +0100187 int (*hwif_quirks)(struct stmmac_priv *priv);
Thierry Reding29555fa2018-05-24 16:09:07 +0200188 struct mutex lock;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700189
Joao Pinto54139cf2017-04-06 09:49:09 +0100190 /* RX Queue */
191 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
Song, Yoong Siangaa042f62020-09-16 15:40:20 +0800192 unsigned int dma_rx_size;
Joao Pinto54139cf2017-04-06 09:49:09 +0100193
Joao Pintoce736782017-04-06 09:49:10 +0100194 /* TX Queue */
195 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
Song, Yoong Siangaa042f62020-09-16 15:40:20 +0800196 unsigned int dma_tx_size;
Joao Pintoce736782017-04-06 09:49:10 +0100197
Jose Abreu8fce3332018-09-17 09:22:56 +0100198 /* Generic channel for NAPI */
199 struct stmmac_channel channel[STMMAC_CH_MAX];
200
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700201 int speed;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700202 unsigned int flow_ctrl;
203 unsigned int pause;
204 struct mii_bus *mii;
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000205 int mii_irq[PHY_MAX_ADDR];
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700206
Jose Abreueeef2f62019-06-11 17:18:46 +0200207 struct phylink_config phylink_config;
208 struct phylink *phylink;
209
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000210 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
Jose Abreu8bf993a2018-03-29 10:40:19 +0100211 struct stmmac_safety_stats sstats;
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000212 struct plat_stmmacenet_data *plat;
213 struct dma_features dma_cap;
214 struct stmmac_counters mmc;
215 int hw_cap_support;
216 int synopsys_id;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700217 u32 msg_enable;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700218 int wolopts;
Deepak Sikri3172d3a2011-09-01 21:51:37 +0000219 int wol_irq;
Giuseppe CAVALLAROcd7201f2012-04-04 04:33:27 +0000220 int clk_csr;
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000221 struct timer_list eee_ctrl_timer;
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000222 int lpi_irq;
223 int eee_enabled;
224 int eee_active;
225 int tx_lpi_timer;
Vineetha G. Jaya Kumaran388e2012020-10-01 23:56:09 +0800226 int tx_lpi_enabled;
227 int eee_tw_timer;
Vineetha G. Jaya Kumaranbe1c7ea2020-10-28 00:00:51 +0800228 bool eee_sw_timer_en;
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000229 unsigned int mode;
Jose Abreu5f0456b2018-04-23 09:05:15 +0100230 unsigned int chain_mode;
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000231 int extend_desc;
Artem Panfilovd6228b72019-01-20 19:05:15 +0300232 struct hwtstamp_config tstamp_config;
Rayagond Kokatanur92ba6882013-03-26 04:43:11 +0000233 struct ptp_clock *ptp_clock;
234 struct ptp_clock_info ptp_clock_ops;
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000235 unsigned int default_addend;
Jose Abreu9a8a02c2018-05-31 18:01:27 +0100236 u32 sub_second_inc;
237 u32 systime_flags;
Giuseppe CAVALLARO1bb6dea2013-04-08 02:10:02 +0000238 u32 adv_ts;
239 int use_riwt;
Srinivas Kandagatla89f7f2c2014-01-16 10:53:00 +0000240 int irq_wake;
Rayagond Kokatanur92ba6882013-03-26 04:43:11 +0000241 spinlock_t ptp_lock;
Alexandre TORGUE36ff7c12016-04-01 11:37:32 +0200242 void __iomem *mmcaddr;
Giuseppe CAVALLAROba1ffd72016-11-14 09:27:29 +0100243 void __iomem *ptpaddr;
Jose Abreu3cd1cfc2019-08-07 10:03:14 +0200244 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Ong Boon Leong8532f612021-03-26 01:39:14 +0800245 int sfty_ce_irq;
246 int sfty_ue_irq;
247 int rx_irq[MTL_MAX_RX_QUEUES];
248 int tx_irq[MTL_MAX_TX_QUEUES];
249 /*irq name */
250 char int_name_mac[IFNAMSIZ + 9];
251 char int_name_wol[IFNAMSIZ + 9];
252 char int_name_lpi[IFNAMSIZ + 9];
253 char int_name_sfty_ce[IFNAMSIZ + 10];
254 char int_name_sfty_ue[IFNAMSIZ + 10];
255 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14];
256 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
Mathieu Olivari466c5ac2015-05-22 19:03:29 -0700257
258#ifdef CONFIG_DEBUG_FS
259 struct dentry *dbgfs_dir;
Mathieu Olivari466c5ac2015-05-22 19:03:29 -0700260#endif
Jose Abreu34877a12018-03-29 10:40:18 +0100261
262 unsigned long state;
263 struct workqueue_struct *wq;
264 struct work_struct service_task;
Jose Abreu4dbbe8d2018-05-04 10:01:38 +0100265
Ong Boon Leong5a558612021-03-24 17:07:42 +0800266 /* Workqueue for handling FPE hand-shaking */
267 unsigned long fpe_task_state;
268 struct workqueue_struct *fpe_wq;
269 struct work_struct fpe_task;
270 char wq_name[IFNAMSIZ + 4];
271
Jose Abreu4dbbe8d2018-05-04 10:01:38 +0100272 /* TC Handling */
273 unsigned int tc_entries_max;
274 unsigned int tc_off_max;
275 struct stmmac_tc_entry *tc_entries;
Jose Abreu425eabd2019-09-04 15:16:56 +0200276 unsigned int flow_entries_max;
277 struct stmmac_flow_entry *flow_entries;
Jose Abreu9a8a02c2018-05-31 18:01:27 +0100278
279 /* Pulse Per Second output */
280 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
Jose Abreu76067452019-08-07 10:03:12 +0200281
282 /* Receive Side Scaling */
283 struct stmmac_rss rss;
Ong Boon Leong5fabb012021-04-01 10:11:15 +0800284
285 /* XDP BPF Program */
286 struct bpf_prog *xdp_prog;
Jose Abreu34877a12018-03-29 10:40:18 +0100287};
288
289enum stmmac_state {
290 STMMAC_DOWN,
291 STMMAC_RESET_REQUESTED,
292 STMMAC_RESETING,
293 STMMAC_SERVICE_SCHED,
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700294};
295
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700296int stmmac_mdio_unregister(struct net_device *ndev);
297int stmmac_mdio_register(struct net_device *ndev);
Srinivas Kandagatla073752a2014-01-16 10:52:27 +0000298int stmmac_mdio_reset(struct mii_bus *mii);
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700299void stmmac_set_ethtool_ops(struct net_device *netdev);
Andy Shevchenko915af652014-11-05 11:45:32 +0200300
Giuseppe CAVALLAROc30a70d2016-10-19 09:06:41 +0200301void stmmac_ptp_register(struct stmmac_priv *priv);
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700302void stmmac_ptp_unregister(struct stmmac_priv *priv);
Ong Boon Leong5fabb012021-04-01 10:11:15 +0800303int stmmac_open(struct net_device *dev);
304int stmmac_release(struct net_device *dev);
Joachim Eastwoodf4e7bd82016-05-01 22:58:19 +0200305int stmmac_resume(struct device *dev);
306int stmmac_suspend(struct device *dev);
307int stmmac_dvr_remove(struct device *dev);
Joachim Eastwood15ffac72015-05-20 20:03:08 +0200308int stmmac_dvr_probe(struct device *device,
309 struct plat_stmmacenet_data *plat_dat,
310 struct stmmac_resources *res);
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000311void stmmac_disable_eee_mode(struct stmmac_priv *priv);
312bool stmmac_eee_init(struct stmmac_priv *priv);
Ong Boon Leong0366f7e2020-09-15 09:28:38 +0800313int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
Song, Yoong Siangaa042f62020-09-16 15:40:20 +0800314int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
Joakim Zhang5ec55822021-03-15 20:16:46 +0800315int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
Ong Boon Leong5a558612021-03-24 17:07:42 +0800316void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable);
Giuseppe CAVALLAROba1377ff2012-04-04 04:33:25 +0000317
Ong Boon Leong5fabb012021-04-01 10:11:15 +0800318static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
319{
320 return !!priv->xdp_prog;
321}
322
323static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv)
324{
325 if (stmmac_xdp_is_enabled(priv))
326 return XDP_PACKET_HEADROOM;
327
328 return 0;
329}
330
Jose Abreu091810d2019-05-24 10:20:19 +0200331#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
332void stmmac_selftest_run(struct net_device *dev,
333 struct ethtool_test *etest, u64 *buf);
334void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
335int stmmac_selftest_get_count(struct stmmac_priv *priv);
336#else
337static inline void stmmac_selftest_run(struct net_device *dev,
338 struct ethtool_test *etest, u64 *buf)
339{
340 /* Not enabled */
341}
342static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
343 u8 *data)
344{
345 /* Not enabled */
346}
347static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
348{
349 return -EOPNOTSUPP;
350}
351#endif /* CONFIG_STMMAC_SELFTESTS */
352
Rayagond Kokatanurbd4242d2012-08-22 21:28:18 +0000353#endif /* __STMMAC_H__ */