Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 27 | * Christian König |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 28 | */ |
| 29 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "radeon_drm.h" |
| 33 | #include "radeon_reg.h" |
| 34 | #include "radeon.h" |
| 35 | #include "atom.h" |
| 36 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 37 | /* |
| 38 | * IB. |
| 39 | */ |
| 40 | int radeon_debugfs_sa_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 42 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 43 | struct radeon_ib *ib, unsigned size) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 45 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 46 | |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 47 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 49 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 50 | return r; |
| 51 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 52 | |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 53 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
| 54 | if (r) { |
| 55 | return r; |
| 56 | } |
| 57 | |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 58 | ib->ring = ring; |
| 59 | ib->fence = NULL; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 60 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
| 61 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
| 62 | ib->vm_id = 0; |
| 63 | ib->is_const_ib = false; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 64 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
| 65 | ib->sync_to[i] = NULL; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 66 | |
| 67 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | } |
| 69 | |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 70 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 72 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 73 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
| 74 | radeon_fence_unref(&ib->fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | } |
| 76 | |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 77 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 78 | struct radeon_ib *const_ib) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 79 | { |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 80 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 81 | bool need_sync = false; |
| 82 | int i, r = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 83 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 84 | if (!ib->length_dw || !ring->ready) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | /* TODO: Nothings in the ib we should report. */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 86 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 87 | return -EINVAL; |
| 88 | } |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 89 | |
Dave Airlie | 6cdf658 | 2009-06-29 18:29:13 +1000 | [diff] [blame] | 90 | /* 64 dwords should be enough for fence too */ |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 91 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 93 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 94 | return r; |
| 95 | } |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 96 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 97 | struct radeon_fence *fence = ib->sync_to[i]; |
| 98 | if (radeon_fence_need_sync(fence, ib->ring)) { |
| 99 | need_sync = true; |
| 100 | radeon_semaphore_sync_rings(rdev, ib->semaphore, |
| 101 | fence->ring, ib->ring); |
| 102 | radeon_fence_note_sync(fence, ib->ring); |
| 103 | } |
| 104 | } |
| 105 | /* immediately free semaphore when we don't need to sync */ |
| 106 | if (!need_sync) { |
| 107 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); |
| 108 | } |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 109 | if (const_ib) { |
| 110 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); |
| 111 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); |
| 112 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 113 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
| 114 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
| 115 | if (r) { |
| 116 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
| 117 | radeon_ring_unlock_undo(rdev, ring); |
| 118 | return r; |
| 119 | } |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 120 | if (const_ib) { |
| 121 | const_ib->fence = radeon_fence_ref(ib->fence); |
| 122 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 123 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | int radeon_ib_pool_init(struct radeon_device *rdev) |
| 128 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 129 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 130 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 131 | if (rdev->ib_pool_ready) { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 132 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 133 | } |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 134 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 135 | RADEON_IB_POOL_SIZE*64*1024, |
| 136 | RADEON_GEM_DOMAIN_GTT); |
| 137 | if (r) { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 138 | return r; |
| 139 | } |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 140 | |
| 141 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
| 142 | if (r) { |
| 143 | return r; |
| 144 | } |
| 145 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 146 | rdev->ib_pool_ready = true; |
| 147 | if (radeon_debugfs_sa_init(rdev)) { |
| 148 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 149 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 150 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
| 154 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 155 | if (rdev->ib_pool_ready) { |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 156 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 157 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
| 158 | rdev->ib_pool_ready = false; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 159 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | } |
| 161 | |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 162 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
| 163 | { |
| 164 | unsigned i; |
| 165 | int r; |
| 166 | |
| 167 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 168 | struct radeon_ring *ring = &rdev->ring[i]; |
| 169 | |
| 170 | if (!ring->ready) |
| 171 | continue; |
| 172 | |
| 173 | r = radeon_ib_test(rdev, i, ring); |
| 174 | if (r) { |
| 175 | ring->ready = false; |
| 176 | |
| 177 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
| 178 | /* oh, oh, that's really bad */ |
| 179 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
| 180 | rdev->accel_working = false; |
| 181 | return r; |
| 182 | |
| 183 | } else { |
| 184 | /* still not good, but we can live with it */ |
| 185 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
| 186 | } |
| 187 | } |
| 188 | } |
| 189 | return 0; |
| 190 | } |
| 191 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 192 | /* |
| 193 | * Ring. |
| 194 | */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 195 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
| 196 | |
| 197 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
| 198 | { |
| 199 | #if DRM_DEBUG_CODE |
| 200 | if (ring->count_dw <= 0) { |
| 201 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 202 | } |
| 203 | #endif |
| 204 | ring->ring[ring->wptr++] = v; |
| 205 | ring->wptr &= ring->ptr_mask; |
| 206 | ring->count_dw--; |
| 207 | ring->ring_free_dw--; |
| 208 | } |
| 209 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 210 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 212 | u32 rptr; |
| 213 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 214 | if (rdev->wb.enabled) |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 215 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 216 | else |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 217 | rptr = RREG32(ring->rptr_reg); |
| 218 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | /* This works because ring_size is a power of 2 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 220 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
| 221 | ring->ring_free_dw -= ring->wptr; |
| 222 | ring->ring_free_dw &= ring->ptr_mask; |
| 223 | if (!ring->ring_free_dw) { |
| 224 | ring->ring_free_dw = ring->ring_size / 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | } |
| 226 | } |
| 227 | |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 228 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 229 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 230 | { |
| 231 | int r; |
| 232 | |
| 233 | /* Align requested size with padding so unlock_commit can |
| 234 | * pad safely */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 235 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
| 236 | while (ndw > (ring->ring_free_dw - 1)) { |
| 237 | radeon_ring_free_size(rdev, ring); |
| 238 | if (ndw < ring->ring_free_dw) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | break; |
| 240 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame^] | 241 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 242 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 243 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 244 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 245 | ring->count_dw = ndw; |
| 246 | ring->wptr_old = ring->wptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 247 | return 0; |
| 248 | } |
| 249 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 250 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 251 | { |
| 252 | int r; |
| 253 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 254 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 255 | r = radeon_ring_alloc(rdev, ring, ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 256 | if (r) { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 257 | mutex_unlock(&rdev->ring_lock); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 258 | return r; |
| 259 | } |
| 260 | return 0; |
| 261 | } |
| 262 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 263 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 264 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | /* We pad to match fetch size */ |
Christian König | 07a7133 | 2012-07-07 12:11:32 +0200 | [diff] [blame] | 266 | while (ring->wptr & ring->align_mask) { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 267 | radeon_ring_write(ring, ring->nop); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | } |
| 269 | DRM_MEMORYBARRIER(); |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 270 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 271 | (void)RREG32(ring->wptr_reg); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 272 | } |
| 273 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 274 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 275 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 276 | radeon_ring_commit(rdev, ring); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 277 | mutex_unlock(&rdev->ring_lock); |
| 278 | } |
| 279 | |
| 280 | void radeon_ring_undo(struct radeon_ring *ring) |
| 281 | { |
| 282 | ring->wptr = ring->wptr_old; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 283 | } |
| 284 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 285 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 287 | radeon_ring_undo(ring); |
| 288 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 289 | } |
| 290 | |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 291 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
| 292 | { |
| 293 | int r; |
| 294 | |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 295 | radeon_ring_free_size(rdev, ring); |
| 296 | if (ring->rptr == ring->wptr) { |
| 297 | r = radeon_ring_alloc(rdev, ring, 1); |
| 298 | if (!r) { |
| 299 | radeon_ring_write(ring, ring->nop); |
| 300 | radeon_ring_commit(rdev, ring); |
| 301 | } |
| 302 | } |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 303 | } |
| 304 | |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 305 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
| 306 | { |
| 307 | ring->last_rptr = ring->rptr; |
| 308 | ring->last_activity = jiffies; |
| 309 | } |
| 310 | |
| 311 | /** |
| 312 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
| 313 | * @rdev: radeon device structure |
| 314 | * @ring: radeon_ring structure holding ring information |
| 315 | * |
| 316 | * We don't need to initialize the lockup tracking information as we will either |
| 317 | * have CP rptr to a different value of jiffies wrap around which will force |
| 318 | * initialization of the lockup tracking informations. |
| 319 | * |
| 320 | * A possible false positivie is if we get call after while and last_cp_rptr == |
| 321 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
| 322 | * if the elapsed time since last call is bigger than 2 second than we return |
| 323 | * false and update the tracking information. Due to this the caller must call |
| 324 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
| 325 | * the fencing code should be cautious about that. |
| 326 | * |
| 327 | * Caller should write to the ring to force CP to do something so we don't get |
| 328 | * false positive when CP is just gived nothing to do. |
| 329 | * |
| 330 | **/ |
| 331 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 332 | { |
| 333 | unsigned long cjiffies, elapsed; |
| 334 | uint32_t rptr; |
| 335 | |
| 336 | cjiffies = jiffies; |
| 337 | if (!time_after(cjiffies, ring->last_activity)) { |
| 338 | /* likely a wrap around */ |
| 339 | radeon_ring_lockup_update(ring); |
| 340 | return false; |
| 341 | } |
| 342 | rptr = RREG32(ring->rptr_reg); |
| 343 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
| 344 | if (ring->rptr != ring->last_rptr) { |
| 345 | /* CP is still working no lockup */ |
| 346 | radeon_ring_lockup_update(ring); |
| 347 | return false; |
| 348 | } |
| 349 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 350 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 351 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| 352 | return true; |
| 353 | } |
| 354 | /* give a chance to the GPU ... */ |
| 355 | return false; |
| 356 | } |
| 357 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 358 | /** |
| 359 | * radeon_ring_backup - Back up the content of a ring |
| 360 | * |
| 361 | * @rdev: radeon_device pointer |
| 362 | * @ring: the ring we want to back up |
| 363 | * |
| 364 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
| 365 | */ |
| 366 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 367 | uint32_t **data) |
| 368 | { |
| 369 | unsigned size, ptr, i; |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 370 | |
| 371 | /* just in case lock the ring */ |
| 372 | mutex_lock(&rdev->ring_lock); |
| 373 | *data = NULL; |
| 374 | |
| 375 | if (ring->ring_obj == NULL || !ring->rptr_save_reg) { |
| 376 | mutex_unlock(&rdev->ring_lock); |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | /* it doesn't make sense to save anything if all fences are signaled */ |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame^] | 381 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 382 | mutex_unlock(&rdev->ring_lock); |
| 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | /* calculate the number of dw on the ring */ |
| 387 | ptr = RREG32(ring->rptr_save_reg); |
| 388 | size = ring->wptr + (ring->ring_size / 4); |
| 389 | size -= ptr; |
| 390 | size &= ring->ptr_mask; |
| 391 | if (size == 0) { |
| 392 | mutex_unlock(&rdev->ring_lock); |
| 393 | return 0; |
| 394 | } |
| 395 | |
| 396 | /* and then save the content of the ring */ |
| 397 | *data = kmalloc(size * 4, GFP_KERNEL); |
| 398 | for (i = 0; i < size; ++i) { |
| 399 | (*data)[i] = ring->ring[ptr++]; |
| 400 | ptr &= ring->ptr_mask; |
| 401 | } |
| 402 | |
| 403 | mutex_unlock(&rdev->ring_lock); |
| 404 | return size; |
| 405 | } |
| 406 | |
| 407 | /** |
| 408 | * radeon_ring_restore - append saved commands to the ring again |
| 409 | * |
| 410 | * @rdev: radeon_device pointer |
| 411 | * @ring: ring to append commands to |
| 412 | * @size: number of dwords we want to write |
| 413 | * @data: saved commands |
| 414 | * |
| 415 | * Allocates space on the ring and restore the previously saved commands. |
| 416 | */ |
| 417 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 418 | unsigned size, uint32_t *data) |
| 419 | { |
| 420 | int i, r; |
| 421 | |
| 422 | if (!size || !data) |
| 423 | return 0; |
| 424 | |
| 425 | /* restore the saved ring content */ |
| 426 | r = radeon_ring_lock(rdev, ring, size); |
| 427 | if (r) |
| 428 | return r; |
| 429 | |
| 430 | for (i = 0; i < size; ++i) { |
| 431 | radeon_ring_write(ring, data[i]); |
| 432 | } |
| 433 | |
| 434 | radeon_ring_unlock_commit(rdev, ring); |
| 435 | kfree(data); |
| 436 | return 0; |
| 437 | } |
| 438 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 439 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 440 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 441 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 442 | { |
| 443 | int r; |
| 444 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 445 | ring->ring_size = ring_size; |
| 446 | ring->rptr_offs = rptr_offs; |
| 447 | ring->rptr_reg = rptr_reg; |
| 448 | ring->wptr_reg = wptr_reg; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 449 | ring->ptr_reg_shift = ptr_reg_shift; |
| 450 | ring->ptr_reg_mask = ptr_reg_mask; |
| 451 | ring->nop = nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 452 | /* Allocate ring buffer */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 453 | if (ring->ring_obj == NULL) { |
| 454 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 455 | RADEON_GEM_DOMAIN_GTT, |
| 456 | NULL, &ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 457 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 458 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 459 | return r; |
| 460 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 461 | r = radeon_bo_reserve(ring->ring_obj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 462 | if (unlikely(r != 0)) |
| 463 | return r; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 464 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
| 465 | &ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 466 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 467 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 468 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 469 | return r; |
| 470 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 471 | r = radeon_bo_kmap(ring->ring_obj, |
| 472 | (void **)&ring->ring); |
| 473 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 474 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 475 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 476 | return r; |
| 477 | } |
| 478 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 479 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
| 480 | ring->ring_free_dw = ring->ring_size / 4; |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 481 | if (radeon_debugfs_ring_init(rdev, ring)) { |
| 482 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
| 483 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 484 | return 0; |
| 485 | } |
| 486 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 487 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 489 | int r; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 490 | struct radeon_bo *ring_obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 491 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 492 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 493 | ring_obj = ring->ring_obj; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 494 | ring->ready = false; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 495 | ring->ring = NULL; |
| 496 | ring->ring_obj = NULL; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 497 | mutex_unlock(&rdev->ring_lock); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 498 | |
| 499 | if (ring_obj) { |
| 500 | r = radeon_bo_reserve(ring_obj, false); |
| 501 | if (likely(r == 0)) { |
| 502 | radeon_bo_kunmap(ring_obj); |
| 503 | radeon_bo_unpin(ring_obj); |
| 504 | radeon_bo_unreserve(ring_obj); |
| 505 | } |
| 506 | radeon_bo_unref(&ring_obj); |
| 507 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 508 | } |
| 509 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 510 | /* |
| 511 | * Debugfs info |
| 512 | */ |
| 513 | #if defined(CONFIG_DEBUG_FS) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 514 | |
| 515 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
| 516 | { |
| 517 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 518 | struct drm_device *dev = node->minor->dev; |
| 519 | struct radeon_device *rdev = dev->dev_private; |
| 520 | int ridx = *(int*)node->info_ent->data; |
| 521 | struct radeon_ring *ring = &rdev->ring[ridx]; |
| 522 | unsigned count, i, j; |
| 523 | |
| 524 | radeon_ring_free_size(rdev, ring); |
| 525 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
| 526 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); |
| 527 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 528 | if (ring->rptr_save_reg) { |
| 529 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, |
| 530 | RREG32(ring->rptr_save_reg)); |
| 531 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 532 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
| 533 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); |
| 534 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
| 535 | seq_printf(m, "%u dwords in ring\n", count); |
| 536 | i = ring->rptr; |
| 537 | for (j = 0; j <= count; j++) { |
| 538 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
| 539 | i = (i + 1) & ring->ptr_mask; |
| 540 | } |
| 541 | return 0; |
| 542 | } |
| 543 | |
| 544 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
| 545 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
| 546 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
| 547 | |
| 548 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
| 549 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, |
| 550 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, |
| 551 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, |
| 552 | }; |
| 553 | |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 554 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
| 555 | { |
| 556 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 557 | struct drm_device *dev = node->minor->dev; |
| 558 | struct radeon_device *rdev = dev->dev_private; |
| 559 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 560 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 561 | |
| 562 | return 0; |
| 563 | |
| 564 | } |
| 565 | |
| 566 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
| 567 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
| 568 | }; |
| 569 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 570 | #endif |
| 571 | |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 572 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 573 | { |
| 574 | #if defined(CONFIG_DEBUG_FS) |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 575 | unsigned i; |
| 576 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
| 577 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
| 578 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
| 579 | unsigned r; |
| 580 | |
| 581 | if (&rdev->ring[ridx] != ring) |
| 582 | continue; |
| 583 | |
| 584 | r = radeon_debugfs_add_files(rdev, info, 1); |
| 585 | if (r) |
| 586 | return r; |
| 587 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 588 | #endif |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 589 | return 0; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 590 | } |
| 591 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 592 | int radeon_debugfs_sa_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 593 | { |
| 594 | #if defined(CONFIG_DEBUG_FS) |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 595 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 596 | #else |
| 597 | return 0; |
| 598 | #endif |
| 599 | } |