Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 27 | * Christian König |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 28 | */ |
| 29 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "radeon_drm.h" |
| 33 | #include "radeon_reg.h" |
| 34 | #include "radeon.h" |
| 35 | #include "atom.h" |
| 36 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 37 | /* |
| 38 | * IB. |
| 39 | */ |
| 40 | int radeon_debugfs_sa_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 42 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 43 | struct radeon_ib *ib, unsigned size) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 45 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 46 | |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 47 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 49 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 50 | return r; |
| 51 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 52 | |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 53 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
| 54 | if (r) { |
| 55 | return r; |
| 56 | } |
| 57 | |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 58 | ib->ring = ring; |
| 59 | ib->fence = NULL; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 60 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
| 61 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
| 62 | ib->vm_id = 0; |
| 63 | ib->is_const_ib = false; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 64 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
| 65 | ib->sync_to[i] = NULL; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 66 | |
| 67 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | } |
| 69 | |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 70 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 72 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 73 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
| 74 | radeon_fence_unref(&ib->fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | } |
| 76 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
| 78 | { |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 79 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 80 | bool need_sync = false; |
| 81 | int i, r = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 82 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 83 | if (!ib->length_dw || !ring->ready) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 84 | /* TODO: Nothings in the ib we should report. */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 85 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 86 | return -EINVAL; |
| 87 | } |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 88 | |
Dave Airlie | 6cdf658 | 2009-06-29 18:29:13 +1000 | [diff] [blame] | 89 | /* 64 dwords should be enough for fence too */ |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 90 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 91 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 92 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 93 | return r; |
| 94 | } |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 95 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 96 | struct radeon_fence *fence = ib->sync_to[i]; |
| 97 | if (radeon_fence_need_sync(fence, ib->ring)) { |
| 98 | need_sync = true; |
| 99 | radeon_semaphore_sync_rings(rdev, ib->semaphore, |
| 100 | fence->ring, ib->ring); |
| 101 | radeon_fence_note_sync(fence, ib->ring); |
| 102 | } |
| 103 | } |
| 104 | /* immediately free semaphore when we don't need to sync */ |
| 105 | if (!need_sync) { |
| 106 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); |
| 107 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 108 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
| 109 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
| 110 | if (r) { |
| 111 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
| 112 | radeon_ring_unlock_undo(rdev, ring); |
| 113 | return r; |
| 114 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 115 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | int radeon_ib_pool_init(struct radeon_device *rdev) |
| 120 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 121 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 123 | if (rdev->ib_pool_ready) { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 124 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | } |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 126 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 127 | RADEON_IB_POOL_SIZE*64*1024, |
| 128 | RADEON_GEM_DOMAIN_GTT); |
| 129 | if (r) { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 130 | return r; |
| 131 | } |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 132 | |
| 133 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
| 134 | if (r) { |
| 135 | return r; |
| 136 | } |
| 137 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 138 | rdev->ib_pool_ready = true; |
| 139 | if (radeon_debugfs_sa_init(rdev)) { |
| 140 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 142 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
| 146 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 147 | if (rdev->ib_pool_ready) { |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 148 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 149 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
| 150 | rdev->ib_pool_ready = false; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 151 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | } |
| 153 | |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 154 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
| 155 | { |
| 156 | unsigned i; |
| 157 | int r; |
| 158 | |
| 159 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 160 | struct radeon_ring *ring = &rdev->ring[i]; |
| 161 | |
| 162 | if (!ring->ready) |
| 163 | continue; |
| 164 | |
| 165 | r = radeon_ib_test(rdev, i, ring); |
| 166 | if (r) { |
| 167 | ring->ready = false; |
| 168 | |
| 169 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
| 170 | /* oh, oh, that's really bad */ |
| 171 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
| 172 | rdev->accel_working = false; |
| 173 | return r; |
| 174 | |
| 175 | } else { |
| 176 | /* still not good, but we can live with it */ |
| 177 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
| 178 | } |
| 179 | } |
| 180 | } |
| 181 | return 0; |
| 182 | } |
| 183 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 184 | /* |
| 185 | * Ring. |
| 186 | */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 187 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
| 188 | |
| 189 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
| 190 | { |
| 191 | #if DRM_DEBUG_CODE |
| 192 | if (ring->count_dw <= 0) { |
| 193 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 194 | } |
| 195 | #endif |
| 196 | ring->ring[ring->wptr++] = v; |
| 197 | ring->wptr &= ring->ptr_mask; |
| 198 | ring->count_dw--; |
| 199 | ring->ring_free_dw--; |
| 200 | } |
| 201 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 202 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 203 | { |
| 204 | /* r1xx-r5xx only has CP ring */ |
| 205 | if (rdev->family < CHIP_R600) |
| 206 | return RADEON_RING_TYPE_GFX_INDEX; |
| 207 | |
| 208 | if (rdev->family >= CHIP_CAYMAN) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 209 | if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 210 | return CAYMAN_RING_TYPE_CP1_INDEX; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 211 | else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 212 | return CAYMAN_RING_TYPE_CP2_INDEX; |
| 213 | } |
| 214 | return RADEON_RING_TYPE_GFX_INDEX; |
| 215 | } |
| 216 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 217 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 218 | { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 219 | u32 rptr; |
| 220 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 221 | if (rdev->wb.enabled) |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 222 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 223 | else |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 224 | rptr = RREG32(ring->rptr_reg); |
| 225 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | /* This works because ring_size is a power of 2 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 227 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
| 228 | ring->ring_free_dw -= ring->wptr; |
| 229 | ring->ring_free_dw &= ring->ptr_mask; |
| 230 | if (!ring->ring_free_dw) { |
| 231 | ring->ring_free_dw = ring->ring_size / 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | } |
| 233 | } |
| 234 | |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 235 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 236 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | { |
| 238 | int r; |
| 239 | |
| 240 | /* Align requested size with padding so unlock_commit can |
| 241 | * pad safely */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 242 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
| 243 | while (ndw > (ring->ring_free_dw - 1)) { |
| 244 | radeon_ring_free_size(rdev, ring); |
| 245 | if (ndw < ring->ring_free_dw) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 246 | break; |
| 247 | } |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 248 | r = radeon_fence_wait_next_locked(rdev, radeon_ring_index(rdev, ring)); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 249 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 252 | ring->count_dw = ndw; |
| 253 | ring->wptr_old = ring->wptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 257 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 258 | { |
| 259 | int r; |
| 260 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 261 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 262 | r = radeon_ring_alloc(rdev, ring, ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 263 | if (r) { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 264 | mutex_unlock(&rdev->ring_lock); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 265 | return r; |
| 266 | } |
| 267 | return 0; |
| 268 | } |
| 269 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 270 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 272 | /* We pad to match fetch size */ |
Christian König | 07a7133 | 2012-07-07 12:11:32 +0200 | [diff] [blame] | 273 | while (ring->wptr & ring->align_mask) { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 274 | radeon_ring_write(ring, ring->nop); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 275 | } |
| 276 | DRM_MEMORYBARRIER(); |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 277 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 278 | (void)RREG32(ring->wptr_reg); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 279 | } |
| 280 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 281 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 282 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 283 | radeon_ring_commit(rdev, ring); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 284 | mutex_unlock(&rdev->ring_lock); |
| 285 | } |
| 286 | |
| 287 | void radeon_ring_undo(struct radeon_ring *ring) |
| 288 | { |
| 289 | ring->wptr = ring->wptr_old; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 290 | } |
| 291 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 292 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 293 | { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 294 | radeon_ring_undo(ring); |
| 295 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 296 | } |
| 297 | |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 298 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
| 299 | { |
| 300 | int r; |
| 301 | |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 302 | radeon_ring_free_size(rdev, ring); |
| 303 | if (ring->rptr == ring->wptr) { |
| 304 | r = radeon_ring_alloc(rdev, ring, 1); |
| 305 | if (!r) { |
| 306 | radeon_ring_write(ring, ring->nop); |
| 307 | radeon_ring_commit(rdev, ring); |
| 308 | } |
| 309 | } |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 310 | } |
| 311 | |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 312 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
| 313 | { |
| 314 | ring->last_rptr = ring->rptr; |
| 315 | ring->last_activity = jiffies; |
| 316 | } |
| 317 | |
| 318 | /** |
| 319 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
| 320 | * @rdev: radeon device structure |
| 321 | * @ring: radeon_ring structure holding ring information |
| 322 | * |
| 323 | * We don't need to initialize the lockup tracking information as we will either |
| 324 | * have CP rptr to a different value of jiffies wrap around which will force |
| 325 | * initialization of the lockup tracking informations. |
| 326 | * |
| 327 | * A possible false positivie is if we get call after while and last_cp_rptr == |
| 328 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
| 329 | * if the elapsed time since last call is bigger than 2 second than we return |
| 330 | * false and update the tracking information. Due to this the caller must call |
| 331 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
| 332 | * the fencing code should be cautious about that. |
| 333 | * |
| 334 | * Caller should write to the ring to force CP to do something so we don't get |
| 335 | * false positive when CP is just gived nothing to do. |
| 336 | * |
| 337 | **/ |
| 338 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 339 | { |
| 340 | unsigned long cjiffies, elapsed; |
| 341 | uint32_t rptr; |
| 342 | |
| 343 | cjiffies = jiffies; |
| 344 | if (!time_after(cjiffies, ring->last_activity)) { |
| 345 | /* likely a wrap around */ |
| 346 | radeon_ring_lockup_update(ring); |
| 347 | return false; |
| 348 | } |
| 349 | rptr = RREG32(ring->rptr_reg); |
| 350 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
| 351 | if (ring->rptr != ring->last_rptr) { |
| 352 | /* CP is still working no lockup */ |
| 353 | radeon_ring_lockup_update(ring); |
| 354 | return false; |
| 355 | } |
| 356 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 357 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 358 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| 359 | return true; |
| 360 | } |
| 361 | /* give a chance to the GPU ... */ |
| 362 | return false; |
| 363 | } |
| 364 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 365 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 366 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 367 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 368 | { |
| 369 | int r; |
| 370 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 371 | ring->ring_size = ring_size; |
| 372 | ring->rptr_offs = rptr_offs; |
| 373 | ring->rptr_reg = rptr_reg; |
| 374 | ring->wptr_reg = wptr_reg; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 375 | ring->ptr_reg_shift = ptr_reg_shift; |
| 376 | ring->ptr_reg_mask = ptr_reg_mask; |
| 377 | ring->nop = nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 378 | /* Allocate ring buffer */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 379 | if (ring->ring_obj == NULL) { |
| 380 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 381 | RADEON_GEM_DOMAIN_GTT, |
| 382 | NULL, &ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 384 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 385 | return r; |
| 386 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 387 | r = radeon_bo_reserve(ring->ring_obj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 388 | if (unlikely(r != 0)) |
| 389 | return r; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 390 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
| 391 | &ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 392 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 393 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 394 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 395 | return r; |
| 396 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 397 | r = radeon_bo_kmap(ring->ring_obj, |
| 398 | (void **)&ring->ring); |
| 399 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 400 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 401 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 402 | return r; |
| 403 | } |
| 404 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 405 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
| 406 | ring->ring_free_dw = ring->ring_size / 4; |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 407 | if (radeon_debugfs_ring_init(rdev, ring)) { |
| 408 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
| 409 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 410 | return 0; |
| 411 | } |
| 412 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 413 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 414 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 415 | int r; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 416 | struct radeon_bo *ring_obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 417 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 418 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 419 | ring_obj = ring->ring_obj; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 420 | ring->ready = false; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 421 | ring->ring = NULL; |
| 422 | ring->ring_obj = NULL; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 423 | mutex_unlock(&rdev->ring_lock); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 424 | |
| 425 | if (ring_obj) { |
| 426 | r = radeon_bo_reserve(ring_obj, false); |
| 427 | if (likely(r == 0)) { |
| 428 | radeon_bo_kunmap(ring_obj); |
| 429 | radeon_bo_unpin(ring_obj); |
| 430 | radeon_bo_unreserve(ring_obj); |
| 431 | } |
| 432 | radeon_bo_unref(&ring_obj); |
| 433 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 434 | } |
| 435 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 436 | /* |
| 437 | * Debugfs info |
| 438 | */ |
| 439 | #if defined(CONFIG_DEBUG_FS) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 440 | |
| 441 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
| 442 | { |
| 443 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 444 | struct drm_device *dev = node->minor->dev; |
| 445 | struct radeon_device *rdev = dev->dev_private; |
| 446 | int ridx = *(int*)node->info_ent->data; |
| 447 | struct radeon_ring *ring = &rdev->ring[ridx]; |
| 448 | unsigned count, i, j; |
| 449 | |
| 450 | radeon_ring_free_size(rdev, ring); |
| 451 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
| 452 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); |
| 453 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame^] | 454 | if (ring->rptr_save_reg) { |
| 455 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, |
| 456 | RREG32(ring->rptr_save_reg)); |
| 457 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 458 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
| 459 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); |
| 460 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
| 461 | seq_printf(m, "%u dwords in ring\n", count); |
| 462 | i = ring->rptr; |
| 463 | for (j = 0; j <= count; j++) { |
| 464 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
| 465 | i = (i + 1) & ring->ptr_mask; |
| 466 | } |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
| 471 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
| 472 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
| 473 | |
| 474 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
| 475 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, |
| 476 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, |
| 477 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, |
| 478 | }; |
| 479 | |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 480 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
| 481 | { |
| 482 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 483 | struct drm_device *dev = node->minor->dev; |
| 484 | struct radeon_device *rdev = dev->dev_private; |
| 485 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 486 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 487 | |
| 488 | return 0; |
| 489 | |
| 490 | } |
| 491 | |
| 492 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
| 493 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
| 494 | }; |
| 495 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 496 | #endif |
| 497 | |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 498 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 499 | { |
| 500 | #if defined(CONFIG_DEBUG_FS) |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 501 | unsigned i; |
| 502 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
| 503 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
| 504 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
| 505 | unsigned r; |
| 506 | |
| 507 | if (&rdev->ring[ridx] != ring) |
| 508 | continue; |
| 509 | |
| 510 | r = radeon_debugfs_add_files(rdev, info, 1); |
| 511 | if (r) |
| 512 | return r; |
| 513 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 514 | #endif |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 515 | return 0; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 516 | } |
| 517 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 518 | int radeon_debugfs_sa_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 519 | { |
| 520 | #if defined(CONFIG_DEBUG_FS) |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 521 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 522 | #else |
| 523 | return 0; |
| 524 | #endif |
| 525 | } |