Kuninori Morimoto | 9e288ce | 2018-09-25 09:34:05 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 3 | config CLK_RENESAS |
| 4 | bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS |
| 5 | default y if ARCH_RENESAS |
| 6 | select CLK_EMEV2 if ARCH_EMEV2 |
| 7 | select CLK_RZA1 if ARCH_R7S72100 |
Chris Brandt | fde35c9 | 2018-09-07 11:58:49 -0500 | [diff] [blame] | 8 | select CLK_R7S9210 if ARCH_R7S9210 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 9 | select CLK_R8A73A4 if ARCH_R8A73A4 |
| 10 | select CLK_R8A7740 if ARCH_R8A7740 |
Lad Prabhakar | e8208a7 | 2020-04-27 15:41:00 +0100 | [diff] [blame] | 11 | select CLK_R8A7742 if ARCH_R8A7742 |
Biju Das | 016f966 | 2018-09-11 11:12:49 +0100 | [diff] [blame] | 12 | select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 13 | select CLK_R8A7745 if ARCH_R8A7745 |
Biju Das | 5bf2fbb | 2018-03-28 20:26:12 +0100 | [diff] [blame] | 14 | select CLK_R8A77470 if ARCH_R8A77470 |
Biju Das | 331a53e | 2018-08-02 15:57:51 +0100 | [diff] [blame] | 15 | select CLK_R8A774A1 if ARCH_R8A774A1 |
Biju Das | 0b9f1c2 | 2019-09-19 09:17:14 +0100 | [diff] [blame] | 16 | select CLK_R8A774B1 if ARCH_R8A774B1 |
Fabrizio Castro | 906e0a4 | 2018-09-12 11:41:53 +0100 | [diff] [blame] | 17 | select CLK_R8A774C0 if ARCH_R8A774C0 |
Marian-Cristian Rotariu | c8a53fa | 2020-07-07 17:18:10 +0100 | [diff] [blame] | 18 | select CLK_R8A774E1 if ARCH_R8A774E1 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 19 | select CLK_R8A7778 if ARCH_R8A7778 |
| 20 | select CLK_R8A7779 if ARCH_R8A7779 |
| 21 | select CLK_R8A7790 if ARCH_R8A7790 |
| 22 | select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 |
| 23 | select CLK_R8A7792 if ARCH_R8A7792 |
| 24 | select CLK_R8A7794 if ARCH_R8A7794 |
Geert Uytterhoeven | 068e7f8 | 2020-02-18 12:25:25 +0100 | [diff] [blame] | 25 | select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 |
Geert Uytterhoeven | 03975b7 | 2019-12-11 11:02:20 +0100 | [diff] [blame] | 26 | select CLK_R8A77960 if ARCH_R8A77960 |
Geert Uytterhoeven | 2ba738d | 2019-10-23 14:29:41 +0200 | [diff] [blame] | 27 | select CLK_R8A77961 if ARCH_R8A77961 |
Jacopo Mondi | 7ce36da9 | 2018-02-20 16:12:03 +0100 | [diff] [blame] | 28 | select CLK_R8A77965 if ARCH_R8A77965 |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 29 | select CLK_R8A77970 if ARCH_R8A77970 |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame] | 30 | select CLK_R8A77980 if ARCH_R8A77980 |
Yoshihiro Shimoda | 3570a2a | 2018-04-20 21:27:44 +0900 | [diff] [blame] | 31 | select CLK_R8A77990 if ARCH_R8A77990 |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 32 | select CLK_R8A77995 if ARCH_R8A77995 |
Yoshihiro Shimoda | 17bcc80 | 2020-09-11 16:43:51 +0900 | [diff] [blame] | 33 | select CLK_R8A779A0 if ARCH_R8A779A0 |
Michel Pollet | 4c3d885 | 2018-06-14 11:56:34 +0100 | [diff] [blame] | 34 | select CLK_R9A06G032 if ARCH_R9A06G032 |
Lad Prabhakar | 17f0ff3 | 2021-06-09 16:32:28 +0100 | [diff] [blame] | 35 | select CLK_R9A07G044 if ARCH_R9A07G044 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 36 | select CLK_SH73A0 if ARCH_SH73A0 |
| 37 | |
| 38 | if CLK_RENESAS |
| 39 | |
| 40 | # SoC |
| 41 | config CLK_EMEV2 |
| 42 | bool "Emma Mobile EV2 clock support" if COMPILE_TEST |
| 43 | |
| 44 | config CLK_RZA1 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 45 | bool "RZ/A1H clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 46 | select CLK_RENESAS_CPG_MSTP |
| 47 | |
Chris Brandt | fde35c9 | 2018-09-07 11:58:49 -0500 | [diff] [blame] | 48 | config CLK_R7S9210 |
| 49 | bool "RZ/A2 clock support" if COMPILE_TEST |
| 50 | select CLK_RENESAS_CPG_MSSR |
| 51 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 52 | config CLK_R8A73A4 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 53 | bool "R-Mobile APE6 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 54 | select CLK_RENESAS_CPG_MSTP |
| 55 | select CLK_RENESAS_DIV6 |
| 56 | |
| 57 | config CLK_R8A7740 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 58 | bool "R-Mobile A1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 59 | select CLK_RENESAS_CPG_MSTP |
| 60 | select CLK_RENESAS_DIV6 |
| 61 | |
Lad Prabhakar | e8208a7 | 2020-04-27 15:41:00 +0100 | [diff] [blame] | 62 | config CLK_R8A7742 |
| 63 | bool "RZ/G1H clock support" if COMPILE_TEST |
| 64 | select CLK_RCAR_GEN2_CPG |
| 65 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 66 | config CLK_R8A7743 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 67 | bool "RZ/G1M clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 68 | select CLK_RCAR_GEN2_CPG |
| 69 | |
| 70 | config CLK_R8A7745 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 71 | bool "RZ/G1E clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 72 | select CLK_RCAR_GEN2_CPG |
| 73 | |
Biju Das | 5bf2fbb | 2018-03-28 20:26:12 +0100 | [diff] [blame] | 74 | config CLK_R8A77470 |
| 75 | bool "RZ/G1C clock support" if COMPILE_TEST |
| 76 | select CLK_RCAR_GEN2_CPG |
| 77 | |
Biju Das | 331a53e | 2018-08-02 15:57:51 +0100 | [diff] [blame] | 78 | config CLK_R8A774A1 |
| 79 | bool "RZ/G2M clock support" if COMPILE_TEST |
| 80 | select CLK_RCAR_GEN3_CPG |
| 81 | |
Biju Das | 0b9f1c2 | 2019-09-19 09:17:14 +0100 | [diff] [blame] | 82 | config CLK_R8A774B1 |
| 83 | bool "RZ/G2N clock support" if COMPILE_TEST |
| 84 | select CLK_RCAR_GEN3_CPG |
| 85 | |
Fabrizio Castro | 906e0a4 | 2018-09-12 11:41:53 +0100 | [diff] [blame] | 86 | config CLK_R8A774C0 |
| 87 | bool "RZ/G2E clock support" if COMPILE_TEST |
| 88 | select CLK_RCAR_GEN3_CPG |
| 89 | |
Marian-Cristian Rotariu | c8a53fa | 2020-07-07 17:18:10 +0100 | [diff] [blame] | 90 | config CLK_R8A774E1 |
| 91 | bool "RZ/G2H clock support" if COMPILE_TEST |
| 92 | select CLK_RCAR_GEN3_CPG |
| 93 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 94 | config CLK_R8A7778 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 95 | bool "R-Car M1A clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 96 | select CLK_RENESAS_CPG_MSTP |
| 97 | |
| 98 | config CLK_R8A7779 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 99 | bool "R-Car H1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 100 | select CLK_RENESAS_CPG_MSTP |
| 101 | |
| 102 | config CLK_R8A7790 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 103 | bool "R-Car H2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 104 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 105 | |
| 106 | config CLK_R8A7791 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 107 | bool "R-Car M2-W/N clock support" if COMPILE_TEST |
Geert Uytterhoeven | 6449ab8 | 2015-10-16 11:41:19 +0200 | [diff] [blame] | 108 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 109 | |
| 110 | config CLK_R8A7792 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 111 | bool "R-Car V2H clock support" if COMPILE_TEST |
Geert Uytterhoeven | fd3c2f3 | 2017-03-19 18:08:59 +0100 | [diff] [blame] | 112 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 113 | |
| 114 | config CLK_R8A7794 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 115 | bool "R-Car E2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 2d75588 | 2017-03-19 18:12:51 +0100 | [diff] [blame] | 116 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 117 | |
| 118 | config CLK_R8A7795 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 119 | bool "R-Car H3 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 120 | select CLK_RCAR_GEN3_CPG |
| 121 | |
Geert Uytterhoeven | 92d1eba | 2019-10-23 14:29:40 +0200 | [diff] [blame] | 122 | config CLK_R8A77960 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 123 | bool "R-Car M3-W clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 124 | select CLK_RCAR_GEN3_CPG |
| 125 | |
Geert Uytterhoeven | 2ba738d | 2019-10-23 14:29:41 +0200 | [diff] [blame] | 126 | config CLK_R8A77961 |
| 127 | bool "R-Car M3-W+ clock support" if COMPILE_TEST |
| 128 | select CLK_RCAR_GEN3_CPG |
| 129 | |
Jacopo Mondi | 7ce36da9 | 2018-02-20 16:12:03 +0100 | [diff] [blame] | 130 | config CLK_R8A77965 |
| 131 | bool "R-Car M3-N clock support" if COMPILE_TEST |
| 132 | select CLK_RCAR_GEN3_CPG |
| 133 | |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 134 | config CLK_R8A77970 |
| 135 | bool "R-Car V3M clock support" if COMPILE_TEST |
| 136 | select CLK_RCAR_GEN3_CPG |
| 137 | |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame] | 138 | config CLK_R8A77980 |
| 139 | bool "R-Car V3H clock support" if COMPILE_TEST |
| 140 | select CLK_RCAR_GEN3_CPG |
| 141 | |
Yoshihiro Shimoda | 3570a2a | 2018-04-20 21:27:44 +0900 | [diff] [blame] | 142 | config CLK_R8A77990 |
| 143 | bool "R-Car E3 clock support" if COMPILE_TEST |
| 144 | select CLK_RCAR_GEN3_CPG |
| 145 | |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 146 | config CLK_R8A77995 |
| 147 | bool "R-Car D3 clock support" if COMPILE_TEST |
| 148 | select CLK_RCAR_GEN3_CPG |
| 149 | |
Yoshihiro Shimoda | 17bcc80 | 2020-09-11 16:43:51 +0900 | [diff] [blame] | 150 | config CLK_R8A779A0 |
| 151 | bool "R-Car V3U clock support" if COMPILE_TEST |
Wolfram Sang | 7925017 | 2020-12-27 18:41:58 +0100 | [diff] [blame] | 152 | select CLK_RCAR_CPG_LIB |
Yoshihiro Shimoda | 17bcc80 | 2020-09-11 16:43:51 +0900 | [diff] [blame] | 153 | select CLK_RENESAS_CPG_MSSR |
| 154 | |
Michel Pollet | 4c3d885 | 2018-06-14 11:56:34 +0100 | [diff] [blame] | 155 | config CLK_R9A06G032 |
Geert Uytterhoeven | e8425dd | 2021-08-11 11:06:40 +0200 | [diff] [blame] | 156 | bool "RZ/N1D clock support" if COMPILE_TEST |
Michel Pollet | 4c3d885 | 2018-06-14 11:56:34 +0100 | [diff] [blame] | 157 | |
Lad Prabhakar | 17f0ff3 | 2021-06-09 16:32:28 +0100 | [diff] [blame] | 158 | config CLK_R9A07G044 |
| 159 | bool "RZ/G2L clock support" if COMPILE_TEST |
| 160 | select CLK_RZG2L |
| 161 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 162 | config CLK_SH73A0 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 163 | bool "SH-Mobile AG5 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 164 | select CLK_RENESAS_CPG_MSTP |
| 165 | select CLK_RENESAS_DIV6 |
| 166 | |
| 167 | |
| 168 | # Family |
Wolfram Sang | 8bb67d8 | 2020-12-27 18:41:57 +0100 | [diff] [blame] | 169 | config CLK_RCAR_CPG_LIB |
| 170 | bool "CPG/MSSR library functions" if COMPILE_TEST |
| 171 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 172 | config CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 173 | bool "R-Car Gen2 CPG clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 174 | select CLK_RENESAS_CPG_MSSR |
| 175 | |
| 176 | config CLK_RCAR_GEN3_CPG |
Lad Prabhakar | 15d683e | 2020-09-11 11:17:03 +0100 | [diff] [blame] | 177 | bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST |
Wolfram Sang | 8bb67d8 | 2020-12-27 18:41:57 +0100 | [diff] [blame] | 178 | select CLK_RCAR_CPG_LIB |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 179 | select CLK_RENESAS_CPG_MSSR |
| 180 | |
Yoshihiro Shimoda | 311accb | 2017-07-25 15:26:27 +0900 | [diff] [blame] | 181 | config CLK_RCAR_USB2_CLOCK_SEL |
| 182 | bool "Renesas R-Car USB2 clock selector support" |
| 183 | depends on ARCH_RENESAS || COMPILE_TEST |
Yoshihiro Shimoda | 1ab4f43 | 2020-03-04 15:42:17 +0900 | [diff] [blame] | 184 | select RESET_CONTROLLER |
Yoshihiro Shimoda | 311accb | 2017-07-25 15:26:27 +0900 | [diff] [blame] | 185 | help |
| 186 | This is a driver for R-Car USB2 clock selector |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 187 | |
Lad Prabhakar | ef3c613 | 2021-06-09 16:32:27 +0100 | [diff] [blame] | 188 | config CLK_RZG2L |
| 189 | bool "Renesas RZ/G2L family clock support" if COMPILE_TEST |
| 190 | select RESET_CONTROLLER |
| 191 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 192 | # Generic |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 193 | config CLK_RENESAS_CPG_MSSR |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 194 | bool "CPG/MSSR clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 195 | select CLK_RENESAS_DIV6 |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 196 | |
| 197 | config CLK_RENESAS_CPG_MSTP |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 198 | bool "MSTP clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 199 | |
| 200 | config CLK_RENESAS_DIV6 |
| 201 | bool "DIV6 clock support" if COMPILE_TEST |
| 202 | |
| 203 | endif # CLK_RENESAS |