blob: 6d0280751bb16e899772e53c223268e691a7e077 [file] [log] [blame]
Kuninori Morimoto9e288ce2018-09-25 09:34:05 +02001# SPDX-License-Identifier: GPL-2.0
2
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02003config CLK_RENESAS
4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
5 default y if ARCH_RENESAS
6 select CLK_EMEV2 if ARCH_EMEV2
7 select CLK_RZA1 if ARCH_R7S72100
Chris Brandtfde35c92018-09-07 11:58:49 -05008 select CLK_R7S9210 if ARCH_R7S9210
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02009 select CLK_R8A73A4 if ARCH_R8A73A4
10 select CLK_R8A7740 if ARCH_R8A7740
Lad Prabhakare8208a72020-04-27 15:41:00 +010011 select CLK_R8A7742 if ARCH_R8A7742
Biju Das016f9662018-09-11 11:12:49 +010012 select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020013 select CLK_R8A7745 if ARCH_R8A7745
Biju Das5bf2fbb2018-03-28 20:26:12 +010014 select CLK_R8A77470 if ARCH_R8A77470
Biju Das331a53e2018-08-02 15:57:51 +010015 select CLK_R8A774A1 if ARCH_R8A774A1
Biju Das0b9f1c22019-09-19 09:17:14 +010016 select CLK_R8A774B1 if ARCH_R8A774B1
Fabrizio Castro906e0a42018-09-12 11:41:53 +010017 select CLK_R8A774C0 if ARCH_R8A774C0
Marian-Cristian Rotariuc8a53fa2020-07-07 17:18:10 +010018 select CLK_R8A774E1 if ARCH_R8A774E1
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020019 select CLK_R8A7778 if ARCH_R8A7778
20 select CLK_R8A7779 if ARCH_R8A7779
21 select CLK_R8A7790 if ARCH_R8A7790
22 select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
23 select CLK_R8A7792 if ARCH_R8A7792
24 select CLK_R8A7794 if ARCH_R8A7794
Geert Uytterhoeven068e7f82020-02-18 12:25:25 +010025 select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
Geert Uytterhoeven03975b72019-12-11 11:02:20 +010026 select CLK_R8A77960 if ARCH_R8A77960
Geert Uytterhoeven2ba738d2019-10-23 14:29:41 +020027 select CLK_R8A77961 if ARCH_R8A77961
Jacopo Mondi7ce36da92018-02-20 16:12:03 +010028 select CLK_R8A77965 if ARCH_R8A77965
Sergei Shtylyov8d46e282017-09-09 00:34:20 +030029 select CLK_R8A77970 if ARCH_R8A77970
Sergei Shtylyovce157832018-02-15 14:58:45 +030030 select CLK_R8A77980 if ARCH_R8A77980
Yoshihiro Shimoda3570a2a2018-04-20 21:27:44 +090031 select CLK_R8A77990 if ARCH_R8A77990
Geert Uytterhoevend71e8512017-07-12 10:47:36 +020032 select CLK_R8A77995 if ARCH_R8A77995
Yoshihiro Shimoda17bcc802020-09-11 16:43:51 +090033 select CLK_R8A779A0 if ARCH_R8A779A0
Michel Pollet4c3d8852018-06-14 11:56:34 +010034 select CLK_R9A06G032 if ARCH_R9A06G032
Lad Prabhakar17f0ff32021-06-09 16:32:28 +010035 select CLK_R9A07G044 if ARCH_R9A07G044
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020036 select CLK_SH73A0 if ARCH_SH73A0
37
38if CLK_RENESAS
39
40# SoC
41config CLK_EMEV2
42 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
43
44config CLK_RZA1
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020045 bool "RZ/A1H clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020046 select CLK_RENESAS_CPG_MSTP
47
Chris Brandtfde35c92018-09-07 11:58:49 -050048config CLK_R7S9210
49 bool "RZ/A2 clock support" if COMPILE_TEST
50 select CLK_RENESAS_CPG_MSSR
51
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020052config CLK_R8A73A4
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020053 bool "R-Mobile APE6 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020054 select CLK_RENESAS_CPG_MSTP
55 select CLK_RENESAS_DIV6
56
57config CLK_R8A7740
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020058 bool "R-Mobile A1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020059 select CLK_RENESAS_CPG_MSTP
60 select CLK_RENESAS_DIV6
61
Lad Prabhakare8208a72020-04-27 15:41:00 +010062config CLK_R8A7742
63 bool "RZ/G1H clock support" if COMPILE_TEST
64 select CLK_RCAR_GEN2_CPG
65
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020066config CLK_R8A7743
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020067 bool "RZ/G1M clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020068 select CLK_RCAR_GEN2_CPG
69
70config CLK_R8A7745
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020071 bool "RZ/G1E clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020072 select CLK_RCAR_GEN2_CPG
73
Biju Das5bf2fbb2018-03-28 20:26:12 +010074config CLK_R8A77470
75 bool "RZ/G1C clock support" if COMPILE_TEST
76 select CLK_RCAR_GEN2_CPG
77
Biju Das331a53e2018-08-02 15:57:51 +010078config CLK_R8A774A1
79 bool "RZ/G2M clock support" if COMPILE_TEST
80 select CLK_RCAR_GEN3_CPG
81
Biju Das0b9f1c22019-09-19 09:17:14 +010082config CLK_R8A774B1
83 bool "RZ/G2N clock support" if COMPILE_TEST
84 select CLK_RCAR_GEN3_CPG
85
Fabrizio Castro906e0a42018-09-12 11:41:53 +010086config CLK_R8A774C0
87 bool "RZ/G2E clock support" if COMPILE_TEST
88 select CLK_RCAR_GEN3_CPG
89
Marian-Cristian Rotariuc8a53fa2020-07-07 17:18:10 +010090config CLK_R8A774E1
91 bool "RZ/G2H clock support" if COMPILE_TEST
92 select CLK_RCAR_GEN3_CPG
93
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020094config CLK_R8A7778
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020095 bool "R-Car M1A clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020096 select CLK_RENESAS_CPG_MSTP
97
98config CLK_R8A7779
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020099 bool "R-Car H1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200100 select CLK_RENESAS_CPG_MSTP
101
102config CLK_R8A7790
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200103 bool "R-Car H2 clock support" if COMPILE_TEST
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +0100104 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200105
106config CLK_R8A7791
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200107 bool "R-Car M2-W/N clock support" if COMPILE_TEST
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +0200108 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200109
110config CLK_R8A7792
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200111 bool "R-Car V2H clock support" if COMPILE_TEST
Geert Uytterhoevenfd3c2f32017-03-19 18:08:59 +0100112 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200113
114config CLK_R8A7794
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200115 bool "R-Car E2 clock support" if COMPILE_TEST
Geert Uytterhoeven2d755882017-03-19 18:12:51 +0100116 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200117
118config CLK_R8A7795
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200119 bool "R-Car H3 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200120 select CLK_RCAR_GEN3_CPG
121
Geert Uytterhoeven92d1eba2019-10-23 14:29:40 +0200122config CLK_R8A77960
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200123 bool "R-Car M3-W clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200124 select CLK_RCAR_GEN3_CPG
125
Geert Uytterhoeven2ba738d2019-10-23 14:29:41 +0200126config CLK_R8A77961
127 bool "R-Car M3-W+ clock support" if COMPILE_TEST
128 select CLK_RCAR_GEN3_CPG
129
Jacopo Mondi7ce36da92018-02-20 16:12:03 +0100130config CLK_R8A77965
131 bool "R-Car M3-N clock support" if COMPILE_TEST
132 select CLK_RCAR_GEN3_CPG
133
Sergei Shtylyov8d46e282017-09-09 00:34:20 +0300134config CLK_R8A77970
135 bool "R-Car V3M clock support" if COMPILE_TEST
136 select CLK_RCAR_GEN3_CPG
137
Sergei Shtylyovce157832018-02-15 14:58:45 +0300138config CLK_R8A77980
139 bool "R-Car V3H clock support" if COMPILE_TEST
140 select CLK_RCAR_GEN3_CPG
141
Yoshihiro Shimoda3570a2a2018-04-20 21:27:44 +0900142config CLK_R8A77990
143 bool "R-Car E3 clock support" if COMPILE_TEST
144 select CLK_RCAR_GEN3_CPG
145
Geert Uytterhoevend71e8512017-07-12 10:47:36 +0200146config CLK_R8A77995
147 bool "R-Car D3 clock support" if COMPILE_TEST
148 select CLK_RCAR_GEN3_CPG
149
Yoshihiro Shimoda17bcc802020-09-11 16:43:51 +0900150config CLK_R8A779A0
151 bool "R-Car V3U clock support" if COMPILE_TEST
Wolfram Sang79250172020-12-27 18:41:58 +0100152 select CLK_RCAR_CPG_LIB
Yoshihiro Shimoda17bcc802020-09-11 16:43:51 +0900153 select CLK_RENESAS_CPG_MSSR
154
Michel Pollet4c3d8852018-06-14 11:56:34 +0100155config CLK_R9A06G032
Geert Uytterhoevene8425dd2021-08-11 11:06:40 +0200156 bool "RZ/N1D clock support" if COMPILE_TEST
Michel Pollet4c3d8852018-06-14 11:56:34 +0100157
Lad Prabhakar17f0ff32021-06-09 16:32:28 +0100158config CLK_R9A07G044
159 bool "RZ/G2L clock support" if COMPILE_TEST
160 select CLK_RZG2L
161
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200162config CLK_SH73A0
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200163 bool "SH-Mobile AG5 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200164 select CLK_RENESAS_CPG_MSTP
165 select CLK_RENESAS_DIV6
166
167
168# Family
Wolfram Sang8bb67d82020-12-27 18:41:57 +0100169config CLK_RCAR_CPG_LIB
170 bool "CPG/MSSR library functions" if COMPILE_TEST
171
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200172config CLK_RCAR_GEN2_CPG
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200173 bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200174 select CLK_RENESAS_CPG_MSSR
175
176config CLK_RCAR_GEN3_CPG
Lad Prabhakar15d683e2020-09-11 11:17:03 +0100177 bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST
Wolfram Sang8bb67d82020-12-27 18:41:57 +0100178 select CLK_RCAR_CPG_LIB
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200179 select CLK_RENESAS_CPG_MSSR
180
Yoshihiro Shimoda311accb2017-07-25 15:26:27 +0900181config CLK_RCAR_USB2_CLOCK_SEL
182 bool "Renesas R-Car USB2 clock selector support"
183 depends on ARCH_RENESAS || COMPILE_TEST
Yoshihiro Shimoda1ab4f432020-03-04 15:42:17 +0900184 select RESET_CONTROLLER
Yoshihiro Shimoda311accb2017-07-25 15:26:27 +0900185 help
186 This is a driver for R-Car USB2 clock selector
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200187
Lad Prabhakaref3c6132021-06-09 16:32:27 +0100188config CLK_RZG2L
189 bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
190 select RESET_CONTROLLER
191
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200192# Generic
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200193config CLK_RENESAS_CPG_MSSR
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200194 bool "CPG/MSSR clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200195 select CLK_RENESAS_DIV6
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200196
197config CLK_RENESAS_CPG_MSTP
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200198 bool "MSTP clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200199
200config CLK_RENESAS_DIV6
201 bool "DIV6 clock support" if COMPILE_TEST
202
203endif # CLK_RENESAS