Kuninori Morimoto | 9e288ce | 2018-09-25 09:34:05 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 3 | config CLK_RENESAS |
| 4 | bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS |
| 5 | default y if ARCH_RENESAS |
| 6 | select CLK_EMEV2 if ARCH_EMEV2 |
| 7 | select CLK_RZA1 if ARCH_R7S72100 |
Chris Brandt | fde35c9 | 2018-09-07 11:58:49 -0500 | [diff] [blame] | 8 | select CLK_R7S9210 if ARCH_R7S9210 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 9 | select CLK_R8A73A4 if ARCH_R8A73A4 |
| 10 | select CLK_R8A7740 if ARCH_R8A7740 |
Biju Das | 016f966 | 2018-09-11 11:12:49 +0100 | [diff] [blame] | 11 | select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 12 | select CLK_R8A7745 if ARCH_R8A7745 |
Biju Das | 5bf2fbb | 2018-03-28 20:26:12 +0100 | [diff] [blame] | 13 | select CLK_R8A77470 if ARCH_R8A77470 |
Biju Das | 331a53e | 2018-08-02 15:57:51 +0100 | [diff] [blame] | 14 | select CLK_R8A774A1 if ARCH_R8A774A1 |
Biju Das | 0b9f1c2 | 2019-09-19 09:17:14 +0100 | [diff] [blame] | 15 | select CLK_R8A774B1 if ARCH_R8A774B1 |
Fabrizio Castro | 906e0a4 | 2018-09-12 11:41:53 +0100 | [diff] [blame] | 16 | select CLK_R8A774C0 if ARCH_R8A774C0 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 17 | select CLK_R8A7778 if ARCH_R8A7778 |
| 18 | select CLK_R8A7779 if ARCH_R8A7779 |
| 19 | select CLK_R8A7790 if ARCH_R8A7790 |
| 20 | select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 |
| 21 | select CLK_R8A7792 if ARCH_R8A7792 |
| 22 | select CLK_R8A7794 if ARCH_R8A7794 |
Geert Uytterhoeven | 068e7f8 | 2020-02-18 12:25:25 +0100 | [diff] [blame] | 23 | select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 |
Geert Uytterhoeven | 03975b7 | 2019-12-11 11:02:20 +0100 | [diff] [blame] | 24 | select CLK_R8A77960 if ARCH_R8A77960 |
Geert Uytterhoeven | 2ba738d | 2019-10-23 14:29:41 +0200 | [diff] [blame] | 25 | select CLK_R8A77961 if ARCH_R8A77961 |
Jacopo Mondi | 7ce36da9 | 2018-02-20 16:12:03 +0100 | [diff] [blame] | 26 | select CLK_R8A77965 if ARCH_R8A77965 |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 27 | select CLK_R8A77970 if ARCH_R8A77970 |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame] | 28 | select CLK_R8A77980 if ARCH_R8A77980 |
Yoshihiro Shimoda | 3570a2a | 2018-04-20 21:27:44 +0900 | [diff] [blame] | 29 | select CLK_R8A77990 if ARCH_R8A77990 |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 30 | select CLK_R8A77995 if ARCH_R8A77995 |
Michel Pollet | 4c3d885 | 2018-06-14 11:56:34 +0100 | [diff] [blame] | 31 | select CLK_R9A06G032 if ARCH_R9A06G032 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 32 | select CLK_SH73A0 if ARCH_SH73A0 |
| 33 | |
| 34 | if CLK_RENESAS |
| 35 | |
| 36 | # SoC |
| 37 | config CLK_EMEV2 |
| 38 | bool "Emma Mobile EV2 clock support" if COMPILE_TEST |
| 39 | |
| 40 | config CLK_RZA1 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 41 | bool "RZ/A1H clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 42 | select CLK_RENESAS_CPG_MSTP |
| 43 | |
Chris Brandt | fde35c9 | 2018-09-07 11:58:49 -0500 | [diff] [blame] | 44 | config CLK_R7S9210 |
| 45 | bool "RZ/A2 clock support" if COMPILE_TEST |
| 46 | select CLK_RENESAS_CPG_MSSR |
| 47 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 48 | config CLK_R8A73A4 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 49 | bool "R-Mobile APE6 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 50 | select CLK_RENESAS_CPG_MSTP |
| 51 | select CLK_RENESAS_DIV6 |
| 52 | |
| 53 | config CLK_R8A7740 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 54 | bool "R-Mobile A1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 55 | select CLK_RENESAS_CPG_MSTP |
| 56 | select CLK_RENESAS_DIV6 |
| 57 | |
| 58 | config CLK_R8A7743 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 59 | bool "RZ/G1M clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 60 | select CLK_RCAR_GEN2_CPG |
| 61 | |
| 62 | config CLK_R8A7745 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 63 | bool "RZ/G1E clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 64 | select CLK_RCAR_GEN2_CPG |
| 65 | |
Biju Das | 5bf2fbb | 2018-03-28 20:26:12 +0100 | [diff] [blame] | 66 | config CLK_R8A77470 |
| 67 | bool "RZ/G1C clock support" if COMPILE_TEST |
| 68 | select CLK_RCAR_GEN2_CPG |
| 69 | |
Biju Das | 331a53e | 2018-08-02 15:57:51 +0100 | [diff] [blame] | 70 | config CLK_R8A774A1 |
| 71 | bool "RZ/G2M clock support" if COMPILE_TEST |
| 72 | select CLK_RCAR_GEN3_CPG |
| 73 | |
Biju Das | 0b9f1c2 | 2019-09-19 09:17:14 +0100 | [diff] [blame] | 74 | config CLK_R8A774B1 |
| 75 | bool "RZ/G2N clock support" if COMPILE_TEST |
| 76 | select CLK_RCAR_GEN3_CPG |
| 77 | |
Fabrizio Castro | 906e0a4 | 2018-09-12 11:41:53 +0100 | [diff] [blame] | 78 | config CLK_R8A774C0 |
| 79 | bool "RZ/G2E clock support" if COMPILE_TEST |
| 80 | select CLK_RCAR_GEN3_CPG |
| 81 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 82 | config CLK_R8A7778 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 83 | bool "R-Car M1A clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 84 | select CLK_RENESAS_CPG_MSTP |
| 85 | |
| 86 | config CLK_R8A7779 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 87 | bool "R-Car H1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 88 | select CLK_RENESAS_CPG_MSTP |
| 89 | |
| 90 | config CLK_R8A7790 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 91 | bool "R-Car H2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 92 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 93 | select CLK_RENESAS_DIV6 |
| 94 | |
| 95 | config CLK_R8A7791 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 96 | bool "R-Car M2-W/N clock support" if COMPILE_TEST |
Geert Uytterhoeven | 6449ab8 | 2015-10-16 11:41:19 +0200 | [diff] [blame] | 97 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 98 | select CLK_RENESAS_DIV6 |
| 99 | |
| 100 | config CLK_R8A7792 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 101 | bool "R-Car V2H clock support" if COMPILE_TEST |
Geert Uytterhoeven | fd3c2f3 | 2017-03-19 18:08:59 +0100 | [diff] [blame] | 102 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 103 | |
| 104 | config CLK_R8A7794 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 105 | bool "R-Car E2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 2d75588 | 2017-03-19 18:12:51 +0100 | [diff] [blame] | 106 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 107 | select CLK_RENESAS_DIV6 |
| 108 | |
| 109 | config CLK_R8A7795 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 110 | bool "R-Car H3 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 111 | select CLK_RCAR_GEN3_CPG |
| 112 | |
Geert Uytterhoeven | 92d1eba | 2019-10-23 14:29:40 +0200 | [diff] [blame] | 113 | config CLK_R8A77960 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 114 | bool "R-Car M3-W clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 115 | select CLK_RCAR_GEN3_CPG |
| 116 | |
Geert Uytterhoeven | 2ba738d | 2019-10-23 14:29:41 +0200 | [diff] [blame] | 117 | config CLK_R8A77961 |
| 118 | bool "R-Car M3-W+ clock support" if COMPILE_TEST |
| 119 | select CLK_RCAR_GEN3_CPG |
| 120 | |
Jacopo Mondi | 7ce36da9 | 2018-02-20 16:12:03 +0100 | [diff] [blame] | 121 | config CLK_R8A77965 |
| 122 | bool "R-Car M3-N clock support" if COMPILE_TEST |
| 123 | select CLK_RCAR_GEN3_CPG |
| 124 | |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 125 | config CLK_R8A77970 |
| 126 | bool "R-Car V3M clock support" if COMPILE_TEST |
| 127 | select CLK_RCAR_GEN3_CPG |
| 128 | |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame] | 129 | config CLK_R8A77980 |
| 130 | bool "R-Car V3H clock support" if COMPILE_TEST |
| 131 | select CLK_RCAR_GEN3_CPG |
| 132 | |
Yoshihiro Shimoda | 3570a2a | 2018-04-20 21:27:44 +0900 | [diff] [blame] | 133 | config CLK_R8A77990 |
| 134 | bool "R-Car E3 clock support" if COMPILE_TEST |
| 135 | select CLK_RCAR_GEN3_CPG |
| 136 | |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 137 | config CLK_R8A77995 |
| 138 | bool "R-Car D3 clock support" if COMPILE_TEST |
| 139 | select CLK_RCAR_GEN3_CPG |
| 140 | |
Michel Pollet | 4c3d885 | 2018-06-14 11:56:34 +0100 | [diff] [blame] | 141 | config CLK_R9A06G032 |
| 142 | bool "Renesas R9A06G032 clock driver" |
| 143 | help |
| 144 | This is a driver for R9A06G032 clocks |
| 145 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 146 | config CLK_SH73A0 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 147 | bool "SH-Mobile AG5 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 148 | select CLK_RENESAS_CPG_MSTP |
| 149 | select CLK_RENESAS_DIV6 |
| 150 | |
| 151 | |
| 152 | # Family |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 153 | config CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 154 | bool "R-Car Gen2 CPG clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 155 | select CLK_RENESAS_CPG_MSSR |
| 156 | |
| 157 | config CLK_RCAR_GEN3_CPG |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 158 | bool "R-Car Gen3 CPG clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 159 | select CLK_RENESAS_CPG_MSSR |
| 160 | |
Yoshihiro Shimoda | 311accb | 2017-07-25 15:26:27 +0900 | [diff] [blame] | 161 | config CLK_RCAR_USB2_CLOCK_SEL |
| 162 | bool "Renesas R-Car USB2 clock selector support" |
| 163 | depends on ARCH_RENESAS || COMPILE_TEST |
Yoshihiro Shimoda | 1ab4f43 | 2020-03-04 15:42:17 +0900 | [diff] [blame^] | 164 | select RESET_CONTROLLER |
Yoshihiro Shimoda | 311accb | 2017-07-25 15:26:27 +0900 | [diff] [blame] | 165 | help |
| 166 | This is a driver for R-Car USB2 clock selector |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 167 | |
| 168 | # Generic |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 169 | config CLK_RENESAS_CPG_MSSR |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 170 | bool "CPG/MSSR clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 171 | select CLK_RENESAS_DIV6 |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 172 | |
| 173 | config CLK_RENESAS_CPG_MSTP |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 174 | bool "MSTP clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 175 | |
| 176 | config CLK_RENESAS_DIV6 |
| 177 | bool "DIV6 clock support" if COMPILE_TEST |
| 178 | |
| 179 | endif # CLK_RENESAS |