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Kuninori Morimoto9e288ce2018-09-25 09:34:05 +02001# SPDX-License-Identifier: GPL-2.0
2
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02003config CLK_RENESAS
4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
5 default y if ARCH_RENESAS
6 select CLK_EMEV2 if ARCH_EMEV2
7 select CLK_RZA1 if ARCH_R7S72100
Chris Brandtfde35c92018-09-07 11:58:49 -05008 select CLK_R7S9210 if ARCH_R7S9210
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02009 select CLK_R8A73A4 if ARCH_R8A73A4
10 select CLK_R8A7740 if ARCH_R8A7740
Biju Das016f9662018-09-11 11:12:49 +010011 select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020012 select CLK_R8A7745 if ARCH_R8A7745
Biju Das5bf2fbb2018-03-28 20:26:12 +010013 select CLK_R8A77470 if ARCH_R8A77470
Biju Das331a53e2018-08-02 15:57:51 +010014 select CLK_R8A774A1 if ARCH_R8A774A1
Biju Das0b9f1c22019-09-19 09:17:14 +010015 select CLK_R8A774B1 if ARCH_R8A774B1
Fabrizio Castro906e0a42018-09-12 11:41:53 +010016 select CLK_R8A774C0 if ARCH_R8A774C0
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020017 select CLK_R8A7778 if ARCH_R8A7778
18 select CLK_R8A7779 if ARCH_R8A7779
19 select CLK_R8A7790 if ARCH_R8A7790
20 select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
21 select CLK_R8A7792 if ARCH_R8A7792
22 select CLK_R8A7794 if ARCH_R8A7794
Geert Uytterhoeven068e7f82020-02-18 12:25:25 +010023 select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
Geert Uytterhoeven03975b72019-12-11 11:02:20 +010024 select CLK_R8A77960 if ARCH_R8A77960
Geert Uytterhoeven2ba738d2019-10-23 14:29:41 +020025 select CLK_R8A77961 if ARCH_R8A77961
Jacopo Mondi7ce36da92018-02-20 16:12:03 +010026 select CLK_R8A77965 if ARCH_R8A77965
Sergei Shtylyov8d46e282017-09-09 00:34:20 +030027 select CLK_R8A77970 if ARCH_R8A77970
Sergei Shtylyovce157832018-02-15 14:58:45 +030028 select CLK_R8A77980 if ARCH_R8A77980
Yoshihiro Shimoda3570a2a2018-04-20 21:27:44 +090029 select CLK_R8A77990 if ARCH_R8A77990
Geert Uytterhoevend71e8512017-07-12 10:47:36 +020030 select CLK_R8A77995 if ARCH_R8A77995
Michel Pollet4c3d8852018-06-14 11:56:34 +010031 select CLK_R9A06G032 if ARCH_R9A06G032
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020032 select CLK_SH73A0 if ARCH_SH73A0
33
34if CLK_RENESAS
35
36# SoC
37config CLK_EMEV2
38 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
39
40config CLK_RZA1
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020041 bool "RZ/A1H clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020042 select CLK_RENESAS_CPG_MSTP
43
Chris Brandtfde35c92018-09-07 11:58:49 -050044config CLK_R7S9210
45 bool "RZ/A2 clock support" if COMPILE_TEST
46 select CLK_RENESAS_CPG_MSSR
47
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020048config CLK_R8A73A4
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020049 bool "R-Mobile APE6 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020050 select CLK_RENESAS_CPG_MSTP
51 select CLK_RENESAS_DIV6
52
53config CLK_R8A7740
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020054 bool "R-Mobile A1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020055 select CLK_RENESAS_CPG_MSTP
56 select CLK_RENESAS_DIV6
57
58config CLK_R8A7743
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020059 bool "RZ/G1M clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020060 select CLK_RCAR_GEN2_CPG
61
62config CLK_R8A7745
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020063 bool "RZ/G1E clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020064 select CLK_RCAR_GEN2_CPG
65
Biju Das5bf2fbb2018-03-28 20:26:12 +010066config CLK_R8A77470
67 bool "RZ/G1C clock support" if COMPILE_TEST
68 select CLK_RCAR_GEN2_CPG
69
Biju Das331a53e2018-08-02 15:57:51 +010070config CLK_R8A774A1
71 bool "RZ/G2M clock support" if COMPILE_TEST
72 select CLK_RCAR_GEN3_CPG
73
Biju Das0b9f1c22019-09-19 09:17:14 +010074config CLK_R8A774B1
75 bool "RZ/G2N clock support" if COMPILE_TEST
76 select CLK_RCAR_GEN3_CPG
77
Fabrizio Castro906e0a42018-09-12 11:41:53 +010078config CLK_R8A774C0
79 bool "RZ/G2E clock support" if COMPILE_TEST
80 select CLK_RCAR_GEN3_CPG
81
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020082config CLK_R8A7778
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020083 bool "R-Car M1A clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020084 select CLK_RENESAS_CPG_MSTP
85
86config CLK_R8A7779
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020087 bool "R-Car H1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020088 select CLK_RENESAS_CPG_MSTP
89
90config CLK_R8A7790
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020091 bool "R-Car H2 clock support" if COMPILE_TEST
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010092 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020093 select CLK_RENESAS_DIV6
94
95config CLK_R8A7791
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020096 bool "R-Car M2-W/N clock support" if COMPILE_TEST
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +020097 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020098 select CLK_RENESAS_DIV6
99
100config CLK_R8A7792
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200101 bool "R-Car V2H clock support" if COMPILE_TEST
Geert Uytterhoevenfd3c2f32017-03-19 18:08:59 +0100102 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200103
104config CLK_R8A7794
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200105 bool "R-Car E2 clock support" if COMPILE_TEST
Geert Uytterhoeven2d755882017-03-19 18:12:51 +0100106 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200107 select CLK_RENESAS_DIV6
108
109config CLK_R8A7795
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200110 bool "R-Car H3 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200111 select CLK_RCAR_GEN3_CPG
112
Geert Uytterhoeven92d1eba2019-10-23 14:29:40 +0200113config CLK_R8A77960
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200114 bool "R-Car M3-W clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200115 select CLK_RCAR_GEN3_CPG
116
Geert Uytterhoeven2ba738d2019-10-23 14:29:41 +0200117config CLK_R8A77961
118 bool "R-Car M3-W+ clock support" if COMPILE_TEST
119 select CLK_RCAR_GEN3_CPG
120
Jacopo Mondi7ce36da92018-02-20 16:12:03 +0100121config CLK_R8A77965
122 bool "R-Car M3-N clock support" if COMPILE_TEST
123 select CLK_RCAR_GEN3_CPG
124
Sergei Shtylyov8d46e282017-09-09 00:34:20 +0300125config CLK_R8A77970
126 bool "R-Car V3M clock support" if COMPILE_TEST
127 select CLK_RCAR_GEN3_CPG
128
Sergei Shtylyovce157832018-02-15 14:58:45 +0300129config CLK_R8A77980
130 bool "R-Car V3H clock support" if COMPILE_TEST
131 select CLK_RCAR_GEN3_CPG
132
Yoshihiro Shimoda3570a2a2018-04-20 21:27:44 +0900133config CLK_R8A77990
134 bool "R-Car E3 clock support" if COMPILE_TEST
135 select CLK_RCAR_GEN3_CPG
136
Geert Uytterhoevend71e8512017-07-12 10:47:36 +0200137config CLK_R8A77995
138 bool "R-Car D3 clock support" if COMPILE_TEST
139 select CLK_RCAR_GEN3_CPG
140
Michel Pollet4c3d8852018-06-14 11:56:34 +0100141config CLK_R9A06G032
142 bool "Renesas R9A06G032 clock driver"
143 help
144 This is a driver for R9A06G032 clocks
145
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200146config CLK_SH73A0
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200147 bool "SH-Mobile AG5 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200148 select CLK_RENESAS_CPG_MSTP
149 select CLK_RENESAS_DIV6
150
151
152# Family
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200153config CLK_RCAR_GEN2_CPG
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200154 bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200155 select CLK_RENESAS_CPG_MSSR
156
157config CLK_RCAR_GEN3_CPG
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200158 bool "R-Car Gen3 CPG clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200159 select CLK_RENESAS_CPG_MSSR
160
Yoshihiro Shimoda311accb2017-07-25 15:26:27 +0900161config CLK_RCAR_USB2_CLOCK_SEL
162 bool "Renesas R-Car USB2 clock selector support"
163 depends on ARCH_RENESAS || COMPILE_TEST
Yoshihiro Shimoda1ab4f432020-03-04 15:42:17 +0900164 select RESET_CONTROLLER
Yoshihiro Shimoda311accb2017-07-25 15:26:27 +0900165 help
166 This is a driver for R-Car USB2 clock selector
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200167
168# Generic
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200169config CLK_RENESAS_CPG_MSSR
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200170 bool "CPG/MSSR clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200171 select CLK_RENESAS_DIV6
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200172
173config CLK_RENESAS_CPG_MSTP
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200174 bool "MSTP clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200175
176config CLK_RENESAS_DIV6
177 bool "DIV6 clock support" if COMPILE_TEST
178
179endif # CLK_RENESAS