Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 1 | config CLK_RENESAS |
| 2 | bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS |
| 3 | default y if ARCH_RENESAS |
| 4 | select CLK_EMEV2 if ARCH_EMEV2 |
| 5 | select CLK_RZA1 if ARCH_R7S72100 |
| 6 | select CLK_R8A73A4 if ARCH_R8A73A4 |
| 7 | select CLK_R8A7740 if ARCH_R8A7740 |
| 8 | select CLK_R8A7743 if ARCH_R8A7743 |
| 9 | select CLK_R8A7745 if ARCH_R8A7745 |
| 10 | select CLK_R8A7778 if ARCH_R8A7778 |
| 11 | select CLK_R8A7779 if ARCH_R8A7779 |
| 12 | select CLK_R8A7790 if ARCH_R8A7790 |
| 13 | select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 |
| 14 | select CLK_R8A7792 if ARCH_R8A7792 |
| 15 | select CLK_R8A7794 if ARCH_R8A7794 |
| 16 | select CLK_R8A7795 if ARCH_R8A7795 |
| 17 | select CLK_R8A7796 if ARCH_R8A7796 |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 18 | select CLK_R8A77970 if ARCH_R8A77970 |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame^] | 19 | select CLK_R8A77980 if ARCH_R8A77980 |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 20 | select CLK_R8A77995 if ARCH_R8A77995 |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 21 | select CLK_SH73A0 if ARCH_SH73A0 |
| 22 | |
| 23 | if CLK_RENESAS |
| 24 | |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 25 | config CLK_RENESAS_LEGACY |
| 26 | bool "Legacy DT clock support" |
Geert Uytterhoeven | 2d75588 | 2017-03-19 18:12:51 +0100 | [diff] [blame] | 27 | depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794 |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 28 | help |
| 29 | Enable backward compatibility with old device trees describing a |
| 30 | hierarchical representation of the various CPG and MSTP clocks. |
| 31 | |
| 32 | Say Y if you want your kernel to work with old DTBs. |
Geert Uytterhoeven | f1a2879 | 2017-04-25 14:04:35 +0200 | [diff] [blame] | 33 | It is safe to say N if you use the DTS that is supplied with the |
| 34 | current kernel source tree. |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 35 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 36 | # SoC |
| 37 | config CLK_EMEV2 |
| 38 | bool "Emma Mobile EV2 clock support" if COMPILE_TEST |
| 39 | |
| 40 | config CLK_RZA1 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 41 | bool "RZ/A1H clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 42 | select CLK_RENESAS_CPG_MSTP |
| 43 | |
| 44 | config CLK_R8A73A4 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 45 | bool "R-Mobile APE6 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 46 | select CLK_RENESAS_CPG_MSTP |
| 47 | select CLK_RENESAS_DIV6 |
| 48 | |
| 49 | config CLK_R8A7740 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 50 | bool "R-Mobile A1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 51 | select CLK_RENESAS_CPG_MSTP |
| 52 | select CLK_RENESAS_DIV6 |
| 53 | |
| 54 | config CLK_R8A7743 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 55 | bool "RZ/G1M clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 56 | select CLK_RCAR_GEN2_CPG |
| 57 | |
| 58 | config CLK_R8A7745 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 59 | bool "RZ/G1E clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 60 | select CLK_RCAR_GEN2_CPG |
| 61 | |
| 62 | config CLK_R8A7778 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 63 | bool "R-Car M1A clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 64 | select CLK_RENESAS_CPG_MSTP |
| 65 | |
| 66 | config CLK_R8A7779 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 67 | bool "R-Car H1 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 68 | select CLK_RENESAS_CPG_MSTP |
| 69 | |
| 70 | config CLK_R8A7790 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 71 | bool "R-Car H2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | d4e59f1 | 2017-03-19 18:05:42 +0100 | [diff] [blame] | 72 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 73 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 74 | select CLK_RENESAS_DIV6 |
| 75 | |
| 76 | config CLK_R8A7791 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 77 | bool "R-Car M2-W/N clock support" if COMPILE_TEST |
Geert Uytterhoeven | 6449ab8 | 2015-10-16 11:41:19 +0200 | [diff] [blame] | 78 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 79 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 80 | select CLK_RENESAS_DIV6 |
| 81 | |
| 82 | config CLK_R8A7792 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 83 | bool "R-Car V2H clock support" if COMPILE_TEST |
Geert Uytterhoeven | fd3c2f3 | 2017-03-19 18:08:59 +0100 | [diff] [blame] | 84 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 85 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 86 | |
| 87 | config CLK_R8A7794 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 88 | bool "R-Car E2 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 2d75588 | 2017-03-19 18:12:51 +0100 | [diff] [blame] | 89 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 90 | select CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 91 | select CLK_RENESAS_DIV6 |
| 92 | |
| 93 | config CLK_R8A7795 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 94 | bool "R-Car H3 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 95 | select CLK_RCAR_GEN3_CPG |
| 96 | |
| 97 | config CLK_R8A7796 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 98 | bool "R-Car M3-W clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 99 | select CLK_RCAR_GEN3_CPG |
| 100 | |
Sergei Shtylyov | 8d46e28 | 2017-09-09 00:34:20 +0300 | [diff] [blame] | 101 | config CLK_R8A77970 |
| 102 | bool "R-Car V3M clock support" if COMPILE_TEST |
| 103 | select CLK_RCAR_GEN3_CPG |
| 104 | |
Sergei Shtylyov | ce15783 | 2018-02-15 14:58:45 +0300 | [diff] [blame^] | 105 | config CLK_R8A77980 |
| 106 | bool "R-Car V3H clock support" if COMPILE_TEST |
| 107 | select CLK_RCAR_GEN3_CPG |
| 108 | |
Geert Uytterhoeven | d71e851 | 2017-07-12 10:47:36 +0200 | [diff] [blame] | 109 | config CLK_R8A77995 |
| 110 | bool "R-Car D3 clock support" if COMPILE_TEST |
| 111 | select CLK_RCAR_GEN3_CPG |
| 112 | |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 113 | config CLK_SH73A0 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 114 | bool "SH-Mobile AG5 clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 115 | select CLK_RENESAS_CPG_MSTP |
| 116 | select CLK_RENESAS_DIV6 |
| 117 | |
| 118 | |
| 119 | # Family |
| 120 | config CLK_RCAR_GEN2 |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 121 | bool "R-Car Gen2 legacy clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 122 | select CLK_RENESAS_CPG_MSTP |
| 123 | select CLK_RENESAS_DIV6 |
| 124 | |
| 125 | config CLK_RCAR_GEN2_CPG |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 126 | bool "R-Car Gen2 CPG clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 127 | select CLK_RENESAS_CPG_MSSR |
| 128 | |
| 129 | config CLK_RCAR_GEN3_CPG |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 130 | bool "R-Car Gen3 CPG clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 131 | select CLK_RENESAS_CPG_MSSR |
| 132 | |
Yoshihiro Shimoda | 311accb | 2017-07-25 15:26:27 +0900 | [diff] [blame] | 133 | config CLK_RCAR_USB2_CLOCK_SEL |
| 134 | bool "Renesas R-Car USB2 clock selector support" |
| 135 | depends on ARCH_RENESAS || COMPILE_TEST |
| 136 | help |
| 137 | This is a driver for R-Car USB2 clock selector |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 138 | |
| 139 | # Generic |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 140 | config CLK_RENESAS_CPG_MSSR |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 141 | bool "CPG/MSSR clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 142 | select CLK_RENESAS_DIV6 |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 143 | |
| 144 | config CLK_RENESAS_CPG_MSTP |
Geert Uytterhoeven | 371dd37 | 2017-05-17 17:25:47 +0200 | [diff] [blame] | 145 | bool "MSTP clock support" if COMPILE_TEST |
Geert Uytterhoeven | 80978a4 | 2017-04-24 16:54:14 +0200 | [diff] [blame] | 146 | |
| 147 | config CLK_RENESAS_DIV6 |
| 148 | bool "DIV6 clock support" if COMPILE_TEST |
| 149 | |
| 150 | endif # CLK_RENESAS |