blob: 43bab4f9c4e273994b884a2eb0136c5dd296f6cc [file] [log] [blame]
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02001config CLK_RENESAS
2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
3 default y if ARCH_RENESAS
4 select CLK_EMEV2 if ARCH_EMEV2
5 select CLK_RZA1 if ARCH_R7S72100
6 select CLK_R8A73A4 if ARCH_R8A73A4
7 select CLK_R8A7740 if ARCH_R8A7740
8 select CLK_R8A7743 if ARCH_R8A7743
9 select CLK_R8A7745 if ARCH_R8A7745
10 select CLK_R8A7778 if ARCH_R8A7778
11 select CLK_R8A7779 if ARCH_R8A7779
12 select CLK_R8A7790 if ARCH_R8A7790
13 select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
14 select CLK_R8A7792 if ARCH_R8A7792
15 select CLK_R8A7794 if ARCH_R8A7794
16 select CLK_R8A7795 if ARCH_R8A7795
17 select CLK_R8A7796 if ARCH_R8A7796
Sergei Shtylyov8d46e282017-09-09 00:34:20 +030018 select CLK_R8A77970 if ARCH_R8A77970
Sergei Shtylyovce157832018-02-15 14:58:45 +030019 select CLK_R8A77980 if ARCH_R8A77980
Geert Uytterhoevend71e8512017-07-12 10:47:36 +020020 select CLK_R8A77995 if ARCH_R8A77995
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020021 select CLK_SH73A0 if ARCH_SH73A0
22
23if CLK_RENESAS
24
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010025config CLK_RENESAS_LEGACY
26 bool "Legacy DT clock support"
Geert Uytterhoeven2d755882017-03-19 18:12:51 +010027 depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010028 help
29 Enable backward compatibility with old device trees describing a
30 hierarchical representation of the various CPG and MSTP clocks.
31
32 Say Y if you want your kernel to work with old DTBs.
Geert Uytterhoevenf1a28792017-04-25 14:04:35 +020033 It is safe to say N if you use the DTS that is supplied with the
34 current kernel source tree.
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010035
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020036# SoC
37config CLK_EMEV2
38 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
39
40config CLK_RZA1
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020041 bool "RZ/A1H clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020042 select CLK_RENESAS_CPG_MSTP
43
44config CLK_R8A73A4
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020045 bool "R-Mobile APE6 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020046 select CLK_RENESAS_CPG_MSTP
47 select CLK_RENESAS_DIV6
48
49config CLK_R8A7740
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020050 bool "R-Mobile A1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020051 select CLK_RENESAS_CPG_MSTP
52 select CLK_RENESAS_DIV6
53
54config CLK_R8A7743
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020055 bool "RZ/G1M clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020056 select CLK_RCAR_GEN2_CPG
57
58config CLK_R8A7745
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020059 bool "RZ/G1E clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020060 select CLK_RCAR_GEN2_CPG
61
62config CLK_R8A7778
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020063 bool "R-Car M1A clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020064 select CLK_RENESAS_CPG_MSTP
65
66config CLK_R8A7779
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020067 bool "R-Car H1 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020068 select CLK_RENESAS_CPG_MSTP
69
70config CLK_R8A7790
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020071 bool "R-Car H2 clock support" if COMPILE_TEST
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010072 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
73 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020074 select CLK_RENESAS_DIV6
75
76config CLK_R8A7791
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020077 bool "R-Car M2-W/N clock support" if COMPILE_TEST
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +020078 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
79 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020080 select CLK_RENESAS_DIV6
81
82config CLK_R8A7792
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020083 bool "R-Car V2H clock support" if COMPILE_TEST
Geert Uytterhoevenfd3c2f32017-03-19 18:08:59 +010084 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
85 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020086
87config CLK_R8A7794
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020088 bool "R-Car E2 clock support" if COMPILE_TEST
Geert Uytterhoeven2d755882017-03-19 18:12:51 +010089 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
90 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020091 select CLK_RENESAS_DIV6
92
93config CLK_R8A7795
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020094 bool "R-Car H3 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020095 select CLK_RCAR_GEN3_CPG
96
97config CLK_R8A7796
Geert Uytterhoeven371dd372017-05-17 17:25:47 +020098 bool "R-Car M3-W clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020099 select CLK_RCAR_GEN3_CPG
100
Sergei Shtylyov8d46e282017-09-09 00:34:20 +0300101config CLK_R8A77970
102 bool "R-Car V3M clock support" if COMPILE_TEST
103 select CLK_RCAR_GEN3_CPG
104
Sergei Shtylyovce157832018-02-15 14:58:45 +0300105config CLK_R8A77980
106 bool "R-Car V3H clock support" if COMPILE_TEST
107 select CLK_RCAR_GEN3_CPG
108
Geert Uytterhoevend71e8512017-07-12 10:47:36 +0200109config CLK_R8A77995
110 bool "R-Car D3 clock support" if COMPILE_TEST
111 select CLK_RCAR_GEN3_CPG
112
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200113config CLK_SH73A0
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200114 bool "SH-Mobile AG5 clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200115 select CLK_RENESAS_CPG_MSTP
116 select CLK_RENESAS_DIV6
117
118
119# Family
120config CLK_RCAR_GEN2
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200121 bool "R-Car Gen2 legacy clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200122 select CLK_RENESAS_CPG_MSTP
123 select CLK_RENESAS_DIV6
124
125config CLK_RCAR_GEN2_CPG
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200126 bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200127 select CLK_RENESAS_CPG_MSSR
128
129config CLK_RCAR_GEN3_CPG
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200130 bool "R-Car Gen3 CPG clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200131 select CLK_RENESAS_CPG_MSSR
132
Yoshihiro Shimoda311accb2017-07-25 15:26:27 +0900133config CLK_RCAR_USB2_CLOCK_SEL
134 bool "Renesas R-Car USB2 clock selector support"
135 depends on ARCH_RENESAS || COMPILE_TEST
136 help
137 This is a driver for R-Car USB2 clock selector
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200138
139# Generic
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200140config CLK_RENESAS_CPG_MSSR
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200141 bool "CPG/MSSR clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200142 select CLK_RENESAS_DIV6
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200143
144config CLK_RENESAS_CPG_MSTP
Geert Uytterhoeven371dd372017-05-17 17:25:47 +0200145 bool "MSTP clock support" if COMPILE_TEST
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200146
147config CLK_RENESAS_DIV6
148 bool "DIV6 clock support" if COMPILE_TEST
149
150endif # CLK_RENESAS