Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 33 | #include <linux/circ_buf.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 40 | /** |
| 41 | * DOC: interrupt handling |
| 42 | * |
| 43 | * These functions provide the basic support for enabling and disabling the |
| 44 | * interrupt handling support. There's a lot more functionality in i915_irq.c |
| 45 | * and related files, but that will be described in separate chapters. |
| 46 | */ |
| 47 | |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
| 49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, |
| 50 | }; |
| 51 | |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
| 53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, |
| 54 | }; |
| 55 | |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
| 57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, |
| 58 | }; |
| 59 | |
Ville Syrjälä | 7c7e10d | 2015-01-09 14:21:12 +0200 | [diff] [blame] | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 66 | }; |
| 67 | |
Ville Syrjälä | 7c7e10d | 2015-01-09 14:21:12 +0200 | [diff] [blame] | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 74 | }; |
| 75 | |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
Ville Syrjälä | 74c0b39 | 2015-08-27 23:56:07 +0300 | [diff] [blame] | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, |
| 81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT |
| 82 | }; |
| 83 | |
Ville Syrjälä | 7c7e10d | 2015-01-09 14:21:12 +0200 | [diff] [blame] | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 91 | }; |
| 92 | |
Ville Syrjälä | 7c7e10d | 2015-01-09 14:21:12 +0200 | [diff] [blame] | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 100 | }; |
| 101 | |
Ville Syrjälä | 4bca26d | 2015-05-11 20:49:10 +0300 | [diff] [blame] | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 109 | }; |
| 110 | |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 111 | /* BXT hpd list */ |
| 112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { |
Sonika Jindal | 7f3561b | 2015-08-10 10:35:35 +0530 | [diff] [blame] | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
| 115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC |
| 116 | }; |
| 117 | |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 118 | static const u32 hpd_gen11[HPD_NUM_PINS] = { |
| 119 | [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG, |
| 120 | [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG, |
| 121 | [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG, |
| 122 | [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 123 | }; |
| 124 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 125 | static const u32 hpd_icp[HPD_NUM_PINS] = { |
| 126 | [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP, |
| 127 | [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP, |
| 128 | [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP, |
| 129 | [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP, |
| 130 | [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP, |
| 131 | [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP |
| 132 | }; |
| 133 | |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 134 | /* IIR can theoretically queue up two events. Be paranoid. */ |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 135 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 136 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 137 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
| 138 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 139 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 140 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 141 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 142 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 143 | } while (0) |
| 144 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 145 | #define GEN3_IRQ_RESET(type) do { \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 146 | I915_WRITE(type##IMR, 0xffffffff); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 147 | POSTING_READ(type##IMR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 148 | I915_WRITE(type##IER, 0); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 149 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 150 | POSTING_READ(type##IIR); \ |
| 151 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 152 | POSTING_READ(type##IIR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 153 | } while (0) |
| 154 | |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 155 | #define GEN2_IRQ_RESET(type) do { \ |
| 156 | I915_WRITE16(type##IMR, 0xffff); \ |
| 157 | POSTING_READ16(type##IMR); \ |
| 158 | I915_WRITE16(type##IER, 0); \ |
| 159 | I915_WRITE16(type##IIR, 0xffff); \ |
| 160 | POSTING_READ16(type##IIR); \ |
| 161 | I915_WRITE16(type##IIR, 0xffff); \ |
| 162 | POSTING_READ16(type##IIR); \ |
| 163 | } while (0) |
| 164 | |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 165 | /* |
| 166 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. |
| 167 | */ |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 168 | static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 169 | i915_reg_t reg) |
Ville Syrjälä | b51a284 | 2015-09-18 20:03:41 +0300 | [diff] [blame] | 170 | { |
| 171 | u32 val = I915_READ(reg); |
| 172 | |
| 173 | if (val == 0) |
| 174 | return; |
| 175 | |
| 176 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 177 | i915_mmio_reg_offset(reg), val); |
Ville Syrjälä | b51a284 | 2015-09-18 20:03:41 +0300 | [diff] [blame] | 178 | I915_WRITE(reg, 0xffffffff); |
| 179 | POSTING_READ(reg); |
| 180 | I915_WRITE(reg, 0xffffffff); |
| 181 | POSTING_READ(reg); |
| 182 | } |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 183 | |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 184 | static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
| 185 | i915_reg_t reg) |
| 186 | { |
| 187 | u16 val = I915_READ16(reg); |
| 188 | |
| 189 | if (val == 0) |
| 190 | return; |
| 191 | |
| 192 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", |
| 193 | i915_mmio_reg_offset(reg), val); |
| 194 | I915_WRITE16(reg, 0xffff); |
| 195 | POSTING_READ16(reg); |
| 196 | I915_WRITE16(reg, 0xffff); |
| 197 | POSTING_READ16(reg); |
| 198 | } |
| 199 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 200 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 201 | gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 202 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
Ville Syrjälä | 7d1bd539 | 2014-10-30 19:42:50 +0200 | [diff] [blame] | 203 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
| 204 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 205 | } while (0) |
| 206 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 207 | #define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \ |
| 208 | gen3_assert_iir_is_zero(dev_priv, type##IIR); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 209 | I915_WRITE(type##IER, (ier_val)); \ |
Ville Syrjälä | 7d1bd539 | 2014-10-30 19:42:50 +0200 | [diff] [blame] | 210 | I915_WRITE(type##IMR, (imr_val)); \ |
| 211 | POSTING_READ(type##IMR); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 212 | } while (0) |
| 213 | |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 214 | #define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \ |
| 215 | gen2_assert_iir_is_zero(dev_priv, type##IIR); \ |
| 216 | I915_WRITE16(type##IER, (ier_val)); \ |
| 217 | I915_WRITE16(type##IMR, (imr_val)); \ |
| 218 | POSTING_READ16(type##IMR); \ |
| 219 | } while (0) |
| 220 | |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 221 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 222 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 223 | |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 224 | /* For display hotplug interrupt */ |
| 225 | static inline void |
| 226 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, |
| 227 | uint32_t mask, |
| 228 | uint32_t bits) |
| 229 | { |
| 230 | uint32_t val; |
| 231 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 232 | lockdep_assert_held(&dev_priv->irq_lock); |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 233 | WARN_ON(bits & ~mask); |
| 234 | |
| 235 | val = I915_READ(PORT_HOTPLUG_EN); |
| 236 | val &= ~mask; |
| 237 | val |= bits; |
| 238 | I915_WRITE(PORT_HOTPLUG_EN, val); |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * i915_hotplug_interrupt_update - update hotplug interrupt enable |
| 243 | * @dev_priv: driver private |
| 244 | * @mask: bits to update |
| 245 | * @bits: bits to enable |
| 246 | * NOTE: the HPD enable bits are modified both inside and outside |
| 247 | * of an interrupt context. To avoid that read-modify-write cycles |
| 248 | * interfer, these bits are protected by a spinlock. Since this |
| 249 | * function is usually not called from a context where the lock is |
| 250 | * held already, this function acquires the lock itself. A non-locking |
| 251 | * version is also available. |
| 252 | */ |
| 253 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
| 254 | uint32_t mask, |
| 255 | uint32_t bits) |
| 256 | { |
| 257 | spin_lock_irq(&dev_priv->irq_lock); |
| 258 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); |
| 259 | spin_unlock_irq(&dev_priv->irq_lock); |
| 260 | } |
| 261 | |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 262 | static u32 |
| 263 | gen11_gt_engine_identity(struct drm_i915_private * const i915, |
| 264 | const unsigned int bank, const unsigned int bit); |
| 265 | |
Oscar Mateo | ff047a8 | 2018-04-24 14:39:55 -0700 | [diff] [blame] | 266 | bool gen11_reset_one_iir(struct drm_i915_private * const i915, |
| 267 | const unsigned int bank, |
| 268 | const unsigned int bit) |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 269 | { |
| 270 | void __iomem * const regs = i915->regs; |
| 271 | u32 dw; |
| 272 | |
| 273 | lockdep_assert_held(&i915->irq_lock); |
| 274 | |
| 275 | dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); |
| 276 | if (dw & BIT(bit)) { |
| 277 | /* |
| 278 | * According to the BSpec, DW_IIR bits cannot be cleared without |
| 279 | * first servicing the Selector & Shared IIR registers. |
| 280 | */ |
| 281 | gen11_gt_engine_identity(i915, bank, bit); |
| 282 | |
| 283 | /* |
| 284 | * We locked GT INT DW by reading it. If we want to (try |
| 285 | * to) recover from this succesfully, we need to clear |
| 286 | * our bit, otherwise we are locking the register for |
| 287 | * everybody. |
| 288 | */ |
| 289 | raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); |
| 290 | |
| 291 | return true; |
| 292 | } |
| 293 | |
| 294 | return false; |
| 295 | } |
| 296 | |
Ville Syrjälä | d9dc34f1 | 2015-08-27 23:55:58 +0300 | [diff] [blame] | 297 | /** |
| 298 | * ilk_update_display_irq - update DEIMR |
| 299 | * @dev_priv: driver private |
| 300 | * @interrupt_mask: mask of interrupt bits to update |
| 301 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 302 | */ |
Ville Syrjälä | fbdedaea | 2015-11-23 18:06:16 +0200 | [diff] [blame] | 303 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
| 304 | uint32_t interrupt_mask, |
| 305 | uint32_t enabled_irq_mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 306 | { |
Ville Syrjälä | d9dc34f1 | 2015-08-27 23:55:58 +0300 | [diff] [blame] | 307 | uint32_t new_val; |
| 308 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 309 | lockdep_assert_held(&dev_priv->irq_lock); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 310 | |
Ville Syrjälä | d9dc34f1 | 2015-08-27 23:55:58 +0300 | [diff] [blame] | 311 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 312 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 313 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 314 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 315 | |
Ville Syrjälä | d9dc34f1 | 2015-08-27 23:55:58 +0300 | [diff] [blame] | 316 | new_val = dev_priv->irq_mask; |
| 317 | new_val &= ~interrupt_mask; |
| 318 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 319 | |
| 320 | if (new_val != dev_priv->irq_mask) { |
| 321 | dev_priv->irq_mask = new_val; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 322 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 323 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 324 | } |
| 325 | } |
| 326 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 327 | /** |
| 328 | * ilk_update_gt_irq - update GTIMR |
| 329 | * @dev_priv: driver private |
| 330 | * @interrupt_mask: mask of interrupt bits to update |
| 331 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 332 | */ |
| 333 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 334 | uint32_t interrupt_mask, |
| 335 | uint32_t enabled_irq_mask) |
| 336 | { |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 337 | lockdep_assert_held(&dev_priv->irq_lock); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 338 | |
Daniel Vetter | 15a17aa | 2014-12-08 16:30:00 +0100 | [diff] [blame] | 339 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 340 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 341 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 342 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 343 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 344 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 345 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 346 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 347 | } |
| 348 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 349 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 350 | { |
| 351 | ilk_update_gt_irq(dev_priv, mask, mask); |
Chris Wilson | 31bb59c | 2016-07-01 17:23:27 +0100 | [diff] [blame] | 352 | POSTING_READ_FW(GTIMR); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 353 | } |
| 354 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 355 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 356 | { |
| 357 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 358 | } |
| 359 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 360 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 361 | { |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 362 | WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11); |
| 363 | |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 364 | return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 365 | } |
| 366 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 367 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 368 | { |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 369 | if (INTEL_GEN(dev_priv) >= 11) |
| 370 | return GEN11_GPM_WGBOXPERF_INTR_MASK; |
| 371 | else if (INTEL_GEN(dev_priv) >= 8) |
| 372 | return GEN8_GT_IMR(2); |
| 373 | else |
| 374 | return GEN6_PMIMR; |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 375 | } |
| 376 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 377 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 378 | { |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 379 | if (INTEL_GEN(dev_priv) >= 11) |
| 380 | return GEN11_GPM_WGBOXPERF_INTR_ENABLE; |
| 381 | else if (INTEL_GEN(dev_priv) >= 8) |
| 382 | return GEN8_GT_IER(2); |
| 383 | else |
| 384 | return GEN6_PMIER; |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 385 | } |
| 386 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 387 | /** |
Ville Syrjälä | 81fd874 | 2015-11-25 16:21:30 +0200 | [diff] [blame] | 388 | * snb_update_pm_irq - update GEN6_PMIMR |
| 389 | * @dev_priv: driver private |
| 390 | * @interrupt_mask: mask of interrupt bits to update |
| 391 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 392 | */ |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 393 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 394 | uint32_t interrupt_mask, |
| 395 | uint32_t enabled_irq_mask) |
| 396 | { |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 397 | uint32_t new_val; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 398 | |
Daniel Vetter | 15a17aa | 2014-12-08 16:30:00 +0100 | [diff] [blame] | 399 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 400 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 401 | lockdep_assert_held(&dev_priv->irq_lock); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 402 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 403 | new_val = dev_priv->pm_imr; |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 404 | new_val &= ~interrupt_mask; |
| 405 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 406 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 407 | if (new_val != dev_priv->pm_imr) { |
| 408 | dev_priv->pm_imr = new_val; |
| 409 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr); |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 410 | POSTING_READ(gen6_pm_imr(dev_priv)); |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 411 | } |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 412 | } |
| 413 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 414 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 415 | { |
Imre Deak | 9939fba | 2014-11-20 23:01:47 +0200 | [diff] [blame] | 416 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 417 | return; |
| 418 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 419 | snb_update_pm_irq(dev_priv, mask, mask); |
| 420 | } |
| 421 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 422 | static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
Imre Deak | 9939fba | 2014-11-20 23:01:47 +0200 | [diff] [blame] | 423 | { |
| 424 | snb_update_pm_irq(dev_priv, mask, 0); |
| 425 | } |
| 426 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 427 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 428 | { |
Imre Deak | 9939fba | 2014-11-20 23:01:47 +0200 | [diff] [blame] | 429 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 430 | return; |
| 431 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 432 | __gen6_mask_pm_irq(dev_priv, mask); |
| 433 | } |
| 434 | |
Oscar Mateo | 3814fd7 | 2017-08-23 16:58:24 -0700 | [diff] [blame] | 435 | static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 436 | { |
| 437 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
| 438 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 439 | lockdep_assert_held(&dev_priv->irq_lock); |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 440 | |
| 441 | I915_WRITE(reg, reset_mask); |
| 442 | I915_WRITE(reg, reset_mask); |
| 443 | POSTING_READ(reg); |
| 444 | } |
| 445 | |
Oscar Mateo | 3814fd7 | 2017-08-23 16:58:24 -0700 | [diff] [blame] | 446 | static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 447 | { |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 448 | lockdep_assert_held(&dev_priv->irq_lock); |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 449 | |
| 450 | dev_priv->pm_ier |= enable_mask; |
| 451 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); |
| 452 | gen6_unmask_pm_irq(dev_priv, enable_mask); |
| 453 | /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ |
| 454 | } |
| 455 | |
Oscar Mateo | 3814fd7 | 2017-08-23 16:58:24 -0700 | [diff] [blame] | 456 | static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 457 | { |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 458 | lockdep_assert_held(&dev_priv->irq_lock); |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 459 | |
| 460 | dev_priv->pm_ier &= ~disable_mask; |
| 461 | __gen6_mask_pm_irq(dev_priv, disable_mask); |
| 462 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); |
| 463 | /* though a barrier is missing here, but don't really need a one */ |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 464 | } |
| 465 | |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 466 | void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) |
| 467 | { |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 468 | spin_lock_irq(&dev_priv->irq_lock); |
| 469 | |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 470 | while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)) |
| 471 | ; |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 472 | |
| 473 | dev_priv->gt_pm.rps.pm_iir = 0; |
| 474 | |
| 475 | spin_unlock_irq(&dev_priv->irq_lock); |
| 476 | } |
| 477 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 478 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 479 | { |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 480 | spin_lock_irq(&dev_priv->irq_lock); |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 481 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 482 | dev_priv->gt_pm.rps.pm_iir = 0; |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 483 | spin_unlock_irq(&dev_priv->irq_lock); |
| 484 | } |
| 485 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 486 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 487 | { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 488 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
| 489 | |
| 490 | if (READ_ONCE(rps->interrupts_enabled)) |
Chris Wilson | f2a91d1 | 2016-09-21 14:51:06 +0100 | [diff] [blame] | 491 | return; |
| 492 | |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 493 | spin_lock_irq(&dev_priv->irq_lock); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 494 | WARN_ON_ONCE(rps->pm_iir); |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 495 | |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 496 | if (INTEL_GEN(dev_priv) >= 11) |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 497 | WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)); |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 498 | else |
| 499 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 500 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 501 | rps->interrupts_enabled = true; |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 502 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Imre Deak | 78e68d3 | 2014-12-15 18:59:27 +0200 | [diff] [blame] | 503 | |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 504 | spin_unlock_irq(&dev_priv->irq_lock); |
| 505 | } |
| 506 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 507 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 508 | { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 509 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
| 510 | |
| 511 | if (!READ_ONCE(rps->interrupts_enabled)) |
Chris Wilson | f2a91d1 | 2016-09-21 14:51:06 +0100 | [diff] [blame] | 512 | return; |
| 513 | |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 514 | spin_lock_irq(&dev_priv->irq_lock); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 515 | rps->interrupts_enabled = false; |
Imre Deak | 9939fba | 2014-11-20 23:01:47 +0200 | [diff] [blame] | 516 | |
Dave Gordon | b20e3cf | 2016-09-12 21:19:35 +0100 | [diff] [blame] | 517 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); |
Imre Deak | 9939fba | 2014-11-20 23:01:47 +0200 | [diff] [blame] | 518 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 519 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Imre Deak | 58072cc | 2015-03-23 19:11:34 +0200 | [diff] [blame] | 520 | |
| 521 | spin_unlock_irq(&dev_priv->irq_lock); |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 522 | synchronize_irq(dev_priv->drm.irq); |
Chris Wilson | c33d247 | 2016-07-04 08:08:36 +0100 | [diff] [blame] | 523 | |
| 524 | /* Now that we will not be generating any more work, flush any |
Oscar Mateo | 3814fd7 | 2017-08-23 16:58:24 -0700 | [diff] [blame] | 525 | * outstanding tasks. As we are called on the RPS idle path, |
Chris Wilson | c33d247 | 2016-07-04 08:08:36 +0100 | [diff] [blame] | 526 | * we will reset the GPU to minimum frequencies, so the current |
| 527 | * state of the worker can be discarded. |
| 528 | */ |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 529 | cancel_work_sync(&rps->work); |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 530 | if (INTEL_GEN(dev_priv) >= 11) |
| 531 | gen11_reset_rps_interrupts(dev_priv); |
| 532 | else |
| 533 | gen6_reset_rps_interrupts(dev_priv); |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 534 | } |
| 535 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 536 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) |
| 537 | { |
Sagar Arun Kamble | 1be333d | 2018-01-24 21:16:56 +0530 | [diff] [blame] | 538 | assert_rpm_wakelock_held(dev_priv); |
| 539 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 540 | spin_lock_irq(&dev_priv->irq_lock); |
| 541 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events); |
| 542 | spin_unlock_irq(&dev_priv->irq_lock); |
| 543 | } |
| 544 | |
| 545 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) |
| 546 | { |
Sagar Arun Kamble | 1be333d | 2018-01-24 21:16:56 +0530 | [diff] [blame] | 547 | assert_rpm_wakelock_held(dev_priv); |
| 548 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 549 | spin_lock_irq(&dev_priv->irq_lock); |
| 550 | if (!dev_priv->guc.interrupts_enabled) { |
| 551 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & |
| 552 | dev_priv->pm_guc_events); |
| 553 | dev_priv->guc.interrupts_enabled = true; |
| 554 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); |
| 555 | } |
| 556 | spin_unlock_irq(&dev_priv->irq_lock); |
| 557 | } |
| 558 | |
| 559 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) |
| 560 | { |
Sagar Arun Kamble | 1be333d | 2018-01-24 21:16:56 +0530 | [diff] [blame] | 561 | assert_rpm_wakelock_held(dev_priv); |
| 562 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 563 | spin_lock_irq(&dev_priv->irq_lock); |
| 564 | dev_priv->guc.interrupts_enabled = false; |
| 565 | |
| 566 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); |
| 567 | |
| 568 | spin_unlock_irq(&dev_priv->irq_lock); |
| 569 | synchronize_irq(dev_priv->drm.irq); |
| 570 | |
| 571 | gen9_reset_guc_interrupts(dev_priv); |
| 572 | } |
| 573 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 574 | /** |
Ville Syrjälä | 81fd874 | 2015-11-25 16:21:30 +0200 | [diff] [blame] | 575 | * bdw_update_port_irq - update DE port interrupt |
| 576 | * @dev_priv: driver private |
| 577 | * @interrupt_mask: mask of interrupt bits to update |
| 578 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 579 | */ |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 580 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
| 581 | uint32_t interrupt_mask, |
| 582 | uint32_t enabled_irq_mask) |
| 583 | { |
| 584 | uint32_t new_val; |
| 585 | uint32_t old_val; |
| 586 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 587 | lockdep_assert_held(&dev_priv->irq_lock); |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 588 | |
| 589 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 590 | |
| 591 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 592 | return; |
| 593 | |
| 594 | old_val = I915_READ(GEN8_DE_PORT_IMR); |
| 595 | |
| 596 | new_val = old_val; |
| 597 | new_val &= ~interrupt_mask; |
| 598 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 599 | |
| 600 | if (new_val != old_val) { |
| 601 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); |
| 602 | POSTING_READ(GEN8_DE_PORT_IMR); |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | /** |
Ville Syrjälä | 013d375 | 2015-11-23 18:06:17 +0200 | [diff] [blame] | 607 | * bdw_update_pipe_irq - update DE pipe interrupt |
| 608 | * @dev_priv: driver private |
| 609 | * @pipe: pipe whose interrupt to update |
| 610 | * @interrupt_mask: mask of interrupt bits to update |
| 611 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 612 | */ |
| 613 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
| 614 | enum pipe pipe, |
| 615 | uint32_t interrupt_mask, |
| 616 | uint32_t enabled_irq_mask) |
| 617 | { |
| 618 | uint32_t new_val; |
| 619 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 620 | lockdep_assert_held(&dev_priv->irq_lock); |
Ville Syrjälä | 013d375 | 2015-11-23 18:06:17 +0200 | [diff] [blame] | 621 | |
| 622 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 623 | |
| 624 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 625 | return; |
| 626 | |
| 627 | new_val = dev_priv->de_irq_mask[pipe]; |
| 628 | new_val &= ~interrupt_mask; |
| 629 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 630 | |
| 631 | if (new_val != dev_priv->de_irq_mask[pipe]) { |
| 632 | dev_priv->de_irq_mask[pipe] = new_val; |
| 633 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 634 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | /** |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 639 | * ibx_display_interrupt_update - update SDEIMR |
| 640 | * @dev_priv: driver private |
| 641 | * @interrupt_mask: mask of interrupt bits to update |
| 642 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 643 | */ |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 644 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 645 | uint32_t interrupt_mask, |
| 646 | uint32_t enabled_irq_mask) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 647 | { |
| 648 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 649 | sdeimr &= ~interrupt_mask; |
| 650 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 651 | |
Daniel Vetter | 15a17aa | 2014-12-08 16:30:00 +0100 | [diff] [blame] | 652 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
| 653 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 654 | lockdep_assert_held(&dev_priv->irq_lock); |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 655 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 656 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 657 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 658 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 659 | I915_WRITE(SDEIMR, sdeimr); |
| 660 | POSTING_READ(SDEIMR); |
| 661 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 662 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 663 | u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, |
| 664 | enum pipe pipe) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 665 | { |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 666 | u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 667 | u32 enable_mask = status_mask << 16; |
| 668 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 669 | lockdep_assert_held(&dev_priv->irq_lock); |
| 670 | |
| 671 | if (INTEL_GEN(dev_priv) < 5) |
| 672 | goto out; |
| 673 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 674 | /* |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 675 | * On pipe A we don't support the PSR interrupt yet, |
| 676 | * on pipe B and C the same bit MBZ. |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 677 | */ |
| 678 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) |
| 679 | return 0; |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 680 | /* |
| 681 | * On pipe B and C we don't support the PSR interrupt yet, on pipe |
| 682 | * A the same bit is for perf counters which we don't use either. |
| 683 | */ |
| 684 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) |
| 685 | return 0; |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 686 | |
| 687 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | |
| 688 | SPRITE0_FLIP_DONE_INT_EN_VLV | |
| 689 | SPRITE1_FLIP_DONE_INT_EN_VLV); |
| 690 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) |
| 691 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; |
| 692 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) |
| 693 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; |
| 694 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 695 | out: |
| 696 | WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
| 697 | status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 698 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", |
| 699 | pipe_name(pipe), enable_mask, status_mask); |
| 700 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 701 | return enable_mask; |
| 702 | } |
| 703 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 704 | void i915_enable_pipestat(struct drm_i915_private *dev_priv, |
| 705 | enum pipe pipe, u32 status_mask) |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 706 | { |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 707 | i915_reg_t reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 708 | u32 enable_mask; |
| 709 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 710 | WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 711 | "pipe %c: status_mask=0x%x\n", |
| 712 | pipe_name(pipe), status_mask); |
| 713 | |
| 714 | lockdep_assert_held(&dev_priv->irq_lock); |
| 715 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
| 716 | |
| 717 | if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) |
| 718 | return; |
| 719 | |
| 720 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
| 721 | enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); |
| 722 | |
| 723 | I915_WRITE(reg, enable_mask | status_mask); |
| 724 | POSTING_READ(reg); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 725 | } |
| 726 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 727 | void i915_disable_pipestat(struct drm_i915_private *dev_priv, |
| 728 | enum pipe pipe, u32 status_mask) |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 729 | { |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 730 | i915_reg_t reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 731 | u32 enable_mask; |
| 732 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 733 | WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 734 | "pipe %c: status_mask=0x%x\n", |
| 735 | pipe_name(pipe), status_mask); |
| 736 | |
| 737 | lockdep_assert_held(&dev_priv->irq_lock); |
| 738 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
| 739 | |
| 740 | if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) |
| 741 | return; |
| 742 | |
| 743 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
| 744 | enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); |
| 745 | |
| 746 | I915_WRITE(reg, enable_mask | status_mask); |
| 747 | POSTING_READ(reg); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 748 | } |
| 749 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 750 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 751 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 752 | * @dev_priv: i915 device private |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 753 | */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 754 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 755 | { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 756 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 757 | return; |
| 758 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 759 | spin_lock_irq(&dev_priv->irq_lock); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 760 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 761 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 762 | if (INTEL_GEN(dev_priv) >= 4) |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 763 | i915_enable_pipestat(dev_priv, PIPE_A, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 764 | PIPE_LEGACY_BLC_EVENT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 765 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 766 | spin_unlock_irq(&dev_priv->irq_lock); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 767 | } |
| 768 | |
Ville Syrjälä | f75f374 | 2014-05-15 20:20:36 +0300 | [diff] [blame] | 769 | /* |
| 770 | * This timing diagram depicts the video signal in and |
| 771 | * around the vertical blanking period. |
| 772 | * |
| 773 | * Assumptions about the fictitious mode used in this example: |
| 774 | * vblank_start >= 3 |
| 775 | * vsync_start = vblank_start + 1 |
| 776 | * vsync_end = vblank_start + 2 |
| 777 | * vtotal = vblank_start + 3 |
| 778 | * |
| 779 | * start of vblank: |
| 780 | * latch double buffered registers |
| 781 | * increment frame counter (ctg+) |
| 782 | * generate start of vblank interrupt (gen4+) |
| 783 | * | |
| 784 | * | frame start: |
| 785 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) |
| 786 | * | may be shifted forward 1-3 extra lines via PIPECONF |
| 787 | * | | |
| 788 | * | | start of vsync: |
| 789 | * | | generate vsync interrupt |
| 790 | * | | | |
| 791 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx |
| 792 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ |
| 793 | * ----va---> <-----------------vb--------------------> <--------va------------- |
| 794 | * | | <----vs-----> | |
| 795 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) |
| 796 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) |
| 797 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) |
| 798 | * | | | |
| 799 | * last visible pixel first visible pixel |
| 800 | * | increment frame counter (gen3/4) |
| 801 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) |
| 802 | * |
| 803 | * x = horizontal active |
| 804 | * _ = horizontal blanking |
| 805 | * hs = horizontal sync |
| 806 | * va = vertical active |
| 807 | * vb = vertical blanking |
| 808 | * vs = vertical sync |
| 809 | * vbs = vblank_start (number) |
| 810 | * |
| 811 | * Summary: |
| 812 | * - most events happen at the start of horizontal sync |
| 813 | * - frame start happens at the start of horizontal blank, 1-4 lines |
| 814 | * (depending on PIPECONF settings) after the start of vblank |
| 815 | * - gen3/4 pixel and frame counter are synchronized with the start |
| 816 | * of horizontal active on the first line of vertical active |
| 817 | */ |
| 818 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 819 | /* Called from drm generic code, passed a 'crtc', which |
| 820 | * we use as a pipe index |
| 821 | */ |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 822 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 823 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 824 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 825 | i915_reg_t high_frame, low_frame; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 826 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
Daniel Vetter | 5caa0fe | 2017-05-09 16:03:29 +0200 | [diff] [blame] | 827 | const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode; |
Ville Syrjälä | 694e409 | 2017-03-09 17:44:30 +0200 | [diff] [blame] | 828 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 829 | |
Daniel Vetter | f3a5c3f | 2015-02-13 21:03:44 +0100 | [diff] [blame] | 830 | htotal = mode->crtc_htotal; |
| 831 | hsync_start = mode->crtc_hsync_start; |
| 832 | vbl_start = mode->crtc_vblank_start; |
| 833 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 834 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 835 | |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 836 | /* Convert to pixel count */ |
| 837 | vbl_start *= htotal; |
| 838 | |
| 839 | /* Start of vblank event occurs at start of hsync */ |
| 840 | vbl_start -= htotal - hsync_start; |
| 841 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 842 | high_frame = PIPEFRAME(pipe); |
| 843 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 844 | |
Ville Syrjälä | 694e409 | 2017-03-09 17:44:30 +0200 | [diff] [blame] | 845 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 846 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 847 | /* |
| 848 | * High & low register fields aren't synchronized, so make sure |
| 849 | * we get a low value that's stable across two reads of the high |
| 850 | * register. |
| 851 | */ |
| 852 | do { |
Ville Syrjälä | 694e409 | 2017-03-09 17:44:30 +0200 | [diff] [blame] | 853 | high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 854 | low = I915_READ_FW(low_frame); |
| 855 | high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 856 | } while (high1 != high2); |
| 857 | |
Ville Syrjälä | 694e409 | 2017-03-09 17:44:30 +0200 | [diff] [blame] | 858 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 859 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 860 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 861 | pixel = low & PIPE_PIXEL_MASK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 862 | low >>= PIPE_FRAME_LOW_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 863 | |
| 864 | /* |
| 865 | * The frame counter increments at beginning of active. |
| 866 | * Cook up a vblank counter by also checking the pixel |
| 867 | * counter against vblank start. |
| 868 | */ |
Ville Syrjälä | edc08d0 | 2013-11-06 13:56:27 -0200 | [diff] [blame] | 869 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 870 | } |
| 871 | |
Dave Airlie | 974e59b | 2015-10-30 09:45:33 +1000 | [diff] [blame] | 872 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 873 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 874 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 875 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 876 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 877 | } |
| 878 | |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 879 | /* |
| 880 | * On certain encoders on certain platforms, pipe |
| 881 | * scanline register will not work to get the scanline, |
| 882 | * since the timings are driven from the PORT or issues |
| 883 | * with scanline register updates. |
| 884 | * This function will use Framestamp and current |
| 885 | * timestamp registers to calculate the scanline. |
| 886 | */ |
| 887 | static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) |
| 888 | { |
| 889 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 890 | struct drm_vblank_crtc *vblank = |
| 891 | &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; |
| 892 | const struct drm_display_mode *mode = &vblank->hwmode; |
| 893 | u32 vblank_start = mode->crtc_vblank_start; |
| 894 | u32 vtotal = mode->crtc_vtotal; |
| 895 | u32 htotal = mode->crtc_htotal; |
| 896 | u32 clock = mode->crtc_clock; |
| 897 | u32 scanline, scan_prev_time, scan_curr_time, scan_post_time; |
| 898 | |
| 899 | /* |
| 900 | * To avoid the race condition where we might cross into the |
| 901 | * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR |
| 902 | * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR |
| 903 | * during the same frame. |
| 904 | */ |
| 905 | do { |
| 906 | /* |
| 907 | * This field provides read back of the display |
| 908 | * pipe frame time stamp. The time stamp value |
| 909 | * is sampled at every start of vertical blank. |
| 910 | */ |
| 911 | scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); |
| 912 | |
| 913 | /* |
| 914 | * The TIMESTAMP_CTR register has the current |
| 915 | * time stamp value. |
| 916 | */ |
| 917 | scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR); |
| 918 | |
| 919 | scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); |
| 920 | } while (scan_post_time != scan_prev_time); |
| 921 | |
| 922 | scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, |
| 923 | clock), 1000 * htotal); |
| 924 | scanline = min(scanline, vtotal - 1); |
| 925 | scanline = (scanline + vblank_start) % vtotal; |
| 926 | |
| 927 | return scanline; |
| 928 | } |
| 929 | |
Ville Syrjälä | 75aa3f6 | 2015-10-22 15:34:56 +0300 | [diff] [blame] | 930 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 931 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 932 | { |
| 933 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 934 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5caa0fe | 2017-05-09 16:03:29 +0200 | [diff] [blame] | 935 | const struct drm_display_mode *mode; |
| 936 | struct drm_vblank_crtc *vblank; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 937 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 938 | int position, vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 939 | |
Ville Syrjälä | 7225953 | 2017-03-02 19:15:05 +0200 | [diff] [blame] | 940 | if (!crtc->active) |
| 941 | return -1; |
| 942 | |
Daniel Vetter | 5caa0fe | 2017-05-09 16:03:29 +0200 | [diff] [blame] | 943 | vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; |
| 944 | mode = &vblank->hwmode; |
| 945 | |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 946 | if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) |
| 947 | return __intel_get_crtc_scanline_from_timestamp(crtc); |
| 948 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 949 | vtotal = mode->crtc_vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 950 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 951 | vtotal /= 2; |
| 952 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 953 | if (IS_GEN2(dev_priv)) |
Ville Syrjälä | 75aa3f6 | 2015-10-22 15:34:56 +0300 | [diff] [blame] | 954 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 955 | else |
Ville Syrjälä | 75aa3f6 | 2015-10-22 15:34:56 +0300 | [diff] [blame] | 956 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 957 | |
| 958 | /* |
Jesse Barnes | 41b578f | 2015-09-22 12:15:54 -0700 | [diff] [blame] | 959 | * On HSW, the DSL reg (0x70000) appears to return 0 if we |
| 960 | * read it just before the start of vblank. So try it again |
| 961 | * so we don't accidentally end up spanning a vblank frame |
| 962 | * increment, causing the pipe_update_end() code to squak at us. |
| 963 | * |
| 964 | * The nature of this problem means we can't simply check the ISR |
| 965 | * bit and return the vblank start value; nor can we use the scanline |
| 966 | * debug register in the transcoder as it appears to have the same |
| 967 | * problem. We may need to extend this to include other platforms, |
| 968 | * but so far testing only shows the problem on HSW. |
| 969 | */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 970 | if (HAS_DDI(dev_priv) && !position) { |
Jesse Barnes | 41b578f | 2015-09-22 12:15:54 -0700 | [diff] [blame] | 971 | int i, temp; |
| 972 | |
| 973 | for (i = 0; i < 100; i++) { |
| 974 | udelay(1); |
Ville Syrjälä | 707bdd3 | 2017-03-09 17:44:31 +0200 | [diff] [blame] | 975 | temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
Jesse Barnes | 41b578f | 2015-09-22 12:15:54 -0700 | [diff] [blame] | 976 | if (temp != position) { |
| 977 | position = temp; |
| 978 | break; |
| 979 | } |
| 980 | } |
| 981 | } |
| 982 | |
| 983 | /* |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 984 | * See update_scanline_offset() for the details on the |
| 985 | * scanline_offset adjustment. |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 986 | */ |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 987 | return (position + crtc->scanline_offset) % vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 988 | } |
| 989 | |
Daniel Vetter | 1bf6ad6 | 2017-05-09 16:03:28 +0200 | [diff] [blame] | 990 | static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
| 991 | bool in_vblank_irq, int *vpos, int *hpos, |
| 992 | ktime_t *stime, ktime_t *etime, |
| 993 | const struct drm_display_mode *mode) |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 994 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 995 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 9818783 | 2016-10-31 22:37:10 +0200 | [diff] [blame] | 996 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
| 997 | pipe); |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 998 | int position; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 999 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 1000 | unsigned long irqflags; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1001 | |
Maarten Lankhorst | fc467a22 | 2015-06-01 12:50:07 +0200 | [diff] [blame] | 1002 | if (WARN_ON(!mode->crtc_clock)) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1003 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1004 | "pipe %c\n", pipe_name(pipe)); |
Daniel Vetter | 1bf6ad6 | 2017-05-09 16:03:28 +0200 | [diff] [blame] | 1005 | return false; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1006 | } |
| 1007 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 1008 | htotal = mode->crtc_htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 1009 | hsync_start = mode->crtc_hsync_start; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 1010 | vtotal = mode->crtc_vtotal; |
| 1011 | vbl_start = mode->crtc_vblank_start; |
| 1012 | vbl_end = mode->crtc_vblank_end; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1013 | |
Ville Syrjälä | d31faf6 | 2013-10-28 16:31:41 +0200 | [diff] [blame] | 1014 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 1015 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
| 1016 | vbl_end /= 2; |
| 1017 | vtotal /= 2; |
| 1018 | } |
| 1019 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 1020 | /* |
| 1021 | * Lock uncore.lock, as we will do multiple timing critical raw |
| 1022 | * register reads, potentially with preemption disabled, so the |
| 1023 | * following code must not block on uncore.lock. |
| 1024 | */ |
| 1025 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 1026 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 1027 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
| 1028 | |
| 1029 | /* Get optional system timestamp before query. */ |
| 1030 | if (stime) |
| 1031 | *stime = ktime_get(); |
| 1032 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1033 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1034 | /* No obvious pixelcount register. Only query vertical |
| 1035 | * scanout position from Display scan line register. |
| 1036 | */ |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 1037 | position = __intel_get_crtc_scanline(intel_crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1038 | } else { |
| 1039 | /* Have access to pixelcount since start of frame. |
| 1040 | * We can split this into vertical and horizontal |
| 1041 | * scanout position. |
| 1042 | */ |
Ville Syrjälä | 75aa3f6 | 2015-10-22 15:34:56 +0300 | [diff] [blame] | 1043 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1044 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1045 | /* convert to pixel counts */ |
| 1046 | vbl_start *= htotal; |
| 1047 | vbl_end *= htotal; |
| 1048 | vtotal *= htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 1049 | |
| 1050 | /* |
Ville Syrjälä | 7e78f1cb | 2014-04-29 13:35:49 +0300 | [diff] [blame] | 1051 | * In interlaced modes, the pixel counter counts all pixels, |
| 1052 | * so one field will have htotal more pixels. In order to avoid |
| 1053 | * the reported position from jumping backwards when the pixel |
| 1054 | * counter is beyond the length of the shorter field, just |
| 1055 | * clamp the position the length of the shorter field. This |
| 1056 | * matches how the scanline counter based position works since |
| 1057 | * the scanline counter doesn't count the two half lines. |
| 1058 | */ |
| 1059 | if (position >= vtotal) |
| 1060 | position = vtotal - 1; |
| 1061 | |
| 1062 | /* |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 1063 | * Start of vblank interrupt is triggered at start of hsync, |
| 1064 | * just prior to the first active line of vblank. However we |
| 1065 | * consider lines to start at the leading edge of horizontal |
| 1066 | * active. So, should we get here before we've crossed into |
| 1067 | * the horizontal active of the first line in vblank, we would |
| 1068 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, |
| 1069 | * always add htotal-hsync_start to the current pixel position. |
| 1070 | */ |
| 1071 | position = (position + htotal - hsync_start) % vtotal; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1072 | } |
| 1073 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 1074 | /* Get optional system timestamp after query. */ |
| 1075 | if (etime) |
| 1076 | *etime = ktime_get(); |
| 1077 | |
| 1078 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
| 1079 | |
| 1080 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 1081 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1082 | /* |
| 1083 | * While in vblank, position will be negative |
| 1084 | * counting up towards 0 at vbl_end. And outside |
| 1085 | * vblank, position will be positive counting |
| 1086 | * up since vbl_end. |
| 1087 | */ |
| 1088 | if (position >= vbl_start) |
| 1089 | position -= vbl_end; |
| 1090 | else |
| 1091 | position += vtotal - vbl_end; |
| 1092 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1093 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1094 | *vpos = position; |
| 1095 | *hpos = 0; |
| 1096 | } else { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1097 | *vpos = position / htotal; |
| 1098 | *hpos = position - (*vpos * htotal); |
| 1099 | } |
| 1100 | |
Daniel Vetter | 1bf6ad6 | 2017-05-09 16:03:28 +0200 | [diff] [blame] | 1101 | return true; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1102 | } |
| 1103 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 1104 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 1105 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1106 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 1107 | unsigned long irqflags; |
| 1108 | int position; |
| 1109 | |
| 1110 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 1111 | position = __intel_get_crtc_scanline(crtc); |
| 1112 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 1113 | |
| 1114 | return position; |
| 1115 | } |
| 1116 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1117 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1118 | { |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1119 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1120 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1121 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1122 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1123 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 1124 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 1125 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1126 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1127 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1128 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1129 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 1130 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1131 | max_avg = I915_READ(RCBMAXAVG); |
| 1132 | min_avg = I915_READ(RCBMINAVG); |
| 1133 | |
| 1134 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1135 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1136 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 1137 | new_delay = dev_priv->ips.cur_delay - 1; |
| 1138 | if (new_delay < dev_priv->ips.max_delay) |
| 1139 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1140 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1141 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 1142 | new_delay = dev_priv->ips.cur_delay + 1; |
| 1143 | if (new_delay > dev_priv->ips.min_delay) |
| 1144 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1145 | } |
| 1146 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1147 | if (ironlake_set_drps(dev_priv, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1148 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1149 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1150 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1151 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1152 | return; |
| 1153 | } |
| 1154 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1155 | static void notify_ring(struct intel_engine_cs *engine) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1156 | { |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1157 | const u32 seqno = intel_engine_get_seqno(engine); |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 1158 | struct i915_request *rq = NULL; |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1159 | struct task_struct *tsk = NULL; |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1160 | struct intel_wait *wait; |
Tvrtko Ursulin | dffabc8 | 2017-02-21 09:13:48 +0000 | [diff] [blame] | 1161 | |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1162 | if (unlikely(!engine->breadcrumbs.irq_armed)) |
Chris Wilson | bcbd5c3 | 2017-10-25 15:39:42 +0100 | [diff] [blame] | 1163 | return; |
| 1164 | |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1165 | rcu_read_lock(); |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1166 | |
Chris Wilson | 61d3dc7 | 2017-03-03 19:08:24 +0000 | [diff] [blame] | 1167 | spin_lock(&engine->breadcrumbs.irq_lock); |
| 1168 | wait = engine->breadcrumbs.irq_wait; |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1169 | if (wait) { |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1170 | /* |
| 1171 | * We use a callback from the dma-fence to submit |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1172 | * requests after waiting on our own requests. To |
| 1173 | * ensure minimum delay in queuing the next request to |
| 1174 | * hardware, signal the fence now rather than wait for |
| 1175 | * the signaler to be woken up. We still wake up the |
| 1176 | * waiter in order to handle the irq-seqno coherency |
| 1177 | * issues (we may receive the interrupt before the |
| 1178 | * seqno is written, see __i915_request_irq_complete()) |
| 1179 | * and to handle coalescing of multiple seqno updates |
| 1180 | * and many waiters. |
| 1181 | */ |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1182 | if (i915_seqno_passed(seqno, wait->seqno)) { |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 1183 | struct i915_request *waiter = wait->request; |
Chris Wilson | de4d210 | 2017-09-18 17:27:34 +0100 | [diff] [blame] | 1184 | |
Chris Wilson | 17b51ad | 2017-09-18 17:27:33 +0100 | [diff] [blame] | 1185 | if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
Chris Wilson | de4d210 | 2017-09-18 17:27:34 +0100 | [diff] [blame] | 1186 | &waiter->fence.flags) && |
| 1187 | intel_wait_check_request(wait, waiter)) |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 1188 | rq = i915_request_get(waiter); |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1189 | |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1190 | tsk = wait->tsk; |
| 1191 | } else { |
Chris Wilson | 69dc4d0 | 2018-06-27 21:13:02 +0100 | [diff] [blame] | 1192 | if (engine->irq_seqno_barrier && |
| 1193 | i915_seqno_passed(seqno, wait->seqno - 1)) { |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1194 | set_bit(ENGINE_IRQ_BREADCRUMB, |
| 1195 | &engine->irq_posted); |
| 1196 | tsk = wait->tsk; |
| 1197 | } |
| 1198 | } |
Chris Wilson | 7879687 | 2018-06-27 21:13:03 +0100 | [diff] [blame^] | 1199 | |
| 1200 | engine->breadcrumbs.irq_count++; |
Chris Wilson | 67b807a8 | 2017-02-27 20:58:50 +0000 | [diff] [blame] | 1201 | } else { |
Chris Wilson | bcbd5c3 | 2017-10-25 15:39:42 +0100 | [diff] [blame] | 1202 | if (engine->breadcrumbs.irq_armed) |
| 1203 | __intel_engine_disarm_breadcrumbs(engine); |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1204 | } |
Chris Wilson | 61d3dc7 | 2017-03-03 19:08:24 +0000 | [diff] [blame] | 1205 | spin_unlock(&engine->breadcrumbs.irq_lock); |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1206 | |
Chris Wilson | 24754d7 | 2017-03-03 14:45:57 +0000 | [diff] [blame] | 1207 | if (rq) { |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1208 | dma_fence_signal(&rq->fence); |
Chris Wilson | 4e9a8be | 2018-03-05 10:41:05 +0000 | [diff] [blame] | 1209 | GEM_BUG_ON(!i915_request_completed(rq)); |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 1210 | i915_request_put(rq); |
Chris Wilson | 24754d7 | 2017-03-03 14:45:57 +0000 | [diff] [blame] | 1211 | } |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1212 | |
Chris Wilson | 3f88325 | 2018-06-27 21:13:01 +0100 | [diff] [blame] | 1213 | if (tsk && tsk->state & TASK_NORMAL) |
| 1214 | wake_up_process(tsk); |
| 1215 | |
| 1216 | rcu_read_unlock(); |
| 1217 | |
Chris Wilson | 56299fb | 2017-02-27 20:58:48 +0000 | [diff] [blame] | 1218 | trace_intel_engine_notify(engine, wait); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1219 | } |
| 1220 | |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1221 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
| 1222 | struct intel_rps_ei *ei) |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1223 | { |
Mika Kuoppala | 679cb6c | 2017-03-15 17:43:03 +0200 | [diff] [blame] | 1224 | ei->ktime = ktime_get_raw(); |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1225 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); |
| 1226 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1227 | } |
| 1228 | |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1229 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
| 1230 | { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1231 | memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei)); |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1232 | } |
| 1233 | |
| 1234 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
| 1235 | { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1236 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
| 1237 | const struct intel_rps_ei *prev = &rps->ei; |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1238 | struct intel_rps_ei now; |
| 1239 | u32 events = 0; |
| 1240 | |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1241 | if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1242 | return 0; |
| 1243 | |
| 1244 | vlv_c0_read(dev_priv, &now); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1245 | |
Mika Kuoppala | 679cb6c | 2017-03-15 17:43:03 +0200 | [diff] [blame] | 1246 | if (prev->ktime) { |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1247 | u64 time, c0; |
Chris Wilson | 569884e | 2017-03-09 21:12:31 +0000 | [diff] [blame] | 1248 | u32 render, media; |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1249 | |
Mika Kuoppala | 679cb6c | 2017-03-15 17:43:03 +0200 | [diff] [blame] | 1250 | time = ktime_us_delta(now.ktime, prev->ktime); |
Chris Wilson | 8f68d59 | 2017-03-13 17:06:17 +0000 | [diff] [blame] | 1251 | |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1252 | time *= dev_priv->czclk_freq; |
| 1253 | |
| 1254 | /* Workload can be split between render + media, |
| 1255 | * e.g. SwapBuffers being blitted in X after being rendered in |
| 1256 | * mesa. To account for this we need to combine both engines |
| 1257 | * into our activity counter. |
| 1258 | */ |
Chris Wilson | 569884e | 2017-03-09 21:12:31 +0000 | [diff] [blame] | 1259 | render = now.render_c0 - prev->render_c0; |
| 1260 | media = now.media_c0 - prev->media_c0; |
| 1261 | c0 = max(render, media); |
Mika Kuoppala | 6b7f6aa | 2017-03-15 18:12:59 +0200 | [diff] [blame] | 1262 | c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1263 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1264 | if (c0 > time * rps->up_threshold) |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1265 | events = GEN6_PM_RP_UP_THRESHOLD; |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1266 | else if (c0 < time * rps->down_threshold) |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 1267 | events = GEN6_PM_RP_DOWN_THRESHOLD; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1268 | } |
| 1269 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1270 | rps->ei = now; |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1271 | return events; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1272 | } |
| 1273 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1274 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1275 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1276 | struct drm_i915_private *dev_priv = |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1277 | container_of(work, struct drm_i915_private, gt_pm.rps.work); |
| 1278 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
Chris Wilson | 7c0a16a | 2017-03-09 21:12:32 +0000 | [diff] [blame] | 1279 | bool client_boost = false; |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 1280 | int new_delay, adj, min, max; |
Chris Wilson | 7c0a16a | 2017-03-09 21:12:32 +0000 | [diff] [blame] | 1281 | u32 pm_iir = 0; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1282 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1283 | spin_lock_irq(&dev_priv->irq_lock); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1284 | if (rps->interrupts_enabled) { |
| 1285 | pm_iir = fetch_and_zero(&rps->pm_iir); |
| 1286 | client_boost = atomic_read(&rps->num_waiters); |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 1287 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1288 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1289 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1290 | /* Make sure we didn't queue anything we're not going to process. */ |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1291 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 1292 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
Chris Wilson | 7c0a16a | 2017-03-09 21:12:32 +0000 | [diff] [blame] | 1293 | goto out; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1294 | |
Sagar Arun Kamble | 9f81750 | 2017-10-10 22:30:05 +0100 | [diff] [blame] | 1295 | mutex_lock(&dev_priv->pcu_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 1296 | |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 1297 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
| 1298 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1299 | adj = rps->last_adj; |
| 1300 | new_delay = rps->cur_freq; |
| 1301 | min = rps->min_freq_softlimit; |
| 1302 | max = rps->max_freq_softlimit; |
Chris Wilson | 7b92c1b | 2017-06-28 13:35:48 +0100 | [diff] [blame] | 1303 | if (client_boost) |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1304 | max = rps->max_freq; |
| 1305 | if (client_boost && new_delay < rps->boost_freq) { |
| 1306 | new_delay = rps->boost_freq; |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 1307 | adj = 0; |
| 1308 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1309 | if (adj > 0) |
| 1310 | adj *= 2; |
Chris Wilson | edcf284 | 2015-04-07 16:20:29 +0100 | [diff] [blame] | 1311 | else /* CHV needs even encode values */ |
| 1312 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; |
Sagar Arun Kamble | 7e79a68 | 2017-01-20 09:18:24 +0530 | [diff] [blame] | 1313 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1314 | if (new_delay >= rps->max_freq_softlimit) |
Sagar Arun Kamble | 7e79a68 | 2017-01-20 09:18:24 +0530 | [diff] [blame] | 1315 | adj = 0; |
Chris Wilson | 7b92c1b | 2017-06-28 13:35:48 +0100 | [diff] [blame] | 1316 | } else if (client_boost) { |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 1317 | adj = 0; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1318 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1319 | if (rps->cur_freq > rps->efficient_freq) |
| 1320 | new_delay = rps->efficient_freq; |
| 1321 | else if (rps->cur_freq > rps->min_freq_softlimit) |
| 1322 | new_delay = rps->min_freq_softlimit; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1323 | adj = 0; |
| 1324 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
| 1325 | if (adj < 0) |
| 1326 | adj *= 2; |
Chris Wilson | edcf284 | 2015-04-07 16:20:29 +0100 | [diff] [blame] | 1327 | else /* CHV needs even encode values */ |
| 1328 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; |
Sagar Arun Kamble | 7e79a68 | 2017-01-20 09:18:24 +0530 | [diff] [blame] | 1329 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1330 | if (new_delay <= rps->min_freq_softlimit) |
Sagar Arun Kamble | 7e79a68 | 2017-01-20 09:18:24 +0530 | [diff] [blame] | 1331 | adj = 0; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1332 | } else { /* unknown event */ |
Chris Wilson | edcf284 | 2015-04-07 16:20:29 +0100 | [diff] [blame] | 1333 | adj = 0; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1334 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1335 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1336 | rps->last_adj = adj; |
Chris Wilson | edcf284 | 2015-04-07 16:20:29 +0100 | [diff] [blame] | 1337 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 1338 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 1339 | * interrupt |
| 1340 | */ |
Chris Wilson | edcf284 | 2015-04-07 16:20:29 +0100 | [diff] [blame] | 1341 | new_delay += adj; |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 1342 | new_delay = clamp_t(int, new_delay, min, max); |
Deepak S | 2754436 | 2014-01-27 21:35:05 +0530 | [diff] [blame] | 1343 | |
Chris Wilson | 9fcee2f | 2017-01-26 10:19:19 +0000 | [diff] [blame] | 1344 | if (intel_set_rps(dev_priv, new_delay)) { |
| 1345 | DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n"); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1346 | rps->last_adj = 0; |
Chris Wilson | 9fcee2f | 2017-01-26 10:19:19 +0000 | [diff] [blame] | 1347 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1348 | |
Sagar Arun Kamble | 9f81750 | 2017-10-10 22:30:05 +0100 | [diff] [blame] | 1349 | mutex_unlock(&dev_priv->pcu_lock); |
Chris Wilson | 7c0a16a | 2017-03-09 21:12:32 +0000 | [diff] [blame] | 1350 | |
| 1351 | out: |
| 1352 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
| 1353 | spin_lock_irq(&dev_priv->irq_lock); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1354 | if (rps->interrupts_enabled) |
Chris Wilson | 7c0a16a | 2017-03-09 21:12:32 +0000 | [diff] [blame] | 1355 | gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events); |
| 1356 | spin_unlock_irq(&dev_priv->irq_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1357 | } |
| 1358 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1359 | |
| 1360 | /** |
| 1361 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 1362 | * occurred. |
| 1363 | * @work: workqueue struct |
| 1364 | * |
| 1365 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 1366 | * this event, userspace should try to remap the bad rows since statistically |
| 1367 | * it is likely the same row is more likely to go bad again. |
| 1368 | */ |
| 1369 | static void ivybridge_parity_work(struct work_struct *work) |
| 1370 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1371 | struct drm_i915_private *dev_priv = |
Joonas Lahtinen | cefcff8 | 2017-04-28 10:58:39 +0300 | [diff] [blame] | 1372 | container_of(work, typeof(*dev_priv), l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1373 | u32 error_status, row, bank, subbank; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1374 | char *parity_event[6]; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1375 | uint32_t misccpctl; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1376 | uint8_t slice = 0; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1377 | |
| 1378 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 1379 | * In order to prevent a get/put style interface, acquire struct mutex |
| 1380 | * any time we access those registers. |
| 1381 | */ |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1382 | mutex_lock(&dev_priv->drm.struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1383 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1384 | /* If we've screwed up tracking, just let the interrupt fire again */ |
| 1385 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) |
| 1386 | goto out; |
| 1387 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1388 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1389 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 1390 | POSTING_READ(GEN7_MISCCPCTL); |
| 1391 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1392 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1393 | i915_reg_t reg; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1394 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1395 | slice--; |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1396 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1397 | break; |
| 1398 | |
| 1399 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
| 1400 | |
Ville Syrjälä | 6fa1c5f | 2015-11-04 23:20:02 +0200 | [diff] [blame] | 1401 | reg = GEN7_L3CDERRST1(slice); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1402 | |
| 1403 | error_status = I915_READ(reg); |
| 1404 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 1405 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 1406 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 1407 | |
| 1408 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); |
| 1409 | POSTING_READ(reg); |
| 1410 | |
| 1411 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
| 1412 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 1413 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 1414 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 1415 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); |
| 1416 | parity_event[5] = NULL; |
| 1417 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1418 | kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1419 | KOBJ_CHANGE, parity_event); |
| 1420 | |
| 1421 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
| 1422 | slice, row, bank, subbank); |
| 1423 | |
| 1424 | kfree(parity_event[4]); |
| 1425 | kfree(parity_event[3]); |
| 1426 | kfree(parity_event[2]); |
| 1427 | kfree(parity_event[1]); |
| 1428 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1429 | |
| 1430 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 1431 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1432 | out: |
| 1433 | WARN_ON(dev_priv->l3_parity.which_slice); |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 1434 | spin_lock_irq(&dev_priv->irq_lock); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1435 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 1436 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1437 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1438 | mutex_unlock(&dev_priv->drm.struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1439 | } |
| 1440 | |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1441 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
| 1442 | u32 iir) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1443 | { |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1444 | if (!HAS_L3_DPF(dev_priv)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1445 | return; |
| 1446 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1447 | spin_lock(&dev_priv->irq_lock); |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1448 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1449 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1450 | |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1451 | iir &= GT_PARITY_ERROR(dev_priv); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1452 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
| 1453 | dev_priv->l3_parity.which_slice |= 1 << 1; |
| 1454 | |
| 1455 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
| 1456 | dev_priv->l3_parity.which_slice |= 1 << 0; |
| 1457 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1458 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1459 | } |
| 1460 | |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1461 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1462 | u32 gt_iir) |
| 1463 | { |
Chris Wilson | f8973c2 | 2016-07-01 17:23:21 +0100 | [diff] [blame] | 1464 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1465 | notify_ring(dev_priv->engine[RCS]); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1466 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1467 | notify_ring(dev_priv->engine[VCS]); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1468 | } |
| 1469 | |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1470 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1471 | u32 gt_iir) |
| 1472 | { |
Chris Wilson | f8973c2 | 2016-07-01 17:23:21 +0100 | [diff] [blame] | 1473 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1474 | notify_ring(dev_priv->engine[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1475 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1476 | notify_ring(dev_priv->engine[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1477 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1478 | notify_ring(dev_priv->engine[BCS]); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1479 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1480 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 1481 | GT_BSD_CS_ERROR_INTERRUPT | |
Daniel Vetter | aaecdf6 | 2014-11-04 15:52:22 +0100 | [diff] [blame] | 1482 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
| 1483 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1484 | |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 1485 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
| 1486 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1487 | } |
| 1488 | |
Chris Wilson | 5d3d69d | 2017-05-17 13:10:06 +0100 | [diff] [blame] | 1489 | static void |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1490 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir) |
Nick Hoath | fbcc1a0 | 2015-10-20 10:23:52 +0100 | [diff] [blame] | 1491 | { |
Mika Kuoppala | b620e87 | 2017-09-22 15:43:03 +0300 | [diff] [blame] | 1492 | struct intel_engine_execlists * const execlists = &engine->execlists; |
Chris Wilson | 31de735 | 2017-03-16 12:56:18 +0000 | [diff] [blame] | 1493 | bool tasklet = false; |
Chris Wilson | f747026 | 2017-01-24 15:20:21 +0000 | [diff] [blame] | 1494 | |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1495 | if (iir & GT_CONTEXT_SWITCH_INTERRUPT) { |
Chris Wilson | 1c645bf | 2018-03-22 07:35:32 +0000 | [diff] [blame] | 1496 | if (READ_ONCE(engine->execlists.active)) |
| 1497 | tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST, |
| 1498 | &engine->irq_posted); |
Chris Wilson | f747026 | 2017-01-24 15:20:21 +0000 | [diff] [blame] | 1499 | } |
Chris Wilson | 31de735 | 2017-03-16 12:56:18 +0000 | [diff] [blame] | 1500 | |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1501 | if (iir & GT_RENDER_USER_INTERRUPT) { |
Chris Wilson | 31de735 | 2017-03-16 12:56:18 +0000 | [diff] [blame] | 1502 | notify_ring(engine); |
Michal Wajdeczko | 93ffbe8 | 2017-12-06 13:53:12 +0000 | [diff] [blame] | 1503 | tasklet |= USES_GUC_SUBMISSION(engine->i915); |
Chris Wilson | 31de735 | 2017-03-16 12:56:18 +0000 | [diff] [blame] | 1504 | } |
| 1505 | |
| 1506 | if (tasklet) |
Sagar Arun Kamble | c6dce8f | 2017-11-16 19:02:37 +0530 | [diff] [blame] | 1507 | tasklet_hi_schedule(&execlists->tasklet); |
Nick Hoath | fbcc1a0 | 2015-10-20 10:23:52 +0100 | [diff] [blame] | 1508 | } |
| 1509 | |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1510 | static void gen8_gt_irq_ack(struct drm_i915_private *i915, |
Chris Wilson | 55ef72f | 2018-02-02 15:34:48 +0000 | [diff] [blame] | 1511 | u32 master_ctl, u32 gt_iir[4]) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1512 | { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1513 | void __iomem * const regs = i915->regs; |
| 1514 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1515 | #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ |
| 1516 | GEN8_GT_BCS_IRQ | \ |
| 1517 | GEN8_GT_VCS1_IRQ | \ |
| 1518 | GEN8_GT_VCS2_IRQ | \ |
| 1519 | GEN8_GT_VECS_IRQ | \ |
| 1520 | GEN8_GT_PM_IRQ | \ |
| 1521 | GEN8_GT_GUC_IRQ) |
| 1522 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1523 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1524 | gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0)); |
| 1525 | if (likely(gt_iir[0])) |
| 1526 | raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1527 | } |
| 1528 | |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1529 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1530 | gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1)); |
| 1531 | if (likely(gt_iir[1])) |
| 1532 | raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]); |
Chris Wilson | 74cdb33 | 2015-04-07 16:21:05 +0100 | [diff] [blame] | 1533 | } |
| 1534 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 1535 | if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1536 | gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2)); |
| 1537 | if (likely(gt_iir[2] & (i915->pm_rps_events | |
| 1538 | i915->pm_guc_events))) |
| 1539 | raw_reg_write(regs, GEN8_GT_IIR(2), |
| 1540 | gt_iir[2] & (i915->pm_rps_events | |
| 1541 | i915->pm_guc_events)); |
| 1542 | } |
| 1543 | |
| 1544 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
| 1545 | gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3)); |
| 1546 | if (likely(gt_iir[3])) |
| 1547 | raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1548 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1549 | } |
| 1550 | |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1551 | static void gen8_gt_irq_handler(struct drm_i915_private *i915, |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1552 | u32 master_ctl, u32 gt_iir[4]) |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 1553 | { |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1554 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1555 | gen8_cs_irq_handler(i915->engine[RCS], |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1556 | gt_iir[0] >> GEN8_RCS_IRQ_SHIFT); |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1557 | gen8_cs_irq_handler(i915->engine[BCS], |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1558 | gt_iir[0] >> GEN8_BCS_IRQ_SHIFT); |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 1559 | } |
| 1560 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1561 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1562 | gen8_cs_irq_handler(i915->engine[VCS], |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1563 | gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT); |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1564 | gen8_cs_irq_handler(i915->engine[VCS2], |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1565 | gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT); |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 1566 | } |
| 1567 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1568 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1569 | gen8_cs_irq_handler(i915->engine[VECS], |
Chris Wilson | 51f6b0f | 2018-03-09 01:08:08 +0000 | [diff] [blame] | 1570 | gt_iir[3] >> GEN8_VECS_IRQ_SHIFT); |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1571 | } |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 1572 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1573 | if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { |
Chris Wilson | 2e4a5b2 | 2018-02-19 10:09:26 +0000 | [diff] [blame] | 1574 | gen6_rps_irq_handler(i915, gt_iir[2]); |
| 1575 | gen9_guc_irq_handler(i915, gt_iir[2]); |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 1576 | } |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 1577 | } |
| 1578 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 1579 | static bool gen11_port_hotplug_long_detect(enum port port, u32 val) |
| 1580 | { |
| 1581 | switch (port) { |
| 1582 | case PORT_C: |
| 1583 | return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); |
| 1584 | case PORT_D: |
| 1585 | return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); |
| 1586 | case PORT_E: |
| 1587 | return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); |
| 1588 | case PORT_F: |
| 1589 | return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); |
| 1590 | default: |
| 1591 | return false; |
| 1592 | } |
| 1593 | } |
| 1594 | |
Imre Deak | 63c88d2 | 2015-07-20 14:43:39 -0700 | [diff] [blame] | 1595 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
| 1596 | { |
| 1597 | switch (port) { |
| 1598 | case PORT_A: |
Ville Syrjälä | 195baa0 | 2015-08-27 23:56:00 +0300 | [diff] [blame] | 1599 | return val & PORTA_HOTPLUG_LONG_DETECT; |
Imre Deak | 63c88d2 | 2015-07-20 14:43:39 -0700 | [diff] [blame] | 1600 | case PORT_B: |
| 1601 | return val & PORTB_HOTPLUG_LONG_DETECT; |
| 1602 | case PORT_C: |
| 1603 | return val & PORTC_HOTPLUG_LONG_DETECT; |
Imre Deak | 63c88d2 | 2015-07-20 14:43:39 -0700 | [diff] [blame] | 1604 | default: |
| 1605 | return false; |
| 1606 | } |
| 1607 | } |
| 1608 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 1609 | static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val) |
| 1610 | { |
| 1611 | switch (port) { |
| 1612 | case PORT_A: |
| 1613 | return val & ICP_DDIA_HPD_LONG_DETECT; |
| 1614 | case PORT_B: |
| 1615 | return val & ICP_DDIB_HPD_LONG_DETECT; |
| 1616 | default: |
| 1617 | return false; |
| 1618 | } |
| 1619 | } |
| 1620 | |
| 1621 | static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val) |
| 1622 | { |
| 1623 | switch (port) { |
| 1624 | case PORT_C: |
| 1625 | return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); |
| 1626 | case PORT_D: |
| 1627 | return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); |
| 1628 | case PORT_E: |
| 1629 | return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); |
| 1630 | case PORT_F: |
| 1631 | return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); |
| 1632 | default: |
| 1633 | return false; |
| 1634 | } |
| 1635 | } |
| 1636 | |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 1637 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
| 1638 | { |
| 1639 | switch (port) { |
| 1640 | case PORT_E: |
| 1641 | return val & PORTE_HOTPLUG_LONG_DETECT; |
| 1642 | default: |
| 1643 | return false; |
| 1644 | } |
| 1645 | } |
| 1646 | |
Ville Syrjälä | 74c0b39 | 2015-08-27 23:56:07 +0300 | [diff] [blame] | 1647 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
| 1648 | { |
| 1649 | switch (port) { |
| 1650 | case PORT_A: |
| 1651 | return val & PORTA_HOTPLUG_LONG_DETECT; |
| 1652 | case PORT_B: |
| 1653 | return val & PORTB_HOTPLUG_LONG_DETECT; |
| 1654 | case PORT_C: |
| 1655 | return val & PORTC_HOTPLUG_LONG_DETECT; |
| 1656 | case PORT_D: |
| 1657 | return val & PORTD_HOTPLUG_LONG_DETECT; |
| 1658 | default: |
| 1659 | return false; |
| 1660 | } |
| 1661 | } |
| 1662 | |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 1663 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
| 1664 | { |
| 1665 | switch (port) { |
| 1666 | case PORT_A: |
| 1667 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; |
| 1668 | default: |
| 1669 | return false; |
| 1670 | } |
| 1671 | } |
| 1672 | |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1673 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1674 | { |
| 1675 | switch (port) { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1676 | case PORT_B: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1677 | return val & PORTB_HOTPLUG_LONG_DETECT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1678 | case PORT_C: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1679 | return val & PORTC_HOTPLUG_LONG_DETECT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1680 | case PORT_D: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1681 | return val & PORTD_HOTPLUG_LONG_DETECT; |
| 1682 | default: |
| 1683 | return false; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1684 | } |
| 1685 | } |
| 1686 | |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1687 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1688 | { |
| 1689 | switch (port) { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1690 | case PORT_B: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1691 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1692 | case PORT_C: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1693 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1694 | case PORT_D: |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1695 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
| 1696 | default: |
| 1697 | return false; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1698 | } |
| 1699 | } |
| 1700 | |
Ville Syrjälä | 42db67d | 2015-08-28 21:26:27 +0300 | [diff] [blame] | 1701 | /* |
| 1702 | * Get a bit mask of pins that have triggered, and which ones may be long. |
| 1703 | * This can be called multiple times with the same masks to accumulate |
| 1704 | * hotplug detection results from several registers. |
| 1705 | * |
| 1706 | * Note that the caller is expected to zero out the masks initially. |
| 1707 | */ |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 1708 | static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, |
| 1709 | u32 *pin_mask, u32 *long_mask, |
| 1710 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
| 1711 | const u32 hpd[HPD_NUM_PINS], |
| 1712 | bool long_pulse_detect(enum port port, u32 val)) |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1713 | { |
Jani Nikula | 8c841e5 | 2015-06-18 13:06:17 +0300 | [diff] [blame] | 1714 | enum port port; |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1715 | int i; |
| 1716 | |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1717 | for_each_hpd_pin(i) { |
Jani Nikula | 8c841e5 | 2015-06-18 13:06:17 +0300 | [diff] [blame] | 1718 | if ((hpd[i] & hotplug_trigger) == 0) |
| 1719 | continue; |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1720 | |
Jani Nikula | 8c841e5 | 2015-06-18 13:06:17 +0300 | [diff] [blame] | 1721 | *pin_mask |= BIT(i); |
| 1722 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 1723 | port = intel_hpd_pin_to_port(dev_priv, i); |
Rodrigo Vivi | 256cfdde | 2017-08-11 11:26:49 -0700 | [diff] [blame] | 1724 | if (port == PORT_NONE) |
Imre Deak | cc24fcd | 2015-07-21 15:32:45 -0700 | [diff] [blame] | 1725 | continue; |
| 1726 | |
Imre Deak | fd63e2a | 2015-07-21 15:32:44 -0700 | [diff] [blame] | 1727 | if (long_pulse_detect(port, dig_hotplug_reg)) |
Jani Nikula | 8c841e5 | 2015-06-18 13:06:17 +0300 | [diff] [blame] | 1728 | *long_mask |= BIT(i); |
Jani Nikula | 676574d | 2015-05-28 15:43:53 +0300 | [diff] [blame] | 1729 | } |
| 1730 | |
| 1731 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", |
| 1732 | hotplug_trigger, dig_hotplug_reg, *pin_mask); |
| 1733 | |
| 1734 | } |
| 1735 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1736 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1737 | { |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1738 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1739 | } |
| 1740 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1741 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1742 | { |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1743 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1744 | } |
| 1745 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1746 | #if defined(CONFIG_DEBUG_FS) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1747 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
| 1748 | enum pipe pipe, |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1749 | uint32_t crc0, uint32_t crc1, |
| 1750 | uint32_t crc2, uint32_t crc3, |
| 1751 | uint32_t crc4) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1752 | { |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1753 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
| 1754 | struct intel_pipe_crc_entry *entry; |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1755 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 1756 | struct drm_driver *driver = dev_priv->drm.driver; |
| 1757 | uint32_t crcs[5]; |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1758 | int head, tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1759 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1760 | spin_lock(&pipe_crc->lock); |
Maarten Lankhorst | 033b7a2 | 2018-03-08 13:02:02 +0100 | [diff] [blame] | 1761 | if (pipe_crc->source && !crtc->base.crc.opened) { |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1762 | if (!pipe_crc->entries) { |
| 1763 | spin_unlock(&pipe_crc->lock); |
| 1764 | DRM_DEBUG_KMS("spurious interrupt\n"); |
| 1765 | return; |
| 1766 | } |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1767 | |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1768 | head = pipe_crc->head; |
| 1769 | tail = pipe_crc->tail; |
| 1770 | |
| 1771 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
| 1772 | spin_unlock(&pipe_crc->lock); |
| 1773 | DRM_ERROR("CRC buffer overflowing\n"); |
| 1774 | return; |
| 1775 | } |
| 1776 | |
| 1777 | entry = &pipe_crc->entries[head]; |
| 1778 | |
| 1779 | entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe); |
| 1780 | entry->crc[0] = crc0; |
| 1781 | entry->crc[1] = crc1; |
| 1782 | entry->crc[2] = crc2; |
| 1783 | entry->crc[3] = crc3; |
| 1784 | entry->crc[4] = crc4; |
| 1785 | |
| 1786 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
| 1787 | pipe_crc->head = head; |
| 1788 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1789 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1790 | |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1791 | wake_up_interruptible(&pipe_crc->wq); |
| 1792 | } else { |
| 1793 | /* |
| 1794 | * For some not yet identified reason, the first CRC is |
| 1795 | * bonkers. So let's just wait for the next vblank and read |
| 1796 | * out the buggy result. |
| 1797 | * |
Rodrigo Vivi | 163e8ae | 2017-09-27 17:20:40 -0700 | [diff] [blame] | 1798 | * On GEN8+ sometimes the second CRC is bonkers as well, so |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1799 | * don't trust that one either. |
| 1800 | */ |
Maarten Lankhorst | 033b7a2 | 2018-03-08 13:02:02 +0100 | [diff] [blame] | 1801 | if (pipe_crc->skipped <= 0 || |
Rodrigo Vivi | 163e8ae | 2017-09-27 17:20:40 -0700 | [diff] [blame] | 1802 | (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1803 | pipe_crc->skipped++; |
| 1804 | spin_unlock(&pipe_crc->lock); |
| 1805 | return; |
| 1806 | } |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1807 | spin_unlock(&pipe_crc->lock); |
Tomeu Vizoso | 8c6b709 | 2017-01-10 14:43:04 +0100 | [diff] [blame] | 1808 | crcs[0] = crc0; |
| 1809 | crcs[1] = crc1; |
| 1810 | crcs[2] = crc2; |
| 1811 | crcs[3] = crc3; |
| 1812 | crcs[4] = crc4; |
Tomeu Vizoso | 246ee52 | 2017-01-10 14:43:05 +0100 | [diff] [blame] | 1813 | drm_crtc_add_crc_entry(&crtc->base, true, |
Daniel Vetter | ca814b2 | 2017-05-24 16:51:47 +0200 | [diff] [blame] | 1814 | drm_crtc_accurate_vblank_count(&crtc->base), |
Tomeu Vizoso | 246ee52 | 2017-01-10 14:43:05 +0100 | [diff] [blame] | 1815 | crcs); |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1816 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1817 | } |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1818 | #else |
| 1819 | static inline void |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1820 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
| 1821 | enum pipe pipe, |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1822 | uint32_t crc0, uint32_t crc1, |
| 1823 | uint32_t crc2, uint32_t crc3, |
| 1824 | uint32_t crc4) {} |
| 1825 | #endif |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1826 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1827 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1828 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
| 1829 | enum pipe pipe) |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1830 | { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1831 | display_pipe_crc_irq_handler(dev_priv, pipe, |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1832 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1833 | 0, 0, 0, 0); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1834 | } |
| 1835 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1836 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
| 1837 | enum pipe pipe) |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1838 | { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1839 | display_pipe_crc_irq_handler(dev_priv, pipe, |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1840 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1841 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), |
| 1842 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), |
| 1843 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), |
| 1844 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1845 | } |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1846 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1847 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
| 1848 | enum pipe pipe) |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1849 | { |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1850 | uint32_t res1, res2; |
| 1851 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1852 | if (INTEL_GEN(dev_priv) >= 3) |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1853 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
| 1854 | else |
| 1855 | res1 = 0; |
| 1856 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1857 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1858 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
| 1859 | else |
| 1860 | res2 = 0; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1861 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 1862 | display_pipe_crc_irq_handler(dev_priv, pipe, |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1863 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
| 1864 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), |
| 1865 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), |
| 1866 | res1, res2); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1867 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1868 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1869 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
| 1870 | * IMR bits until the work is done. Other interrupts can be processed without |
| 1871 | * the work queue. */ |
| 1872 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1873 | { |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1874 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
| 1875 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1876 | if (pm_iir & dev_priv->pm_rps_events) { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1877 | spin_lock(&dev_priv->irq_lock); |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 1878 | gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 1879 | if (rps->interrupts_enabled) { |
| 1880 | rps->pm_iir |= pm_iir & dev_priv->pm_rps_events; |
| 1881 | schedule_work(&rps->work); |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 1882 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1883 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1884 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1885 | |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 1886 | if (INTEL_GEN(dev_priv) >= 8) |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 1887 | return; |
| 1888 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1889 | if (HAS_VEBOX(dev_priv)) { |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1890 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 1891 | notify_ring(dev_priv->engine[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1892 | |
Daniel Vetter | aaecdf6 | 2014-11-04 15:52:22 +0100 | [diff] [blame] | 1893 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
| 1894 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1895 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1896 | } |
| 1897 | |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 1898 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) |
| 1899 | { |
Michal Wajdeczko | 93bf809 | 2018-03-08 16:46:55 +0100 | [diff] [blame] | 1900 | if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) |
| 1901 | intel_guc_to_host_event_handler(&dev_priv->guc); |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 1902 | } |
| 1903 | |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 1904 | static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) |
| 1905 | { |
| 1906 | enum pipe pipe; |
| 1907 | |
| 1908 | for_each_pipe(dev_priv, pipe) { |
| 1909 | I915_WRITE(PIPESTAT(pipe), |
| 1910 | PIPESTAT_INT_STATUS_MASK | |
| 1911 | PIPE_FIFO_UNDERRUN_STATUS); |
| 1912 | |
| 1913 | dev_priv->pipestat_irq_mask[pipe] = 0; |
| 1914 | } |
| 1915 | } |
| 1916 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 1917 | static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
| 1918 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1919 | { |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1920 | int pipe; |
| 1921 | |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 1922 | spin_lock(&dev_priv->irq_lock); |
Ville Syrjälä | 1ca993d | 2016-02-18 21:54:26 +0200 | [diff] [blame] | 1923 | |
| 1924 | if (!dev_priv->display_irqs_enabled) { |
| 1925 | spin_unlock(&dev_priv->irq_lock); |
| 1926 | return; |
| 1927 | } |
| 1928 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1929 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1930 | i915_reg_t reg; |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 1931 | u32 status_mask, enable_mask, iir_bit = 0; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1932 | |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1933 | /* |
| 1934 | * PIPESTAT bits get signalled even when the interrupt is |
| 1935 | * disabled with the mask bits, and some of the status bits do |
| 1936 | * not generate interrupts at all (like the underrun bit). Hence |
| 1937 | * we need to be careful that we only handle what we want to |
| 1938 | * handle. |
| 1939 | */ |
Daniel Vetter | 0f239f4 | 2014-09-30 10:56:49 +0200 | [diff] [blame] | 1940 | |
| 1941 | /* fifo underruns are filterered in the underrun handler. */ |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 1942 | status_mask = PIPE_FIFO_UNDERRUN_STATUS; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1943 | |
| 1944 | switch (pipe) { |
| 1945 | case PIPE_A: |
| 1946 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; |
| 1947 | break; |
| 1948 | case PIPE_B: |
| 1949 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
| 1950 | break; |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 1951 | case PIPE_C: |
| 1952 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
| 1953 | break; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1954 | } |
| 1955 | if (iir & iir_bit) |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 1956 | status_mask |= dev_priv->pipestat_irq_mask[pipe]; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1957 | |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 1958 | if (!status_mask) |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1959 | continue; |
| 1960 | |
| 1961 | reg = PIPESTAT(pipe); |
Ville Syrjälä | 6b12ca5 | 2017-09-14 18:17:31 +0300 | [diff] [blame] | 1962 | pipe_stats[pipe] = I915_READ(reg) & status_mask; |
| 1963 | enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1964 | |
| 1965 | /* |
| 1966 | * Clear the PIPE*STAT regs before the IIR |
Ville Syrjälä | 132c27c | 2018-06-11 23:02:55 +0300 | [diff] [blame] | 1967 | * |
| 1968 | * Toggle the enable bits to make sure we get an |
| 1969 | * edge in the ISR pipe event bit if we don't clear |
| 1970 | * all the enabled status bits. Otherwise the edge |
| 1971 | * triggered IIR on i965/g4x wouldn't notice that |
| 1972 | * an interrupt is still pending. |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1973 | */ |
Ville Syrjälä | 132c27c | 2018-06-11 23:02:55 +0300 | [diff] [blame] | 1974 | if (pipe_stats[pipe]) { |
| 1975 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1976 | I915_WRITE(reg, enable_mask); |
| 1977 | } |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1978 | } |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 1979 | spin_unlock(&dev_priv->irq_lock); |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 1980 | } |
| 1981 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 1982 | static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
| 1983 | u16 iir, u32 pipe_stats[I915_MAX_PIPES]) |
| 1984 | { |
| 1985 | enum pipe pipe; |
| 1986 | |
| 1987 | for_each_pipe(dev_priv, pipe) { |
| 1988 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) |
| 1989 | drm_handle_vblank(&dev_priv->drm, pipe); |
| 1990 | |
| 1991 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
| 1992 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
| 1993 | |
| 1994 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1995 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
| 1996 | } |
| 1997 | } |
| 1998 | |
| 1999 | static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
| 2000 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) |
| 2001 | { |
| 2002 | bool blc_event = false; |
| 2003 | enum pipe pipe; |
| 2004 | |
| 2005 | for_each_pipe(dev_priv, pipe) { |
| 2006 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) |
| 2007 | drm_handle_vblank(&dev_priv->drm, pipe); |
| 2008 | |
| 2009 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2010 | blc_event = true; |
| 2011 | |
| 2012 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
| 2013 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
| 2014 | |
| 2015 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2016 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
| 2017 | } |
| 2018 | |
| 2019 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2020 | intel_opregion_asle_intr(dev_priv); |
| 2021 | } |
| 2022 | |
| 2023 | static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
| 2024 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) |
| 2025 | { |
| 2026 | bool blc_event = false; |
| 2027 | enum pipe pipe; |
| 2028 | |
| 2029 | for_each_pipe(dev_priv, pipe) { |
| 2030 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) |
| 2031 | drm_handle_vblank(&dev_priv->drm, pipe); |
| 2032 | |
| 2033 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2034 | blc_event = true; |
| 2035 | |
| 2036 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
| 2037 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
| 2038 | |
| 2039 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2040 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
| 2041 | } |
| 2042 | |
| 2043 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2044 | intel_opregion_asle_intr(dev_priv); |
| 2045 | |
| 2046 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 2047 | gmbus_irq_handler(dev_priv); |
| 2048 | } |
| 2049 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2050 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2051 | u32 pipe_stats[I915_MAX_PIPES]) |
| 2052 | { |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2053 | enum pipe pipe; |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2054 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2055 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 2056 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) |
| 2057 | drm_handle_vblank(&dev_priv->drm, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2058 | |
| 2059 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2060 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2061 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2062 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2063 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2064 | } |
| 2065 | |
| 2066 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2067 | gmbus_irq_handler(dev_priv); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2068 | } |
| 2069 | |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2070 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2071 | { |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2072 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2073 | |
| 2074 | if (hotplug_status) |
| 2075 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 2076 | |
| 2077 | return hotplug_status; |
| 2078 | } |
| 2079 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2080 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2081 | u32 hotplug_status) |
| 2082 | { |
Ville Syrjälä | 42db67d | 2015-08-28 21:26:27 +0300 | [diff] [blame] | 2083 | u32 pin_mask = 0, long_mask = 0; |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2084 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2085 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
| 2086 | IS_CHERRYVIEW(dev_priv)) { |
Jani Nikula | 0d2e429 | 2015-05-27 15:03:39 +0300 | [diff] [blame] | 2087 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2088 | |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2089 | if (hotplug_trigger) { |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2090 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2091 | hotplug_trigger, hotplug_trigger, |
| 2092 | hpd_status_g4x, |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2093 | i9xx_port_hotplug_long_detect); |
| 2094 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2095 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2096 | } |
Jani Nikula | 369712e | 2015-05-27 15:03:40 +0300 | [diff] [blame] | 2097 | |
| 2098 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2099 | dp_aux_irq_handler(dev_priv); |
Jani Nikula | 0d2e429 | 2015-05-27 15:03:39 +0300 | [diff] [blame] | 2100 | } else { |
| 2101 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2102 | |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2103 | if (hotplug_trigger) { |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2104 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2105 | hotplug_trigger, hotplug_trigger, |
| 2106 | hpd_status_i915, |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2107 | i9xx_port_hotplug_long_detect); |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2108 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Ville Syrjälä | 58f2cf2 | 2015-08-28 22:59:08 +0300 | [diff] [blame] | 2109 | } |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2110 | } |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2111 | } |
| 2112 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2113 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2114 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2115 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2116 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2117 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2118 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 2119 | if (!intel_irqs_enabled(dev_priv)) |
| 2120 | return IRQ_NONE; |
| 2121 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2122 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 2123 | disable_rpm_wakeref_asserts(dev_priv); |
| 2124 | |
Ville Syrjälä | 1e1cace | 2016-04-13 21:19:52 +0300 | [diff] [blame] | 2125 | do { |
Ville Syrjälä | 6e81480 | 2016-04-13 21:19:53 +0300 | [diff] [blame] | 2126 | u32 iir, gt_iir, pm_iir; |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2127 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2128 | u32 hotplug_status = 0; |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2129 | u32 ier = 0; |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2130 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2131 | gt_iir = I915_READ(GTIIR); |
| 2132 | pm_iir = I915_READ(GEN6_PMIIR); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2133 | iir = I915_READ(VLV_IIR); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2134 | |
| 2135 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
Ville Syrjälä | 1e1cace | 2016-04-13 21:19:52 +0300 | [diff] [blame] | 2136 | break; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2137 | |
| 2138 | ret = IRQ_HANDLED; |
| 2139 | |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2140 | /* |
| 2141 | * Theory on interrupt generation, based on empirical evidence: |
| 2142 | * |
| 2143 | * x = ((VLV_IIR & VLV_IER) || |
| 2144 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && |
| 2145 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); |
| 2146 | * |
| 2147 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. |
| 2148 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to |
| 2149 | * guarantee the CPU interrupt will be raised again even if we |
| 2150 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR |
| 2151 | * bits this time around. |
| 2152 | */ |
Ville Syrjälä | 4a0a020 | 2016-04-13 21:19:50 +0300 | [diff] [blame] | 2153 | I915_WRITE(VLV_MASTER_IER, 0); |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2154 | ier = I915_READ(VLV_IER); |
| 2155 | I915_WRITE(VLV_IER, 0); |
Ville Syrjälä | 4a0a020 | 2016-04-13 21:19:50 +0300 | [diff] [blame] | 2156 | |
| 2157 | if (gt_iir) |
| 2158 | I915_WRITE(GTIIR, gt_iir); |
| 2159 | if (pm_iir) |
| 2160 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 2161 | |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2162 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2163 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2164 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2165 | /* Call regardless, as some status bits might not be |
| 2166 | * signalled in iir */ |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 2167 | i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2168 | |
Jerome Anand | eef5732 | 2017-01-25 04:27:49 +0530 | [diff] [blame] | 2169 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
| 2170 | I915_LPE_PIPE_B_INTERRUPT)) |
| 2171 | intel_lpe_audio_irq_handler(dev_priv); |
| 2172 | |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2173 | /* |
| 2174 | * VLV_IIR is single buffered, and reflects the level |
| 2175 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. |
| 2176 | */ |
| 2177 | if (iir) |
| 2178 | I915_WRITE(VLV_IIR, iir); |
Ville Syrjälä | 4a0a020 | 2016-04-13 21:19:50 +0300 | [diff] [blame] | 2179 | |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2180 | I915_WRITE(VLV_IER, ier); |
Ville Syrjälä | 4a0a020 | 2016-04-13 21:19:50 +0300 | [diff] [blame] | 2181 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
| 2182 | POSTING_READ(VLV_MASTER_IER); |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2183 | |
Ville Syrjälä | 5289487 | 2016-04-13 21:19:56 +0300 | [diff] [blame] | 2184 | if (gt_iir) |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 2185 | snb_gt_irq_handler(dev_priv, gt_iir); |
Ville Syrjälä | 5289487 | 2016-04-13 21:19:56 +0300 | [diff] [blame] | 2186 | if (pm_iir) |
| 2187 | gen6_rps_irq_handler(dev_priv, pm_iir); |
| 2188 | |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2189 | if (hotplug_status) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2190 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2191 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2192 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
Ville Syrjälä | 1e1cace | 2016-04-13 21:19:52 +0300 | [diff] [blame] | 2193 | } while (0); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2194 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2195 | enable_rpm_wakeref_asserts(dev_priv); |
| 2196 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2197 | return ret; |
| 2198 | } |
| 2199 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2200 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
| 2201 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2202 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2203 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2204 | irqreturn_t ret = IRQ_NONE; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2205 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 2206 | if (!intel_irqs_enabled(dev_priv)) |
| 2207 | return IRQ_NONE; |
| 2208 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2209 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 2210 | disable_rpm_wakeref_asserts(dev_priv); |
| 2211 | |
Chris Wilson | 579de73 | 2016-03-14 09:01:57 +0000 | [diff] [blame] | 2212 | do { |
Ville Syrjälä | 6e81480 | 2016-04-13 21:19:53 +0300 | [diff] [blame] | 2213 | u32 master_ctl, iir; |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2214 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2215 | u32 hotplug_status = 0; |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2216 | u32 gt_iir[4]; |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2217 | u32 ier = 0; |
| 2218 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2219 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
| 2220 | iir = I915_READ(VLV_IIR); |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 2221 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2222 | if (master_ctl == 0 && iir == 0) |
| 2223 | break; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2224 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 2225 | ret = IRQ_HANDLED; |
| 2226 | |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2227 | /* |
| 2228 | * Theory on interrupt generation, based on empirical evidence: |
| 2229 | * |
| 2230 | * x = ((VLV_IIR & VLV_IER) || |
| 2231 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && |
| 2232 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); |
| 2233 | * |
| 2234 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. |
| 2235 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to |
| 2236 | * guarantee the CPU interrupt will be raised again even if we |
| 2237 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL |
| 2238 | * bits this time around. |
| 2239 | */ |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2240 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2241 | ier = I915_READ(VLV_IER); |
| 2242 | I915_WRITE(VLV_IER, 0); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2243 | |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 2244 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2245 | |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2246 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2247 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2248 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 2249 | /* Call regardless, as some status bits might not be |
| 2250 | * signalled in iir */ |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 2251 | i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2252 | |
Jerome Anand | eef5732 | 2017-01-25 04:27:49 +0530 | [diff] [blame] | 2253 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
| 2254 | I915_LPE_PIPE_B_INTERRUPT | |
| 2255 | I915_LPE_PIPE_C_INTERRUPT)) |
| 2256 | intel_lpe_audio_irq_handler(dev_priv); |
| 2257 | |
Ville Syrjälä | 7ce4d1f | 2016-04-13 21:19:49 +0300 | [diff] [blame] | 2258 | /* |
| 2259 | * VLV_IIR is single buffered, and reflects the level |
| 2260 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. |
| 2261 | */ |
| 2262 | if (iir) |
| 2263 | I915_WRITE(VLV_IIR, iir); |
| 2264 | |
Ville Syrjälä | a5e485a | 2016-04-13 21:19:51 +0300 | [diff] [blame] | 2265 | I915_WRITE(VLV_IER, ier); |
Ville Syrjälä | e5328c4 | 2016-04-13 21:19:47 +0300 | [diff] [blame] | 2266 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2267 | POSTING_READ(GEN8_MASTER_IRQ); |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2268 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2269 | gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir); |
Ville Syrjälä | e30e251 | 2016-04-13 21:19:58 +0300 | [diff] [blame] | 2270 | |
Ville Syrjälä | 1ae3c34 | 2016-04-13 21:19:54 +0300 | [diff] [blame] | 2271 | if (hotplug_status) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2272 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
Ville Syrjälä | 2ecb8ca | 2016-04-13 21:19:55 +0300 | [diff] [blame] | 2273 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2274 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
Chris Wilson | 579de73 | 2016-03-14 09:01:57 +0000 | [diff] [blame] | 2275 | } while (0); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2276 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2277 | enable_rpm_wakeref_asserts(dev_priv); |
| 2278 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2279 | return ret; |
| 2280 | } |
| 2281 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2282 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
| 2283 | u32 hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2284 | const u32 hpd[HPD_NUM_PINS]) |
| 2285 | { |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2286 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
| 2287 | |
Jani Nikula | 6a39d7c | 2015-11-25 16:47:22 +0200 | [diff] [blame] | 2288 | /* |
| 2289 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU |
| 2290 | * unless we touch the hotplug register, even if hotplug_trigger is |
| 2291 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" |
| 2292 | * errors. |
| 2293 | */ |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2294 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
Jani Nikula | 6a39d7c | 2015-11-25 16:47:22 +0200 | [diff] [blame] | 2295 | if (!hotplug_trigger) { |
| 2296 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | |
| 2297 | PORTD_HOTPLUG_STATUS_MASK | |
| 2298 | PORTC_HOTPLUG_STATUS_MASK | |
| 2299 | PORTB_HOTPLUG_STATUS_MASK; |
| 2300 | dig_hotplug_reg &= ~mask; |
| 2301 | } |
| 2302 | |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2303 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
Jani Nikula | 6a39d7c | 2015-11-25 16:47:22 +0200 | [diff] [blame] | 2304 | if (!hotplug_trigger) |
| 2305 | return; |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2306 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2307 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2308 | dig_hotplug_reg, hpd, |
| 2309 | pch_port_hotplug_long_detect); |
| 2310 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2311 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2312 | } |
| 2313 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2314 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2315 | { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2316 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2317 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2318 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2319 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2320 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2321 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 2322 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 2323 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2324 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2325 | port_name(port)); |
| 2326 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2327 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 2328 | if (pch_iir & SDE_AUX_MASK) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2329 | dp_aux_irq_handler(dev_priv); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 2330 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2331 | if (pch_iir & SDE_GMBUS) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2332 | gmbus_irq_handler(dev_priv); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2333 | |
| 2334 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 2335 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 2336 | |
| 2337 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 2338 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 2339 | |
| 2340 | if (pch_iir & SDE_POISON) |
| 2341 | DRM_ERROR("PCH poison interrupt\n"); |
| 2342 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2343 | if (pch_iir & SDE_FDI_MASK) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2344 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2345 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 2346 | pipe_name(pipe), |
| 2347 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2348 | |
| 2349 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 2350 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 2351 | |
| 2352 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 2353 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 2354 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2355 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Matthias Kaehlcke | a219603 | 2017-07-17 11:14:03 -0700 | [diff] [blame] | 2356 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2357 | |
| 2358 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
Matthias Kaehlcke | a219603 | 2017-07-17 11:14:03 -0700 | [diff] [blame] | 2359 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2360 | } |
| 2361 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2362 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2363 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2364 | u32 err_int = I915_READ(GEN7_ERR_INT); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2365 | enum pipe pipe; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2366 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2367 | if (err_int & ERR_INT_POISON) |
| 2368 | DRM_ERROR("Poison interrupt\n"); |
| 2369 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2370 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2371 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
| 2372 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2373 | |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2374 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2375 | if (IS_IVYBRIDGE(dev_priv)) |
| 2376 | ivb_pipe_crc_irq_handler(dev_priv, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2377 | else |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2378 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2379 | } |
| 2380 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2381 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2382 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 2383 | } |
| 2384 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2385 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2386 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2387 | u32 serr_int = I915_READ(SERR_INT); |
Mika Kahola | 45c1cd8 | 2017-10-10 13:17:06 +0300 | [diff] [blame] | 2388 | enum pipe pipe; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2389 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2390 | if (serr_int & SERR_INT_POISON) |
| 2391 | DRM_ERROR("PCH poison interrupt\n"); |
| 2392 | |
Mika Kahola | 45c1cd8 | 2017-10-10 13:17:06 +0300 | [diff] [blame] | 2393 | for_each_pipe(dev_priv, pipe) |
| 2394 | if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) |
| 2395 | intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2396 | |
| 2397 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2398 | } |
| 2399 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2400 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2401 | { |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2402 | int pipe; |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2403 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2404 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2405 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2406 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2407 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 2408 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 2409 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 2410 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 2411 | port_name(port)); |
| 2412 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2413 | |
| 2414 | if (pch_iir & SDE_AUX_MASK_CPT) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2415 | dp_aux_irq_handler(dev_priv); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2416 | |
| 2417 | if (pch_iir & SDE_GMBUS_CPT) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2418 | gmbus_irq_handler(dev_priv); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2419 | |
| 2420 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 2421 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 2422 | |
| 2423 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 2424 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 2425 | |
| 2426 | if (pch_iir & SDE_FDI_MASK_CPT) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2427 | for_each_pipe(dev_priv, pipe) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2428 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 2429 | pipe_name(pipe), |
| 2430 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2431 | |
| 2432 | if (pch_iir & SDE_ERROR_CPT) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2433 | cpt_serr_int_handler(dev_priv); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2434 | } |
| 2435 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 2436 | static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
| 2437 | { |
| 2438 | u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; |
| 2439 | u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; |
| 2440 | u32 pin_mask = 0, long_mask = 0; |
| 2441 | |
| 2442 | if (ddi_hotplug_trigger) { |
| 2443 | u32 dig_hotplug_reg; |
| 2444 | |
| 2445 | dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); |
| 2446 | I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg); |
| 2447 | |
| 2448 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2449 | ddi_hotplug_trigger, |
| 2450 | dig_hotplug_reg, hpd_icp, |
| 2451 | icp_ddi_port_hotplug_long_detect); |
| 2452 | } |
| 2453 | |
| 2454 | if (tc_hotplug_trigger) { |
| 2455 | u32 dig_hotplug_reg; |
| 2456 | |
| 2457 | dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); |
| 2458 | I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg); |
| 2459 | |
| 2460 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2461 | tc_hotplug_trigger, |
| 2462 | dig_hotplug_reg, hpd_icp, |
| 2463 | icp_tc_port_hotplug_long_detect); |
| 2464 | } |
| 2465 | |
| 2466 | if (pin_mask) |
| 2467 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
| 2468 | |
| 2469 | if (pch_iir & SDE_GMBUS_ICP) |
| 2470 | gmbus_irq_handler(dev_priv); |
| 2471 | } |
| 2472 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2473 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2474 | { |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2475 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
| 2476 | ~SDE_PORTE_HOTPLUG_SPT; |
| 2477 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; |
| 2478 | u32 pin_mask = 0, long_mask = 0; |
| 2479 | |
| 2480 | if (hotplug_trigger) { |
| 2481 | u32 dig_hotplug_reg; |
| 2482 | |
| 2483 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 2484 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
| 2485 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2486 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2487 | hotplug_trigger, dig_hotplug_reg, hpd_spt, |
Ville Syrjälä | 74c0b39 | 2015-08-27 23:56:07 +0300 | [diff] [blame] | 2488 | spt_port_hotplug_long_detect); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2489 | } |
| 2490 | |
| 2491 | if (hotplug2_trigger) { |
| 2492 | u32 dig_hotplug_reg; |
| 2493 | |
| 2494 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); |
| 2495 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); |
| 2496 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2497 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, |
| 2498 | hotplug2_trigger, dig_hotplug_reg, hpd_spt, |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2499 | spt_port_hotplug2_long_detect); |
| 2500 | } |
| 2501 | |
| 2502 | if (pin_mask) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2503 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2504 | |
| 2505 | if (pch_iir & SDE_GMBUS_CPT) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2506 | gmbus_irq_handler(dev_priv); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2507 | } |
| 2508 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2509 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
| 2510 | u32 hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2511 | const u32 hpd[HPD_NUM_PINS]) |
| 2512 | { |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2513 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
| 2514 | |
| 2515 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); |
| 2516 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); |
| 2517 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2518 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2519 | dig_hotplug_reg, hpd, |
| 2520 | ilk_port_hotplug_long_detect); |
| 2521 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2522 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2523 | } |
| 2524 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2525 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
| 2526 | u32 de_iir) |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2527 | { |
Daniel Vetter | 40da17c2 | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2528 | enum pipe pipe; |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 2529 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
| 2530 | |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2531 | if (hotplug_trigger) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2532 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2533 | |
| 2534 | if (de_iir & DE_AUX_CHANNEL_A) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2535 | dp_aux_irq_handler(dev_priv); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2536 | |
| 2537 | if (de_iir & DE_GSE) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2538 | intel_opregion_asle_intr(dev_priv); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2539 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2540 | if (de_iir & DE_POISON) |
| 2541 | DRM_ERROR("Poison interrupt\n"); |
| 2542 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2543 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 2544 | if (de_iir & DE_PIPE_VBLANK(pipe)) |
| 2545 | drm_handle_vblank(&dev_priv->drm, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2546 | |
Daniel Vetter | 40da17c2 | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2547 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2548 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2549 | |
Daniel Vetter | 40da17c2 | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2550 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2551 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2552 | } |
| 2553 | |
| 2554 | /* check event from PCH */ |
| 2555 | if (de_iir & DE_PCH_EVENT) { |
| 2556 | u32 pch_iir = I915_READ(SDEIIR); |
| 2557 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2558 | if (HAS_PCH_CPT(dev_priv)) |
| 2559 | cpt_irq_handler(dev_priv, pch_iir); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2560 | else |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2561 | ibx_irq_handler(dev_priv, pch_iir); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2562 | |
| 2563 | /* should clear PCH hotplug event before clear CPU irq */ |
| 2564 | I915_WRITE(SDEIIR, pch_iir); |
| 2565 | } |
| 2566 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2567 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
| 2568 | ironlake_rps_change_irq_handler(dev_priv); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2569 | } |
| 2570 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2571 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
| 2572 | u32 de_iir) |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2573 | { |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 2574 | enum pipe pipe; |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 2575 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
| 2576 | |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2577 | if (hotplug_trigger) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2578 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2579 | |
| 2580 | if (de_iir & DE_ERR_INT_IVB) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2581 | ivb_err_int_handler(dev_priv); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2582 | |
Dhinakaran Pandiyan | 54fd314 | 2018-04-04 18:37:17 -0700 | [diff] [blame] | 2583 | if (de_iir & DE_EDP_PSR_INT_HSW) { |
| 2584 | u32 psr_iir = I915_READ(EDP_PSR_IIR); |
| 2585 | |
| 2586 | intel_psr_irq_handler(dev_priv, psr_iir); |
| 2587 | I915_WRITE(EDP_PSR_IIR, psr_iir); |
| 2588 | } |
Daniel Vetter | fc34044 | 2018-04-05 15:00:23 -0700 | [diff] [blame] | 2589 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2590 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2591 | dp_aux_irq_handler(dev_priv); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2592 | |
| 2593 | if (de_iir & DE_GSE_IVB) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2594 | intel_opregion_asle_intr(dev_priv); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2595 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2596 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 2597 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) |
| 2598 | drm_handle_vblank(&dev_priv->drm, pipe); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2599 | } |
| 2600 | |
| 2601 | /* check event from PCH */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2602 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2603 | u32 pch_iir = I915_READ(SDEIIR); |
| 2604 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2605 | cpt_irq_handler(dev_priv, pch_iir); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2606 | |
| 2607 | /* clear PCH hotplug event before clear CPU irq */ |
| 2608 | I915_WRITE(SDEIIR, pch_iir); |
| 2609 | } |
| 2610 | } |
| 2611 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2612 | /* |
| 2613 | * To handle irqs with the minimum potential races with fresh interrupts, we: |
| 2614 | * 1 - Disable Master Interrupt Control. |
| 2615 | * 2 - Find the source(s) of the interrupt. |
| 2616 | * 3 - Clear the Interrupt Identity bits (IIR). |
| 2617 | * 4 - Process the interrupt(s) that had bits set in the IIRs. |
| 2618 | * 5 - Re-enable Master Interrupt Control. |
| 2619 | */ |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2620 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2621 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2622 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2623 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2624 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2625 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2626 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 2627 | if (!intel_irqs_enabled(dev_priv)) |
| 2628 | return IRQ_NONE; |
| 2629 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2630 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 2631 | disable_rpm_wakeref_asserts(dev_priv); |
| 2632 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2633 | /* disable master interrupt before clearing iir */ |
| 2634 | de_ier = I915_READ(DEIER); |
| 2635 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 2636 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2637 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2638 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 2639 | * interrupts will will be stored on its back queue, and then we'll be |
| 2640 | * able to process them after we restore SDEIER (as soon as we restore |
| 2641 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 2642 | * due to its back queue). */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2643 | if (!HAS_PCH_NOP(dev_priv)) { |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2644 | sde_ier = I915_READ(SDEIER); |
| 2645 | I915_WRITE(SDEIER, 0); |
| 2646 | POSTING_READ(SDEIER); |
| 2647 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2648 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2649 | /* Find, clear, then process each source of interrupt */ |
| 2650 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2651 | gt_iir = I915_READ(GTIIR); |
| 2652 | if (gt_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2653 | I915_WRITE(GTIIR, gt_iir); |
| 2654 | ret = IRQ_HANDLED; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2655 | if (INTEL_GEN(dev_priv) >= 6) |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 2656 | snb_gt_irq_handler(dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 2657 | else |
Ville Syrjälä | 261e40b | 2016-04-13 21:19:57 +0300 | [diff] [blame] | 2658 | ilk_gt_irq_handler(dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2659 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2660 | |
| 2661 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2662 | if (de_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2663 | I915_WRITE(DEIIR, de_iir); |
| 2664 | ret = IRQ_HANDLED; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2665 | if (INTEL_GEN(dev_priv) >= 7) |
| 2666 | ivb_display_irq_handler(dev_priv, de_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2667 | else |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2668 | ilk_display_irq_handler(dev_priv, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2669 | } |
| 2670 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2671 | if (INTEL_GEN(dev_priv) >= 6) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2672 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 2673 | if (pm_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2674 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 2675 | ret = IRQ_HANDLED; |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2676 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2677 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2678 | } |
| 2679 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2680 | I915_WRITE(DEIER, de_ier); |
| 2681 | POSTING_READ(DEIER); |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2682 | if (!HAS_PCH_NOP(dev_priv)) { |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2683 | I915_WRITE(SDEIER, sde_ier); |
| 2684 | POSTING_READ(SDEIER); |
| 2685 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2686 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2687 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 2688 | enable_rpm_wakeref_asserts(dev_priv); |
| 2689 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2690 | return ret; |
| 2691 | } |
| 2692 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2693 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
| 2694 | u32 hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2695 | const u32 hpd[HPD_NUM_PINS]) |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2696 | { |
Ville Syrjälä | cebd87a | 2015-08-27 23:56:09 +0300 | [diff] [blame] | 2697 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2698 | |
Ville Syrjälä | a52bb15 | 2015-08-27 23:56:11 +0300 | [diff] [blame] | 2699 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 2700 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2701 | |
Rodrigo Vivi | cf53902 | 2018-01-29 15:22:21 -0800 | [diff] [blame] | 2702 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2703 | dig_hotplug_reg, hpd, |
Ville Syrjälä | cebd87a | 2015-08-27 23:56:09 +0300 | [diff] [blame] | 2704 | bxt_port_hotplug_long_detect); |
Ville Syrjälä | 40e5641 | 2015-08-27 23:56:10 +0300 | [diff] [blame] | 2705 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2706 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2707 | } |
| 2708 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2709 | static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) |
| 2710 | { |
| 2711 | u32 pin_mask = 0, long_mask = 0; |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 2712 | u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; |
| 2713 | u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2714 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2715 | if (trigger_tc) { |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 2716 | u32 dig_hotplug_reg; |
| 2717 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2718 | dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL); |
| 2719 | I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); |
| 2720 | |
| 2721 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 2722 | dig_hotplug_reg, hpd_gen11, |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2723 | gen11_port_hotplug_long_detect); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2724 | } |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 2725 | |
| 2726 | if (trigger_tbt) { |
| 2727 | u32 dig_hotplug_reg; |
| 2728 | |
| 2729 | dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL); |
| 2730 | I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); |
| 2731 | |
| 2732 | intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, |
| 2733 | dig_hotplug_reg, hpd_gen11, |
| 2734 | gen11_port_hotplug_long_detect); |
| 2735 | } |
| 2736 | |
| 2737 | if (pin_mask) |
| 2738 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
| 2739 | else |
| 2740 | DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2741 | } |
| 2742 | |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2743 | static irqreturn_t |
| 2744 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2745 | { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2746 | irqreturn_t ret = IRQ_NONE; |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2747 | u32 iir; |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2748 | enum pipe pipe; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 2749 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2750 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2751 | iir = I915_READ(GEN8_DE_MISC_IIR); |
| 2752 | if (iir) { |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 2753 | bool found = false; |
| 2754 | |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2755 | I915_WRITE(GEN8_DE_MISC_IIR, iir); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2756 | ret = IRQ_HANDLED; |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 2757 | |
| 2758 | if (iir & GEN8_DE_MISC_GSE) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2759 | intel_opregion_asle_intr(dev_priv); |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 2760 | found = true; |
| 2761 | } |
| 2762 | |
| 2763 | if (iir & GEN8_DE_EDP_PSR) { |
Dhinakaran Pandiyan | 54fd314 | 2018-04-04 18:37:17 -0700 | [diff] [blame] | 2764 | u32 psr_iir = I915_READ(EDP_PSR_IIR); |
| 2765 | |
| 2766 | intel_psr_irq_handler(dev_priv, psr_iir); |
| 2767 | I915_WRITE(EDP_PSR_IIR, psr_iir); |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 2768 | found = true; |
| 2769 | } |
| 2770 | |
| 2771 | if (!found) |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2772 | DRM_ERROR("Unexpected DE Misc interrupt\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2773 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2774 | else |
| 2775 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2776 | } |
| 2777 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 2778 | if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { |
| 2779 | iir = I915_READ(GEN11_DE_HPD_IIR); |
| 2780 | if (iir) { |
| 2781 | I915_WRITE(GEN11_DE_HPD_IIR, iir); |
| 2782 | ret = IRQ_HANDLED; |
| 2783 | gen11_hpd_irq_handler(dev_priv, iir); |
| 2784 | } else { |
| 2785 | DRM_ERROR("The master control interrupt lied, (DE HPD)!\n"); |
| 2786 | } |
| 2787 | } |
| 2788 | |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2789 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2790 | iir = I915_READ(GEN8_DE_PORT_IIR); |
| 2791 | if (iir) { |
| 2792 | u32 tmp_mask; |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2793 | bool found = false; |
Ville Syrjälä | cebd87a | 2015-08-27 23:56:09 +0300 | [diff] [blame] | 2794 | |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2795 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2796 | ret = IRQ_HANDLED; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 2797 | |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2798 | tmp_mask = GEN8_AUX_CHANNEL_A; |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 2799 | if (INTEL_GEN(dev_priv) >= 9) |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2800 | tmp_mask |= GEN9_AUX_CHANNEL_B | |
| 2801 | GEN9_AUX_CHANNEL_C | |
| 2802 | GEN9_AUX_CHANNEL_D; |
| 2803 | |
James Ausmus | bb187e9 | 2018-06-11 17:25:12 -0700 | [diff] [blame] | 2804 | if (INTEL_GEN(dev_priv) >= 11) |
| 2805 | tmp_mask |= ICL_AUX_CHANNEL_E; |
| 2806 | |
Dhinakaran Pandiyan | 9bb635d | 2018-05-21 17:25:35 -0700 | [diff] [blame] | 2807 | if (IS_CNL_WITH_PORT_F(dev_priv) || |
| 2808 | INTEL_GEN(dev_priv) >= 11) |
Rodrigo Vivi | a324fca | 2018-01-29 15:22:15 -0800 | [diff] [blame] | 2809 | tmp_mask |= CNL_AUX_CHANNEL_F; |
| 2810 | |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2811 | if (iir & tmp_mask) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2812 | dp_aux_irq_handler(dev_priv); |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2813 | found = true; |
| 2814 | } |
| 2815 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2816 | if (IS_GEN9_LP(dev_priv)) { |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2817 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; |
| 2818 | if (tmp_mask) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2819 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
| 2820 | hpd_bxt); |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2821 | found = true; |
| 2822 | } |
| 2823 | } else if (IS_BROADWELL(dev_priv)) { |
| 2824 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; |
| 2825 | if (tmp_mask) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2826 | ilk_hpd_irq_handler(dev_priv, |
| 2827 | tmp_mask, hpd_bdw); |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2828 | found = true; |
| 2829 | } |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2830 | } |
| 2831 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2832 | if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2833 | gmbus_irq_handler(dev_priv); |
Shashank Sharma | 9e63743 | 2014-08-22 17:40:43 +0530 | [diff] [blame] | 2834 | found = true; |
| 2835 | } |
| 2836 | |
Shashank Sharma | d04a492 | 2014-08-22 17:40:41 +0530 | [diff] [blame] | 2837 | if (!found) |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2838 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2839 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2840 | else |
| 2841 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2842 | } |
| 2843 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2844 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 2845 | u32 fault_errors; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2846 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2847 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
| 2848 | continue; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2849 | |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2850 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
| 2851 | if (!iir) { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2852 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2853 | continue; |
| 2854 | } |
| 2855 | |
| 2856 | ret = IRQ_HANDLED; |
| 2857 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); |
| 2858 | |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 2859 | if (iir & GEN8_PIPE_VBLANK) |
| 2860 | drm_handle_vblank(&dev_priv->drm, pipe); |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2861 | |
| 2862 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2863 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2864 | |
| 2865 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
| 2866 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
| 2867 | |
| 2868 | fault_errors = iir; |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 2869 | if (INTEL_GEN(dev_priv) >= 9) |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2870 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
| 2871 | else |
| 2872 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
| 2873 | |
| 2874 | if (fault_errors) |
Tvrtko Ursulin | 1353ec3 | 2016-10-27 13:48:32 +0100 | [diff] [blame] | 2875 | DRM_ERROR("Fault errors on pipe %c: 0x%08x\n", |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2876 | pipe_name(pipe), |
| 2877 | fault_errors); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2878 | } |
| 2879 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2880 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
Shashank Sharma | 266ea3d | 2014-08-22 17:40:42 +0530 | [diff] [blame] | 2881 | master_ctl & GEN8_DE_PCH_IRQ) { |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2882 | /* |
| 2883 | * FIXME(BDW): Assume for now that the new interrupt handling |
| 2884 | * scheme also closed the SDE interrupt handling race we've seen |
| 2885 | * on older pch-split platforms. But this needs testing. |
| 2886 | */ |
Tvrtko Ursulin | e32192e | 2016-01-12 16:04:06 +0000 | [diff] [blame] | 2887 | iir = I915_READ(SDEIIR); |
| 2888 | if (iir) { |
| 2889 | I915_WRITE(SDEIIR, iir); |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2890 | ret = IRQ_HANDLED; |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2891 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 2892 | if (HAS_PCH_ICP(dev_priv)) |
| 2893 | icp_irq_handler(dev_priv, iir); |
| 2894 | else if (HAS_PCH_SPT(dev_priv) || |
| 2895 | HAS_PCH_KBP(dev_priv) || |
| 2896 | HAS_PCH_CNP(dev_priv)) |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2897 | spt_irq_handler(dev_priv, iir); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 2898 | else |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 2899 | cpt_irq_handler(dev_priv, iir); |
Jani Nikula | 2dfb0b8 | 2016-01-07 10:29:10 +0200 | [diff] [blame] | 2900 | } else { |
| 2901 | /* |
| 2902 | * Like on previous PCH there seems to be something |
| 2903 | * fishy going on with forwarding PCH interrupts. |
| 2904 | */ |
| 2905 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); |
| 2906 | } |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2907 | } |
| 2908 | |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2909 | return ret; |
| 2910 | } |
| 2911 | |
| 2912 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
| 2913 | { |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2914 | struct drm_i915_private *dev_priv = to_i915(arg); |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2915 | u32 master_ctl; |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2916 | u32 gt_iir[4]; |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2917 | |
| 2918 | if (!intel_irqs_enabled(dev_priv)) |
| 2919 | return IRQ_NONE; |
| 2920 | |
| 2921 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
| 2922 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
| 2923 | if (!master_ctl) |
| 2924 | return IRQ_NONE; |
| 2925 | |
| 2926 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
| 2927 | |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2928 | /* Find, clear, then process each source of interrupt */ |
Chris Wilson | 55ef72f | 2018-02-02 15:34:48 +0000 | [diff] [blame] | 2929 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2930 | |
| 2931 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 2932 | if (master_ctl & ~GEN8_GT_IRQS) { |
| 2933 | disable_rpm_wakeref_asserts(dev_priv); |
| 2934 | gen8_de_irq_handler(dev_priv, master_ctl); |
| 2935 | enable_rpm_wakeref_asserts(dev_priv); |
| 2936 | } |
Tvrtko Ursulin | f11a0f4 | 2016-01-12 16:04:07 +0000 | [diff] [blame] | 2937 | |
Chris Wilson | cb0d205 | 2015-04-07 16:21:04 +0100 | [diff] [blame] | 2938 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2939 | |
Chris Wilson | f0fd96f | 2018-02-15 07:37:12 +0000 | [diff] [blame] | 2940 | gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir); |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2941 | |
Chris Wilson | 55ef72f | 2018-02-02 15:34:48 +0000 | [diff] [blame] | 2942 | return IRQ_HANDLED; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2943 | } |
| 2944 | |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 2945 | struct wedge_me { |
| 2946 | struct delayed_work work; |
| 2947 | struct drm_i915_private *i915; |
| 2948 | const char *name; |
| 2949 | }; |
| 2950 | |
| 2951 | static void wedge_me(struct work_struct *work) |
| 2952 | { |
| 2953 | struct wedge_me *w = container_of(work, typeof(*w), work.work); |
| 2954 | |
| 2955 | dev_err(w->i915->drm.dev, |
| 2956 | "%s timed out, cancelling all in-flight rendering.\n", |
| 2957 | w->name); |
| 2958 | i915_gem_set_wedged(w->i915); |
| 2959 | } |
| 2960 | |
| 2961 | static void __init_wedge(struct wedge_me *w, |
| 2962 | struct drm_i915_private *i915, |
| 2963 | long timeout, |
| 2964 | const char *name) |
| 2965 | { |
| 2966 | w->i915 = i915; |
| 2967 | w->name = name; |
| 2968 | |
| 2969 | INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me); |
| 2970 | schedule_delayed_work(&w->work, timeout); |
| 2971 | } |
| 2972 | |
| 2973 | static void __fini_wedge(struct wedge_me *w) |
| 2974 | { |
| 2975 | cancel_delayed_work_sync(&w->work); |
| 2976 | destroy_delayed_work_on_stack(&w->work); |
| 2977 | w->i915 = NULL; |
| 2978 | } |
| 2979 | |
| 2980 | #define i915_wedge_on_timeout(W, DEV, TIMEOUT) \ |
| 2981 | for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \ |
| 2982 | (W)->i915; \ |
| 2983 | __fini_wedge((W))) |
| 2984 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 2985 | static u32 |
Mika Kuoppala | f744dbc | 2018-04-06 12:31:45 +0300 | [diff] [blame] | 2986 | gen11_gt_engine_identity(struct drm_i915_private * const i915, |
| 2987 | const unsigned int bank, const unsigned int bit) |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 2988 | { |
| 2989 | void __iomem * const regs = i915->regs; |
| 2990 | u32 timeout_ts; |
| 2991 | u32 ident; |
| 2992 | |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 2993 | lockdep_assert_held(&i915->irq_lock); |
| 2994 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 2995 | raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); |
| 2996 | |
| 2997 | /* |
| 2998 | * NB: Specs do not specify how long to spin wait, |
| 2999 | * so we do ~100us as an educated guess. |
| 3000 | */ |
| 3001 | timeout_ts = (local_clock() >> 10) + 100; |
| 3002 | do { |
| 3003 | ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); |
| 3004 | } while (!(ident & GEN11_INTR_DATA_VALID) && |
| 3005 | !time_after32(local_clock() >> 10, timeout_ts)); |
| 3006 | |
| 3007 | if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { |
| 3008 | DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", |
| 3009 | bank, bit, ident); |
| 3010 | return 0; |
| 3011 | } |
| 3012 | |
| 3013 | raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), |
| 3014 | GEN11_INTR_DATA_VALID); |
| 3015 | |
Mika Kuoppala | f744dbc | 2018-04-06 12:31:45 +0300 | [diff] [blame] | 3016 | return ident; |
| 3017 | } |
| 3018 | |
| 3019 | static void |
| 3020 | gen11_other_irq_handler(struct drm_i915_private * const i915, |
| 3021 | const u8 instance, const u16 iir) |
| 3022 | { |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 3023 | if (instance == OTHER_GTPM_INSTANCE) |
| 3024 | return gen6_rps_irq_handler(i915, iir); |
| 3025 | |
Mika Kuoppala | f744dbc | 2018-04-06 12:31:45 +0300 | [diff] [blame] | 3026 | WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", |
| 3027 | instance, iir); |
| 3028 | } |
| 3029 | |
| 3030 | static void |
| 3031 | gen11_engine_irq_handler(struct drm_i915_private * const i915, |
| 3032 | const u8 class, const u8 instance, const u16 iir) |
| 3033 | { |
| 3034 | struct intel_engine_cs *engine; |
| 3035 | |
| 3036 | if (instance <= MAX_ENGINE_INSTANCE) |
| 3037 | engine = i915->engine_class[class][instance]; |
| 3038 | else |
| 3039 | engine = NULL; |
| 3040 | |
| 3041 | if (likely(engine)) |
| 3042 | return gen8_cs_irq_handler(engine, iir); |
| 3043 | |
| 3044 | WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n", |
| 3045 | class, instance); |
| 3046 | } |
| 3047 | |
| 3048 | static void |
| 3049 | gen11_gt_identity_handler(struct drm_i915_private * const i915, |
| 3050 | const u32 identity) |
| 3051 | { |
| 3052 | const u8 class = GEN11_INTR_ENGINE_CLASS(identity); |
| 3053 | const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); |
| 3054 | const u16 intr = GEN11_INTR_ENGINE_INTR(identity); |
| 3055 | |
| 3056 | if (unlikely(!intr)) |
| 3057 | return; |
| 3058 | |
| 3059 | if (class <= COPY_ENGINE_CLASS) |
| 3060 | return gen11_engine_irq_handler(i915, class, instance, intr); |
| 3061 | |
| 3062 | if (class == OTHER_CLASS) |
| 3063 | return gen11_other_irq_handler(i915, instance, intr); |
| 3064 | |
| 3065 | WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", |
| 3066 | class, instance, intr); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3067 | } |
| 3068 | |
| 3069 | static void |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 3070 | gen11_gt_bank_handler(struct drm_i915_private * const i915, |
| 3071 | const unsigned int bank) |
| 3072 | { |
| 3073 | void __iomem * const regs = i915->regs; |
| 3074 | unsigned long intr_dw; |
| 3075 | unsigned int bit; |
| 3076 | |
| 3077 | lockdep_assert_held(&i915->irq_lock); |
| 3078 | |
| 3079 | intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); |
| 3080 | |
| 3081 | if (unlikely(!intr_dw)) { |
| 3082 | DRM_ERROR("GT_INTR_DW%u blank!\n", bank); |
| 3083 | return; |
| 3084 | } |
| 3085 | |
| 3086 | for_each_set_bit(bit, &intr_dw, 32) { |
| 3087 | const u32 ident = gen11_gt_engine_identity(i915, |
| 3088 | bank, bit); |
| 3089 | |
| 3090 | gen11_gt_identity_handler(i915, ident); |
| 3091 | } |
| 3092 | |
| 3093 | /* Clear must be after shared has been served for engine */ |
| 3094 | raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); |
| 3095 | } |
| 3096 | |
| 3097 | static void |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3098 | gen11_gt_irq_handler(struct drm_i915_private * const i915, |
| 3099 | const u32 master_ctl) |
| 3100 | { |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3101 | unsigned int bank; |
| 3102 | |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 3103 | spin_lock(&i915->irq_lock); |
| 3104 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3105 | for (bank = 0; bank < 2; bank++) { |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 3106 | if (master_ctl & GEN11_GT_DW_IRQ(bank)) |
| 3107 | gen11_gt_bank_handler(i915, bank); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3108 | } |
Oscar Mateo | 96606f3 | 2018-04-06 12:32:37 +0300 | [diff] [blame] | 3109 | |
| 3110 | spin_unlock(&i915->irq_lock); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3111 | } |
| 3112 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3113 | static void |
| 3114 | gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl, |
| 3115 | u32 *iir) |
| 3116 | { |
| 3117 | void __iomem * const regs = dev_priv->regs; |
| 3118 | |
| 3119 | if (!(master_ctl & GEN11_GU_MISC_IRQ)) |
| 3120 | return; |
| 3121 | |
| 3122 | *iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); |
| 3123 | if (likely(*iir)) |
| 3124 | raw_reg_write(regs, GEN11_GU_MISC_IIR, *iir); |
| 3125 | } |
| 3126 | |
| 3127 | static void |
| 3128 | gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, |
| 3129 | const u32 master_ctl, const u32 iir) |
| 3130 | { |
| 3131 | if (!(master_ctl & GEN11_GU_MISC_IRQ)) |
| 3132 | return; |
| 3133 | |
| 3134 | if (unlikely(!iir)) { |
| 3135 | DRM_ERROR("GU_MISC iir blank!\n"); |
| 3136 | return; |
| 3137 | } |
| 3138 | |
| 3139 | if (iir & GEN11_GU_MISC_GSE) |
| 3140 | intel_opregion_asle_intr(dev_priv); |
| 3141 | else |
| 3142 | DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n", iir); |
| 3143 | } |
| 3144 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3145 | static irqreturn_t gen11_irq_handler(int irq, void *arg) |
| 3146 | { |
| 3147 | struct drm_i915_private * const i915 = to_i915(arg); |
| 3148 | void __iomem * const regs = i915->regs; |
| 3149 | u32 master_ctl; |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3150 | u32 gu_misc_iir; |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3151 | |
| 3152 | if (!intel_irqs_enabled(i915)) |
| 3153 | return IRQ_NONE; |
| 3154 | |
| 3155 | master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); |
| 3156 | master_ctl &= ~GEN11_MASTER_IRQ; |
| 3157 | if (!master_ctl) |
| 3158 | return IRQ_NONE; |
| 3159 | |
| 3160 | /* Disable interrupts. */ |
| 3161 | raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); |
| 3162 | |
| 3163 | /* Find, clear, then process each source of interrupt. */ |
| 3164 | gen11_gt_irq_handler(i915, master_ctl); |
| 3165 | |
| 3166 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 3167 | if (master_ctl & GEN11_DISPLAY_IRQ) { |
| 3168 | const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); |
| 3169 | |
| 3170 | disable_rpm_wakeref_asserts(i915); |
| 3171 | /* |
| 3172 | * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ |
| 3173 | * for the display related bits. |
| 3174 | */ |
| 3175 | gen8_de_irq_handler(i915, disp_ctl); |
| 3176 | enable_rpm_wakeref_asserts(i915); |
| 3177 | } |
| 3178 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3179 | gen11_gu_misc_irq_ack(i915, master_ctl, &gu_misc_iir); |
| 3180 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3181 | /* Acknowledge and enable interrupts. */ |
| 3182 | raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl); |
| 3183 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3184 | gen11_gu_misc_irq_handler(i915, master_ctl, gu_misc_iir); |
| 3185 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3186 | return IRQ_HANDLED; |
| 3187 | } |
| 3188 | |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3189 | static void i915_reset_device(struct drm_i915_private *dev_priv, |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3190 | u32 engine_mask, |
| 3191 | const char *reason) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3192 | { |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3193 | struct i915_gpu_error *error = &dev_priv->gpu_error; |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3194 | struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 3195 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 3196 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 3197 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3198 | struct wedge_me w; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3199 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3200 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3201 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 3202 | DRM_DEBUG_DRIVER("resetting chip\n"); |
| 3203 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); |
| 3204 | |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3205 | /* Use a watchdog to ensure that our reset completes */ |
| 3206 | i915_wedge_on_timeout(&w, dev_priv, 5*HZ) { |
| 3207 | intel_prepare_reset(dev_priv); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3208 | |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3209 | error->reason = reason; |
| 3210 | error->stalled_mask = engine_mask; |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3211 | |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3212 | /* Signal that locked waiters should reset the GPU */ |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3213 | smp_mb__before_atomic(); |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3214 | set_bit(I915_RESET_HANDOFF, &error->flags); |
| 3215 | wake_up_all(&error->wait_queue); |
Chris Wilson | 8c185ec | 2017-03-16 17:13:02 +0000 | [diff] [blame] | 3216 | |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3217 | /* Wait for anyone holding the lock to wakeup, without |
| 3218 | * blocking indefinitely on struct_mutex. |
Chris Wilson | 780f262 | 2016-09-09 14:11:52 +0100 | [diff] [blame] | 3219 | */ |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3220 | do { |
| 3221 | if (mutex_trylock(&dev_priv->drm.struct_mutex)) { |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3222 | i915_reset(dev_priv, engine_mask, reason); |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3223 | mutex_unlock(&dev_priv->drm.struct_mutex); |
| 3224 | } |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3225 | } while (wait_on_bit_timeout(&error->flags, |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3226 | I915_RESET_HANDOFF, |
| 3227 | TASK_UNINTERRUPTIBLE, |
| 3228 | 1)); |
Chris Wilson | 780f262 | 2016-09-09 14:11:52 +0100 | [diff] [blame] | 3229 | |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3230 | error->stalled_mask = 0; |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3231 | error->reason = NULL; |
| 3232 | |
Chris Wilson | 36703e7 | 2017-06-22 11:56:25 +0100 | [diff] [blame] | 3233 | intel_finish_reset(dev_priv); |
| 3234 | } |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 3235 | |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3236 | if (!test_bit(I915_WEDGED, &error->flags)) |
| 3237 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3238 | } |
| 3239 | |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3240 | static void i915_clear_error_registers(struct drm_i915_private *dev_priv) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3241 | { |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3242 | u32 eir; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3243 | |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3244 | if (!IS_GEN2(dev_priv)) |
| 3245 | I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3246 | |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3247 | if (INTEL_GEN(dev_priv) < 4) |
| 3248 | I915_WRITE(IPEIR, I915_READ(IPEIR)); |
| 3249 | else |
| 3250 | I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3251 | |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3252 | I915_WRITE(EIR, I915_READ(EIR)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3253 | eir = I915_READ(EIR); |
| 3254 | if (eir) { |
| 3255 | /* |
| 3256 | * some errors might have become stuck, |
| 3257 | * mask them. |
| 3258 | */ |
Chris Wilson | eaa14c2 | 2016-10-19 13:52:03 +0100 | [diff] [blame] | 3259 | DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3260 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 3261 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3262 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 3263 | } |
| 3264 | |
| 3265 | /** |
Mika Kuoppala | b8d24a0 | 2015-01-28 17:03:14 +0200 | [diff] [blame] | 3266 | * i915_handle_error - handle a gpu error |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3267 | * @dev_priv: i915 device private |
arun.siluvery@linux.intel.com | 14b730f | 2016-03-18 20:07:55 +0000 | [diff] [blame] | 3268 | * @engine_mask: mask representing engines that are hung |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3269 | * @flags: control flags |
Michel Thierry | 87c390b | 2017-01-11 20:18:08 -0800 | [diff] [blame] | 3270 | * @fmt: Error message format string |
| 3271 | * |
Javier Martinez Canillas | aafd858 | 2015-10-08 09:57:49 +0200 | [diff] [blame] | 3272 | * Do some basic checking of register state at error time and |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 3273 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 3274 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 3275 | * so userspace knows something bad happened (should trigger collection |
| 3276 | * of a ring dump etc.). |
| 3277 | */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3278 | void i915_handle_error(struct drm_i915_private *dev_priv, |
| 3279 | u32 engine_mask, |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3280 | unsigned long flags, |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3281 | const char *fmt, ...) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 3282 | { |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3283 | struct intel_engine_cs *engine; |
| 3284 | unsigned int tmp; |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3285 | char error_msg[80]; |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3286 | char *msg = NULL; |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 3287 | |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3288 | if (fmt) { |
| 3289 | va_list args; |
| 3290 | |
| 3291 | va_start(args, fmt); |
| 3292 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); |
| 3293 | va_end(args); |
| 3294 | |
| 3295 | msg = error_msg; |
| 3296 | } |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3297 | |
Chris Wilson | 1604a86 | 2017-03-14 17:18:40 +0000 | [diff] [blame] | 3298 | /* |
| 3299 | * In most cases it's guaranteed that we get here with an RPM |
| 3300 | * reference held, for example because there is a pending GPU |
| 3301 | * request that won't finish until the reset is done. This |
| 3302 | * isn't the case at least when we get here by doing a |
| 3303 | * simulated reset via debugfs, so get an RPM reference. |
| 3304 | */ |
| 3305 | intel_runtime_pm_get(dev_priv); |
| 3306 | |
Chris Wilson | 873d66f | 2018-03-16 21:49:59 +0000 | [diff] [blame] | 3307 | engine_mask &= INTEL_INFO(dev_priv)->ring_mask; |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3308 | |
| 3309 | if (flags & I915_ERROR_CAPTURE) { |
| 3310 | i915_capture_error_state(dev_priv, engine_mask, msg); |
| 3311 | i915_clear_error_registers(dev_priv); |
| 3312 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3313 | |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3314 | /* |
| 3315 | * Try engine reset when available. We fall back to full reset if |
| 3316 | * single reset fails. |
| 3317 | */ |
| 3318 | if (intel_has_reset_engine(dev_priv)) { |
| 3319 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { |
Daniel Vetter | 9db529a | 2017-08-08 10:08:28 +0200 | [diff] [blame] | 3320 | BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3321 | if (test_and_set_bit(I915_RESET_ENGINE + engine->id, |
| 3322 | &dev_priv->gpu_error.flags)) |
| 3323 | continue; |
| 3324 | |
Chris Wilson | ce80075 | 2018-03-20 10:04:49 +0000 | [diff] [blame] | 3325 | if (i915_reset_engine(engine, msg) == 0) |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3326 | engine_mask &= ~intel_engine_flag(engine); |
| 3327 | |
| 3328 | clear_bit(I915_RESET_ENGINE + engine->id, |
| 3329 | &dev_priv->gpu_error.flags); |
| 3330 | wake_up_bit(&dev_priv->gpu_error.flags, |
| 3331 | I915_RESET_ENGINE + engine->id); |
| 3332 | } |
| 3333 | } |
| 3334 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 3335 | if (!engine_mask) |
Chris Wilson | 1604a86 | 2017-03-14 17:18:40 +0000 | [diff] [blame] | 3336 | goto out; |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3337 | |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3338 | /* Full reset needs the mutex, stop any other user trying to do so. */ |
Chris Wilson | d536730 | 2017-06-20 10:57:43 +0100 | [diff] [blame] | 3339 | if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) { |
| 3340 | wait_event(dev_priv->gpu_error.reset_queue, |
| 3341 | !test_bit(I915_RESET_BACKOFF, |
| 3342 | &dev_priv->gpu_error.flags)); |
Chris Wilson | 1604a86 | 2017-03-14 17:18:40 +0000 | [diff] [blame] | 3343 | goto out; |
Chris Wilson | d536730 | 2017-06-20 10:57:43 +0100 | [diff] [blame] | 3344 | } |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 3345 | |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3346 | /* Prevent any other reset-engine attempt. */ |
| 3347 | for_each_engine(engine, dev_priv, tmp) { |
| 3348 | while (test_and_set_bit(I915_RESET_ENGINE + engine->id, |
| 3349 | &dev_priv->gpu_error.flags)) |
| 3350 | wait_on_bit(&dev_priv->gpu_error.flags, |
| 3351 | I915_RESET_ENGINE + engine->id, |
| 3352 | TASK_UNINTERRUPTIBLE); |
| 3353 | } |
| 3354 | |
Chris Wilson | d0667e9 | 2018-04-06 23:03:54 +0100 | [diff] [blame] | 3355 | i915_reset_device(dev_priv, engine_mask, msg); |
Chris Wilson | d536730 | 2017-06-20 10:57:43 +0100 | [diff] [blame] | 3356 | |
Michel Thierry | 142bc7d | 2017-06-20 10:57:46 +0100 | [diff] [blame] | 3357 | for_each_engine(engine, dev_priv, tmp) { |
| 3358 | clear_bit(I915_RESET_ENGINE + engine->id, |
| 3359 | &dev_priv->gpu_error.flags); |
| 3360 | } |
| 3361 | |
Chris Wilson | d536730 | 2017-06-20 10:57:43 +0100 | [diff] [blame] | 3362 | clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags); |
| 3363 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 1604a86 | 2017-03-14 17:18:40 +0000 | [diff] [blame] | 3364 | |
| 3365 | out: |
| 3366 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 3367 | } |
| 3368 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 3369 | /* Called from drm generic code, passed 'crtc' which |
| 3370 | * we use as a pipe index |
| 3371 | */ |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 3372 | static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 3373 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3374 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 3375 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 3376 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3377 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 3378 | i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
| 3379 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3380 | |
| 3381 | return 0; |
| 3382 | } |
| 3383 | |
| 3384 | static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe) |
| 3385 | { |
| 3386 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3387 | unsigned long irqflags; |
| 3388 | |
| 3389 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3390 | i915_enable_pipestat(dev_priv, pipe, |
| 3391 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3392 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 3393 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 3394 | return 0; |
| 3395 | } |
| 3396 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 3397 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3398 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3399 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3400 | unsigned long irqflags; |
Tvrtko Ursulin | 55b8f2a | 2016-10-14 09:17:22 +0100 | [diff] [blame] | 3401 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 3402 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3403 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3404 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | fbdedaea | 2015-11-23 18:06:16 +0200 | [diff] [blame] | 3405 | ilk_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 3406 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3407 | |
Dhinakaran Pandiyan | 2e8bf22 | 2018-02-02 21:13:02 -0800 | [diff] [blame] | 3408 | /* Even though there is no DMC, frame counter can get stuck when |
| 3409 | * PSR is active as no frames are generated. |
| 3410 | */ |
| 3411 | if (HAS_PSR(dev_priv)) |
| 3412 | drm_vblank_restore(dev, pipe); |
| 3413 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 3414 | return 0; |
| 3415 | } |
| 3416 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 3417 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3418 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3419 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3420 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3421 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3422 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | 013d375 | 2015-11-23 18:06:17 +0200 | [diff] [blame] | 3423 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3424 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | 013d375 | 2015-11-23 18:06:17 +0200 | [diff] [blame] | 3425 | |
Dhinakaran Pandiyan | 2e8bf22 | 2018-02-02 21:13:02 -0800 | [diff] [blame] | 3426 | /* Even if there is no DMC, frame counter can get stuck when |
| 3427 | * PSR is active as no frames are generated, so check only for PSR. |
| 3428 | */ |
| 3429 | if (HAS_PSR(dev_priv)) |
| 3430 | drm_vblank_restore(dev, pipe); |
| 3431 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3432 | return 0; |
| 3433 | } |
| 3434 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 3435 | /* Called from drm generic code, passed 'crtc' which |
| 3436 | * we use as a pipe index |
| 3437 | */ |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 3438 | static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe) |
| 3439 | { |
| 3440 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3441 | unsigned long irqflags; |
| 3442 | |
| 3443 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3444 | i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
| 3445 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3446 | } |
| 3447 | |
| 3448 | static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 3449 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3450 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 3451 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 3452 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3453 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3454 | i915_disable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 3455 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3456 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3457 | } |
| 3458 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 3459 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3460 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3461 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3462 | unsigned long irqflags; |
Tvrtko Ursulin | 55b8f2a | 2016-10-14 09:17:22 +0100 | [diff] [blame] | 3463 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 3464 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3465 | |
| 3466 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | fbdedaea | 2015-11-23 18:06:16 +0200 | [diff] [blame] | 3467 | ilk_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 3468 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3469 | } |
| 3470 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 3471 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3472 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3473 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3474 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3475 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3476 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | 013d375 | 2015-11-23 18:06:17 +0200 | [diff] [blame] | 3477 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3478 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3479 | } |
| 3480 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3481 | static void ibx_irq_reset(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3482 | { |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3483 | if (HAS_PCH_NOP(dev_priv)) |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3484 | return; |
| 3485 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3486 | GEN3_IRQ_RESET(SDE); |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3487 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3488 | if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3489 | I915_WRITE(SERR_INT, 0xffffffff); |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3490 | } |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3491 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3492 | /* |
| 3493 | * SDEIER is also touched by the interrupt handler to work around missed PCH |
| 3494 | * interrupts. Hence we can't update it after the interrupt handler is enabled - |
| 3495 | * instead we unconditionally enable all PCH interrupt sources here, but then |
| 3496 | * only unmask them as needed with SDEIMR. |
| 3497 | * |
| 3498 | * This function needs to be called before interrupts are enabled. |
| 3499 | */ |
| 3500 | static void ibx_irq_pre_postinstall(struct drm_device *dev) |
| 3501 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3502 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3503 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3504 | if (HAS_PCH_NOP(dev_priv)) |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3505 | return; |
| 3506 | |
| 3507 | WARN_ON(I915_READ(SDEIER) != 0); |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3508 | I915_WRITE(SDEIER, 0xffffffff); |
| 3509 | POSTING_READ(SDEIER); |
| 3510 | } |
| 3511 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3512 | static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3513 | { |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3514 | GEN3_IRQ_RESET(GT); |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3515 | if (INTEL_GEN(dev_priv) >= 6) |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3516 | GEN3_IRQ_RESET(GEN6_PM); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3517 | } |
| 3518 | |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3519 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
| 3520 | { |
Ville Syrjälä | 71b8b41 | 2016-04-11 16:56:31 +0300 | [diff] [blame] | 3521 | if (IS_CHERRYVIEW(dev_priv)) |
| 3522 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
| 3523 | else |
| 3524 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 3525 | |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 3526 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3527 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3528 | |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 3529 | i9xx_pipestat_irq_reset(dev_priv); |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3530 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3531 | GEN3_IRQ_RESET(VLV_); |
Chris Wilson | 8bd099a | 2017-11-30 12:52:53 +0000 | [diff] [blame] | 3532 | dev_priv->irq_mask = ~0u; |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3533 | } |
| 3534 | |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3535 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
| 3536 | { |
| 3537 | u32 pipestat_mask; |
Ville Syrjälä | 9ab981f | 2016-04-11 16:56:28 +0300 | [diff] [blame] | 3538 | u32 enable_mask; |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3539 | enum pipe pipe; |
| 3540 | |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 3541 | pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3542 | |
| 3543 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 3544 | for_each_pipe(dev_priv, pipe) |
| 3545 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); |
| 3546 | |
Ville Syrjälä | 9ab981f | 2016-04-11 16:56:28 +0300 | [diff] [blame] | 3547 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3548 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Ville Syrjälä | ebf5f92 | 2017-04-27 19:02:22 +0300 | [diff] [blame] | 3549 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3550 | I915_LPE_PIPE_A_INTERRUPT | |
| 3551 | I915_LPE_PIPE_B_INTERRUPT; |
| 3552 | |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3553 | if (IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | ebf5f92 | 2017-04-27 19:02:22 +0300 | [diff] [blame] | 3554 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | |
| 3555 | I915_LPE_PIPE_C_INTERRUPT; |
Ville Syrjälä | 6b7eafc | 2016-04-11 16:56:29 +0300 | [diff] [blame] | 3556 | |
Chris Wilson | 8bd099a | 2017-11-30 12:52:53 +0000 | [diff] [blame] | 3557 | WARN_ON(dev_priv->irq_mask != ~0u); |
Ville Syrjälä | 6b7eafc | 2016-04-11 16:56:29 +0300 | [diff] [blame] | 3558 | |
Ville Syrjälä | 9ab981f | 2016-04-11 16:56:28 +0300 | [diff] [blame] | 3559 | dev_priv->irq_mask = ~enable_mask; |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3560 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3561 | GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3562 | } |
| 3563 | |
| 3564 | /* drm_dma.h hooks |
| 3565 | */ |
| 3566 | static void ironlake_irq_reset(struct drm_device *dev) |
| 3567 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3568 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3569 | |
Ville Syrjälä | d420a50 | 2017-08-18 21:37:03 +0300 | [diff] [blame] | 3570 | if (IS_GEN5(dev_priv)) |
| 3571 | I915_WRITE(HWSTAM, 0xffffffff); |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3572 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3573 | GEN3_IRQ_RESET(DE); |
Tvrtko Ursulin | 5db9401 | 2016-10-13 11:03:10 +0100 | [diff] [blame] | 3574 | if (IS_GEN7(dev_priv)) |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3575 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
| 3576 | |
Daniel Vetter | fc34044 | 2018-04-05 15:00:23 -0700 | [diff] [blame] | 3577 | if (IS_HASWELL(dev_priv)) { |
| 3578 | I915_WRITE(EDP_PSR_IMR, 0xffffffff); |
| 3579 | I915_WRITE(EDP_PSR_IIR, 0xffffffff); |
| 3580 | } |
| 3581 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3582 | gen5_gt_irq_reset(dev_priv); |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3583 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3584 | ibx_irq_reset(dev_priv); |
Ville Syrjälä | 8bb6130 | 2016-04-12 18:56:44 +0300 | [diff] [blame] | 3585 | } |
| 3586 | |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 3587 | static void valleyview_irq_reset(struct drm_device *dev) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3588 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3589 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3590 | |
Ville Syrjälä | 34c7b8a | 2016-04-13 21:19:48 +0300 | [diff] [blame] | 3591 | I915_WRITE(VLV_MASTER_IER, 0); |
| 3592 | POSTING_READ(VLV_MASTER_IER); |
| 3593 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3594 | gen5_gt_irq_reset(dev_priv); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3595 | |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 3596 | spin_lock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 9918271 | 2016-04-11 16:56:25 +0300 | [diff] [blame] | 3597 | if (dev_priv->display_irqs_enabled) |
| 3598 | vlv_display_irq_reset(dev_priv); |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 3599 | spin_unlock_irq(&dev_priv->irq_lock); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3600 | } |
| 3601 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3602 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
| 3603 | { |
| 3604 | GEN8_IRQ_RESET_NDX(GT, 0); |
| 3605 | GEN8_IRQ_RESET_NDX(GT, 1); |
| 3606 | GEN8_IRQ_RESET_NDX(GT, 2); |
| 3607 | GEN8_IRQ_RESET_NDX(GT, 3); |
| 3608 | } |
| 3609 | |
Paulo Zanoni | 823f6b3 | 2014-04-01 15:37:26 -0300 | [diff] [blame] | 3610 | static void gen8_irq_reset(struct drm_device *dev) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3611 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3612 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3613 | int pipe; |
| 3614 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3615 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3616 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3617 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3618 | gen8_gt_irq_reset(dev_priv); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3619 | |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 3620 | I915_WRITE(EDP_PSR_IMR, 0xffffffff); |
| 3621 | I915_WRITE(EDP_PSR_IIR, 0xffffffff); |
| 3622 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3623 | for_each_pipe(dev_priv, pipe) |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 3624 | if (intel_display_power_is_enabled(dev_priv, |
| 3625 | POWER_DOMAIN_PIPE(pipe))) |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 3626 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3627 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3628 | GEN3_IRQ_RESET(GEN8_DE_PORT_); |
| 3629 | GEN3_IRQ_RESET(GEN8_DE_MISC_); |
| 3630 | GEN3_IRQ_RESET(GEN8_PCU_); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3631 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3632 | if (HAS_PCH_SPLIT(dev_priv)) |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 3633 | ibx_irq_reset(dev_priv); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3634 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3635 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3636 | static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) |
| 3637 | { |
| 3638 | /* Disable RCS, BCS, VCS and VECS class engines. */ |
| 3639 | I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0); |
| 3640 | I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0); |
| 3641 | |
| 3642 | /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ |
| 3643 | I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0); |
| 3644 | I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0); |
| 3645 | I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0); |
| 3646 | I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0); |
| 3647 | I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0); |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 3648 | |
| 3649 | I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); |
| 3650 | I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3651 | } |
| 3652 | |
| 3653 | static void gen11_irq_reset(struct drm_device *dev) |
| 3654 | { |
| 3655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3656 | int pipe; |
| 3657 | |
| 3658 | I915_WRITE(GEN11_GFX_MSTR_IRQ, 0); |
| 3659 | POSTING_READ(GEN11_GFX_MSTR_IRQ); |
| 3660 | |
| 3661 | gen11_gt_irq_reset(dev_priv); |
| 3662 | |
| 3663 | I915_WRITE(GEN11_DISPLAY_INT_CTL, 0); |
| 3664 | |
| 3665 | for_each_pipe(dev_priv, pipe) |
| 3666 | if (intel_display_power_is_enabled(dev_priv, |
| 3667 | POWER_DOMAIN_PIPE(pipe))) |
| 3668 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
| 3669 | |
| 3670 | GEN3_IRQ_RESET(GEN8_DE_PORT_); |
| 3671 | GEN3_IRQ_RESET(GEN8_DE_MISC_); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3672 | GEN3_IRQ_RESET(GEN11_DE_HPD_); |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3673 | GEN3_IRQ_RESET(GEN11_GU_MISC_); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3674 | GEN3_IRQ_RESET(GEN8_PCU_); |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3675 | |
| 3676 | if (HAS_PCH_ICP(dev_priv)) |
| 3677 | GEN3_IRQ_RESET(SDE); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 3678 | } |
| 3679 | |
Damien Lespiau | 4c6c03b | 2015-03-06 18:50:48 +0000 | [diff] [blame] | 3680 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
Imre Deak | 001bd2c | 2017-07-12 18:54:13 +0300 | [diff] [blame] | 3681 | u8 pipe_mask) |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3682 | { |
Paulo Zanoni | 1180e20 | 2014-10-07 18:02:52 -0300 | [diff] [blame] | 3683 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
Ville Syrjälä | 6831f3e | 2016-02-19 20:47:31 +0200 | [diff] [blame] | 3684 | enum pipe pipe; |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3685 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 3686 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 9dfe2e3 | 2017-09-28 13:06:24 +0300 | [diff] [blame] | 3687 | |
| 3688 | if (!intel_irqs_enabled(dev_priv)) { |
| 3689 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3690 | return; |
| 3691 | } |
| 3692 | |
Ville Syrjälä | 6831f3e | 2016-02-19 20:47:31 +0200 | [diff] [blame] | 3693 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
| 3694 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, |
| 3695 | dev_priv->de_irq_mask[pipe], |
| 3696 | ~dev_priv->de_irq_mask[pipe] | extra_ier); |
Imre Deak | 9dfe2e3 | 2017-09-28 13:06:24 +0300 | [diff] [blame] | 3697 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 3698 | spin_unlock_irq(&dev_priv->irq_lock); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3699 | } |
| 3700 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 3701 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
Imre Deak | 001bd2c | 2017-07-12 18:54:13 +0300 | [diff] [blame] | 3702 | u8 pipe_mask) |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 3703 | { |
Ville Syrjälä | 6831f3e | 2016-02-19 20:47:31 +0200 | [diff] [blame] | 3704 | enum pipe pipe; |
| 3705 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 3706 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 9dfe2e3 | 2017-09-28 13:06:24 +0300 | [diff] [blame] | 3707 | |
| 3708 | if (!intel_irqs_enabled(dev_priv)) { |
| 3709 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3710 | return; |
| 3711 | } |
| 3712 | |
Ville Syrjälä | 6831f3e | 2016-02-19 20:47:31 +0200 | [diff] [blame] | 3713 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
| 3714 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
Imre Deak | 9dfe2e3 | 2017-09-28 13:06:24 +0300 | [diff] [blame] | 3715 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 3716 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3717 | |
| 3718 | /* make sure we're done processing display irqs */ |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3719 | synchronize_irq(dev_priv->drm.irq); |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 3720 | } |
| 3721 | |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 3722 | static void cherryview_irq_reset(struct drm_device *dev) |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3723 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3724 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3725 | |
| 3726 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3727 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3728 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3729 | gen8_gt_irq_reset(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3730 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 3731 | GEN3_IRQ_RESET(GEN8_PCU_); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3732 | |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 3733 | spin_lock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 9918271 | 2016-04-11 16:56:25 +0300 | [diff] [blame] | 3734 | if (dev_priv->display_irqs_enabled) |
| 3735 | vlv_display_irq_reset(dev_priv); |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 3736 | spin_unlock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3737 | } |
| 3738 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3739 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 87a0210 | 2015-08-27 23:55:57 +0300 | [diff] [blame] | 3740 | const u32 hpd[HPD_NUM_PINS]) |
| 3741 | { |
Ville Syrjälä | 87a0210 | 2015-08-27 23:55:57 +0300 | [diff] [blame] | 3742 | struct intel_encoder *encoder; |
| 3743 | u32 enabled_irqs = 0; |
| 3744 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3745 | for_each_intel_encoder(&dev_priv->drm, encoder) |
Ville Syrjälä | 87a0210 | 2015-08-27 23:55:57 +0300 | [diff] [blame] | 3746 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
| 3747 | enabled_irqs |= hpd[encoder->hpd_pin]; |
| 3748 | |
| 3749 | return enabled_irqs; |
| 3750 | } |
| 3751 | |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3752 | static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3753 | { |
| 3754 | u32 hotplug; |
| 3755 | |
| 3756 | /* |
| 3757 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 3758 | * duration to 2ms (which is the minimum in the Display Port spec). |
| 3759 | * The pulse duration bits are reserved on LPT+. |
| 3760 | */ |
| 3761 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 3762 | hotplug &= ~(PORTB_PULSE_DURATION_MASK | |
| 3763 | PORTC_PULSE_DURATION_MASK | |
| 3764 | PORTD_PULSE_DURATION_MASK); |
| 3765 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 3766 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 3767 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 3768 | /* |
| 3769 | * When CPU and PCH are on the same package, port A |
| 3770 | * HPD must be enabled in both north and south. |
| 3771 | */ |
| 3772 | if (HAS_PCH_LPT_LP(dev_priv)) |
| 3773 | hotplug |= PORTA_HOTPLUG_ENABLE; |
| 3774 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 3775 | } |
| 3776 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3777 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3778 | { |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3779 | u32 hotplug_irqs, enabled_irqs; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3780 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3781 | if (HAS_PCH_IBX(dev_priv)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3782 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3783 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3784 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3785 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3786 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3787 | } |
| 3788 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3789 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3790 | |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3791 | ibx_hpd_detection_setup(dev_priv); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 3792 | } |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 3793 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3794 | static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3795 | { |
| 3796 | u32 hotplug; |
| 3797 | |
| 3798 | hotplug = I915_READ(SHOTPLUG_CTL_DDI); |
| 3799 | hotplug |= ICP_DDIA_HPD_ENABLE | |
| 3800 | ICP_DDIB_HPD_ENABLE; |
| 3801 | I915_WRITE(SHOTPLUG_CTL_DDI, hotplug); |
| 3802 | |
| 3803 | hotplug = I915_READ(SHOTPLUG_CTL_TC); |
| 3804 | hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) | |
| 3805 | ICP_TC_HPD_ENABLE(PORT_TC2) | |
| 3806 | ICP_TC_HPD_ENABLE(PORT_TC3) | |
| 3807 | ICP_TC_HPD_ENABLE(PORT_TC4); |
| 3808 | I915_WRITE(SHOTPLUG_CTL_TC, hotplug); |
| 3809 | } |
| 3810 | |
| 3811 | static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) |
| 3812 | { |
| 3813 | u32 hotplug_irqs, enabled_irqs; |
| 3814 | |
| 3815 | hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP; |
| 3816 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp); |
| 3817 | |
| 3818 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
| 3819 | |
| 3820 | icp_hpd_detection_setup(dev_priv); |
| 3821 | } |
| 3822 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3823 | static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3824 | { |
| 3825 | u32 hotplug; |
| 3826 | |
| 3827 | hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL); |
| 3828 | hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | |
| 3829 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | |
| 3830 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | |
| 3831 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); |
| 3832 | I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 3833 | |
| 3834 | hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); |
| 3835 | hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | |
| 3836 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | |
| 3837 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | |
| 3838 | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); |
| 3839 | I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3840 | } |
| 3841 | |
| 3842 | static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) |
| 3843 | { |
| 3844 | u32 hotplug_irqs, enabled_irqs; |
| 3845 | u32 val; |
| 3846 | |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 3847 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11); |
| 3848 | hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3849 | |
| 3850 | val = I915_READ(GEN11_DE_HPD_IMR); |
| 3851 | val &= ~hotplug_irqs; |
| 3852 | I915_WRITE(GEN11_DE_HPD_IMR, val); |
| 3853 | POSTING_READ(GEN11_DE_HPD_IMR); |
| 3854 | |
| 3855 | gen11_hpd_detection_setup(dev_priv); |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3856 | |
| 3857 | if (HAS_PCH_ICP(dev_priv)) |
| 3858 | icp_hpd_irq_setup(dev_priv); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3859 | } |
| 3860 | |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3861 | static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3862 | { |
Rodrigo Vivi | 3b92e26 | 2017-09-19 14:57:03 -0700 | [diff] [blame] | 3863 | u32 val, hotplug; |
| 3864 | |
| 3865 | /* Display WA #1179 WaHardHangonHotPlug: cnp */ |
| 3866 | if (HAS_PCH_CNP(dev_priv)) { |
| 3867 | val = I915_READ(SOUTH_CHICKEN1); |
| 3868 | val &= ~CHASSIS_CLK_REQ_DURATION_MASK; |
| 3869 | val |= CHASSIS_CLK_REQ_DURATION(0xf); |
| 3870 | I915_WRITE(SOUTH_CHICKEN1, val); |
| 3871 | } |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3872 | |
| 3873 | /* Enable digital hotplug on the PCH */ |
| 3874 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 3875 | hotplug |= PORTA_HOTPLUG_ENABLE | |
| 3876 | PORTB_HOTPLUG_ENABLE | |
| 3877 | PORTC_HOTPLUG_ENABLE | |
| 3878 | PORTD_HOTPLUG_ENABLE; |
| 3879 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 3880 | |
| 3881 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); |
| 3882 | hotplug |= PORTE_HOTPLUG_ENABLE; |
| 3883 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); |
| 3884 | } |
| 3885 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3886 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 3887 | { |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3888 | u32 hotplug_irqs, enabled_irqs; |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 3889 | |
| 3890 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3891 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 3892 | |
| 3893 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
| 3894 | |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3895 | spt_hpd_detection_setup(dev_priv); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3896 | } |
| 3897 | |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3898 | static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3899 | { |
| 3900 | u32 hotplug; |
| 3901 | |
| 3902 | /* |
| 3903 | * Enable digital hotplug on the CPU, and configure the DP short pulse |
| 3904 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 3905 | * The pulse duration bits are reserved on HSW+. |
| 3906 | */ |
| 3907 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); |
| 3908 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; |
| 3909 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | |
| 3910 | DIGITAL_PORTA_PULSE_DURATION_2ms; |
| 3911 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); |
| 3912 | } |
| 3913 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3914 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3915 | { |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3916 | u32 hotplug_irqs, enabled_irqs; |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3917 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3918 | if (INTEL_GEN(dev_priv) >= 8) { |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 3919 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3920 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 3921 | |
| 3922 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3923 | } else if (INTEL_GEN(dev_priv) >= 7) { |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 3924 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3925 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 3926 | |
| 3927 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 3928 | } else { |
| 3929 | hotplug_irqs = DE_DP_A_HOTPLUG; |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3930 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3931 | |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 3932 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
| 3933 | } |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3934 | |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 3935 | ilk_hpd_detection_setup(dev_priv); |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3936 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 3937 | ibx_hpd_irq_setup(dev_priv); |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 3938 | } |
| 3939 | |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3940 | static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, |
| 3941 | u32 enabled_irqs) |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 3942 | { |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3943 | u32 hotplug; |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 3944 | |
Ville Syrjälä | a52bb15 | 2015-08-27 23:56:11 +0300 | [diff] [blame] | 3945 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3946 | hotplug |= PORTA_HOTPLUG_ENABLE | |
| 3947 | PORTB_HOTPLUG_ENABLE | |
| 3948 | PORTC_HOTPLUG_ENABLE; |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3949 | |
| 3950 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", |
| 3951 | hotplug, enabled_irqs); |
| 3952 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; |
| 3953 | |
| 3954 | /* |
| 3955 | * For BXT invert bit has to be set based on AOB design |
| 3956 | * for HPD detection logic, update it based on VBT fields. |
| 3957 | */ |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3958 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && |
| 3959 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) |
| 3960 | hotplug |= BXT_DDIA_HPD_INVERT; |
| 3961 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && |
| 3962 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) |
| 3963 | hotplug |= BXT_DDIB_HPD_INVERT; |
| 3964 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && |
| 3965 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) |
| 3966 | hotplug |= BXT_DDIC_HPD_INVERT; |
| 3967 | |
Ville Syrjälä | a52bb15 | 2015-08-27 23:56:11 +0300 | [diff] [blame] | 3968 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 3969 | } |
| 3970 | |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 3971 | static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
| 3972 | { |
| 3973 | __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); |
| 3974 | } |
| 3975 | |
| 3976 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
| 3977 | { |
| 3978 | u32 hotplug_irqs, enabled_irqs; |
| 3979 | |
| 3980 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); |
| 3981 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; |
| 3982 | |
| 3983 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
| 3984 | |
| 3985 | __bxt_hpd_detection_setup(dev_priv, enabled_irqs); |
| 3986 | } |
| 3987 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3988 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 3989 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3990 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3991 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3992 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3993 | if (HAS_PCH_NOP(dev_priv)) |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 3994 | return; |
| 3995 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 3996 | if (HAS_PCH_IBX(dev_priv)) |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3997 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
Dhinakaran Pandiyan | 4ebc650 | 2017-09-08 17:42:55 -0700 | [diff] [blame] | 3998 | else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3999 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
Dhinakaran Pandiyan | 4ebc650 | 2017-09-08 17:42:55 -0700 | [diff] [blame] | 4000 | else |
| 4001 | mask = SDE_GMBUS_CPT; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4002 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 4003 | gen3_assert_iir_is_zero(dev_priv, SDEIIR); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 4004 | I915_WRITE(SDEIMR, ~mask); |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 4005 | |
| 4006 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || |
| 4007 | HAS_PCH_LPT(dev_priv)) |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 4008 | ibx_hpd_detection_setup(dev_priv); |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 4009 | else |
| 4010 | spt_hpd_detection_setup(dev_priv); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 4011 | } |
| 4012 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4013 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 4014 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4015 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4016 | u32 pm_irqs, gt_irqs; |
| 4017 | |
| 4018 | pm_irqs = gt_irqs = 0; |
| 4019 | |
| 4020 | dev_priv->gt_irq_mask = ~0; |
Tvrtko Ursulin | 3c9192b | 2016-10-13 11:03:05 +0100 | [diff] [blame] | 4021 | if (HAS_L3_DPF(dev_priv)) { |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4022 | /* L3 parity interrupt is always unmasked. */ |
Tvrtko Ursulin | 772c2a5 | 2016-10-13 11:03:01 +0100 | [diff] [blame] | 4023 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); |
| 4024 | gt_irqs |= GT_PARITY_ERROR(dev_priv); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4025 | } |
| 4026 | |
| 4027 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
Tvrtko Ursulin | 5db9401 | 2016-10-13 11:03:10 +0100 | [diff] [blame] | 4028 | if (IS_GEN5(dev_priv)) { |
Chris Wilson | f8973c2 | 2016-07-01 17:23:21 +0100 | [diff] [blame] | 4029 | gt_irqs |= ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4030 | } else { |
| 4031 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 4032 | } |
| 4033 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 4034 | GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4035 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 4036 | if (INTEL_GEN(dev_priv) >= 6) { |
Imre Deak | 78e68d3 | 2014-12-15 18:59:27 +0200 | [diff] [blame] | 4037 | /* |
| 4038 | * RPS interrupts will get enabled/disabled on demand when RPS |
| 4039 | * itself is enabled/disabled. |
| 4040 | */ |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 4041 | if (HAS_VEBOX(dev_priv)) { |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4042 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 4043 | dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT; |
| 4044 | } |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4045 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 4046 | dev_priv->pm_imr = 0xffffffff; |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 4047 | GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4048 | } |
| 4049 | } |
| 4050 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4051 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4052 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4053 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 4054 | u32 display_mask, extra_mask; |
| 4055 | |
Tvrtko Ursulin | b243f53 | 2016-11-16 08:55:38 +0000 | [diff] [blame] | 4056 | if (INTEL_GEN(dev_priv) >= 7) { |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 4057 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4058 | DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 4059 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 4060 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
| 4061 | DE_DP_A_HOTPLUG_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 4062 | } else { |
| 4063 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4064 | DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | |
| 4065 | DE_PIPEA_CRC_DONE | DE_POISON); |
Ville Syrjälä | e4ce95a | 2015-08-27 23:56:03 +0300 | [diff] [blame] | 4066 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
| 4067 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | |
| 4068 | DE_DP_A_HOTPLUG); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 4069 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4070 | |
Daniel Vetter | fc34044 | 2018-04-05 15:00:23 -0700 | [diff] [blame] | 4071 | if (IS_HASWELL(dev_priv)) { |
| 4072 | gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); |
Dhinakaran Pandiyan | 54fd314 | 2018-04-04 18:37:17 -0700 | [diff] [blame] | 4073 | intel_psr_irq_control(dev_priv, dev_priv->psr.debug); |
Daniel Vetter | fc34044 | 2018-04-05 15:00:23 -0700 | [diff] [blame] | 4074 | display_mask |= DE_EDP_PSR_INT_HSW; |
| 4075 | } |
| 4076 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4077 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4078 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 4079 | ibx_irq_pre_postinstall(dev); |
| 4080 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 4081 | GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4082 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4083 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4084 | |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 4085 | ilk_hpd_detection_setup(dev_priv); |
| 4086 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 4087 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 4088 | |
Tvrtko Ursulin | 50a0bc9 | 2016-10-13 11:02:58 +0100 | [diff] [blame] | 4089 | if (IS_IRONLAKE_M(dev_priv)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 4090 | /* Enable PCU event interrupts |
| 4091 | * |
| 4092 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 4093 | * setup is guaranteed to run in single-threaded context. But we |
| 4094 | * need it to make the assert_spin_locked happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4095 | spin_lock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | fbdedaea | 2015-11-23 18:06:16 +0200 | [diff] [blame] | 4096 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4097 | spin_unlock_irq(&dev_priv->irq_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 4098 | } |
| 4099 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 4100 | return 0; |
| 4101 | } |
| 4102 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 4103 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
| 4104 | { |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 4105 | lockdep_assert_held(&dev_priv->irq_lock); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 4106 | |
| 4107 | if (dev_priv->display_irqs_enabled) |
| 4108 | return; |
| 4109 | |
| 4110 | dev_priv->display_irqs_enabled = true; |
| 4111 | |
Ville Syrjälä | d6c6980 | 2016-04-11 16:56:27 +0300 | [diff] [blame] | 4112 | if (intel_irqs_enabled(dev_priv)) { |
| 4113 | vlv_display_irq_reset(dev_priv); |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4114 | vlv_display_irq_postinstall(dev_priv); |
Ville Syrjälä | d6c6980 | 2016-04-11 16:56:27 +0300 | [diff] [blame] | 4115 | } |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 4116 | } |
| 4117 | |
| 4118 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) |
| 4119 | { |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 4120 | lockdep_assert_held(&dev_priv->irq_lock); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 4121 | |
| 4122 | if (!dev_priv->display_irqs_enabled) |
| 4123 | return; |
| 4124 | |
| 4125 | dev_priv->display_irqs_enabled = false; |
| 4126 | |
Imre Deak | 950eaba | 2014-09-08 15:21:09 +0300 | [diff] [blame] | 4127 | if (intel_irqs_enabled(dev_priv)) |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4128 | vlv_display_irq_reset(dev_priv); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 4129 | } |
| 4130 | |
Ville Syrjälä | 0e6c9a9 | 2014-10-30 19:43:00 +0200 | [diff] [blame] | 4131 | |
| 4132 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 4133 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4134 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 0e6c9a9 | 2014-10-30 19:43:00 +0200 | [diff] [blame] | 4135 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 4136 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4137 | |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4138 | spin_lock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 9918271 | 2016-04-11 16:56:25 +0300 | [diff] [blame] | 4139 | if (dev_priv->display_irqs_enabled) |
| 4140 | vlv_display_irq_postinstall(dev_priv); |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4141 | spin_unlock_irq(&dev_priv->irq_lock); |
| 4142 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4143 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Ville Syrjälä | 34c7b8a | 2016-04-13 21:19:48 +0300 | [diff] [blame] | 4144 | POSTING_READ(VLV_MASTER_IER); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4145 | |
| 4146 | return 0; |
| 4147 | } |
| 4148 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4149 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
| 4150 | { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4151 | /* These are interrupts we'll toggle with the ring mask register */ |
| 4152 | uint32_t gt_interrupts[] = { |
| 4153 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 4154 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 4155 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
| 4156 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4157 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 4158 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
| 4159 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | |
| 4160 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4161 | 0, |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 4162 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
| 4163 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4164 | }; |
| 4165 | |
Tvrtko Ursulin | 9873573 | 2016-04-19 16:46:08 +0100 | [diff] [blame] | 4166 | if (HAS_L3_DPF(dev_priv)) |
| 4167 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
| 4168 | |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 4169 | dev_priv->pm_ier = 0x0; |
| 4170 | dev_priv->pm_imr = ~dev_priv->pm_ier; |
Deepak S | 9a2d2d8 | 2014-08-22 08:32:40 +0530 | [diff] [blame] | 4171 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
| 4172 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); |
Imre Deak | 78e68d3 | 2014-12-15 18:59:27 +0200 | [diff] [blame] | 4173 | /* |
| 4174 | * RPS interrupts will get enabled/disabled on demand when RPS itself |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 4175 | * is enabled/disabled. Same wil be the case for GuC interrupts. |
Imre Deak | 78e68d3 | 2014-12-15 18:59:27 +0200 | [diff] [blame] | 4176 | */ |
Akash Goel | f4e9af4 | 2016-10-12 21:54:30 +0530 | [diff] [blame] | 4177 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); |
Deepak S | 9a2d2d8 | 2014-08-22 08:32:40 +0530 | [diff] [blame] | 4178 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4179 | } |
| 4180 | |
| 4181 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) |
| 4182 | { |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 4183 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
| 4184 | uint32_t de_pipe_enables; |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4185 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
| 4186 | u32 de_port_enables; |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 4187 | u32 de_misc_masked = GEN8_DE_EDP_PSR; |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4188 | enum pipe pipe; |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 4189 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 4190 | if (INTEL_GEN(dev_priv) <= 10) |
| 4191 | de_misc_masked |= GEN8_DE_MISC_GSE; |
| 4192 | |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 4193 | if (INTEL_GEN(dev_priv) >= 9) { |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4194 | de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4195 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
| 4196 | GEN9_AUX_CHANNEL_D; |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 4197 | if (IS_GEN9_LP(dev_priv)) |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4198 | de_port_masked |= BXT_DE_PORT_GMBUS; |
| 4199 | } else { |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4200 | de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4201 | } |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 4202 | |
James Ausmus | bb187e9 | 2018-06-11 17:25:12 -0700 | [diff] [blame] | 4203 | if (INTEL_GEN(dev_priv) >= 11) |
| 4204 | de_port_masked |= ICL_AUX_CHANNEL_E; |
| 4205 | |
Dhinakaran Pandiyan | 9bb635d | 2018-05-21 17:25:35 -0700 | [diff] [blame] | 4206 | if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11) |
Rodrigo Vivi | a324fca | 2018-01-29 15:22:15 -0800 | [diff] [blame] | 4207 | de_port_masked |= CNL_AUX_CHANNEL_F; |
| 4208 | |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 4209 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
| 4210 | GEN8_PIPE_FIFO_UNDERRUN; |
| 4211 | |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4212 | de_port_enables = de_port_masked; |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 4213 | if (IS_GEN9_LP(dev_priv)) |
Ville Syrjälä | a52bb15 | 2015-08-27 23:56:11 +0300 | [diff] [blame] | 4214 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; |
| 4215 | else if (IS_BROADWELL(dev_priv)) |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4216 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
| 4217 | |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 4218 | gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); |
Dhinakaran Pandiyan | 54fd314 | 2018-04-04 18:37:17 -0700 | [diff] [blame] | 4219 | intel_psr_irq_control(dev_priv, dev_priv->psr.debug); |
Ville Syrjälä | e04f7ec | 2018-04-03 14:24:18 -0700 | [diff] [blame] | 4220 | |
Mika Kahola | 0a195c0 | 2017-10-10 13:17:04 +0300 | [diff] [blame] | 4221 | for_each_pipe(dev_priv, pipe) { |
| 4222 | dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4223 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 4224 | if (intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 4225 | POWER_DOMAIN_PIPE(pipe))) |
| 4226 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, |
| 4227 | dev_priv->de_irq_mask[pipe], |
| 4228 | de_pipe_enables); |
Mika Kahola | 0a195c0 | 2017-10-10 13:17:04 +0300 | [diff] [blame] | 4229 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4230 | |
Ville Syrjälä | 3488d4e | 2017-08-18 21:36:52 +0300 | [diff] [blame] | 4231 | GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
| 4232 | GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 4233 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 4234 | if (INTEL_GEN(dev_priv) >= 11) { |
| 4235 | u32 de_hpd_masked = 0; |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 4236 | u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | |
| 4237 | GEN11_DE_TBT_HOTPLUG_MASK; |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 4238 | |
| 4239 | GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); |
| 4240 | gen11_hpd_detection_setup(dev_priv); |
| 4241 | } else if (IS_GEN9_LP(dev_priv)) { |
Imre Deak | 2a57d9c | 2017-01-27 11:39:18 +0200 | [diff] [blame] | 4242 | bxt_hpd_detection_setup(dev_priv); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 4243 | } else if (IS_BROADWELL(dev_priv)) { |
Imre Deak | 1a56b1a | 2017-01-27 11:39:21 +0200 | [diff] [blame] | 4244 | ilk_hpd_detection_setup(dev_priv); |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 4245 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4246 | } |
| 4247 | |
| 4248 | static int gen8_irq_postinstall(struct drm_device *dev) |
| 4249 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4250 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4251 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 4252 | if (HAS_PCH_SPLIT(dev_priv)) |
Shashank Sharma | 266ea3d | 2014-08-22 17:40:42 +0530 | [diff] [blame] | 4253 | ibx_irq_pre_postinstall(dev); |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 4254 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4255 | gen8_gt_irq_postinstall(dev_priv); |
| 4256 | gen8_de_irq_postinstall(dev_priv); |
| 4257 | |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 4258 | if (HAS_PCH_SPLIT(dev_priv)) |
Shashank Sharma | 266ea3d | 2014-08-22 17:40:42 +0530 | [diff] [blame] | 4259 | ibx_irq_postinstall(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4260 | |
Ville Syrjälä | e5328c4 | 2016-04-13 21:19:47 +0300 | [diff] [blame] | 4261 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4262 | POSTING_READ(GEN8_MASTER_IRQ); |
| 4263 | |
| 4264 | return 0; |
| 4265 | } |
| 4266 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4267 | static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
| 4268 | { |
| 4269 | const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT; |
| 4270 | |
| 4271 | BUILD_BUG_ON(irqs & 0xffff0000); |
| 4272 | |
| 4273 | /* Enable RCS, BCS, VCS and VECS class interrupts. */ |
| 4274 | I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs); |
| 4275 | I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs); |
| 4276 | |
| 4277 | /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ |
| 4278 | I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16)); |
| 4279 | I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16)); |
| 4280 | I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16)); |
| 4281 | I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16)); |
| 4282 | I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16)); |
| 4283 | |
Oscar Mateo | d02b98b | 2018-04-05 17:00:50 +0300 | [diff] [blame] | 4284 | /* |
| 4285 | * RPS interrupts will get enabled/disabled on demand when RPS itself |
| 4286 | * is enabled/disabled. |
| 4287 | */ |
| 4288 | dev_priv->pm_ier = 0x0; |
| 4289 | dev_priv->pm_imr = ~dev_priv->pm_ier; |
| 4290 | I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); |
| 4291 | I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4292 | } |
| 4293 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 4294 | static void icp_irq_postinstall(struct drm_device *dev) |
| 4295 | { |
| 4296 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 4297 | u32 mask = SDE_GMBUS_ICP; |
| 4298 | |
| 4299 | WARN_ON(I915_READ(SDEIER) != 0); |
| 4300 | I915_WRITE(SDEIER, 0xffffffff); |
| 4301 | POSTING_READ(SDEIER); |
| 4302 | |
| 4303 | gen3_assert_iir_is_zero(dev_priv, SDEIIR); |
| 4304 | I915_WRITE(SDEIMR, ~mask); |
| 4305 | |
| 4306 | icp_hpd_detection_setup(dev_priv); |
| 4307 | } |
| 4308 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4309 | static int gen11_irq_postinstall(struct drm_device *dev) |
| 4310 | { |
| 4311 | struct drm_i915_private *dev_priv = dev->dev_private; |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 4312 | u32 gu_misc_masked = GEN11_GU_MISC_GSE; |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4313 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 4314 | if (HAS_PCH_ICP(dev_priv)) |
| 4315 | icp_irq_postinstall(dev); |
| 4316 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4317 | gen11_gt_irq_postinstall(dev_priv); |
| 4318 | gen8_de_irq_postinstall(dev_priv); |
| 4319 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 4320 | GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); |
| 4321 | |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4322 | I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); |
| 4323 | |
| 4324 | I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); |
| 4325 | POSTING_READ(GEN11_GFX_MSTR_IRQ); |
| 4326 | |
| 4327 | return 0; |
| 4328 | } |
| 4329 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4330 | static int cherryview_irq_postinstall(struct drm_device *dev) |
| 4331 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4332 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4333 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4334 | gen8_gt_irq_postinstall(dev_priv); |
| 4335 | |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4336 | spin_lock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 9918271 | 2016-04-11 16:56:25 +0300 | [diff] [blame] | 4337 | if (dev_priv->display_irqs_enabled) |
| 4338 | vlv_display_irq_postinstall(dev_priv); |
Ville Syrjälä | ad22d10 | 2016-04-12 18:56:14 +0300 | [diff] [blame] | 4339 | spin_unlock_irq(&dev_priv->irq_lock); |
| 4340 | |
Ville Syrjälä | e5328c4 | 2016-04-13 21:19:47 +0300 | [diff] [blame] | 4341 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4342 | POSTING_READ(GEN8_MASTER_IRQ); |
| 4343 | |
| 4344 | return 0; |
| 4345 | } |
| 4346 | |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4347 | static void i8xx_irq_reset(struct drm_device *dev) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4348 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4349 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4350 | |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 4351 | i9xx_pipestat_irq_reset(dev_priv); |
| 4352 | |
Ville Syrjälä | d420a50 | 2017-08-18 21:37:03 +0300 | [diff] [blame] | 4353 | I915_WRITE16(HWSTAM, 0xffff); |
| 4354 | |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 4355 | GEN2_IRQ_RESET(); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4356 | } |
| 4357 | |
| 4358 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 4359 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4360 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 4361 | u16 enable_mask; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4362 | |
Ville Syrjälä | 045cebd | 2017-08-18 21:36:55 +0300 | [diff] [blame] | 4363 | I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE | |
| 4364 | I915_ERROR_MEMORY_REFRESH)); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4365 | |
| 4366 | /* Unmask the interrupts that we always want on. */ |
| 4367 | dev_priv->irq_mask = |
| 4368 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4369 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4370 | |
Ville Syrjälä | e9e9848 | 2017-08-18 21:36:54 +0300 | [diff] [blame] | 4371 | enable_mask = |
| 4372 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4373 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4374 | I915_USER_INTERRUPT; |
| 4375 | |
| 4376 | GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4377 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4378 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4379 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4380 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4381 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4382 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4383 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4384 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4385 | return 0; |
| 4386 | } |
| 4387 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4388 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4389 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4390 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4391 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4392 | irqreturn_t ret = IRQ_NONE; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4393 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 4394 | if (!intel_irqs_enabled(dev_priv)) |
| 4395 | return IRQ_NONE; |
| 4396 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4397 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 4398 | disable_rpm_wakeref_asserts(dev_priv); |
| 4399 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4400 | do { |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4401 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4402 | u16 iir; |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4403 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4404 | iir = I915_READ16(IIR); |
| 4405 | if (iir == 0) |
| 4406 | break; |
| 4407 | |
| 4408 | ret = IRQ_HANDLED; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4409 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4410 | /* Call regardless, as some status bits might not be |
| 4411 | * signalled in iir */ |
| 4412 | i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4413 | |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 4414 | I915_WRITE16(IIR, iir); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4415 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4416 | if (iir & I915_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 4417 | notify_ring(dev_priv->engine[RCS]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4418 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4419 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 4420 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
| 4421 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4422 | i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4423 | } while (0); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4424 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4425 | enable_rpm_wakeref_asserts(dev_priv); |
| 4426 | |
| 4427 | return ret; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4428 | } |
| 4429 | |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4430 | static void i915_irq_reset(struct drm_device *dev) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4431 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4432 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4433 | |
Tvrtko Ursulin | 56b857a | 2016-11-07 09:29:20 +0000 | [diff] [blame] | 4434 | if (I915_HAS_HOTPLUG(dev_priv)) { |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 4435 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4436 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 4437 | } |
| 4438 | |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 4439 | i9xx_pipestat_irq_reset(dev_priv); |
| 4440 | |
Ville Syrjälä | d420a50 | 2017-08-18 21:37:03 +0300 | [diff] [blame] | 4441 | I915_WRITE(HWSTAM, 0xffffffff); |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 4442 | |
Ville Syrjälä | ba7eb78 | 2017-08-18 21:36:53 +0300 | [diff] [blame] | 4443 | GEN3_IRQ_RESET(); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4444 | } |
| 4445 | |
| 4446 | static int i915_irq_postinstall(struct drm_device *dev) |
| 4447 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4448 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4449 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4450 | |
Ville Syrjälä | 045cebd | 2017-08-18 21:36:55 +0300 | [diff] [blame] | 4451 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | |
| 4452 | I915_ERROR_MEMORY_REFRESH)); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4453 | |
| 4454 | /* Unmask the interrupts that we always want on. */ |
| 4455 | dev_priv->irq_mask = |
| 4456 | ~(I915_ASLE_INTERRUPT | |
| 4457 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Ville Syrjälä | 842ebf7 | 2017-08-18 21:36:50 +0300 | [diff] [blame] | 4458 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4459 | |
| 4460 | enable_mask = |
| 4461 | I915_ASLE_INTERRUPT | |
| 4462 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4463 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4464 | I915_USER_INTERRUPT; |
| 4465 | |
Tvrtko Ursulin | 56b857a | 2016-11-07 09:29:20 +0000 | [diff] [blame] | 4466 | if (I915_HAS_HOTPLUG(dev_priv)) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4467 | /* Enable in IER... */ |
| 4468 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 4469 | /* and unmask in IMR */ |
| 4470 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 4471 | } |
| 4472 | |
Ville Syrjälä | ba7eb78 | 2017-08-18 21:36:53 +0300 | [diff] [blame] | 4473 | GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4474 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4475 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4476 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4477 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4478 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4479 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4480 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4481 | |
Ville Syrjälä | c30bb1f | 2017-08-18 21:36:57 +0300 | [diff] [blame] | 4482 | i915_enable_asle_pipestat(dev_priv); |
| 4483 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4484 | return 0; |
| 4485 | } |
| 4486 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4487 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4488 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4489 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4490 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4491 | irqreturn_t ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4492 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 4493 | if (!intel_irqs_enabled(dev_priv)) |
| 4494 | return IRQ_NONE; |
| 4495 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4496 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 4497 | disable_rpm_wakeref_asserts(dev_priv); |
| 4498 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4499 | do { |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4500 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4501 | u32 hotplug_status = 0; |
| 4502 | u32 iir; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4503 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4504 | iir = I915_READ(IIR); |
| 4505 | if (iir == 0) |
| 4506 | break; |
| 4507 | |
| 4508 | ret = IRQ_HANDLED; |
| 4509 | |
| 4510 | if (I915_HAS_HOTPLUG(dev_priv) && |
| 4511 | iir & I915_DISPLAY_PORT_INTERRUPT) |
| 4512 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4513 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4514 | /* Call regardless, as some status bits might not be |
| 4515 | * signalled in iir */ |
| 4516 | i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4517 | |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 4518 | I915_WRITE(IIR, iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4519 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4520 | if (iir & I915_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 4521 | notify_ring(dev_priv->engine[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4522 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4523 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 4524 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4525 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4526 | if (hotplug_status) |
| 4527 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
| 4528 | |
| 4529 | i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); |
| 4530 | } while (0); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4531 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4532 | enable_rpm_wakeref_asserts(dev_priv); |
| 4533 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4534 | return ret; |
| 4535 | } |
| 4536 | |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4537 | static void i965_irq_reset(struct drm_device *dev) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4538 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4539 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4540 | |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 4541 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4542 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4543 | |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 4544 | i9xx_pipestat_irq_reset(dev_priv); |
| 4545 | |
Ville Syrjälä | d420a50 | 2017-08-18 21:37:03 +0300 | [diff] [blame] | 4546 | I915_WRITE(HWSTAM, 0xffffffff); |
Ville Syrjälä | 44d9241 | 2017-08-18 21:36:51 +0300 | [diff] [blame] | 4547 | |
Ville Syrjälä | ba7eb78 | 2017-08-18 21:36:53 +0300 | [diff] [blame] | 4548 | GEN3_IRQ_RESET(); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4549 | } |
| 4550 | |
| 4551 | static int i965_irq_postinstall(struct drm_device *dev) |
| 4552 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4553 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4554 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4555 | u32 error_mask; |
| 4556 | |
Ville Syrjälä | 045cebd | 2017-08-18 21:36:55 +0300 | [diff] [blame] | 4557 | /* |
| 4558 | * Enable some error detection, note the instruction error mask |
| 4559 | * bit is reserved, so we leave it masked. |
| 4560 | */ |
| 4561 | if (IS_G4X(dev_priv)) { |
| 4562 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 4563 | GM45_ERROR_MEM_PRIV | |
| 4564 | GM45_ERROR_CP_PRIV | |
| 4565 | I915_ERROR_MEMORY_REFRESH); |
| 4566 | } else { |
| 4567 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 4568 | I915_ERROR_MEMORY_REFRESH); |
| 4569 | } |
| 4570 | I915_WRITE(EMR, error_mask); |
| 4571 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4572 | /* Unmask the interrupts that we always want on. */ |
Ville Syrjälä | c30bb1f | 2017-08-18 21:36:57 +0300 | [diff] [blame] | 4573 | dev_priv->irq_mask = |
| 4574 | ~(I915_ASLE_INTERRUPT | |
| 4575 | I915_DISPLAY_PORT_INTERRUPT | |
| 4576 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4577 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4578 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4579 | |
Ville Syrjälä | c30bb1f | 2017-08-18 21:36:57 +0300 | [diff] [blame] | 4580 | enable_mask = |
| 4581 | I915_ASLE_INTERRUPT | |
| 4582 | I915_DISPLAY_PORT_INTERRUPT | |
| 4583 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4584 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4585 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 4586 | I915_USER_INTERRUPT; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4587 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 4588 | if (IS_G4X(dev_priv)) |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4589 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4590 | |
Ville Syrjälä | c30bb1f | 2017-08-18 21:36:57 +0300 | [diff] [blame] | 4591 | GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); |
| 4592 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 4593 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4594 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4595 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4596 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 4597 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4598 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4599 | spin_unlock_irq(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4600 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 4601 | i915_enable_asle_pipestat(dev_priv); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4602 | |
| 4603 | return 0; |
| 4604 | } |
| 4605 | |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 4606 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4607 | { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4608 | u32 hotplug_en; |
| 4609 | |
Chris Wilson | 6752041 | 2017-03-02 13:28:01 +0000 | [diff] [blame] | 4610 | lockdep_assert_held(&dev_priv->irq_lock); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4611 | |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4612 | /* Note HDMI and DP share hotplug bits */ |
| 4613 | /* enable bits are the same for all generations */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 4614 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4615 | /* Programming the CRT detection parameters tends |
| 4616 | to generate a spurious hotplug event about three |
| 4617 | seconds later. So just do it once. |
| 4618 | */ |
Tvrtko Ursulin | 91d1425 | 2016-05-06 14:48:28 +0100 | [diff] [blame] | 4619 | if (IS_G4X(dev_priv)) |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4620 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4621 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4622 | |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4623 | /* Ignore TV since it's buggy */ |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 4624 | i915_hotplug_interrupt_update_locked(dev_priv, |
Jani Nikula | f9e3dc7 | 2015-10-21 17:22:43 +0300 | [diff] [blame] | 4625 | HOTPLUG_INT_EN_MASK | |
| 4626 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | |
| 4627 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, |
| 4628 | hotplug_en); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4629 | } |
| 4630 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4631 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4632 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4633 | struct drm_device *dev = arg; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4634 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4635 | irqreturn_t ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4636 | |
Imre Deak | 2dd2a88 | 2015-02-24 11:14:30 +0200 | [diff] [blame] | 4637 | if (!intel_irqs_enabled(dev_priv)) |
| 4638 | return IRQ_NONE; |
| 4639 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4640 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
| 4641 | disable_rpm_wakeref_asserts(dev_priv); |
| 4642 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4643 | do { |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4644 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4645 | u32 hotplug_status = 0; |
| 4646 | u32 iir; |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4647 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4648 | iir = I915_READ(IIR); |
| 4649 | if (iir == 0) |
| 4650 | break; |
| 4651 | |
| 4652 | ret = IRQ_HANDLED; |
| 4653 | |
| 4654 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 4655 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4656 | |
Ville Syrjälä | eb64343 | 2017-08-18 21:36:59 +0300 | [diff] [blame] | 4657 | /* Call regardless, as some status bits might not be |
| 4658 | * signalled in iir */ |
| 4659 | i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4660 | |
Daniel Vetter | fd3a402 | 2017-07-20 19:57:51 +0200 | [diff] [blame] | 4661 | I915_WRITE(IIR, iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4662 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4663 | if (iir & I915_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 4664 | notify_ring(dev_priv->engine[RCS]); |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4665 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4666 | if (iir & I915_BSD_USER_INTERRUPT) |
Akash Goel | 3b3f165 | 2016-10-13 22:44:48 +0530 | [diff] [blame] | 4667 | notify_ring(dev_priv->engine[VCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4668 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4669 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 4670 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 4671 | |
Ville Syrjälä | af722d2 | 2017-08-18 21:37:00 +0300 | [diff] [blame] | 4672 | if (hotplug_status) |
| 4673 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
| 4674 | |
| 4675 | i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); |
| 4676 | } while (0); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4677 | |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 4678 | enable_rpm_wakeref_asserts(dev_priv); |
| 4679 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4680 | return ret; |
| 4681 | } |
| 4682 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4683 | /** |
| 4684 | * intel_irq_init - initializes irq support |
| 4685 | * @dev_priv: i915 device instance |
| 4686 | * |
| 4687 | * This function initializes all the irq support including work items, timers |
| 4688 | * and all the vtables. It does not setup the interrupt itself though. |
| 4689 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4690 | void intel_irq_init(struct drm_i915_private *dev_priv) |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4691 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4692 | struct drm_device *dev = &dev_priv->drm; |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 4693 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
Joonas Lahtinen | cefcff8 | 2017-04-28 10:58:39 +0300 | [diff] [blame] | 4694 | int i; |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4695 | |
Jani Nikula | 77913b3 | 2015-06-18 13:06:16 +0300 | [diff] [blame] | 4696 | intel_hpd_init_work(dev_priv); |
| 4697 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 4698 | INIT_WORK(&rps->work, gen6_pm_rps_work); |
Joonas Lahtinen | cefcff8 | 2017-04-28 10:58:39 +0300 | [diff] [blame] | 4699 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4700 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Joonas Lahtinen | cefcff8 | 2017-04-28 10:58:39 +0300 | [diff] [blame] | 4701 | for (i = 0; i < MAX_L3_SLICES; ++i) |
| 4702 | dev_priv->l3_parity.remap_info[i] = NULL; |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4703 | |
Tvrtko Ursulin | 4805fe8 | 2016-11-04 14:42:46 +0000 | [diff] [blame] | 4704 | if (HAS_GUC_SCHED(dev_priv)) |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 4705 | dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; |
| 4706 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4707 | /* Let's track the enabled rps events */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4708 | if (IS_VALLEYVIEW(dev_priv)) |
Ville Syrjälä | 6c65a587 | 2014-08-29 14:14:07 +0300 | [diff] [blame] | 4709 | /* WaGsvRC0ResidencyMethod:vlv */ |
Chris Wilson | e0e8c7c | 2017-03-09 21:12:30 +0000 | [diff] [blame] | 4710 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4711 | else |
| 4712 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4713 | |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 4714 | rps->pm_intrmsk_mbz = 0; |
Sagar Arun Kamble | 1800ad2 | 2016-05-31 13:58:27 +0530 | [diff] [blame] | 4715 | |
| 4716 | /* |
Mika Kuoppala | acf2dc2 | 2017-04-13 14:15:27 +0300 | [diff] [blame] | 4717 | * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer |
Sagar Arun Kamble | 1800ad2 | 2016-05-31 13:58:27 +0530 | [diff] [blame] | 4718 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
| 4719 | * |
| 4720 | * TODO: verify if this can be reproduced on VLV,CHV. |
| 4721 | */ |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 4722 | if (INTEL_GEN(dev_priv) <= 7) |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 4723 | rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; |
Sagar Arun Kamble | 1800ad2 | 2016-05-31 13:58:27 +0530 | [diff] [blame] | 4724 | |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 4725 | if (INTEL_GEN(dev_priv) >= 8) |
Sagar Arun Kamble | 562d9ba | 2017-10-10 22:30:06 +0100 | [diff] [blame] | 4726 | rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; |
Sagar Arun Kamble | 1800ad2 | 2016-05-31 13:58:27 +0530 | [diff] [blame] | 4727 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4728 | if (IS_GEN2(dev_priv)) { |
Rodrigo Vivi | 4194c08 | 2016-08-03 10:00:56 -0700 | [diff] [blame] | 4729 | /* Gen2 doesn't have a hardware frame counter */ |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 4730 | dev->max_vblank_count = 0; |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 4731 | } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4732 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
Ville Syrjälä | fd8f507c | 2015-09-18 20:03:42 +0300 | [diff] [blame] | 4733 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 4734 | } else { |
| 4735 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 4736 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4737 | } |
| 4738 | |
Ville Syrjälä | 21da270 | 2014-08-06 14:49:55 +0300 | [diff] [blame] | 4739 | /* |
| 4740 | * Opt out of the vblank disable timer on everything except gen2. |
| 4741 | * Gen2 doesn't have a hardware frame counter and so depends on |
| 4742 | * vblank interrupts to produce sane vblank seuquence numbers. |
| 4743 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4744 | if (!IS_GEN2(dev_priv)) |
Ville Syrjälä | 21da270 | 2014-08-06 14:49:55 +0300 | [diff] [blame] | 4745 | dev->vblank_disable_immediate = true; |
| 4746 | |
Chris Wilson | 262fd48 | 2017-02-15 13:15:47 +0000 | [diff] [blame] | 4747 | /* Most platforms treat the display irq block as an always-on |
| 4748 | * power domain. vlv/chv can disable it at runtime and need |
| 4749 | * special care to avoid writing any of the display block registers |
| 4750 | * outside of the power domain. We defer setting up the display irqs |
| 4751 | * in this case to the runtime pm. |
| 4752 | */ |
| 4753 | dev_priv->display_irqs_enabled = true; |
| 4754 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 4755 | dev_priv->display_irqs_enabled = false; |
| 4756 | |
Lyude | 317eaa9 | 2017-02-03 21:18:25 -0500 | [diff] [blame] | 4757 | dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; |
| 4758 | |
Daniel Vetter | 1bf6ad6 | 2017-05-09 16:03:28 +0200 | [diff] [blame] | 4759 | dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos; |
Daniel Vetter | f3a5c3f | 2015-02-13 21:03:44 +0100 | [diff] [blame] | 4760 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4761 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4762 | if (IS_CHERRYVIEW(dev_priv)) { |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4763 | dev->driver->irq_handler = cherryview_irq_handler; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4764 | dev->driver->irq_preinstall = cherryview_irq_reset; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4765 | dev->driver->irq_postinstall = cherryview_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4766 | dev->driver->irq_uninstall = cherryview_irq_reset; |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 4767 | dev->driver->enable_vblank = i965_enable_vblank; |
| 4768 | dev->driver->disable_vblank = i965_disable_vblank; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4769 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4770 | } else if (IS_VALLEYVIEW(dev_priv)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4771 | dev->driver->irq_handler = valleyview_irq_handler; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4772 | dev->driver->irq_preinstall = valleyview_irq_reset; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4773 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4774 | dev->driver->irq_uninstall = valleyview_irq_reset; |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 4775 | dev->driver->enable_vblank = i965_enable_vblank; |
| 4776 | dev->driver->disable_vblank = i965_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 4777 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Mika Kuoppala | 51951ae | 2018-02-28 12:11:53 +0200 | [diff] [blame] | 4778 | } else if (INTEL_GEN(dev_priv) >= 11) { |
| 4779 | dev->driver->irq_handler = gen11_irq_handler; |
| 4780 | dev->driver->irq_preinstall = gen11_irq_reset; |
| 4781 | dev->driver->irq_postinstall = gen11_irq_postinstall; |
| 4782 | dev->driver->irq_uninstall = gen11_irq_reset; |
| 4783 | dev->driver->enable_vblank = gen8_enable_vblank; |
| 4784 | dev->driver->disable_vblank = gen8_disable_vblank; |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 4785 | dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; |
Pandiyan, Dhinakaran | bca2bf2 | 2017-07-18 11:28:00 -0700 | [diff] [blame] | 4786 | } else if (INTEL_GEN(dev_priv) >= 8) { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4787 | dev->driver->irq_handler = gen8_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4788 | dev->driver->irq_preinstall = gen8_irq_reset; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4789 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4790 | dev->driver->irq_uninstall = gen8_irq_reset; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4791 | dev->driver->enable_vblank = gen8_enable_vblank; |
| 4792 | dev->driver->disable_vblank = gen8_disable_vblank; |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 4793 | if (IS_GEN9_LP(dev_priv)) |
Shashank Sharma | e0a20ad | 2015-03-27 14:54:14 +0200 | [diff] [blame] | 4794 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
Rodrigo Vivi | 7b22b8c | 2017-06-02 13:06:39 -0700 | [diff] [blame] | 4795 | else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || |
| 4796 | HAS_PCH_CNP(dev_priv)) |
Ville Syrjälä | 6dbf30c | 2015-08-27 23:56:02 +0300 | [diff] [blame] | 4797 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; |
| 4798 | else |
Ville Syrjälä | 3a3b3c7 | 2015-08-27 23:56:06 +0300 | [diff] [blame] | 4799 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 4800 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4801 | dev->driver->irq_handler = ironlake_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4802 | dev->driver->irq_preinstall = ironlake_irq_reset; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4803 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4804 | dev->driver->irq_uninstall = ironlake_irq_reset; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4805 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 4806 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Ville Syrjälä | 23bb4cb | 2015-08-27 23:56:04 +0300 | [diff] [blame] | 4807 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4808 | } else { |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 4809 | if (IS_GEN2(dev_priv)) { |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4810 | dev->driver->irq_preinstall = i8xx_irq_reset; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4811 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 4812 | dev->driver->irq_handler = i8xx_irq_handler; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4813 | dev->driver->irq_uninstall = i8xx_irq_reset; |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 4814 | dev->driver->enable_vblank = i8xx_enable_vblank; |
| 4815 | dev->driver->disable_vblank = i8xx_disable_vblank; |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 4816 | } else if (IS_GEN3(dev_priv)) { |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4817 | dev->driver->irq_preinstall = i915_irq_reset; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4818 | dev->driver->irq_postinstall = i915_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4819 | dev->driver->irq_uninstall = i915_irq_reset; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4820 | dev->driver->irq_handler = i915_irq_handler; |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 4821 | dev->driver->enable_vblank = i8xx_enable_vblank; |
| 4822 | dev->driver->disable_vblank = i8xx_disable_vblank; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4823 | } else { |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4824 | dev->driver->irq_preinstall = i965_irq_reset; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4825 | dev->driver->irq_postinstall = i965_irq_postinstall; |
Ville Syrjälä | 6bcdb1c | 2017-08-18 21:37:04 +0300 | [diff] [blame] | 4826 | dev->driver->irq_uninstall = i965_irq_reset; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4827 | dev->driver->irq_handler = i965_irq_handler; |
Chris Wilson | 86e83e3 | 2016-10-07 20:49:52 +0100 | [diff] [blame] | 4828 | dev->driver->enable_vblank = i965_enable_vblank; |
| 4829 | dev->driver->disable_vblank = i965_disable_vblank; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4830 | } |
Ville Syrjälä | 778eb33 | 2015-01-09 14:21:13 +0200 | [diff] [blame] | 4831 | if (I915_HAS_HOTPLUG(dev_priv)) |
| 4832 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4833 | } |
| 4834 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4835 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4836 | /** |
Joonas Lahtinen | cefcff8 | 2017-04-28 10:58:39 +0300 | [diff] [blame] | 4837 | * intel_irq_fini - deinitializes IRQ support |
| 4838 | * @i915: i915 device instance |
| 4839 | * |
| 4840 | * This function deinitializes all the IRQ support. |
| 4841 | */ |
| 4842 | void intel_irq_fini(struct drm_i915_private *i915) |
| 4843 | { |
| 4844 | int i; |
| 4845 | |
| 4846 | for (i = 0; i < MAX_L3_SLICES; ++i) |
| 4847 | kfree(i915->l3_parity.remap_info[i]); |
| 4848 | } |
| 4849 | |
| 4850 | /** |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4851 | * intel_irq_install - enables the hardware interrupt |
| 4852 | * @dev_priv: i915 device instance |
| 4853 | * |
| 4854 | * This function enables the hardware interrupt handling, but leaves the hotplug |
| 4855 | * handling still disabled. It is called after intel_irq_init(). |
| 4856 | * |
| 4857 | * In the driver load and resume code we need working interrupts in a few places |
| 4858 | * but don't want to deal with the hassle of concurrent probe and hotplug |
| 4859 | * workers. Hence the split into this two-stage approach. |
| 4860 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4861 | int intel_irq_install(struct drm_i915_private *dev_priv) |
| 4862 | { |
| 4863 | /* |
| 4864 | * We enable some interrupt sources in our postinstall hooks, so mark |
| 4865 | * interrupts as enabled _before_ actually enabling them to avoid |
| 4866 | * special cases in our ordering checks. |
| 4867 | */ |
Sagar Arun Kamble | ad1443f | 2017-10-10 22:30:04 +0100 | [diff] [blame] | 4868 | dev_priv->runtime_pm.irqs_enabled = true; |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4869 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4870 | return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq); |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4871 | } |
| 4872 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4873 | /** |
| 4874 | * intel_irq_uninstall - finilizes all irq handling |
| 4875 | * @dev_priv: i915 device instance |
| 4876 | * |
| 4877 | * This stops interrupt and hotplug handling and unregisters and frees all |
| 4878 | * resources acquired in the init functions. |
| 4879 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4880 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
| 4881 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4882 | drm_irq_uninstall(&dev_priv->drm); |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4883 | intel_hpd_cancel_work(dev_priv); |
Sagar Arun Kamble | ad1443f | 2017-10-10 22:30:04 +0100 | [diff] [blame] | 4884 | dev_priv->runtime_pm.irqs_enabled = false; |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4885 | } |
| 4886 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4887 | /** |
| 4888 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling |
| 4889 | * @dev_priv: i915 device instance |
| 4890 | * |
| 4891 | * This function is used to disable interrupts at runtime, both in the runtime |
| 4892 | * pm and the system suspend/resume code. |
| 4893 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4894 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4895 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4896 | dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); |
Sagar Arun Kamble | ad1443f | 2017-10-10 22:30:04 +0100 | [diff] [blame] | 4897 | dev_priv->runtime_pm.irqs_enabled = false; |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4898 | synchronize_irq(dev_priv->drm.irq); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4899 | } |
| 4900 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4901 | /** |
| 4902 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling |
| 4903 | * @dev_priv: i915 device instance |
| 4904 | * |
| 4905 | * This function is used to enable interrupts at runtime, both in the runtime |
| 4906 | * pm and the system suspend/resume code. |
| 4907 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4908 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4909 | { |
Sagar Arun Kamble | ad1443f | 2017-10-10 22:30:04 +0100 | [diff] [blame] | 4910 | dev_priv->runtime_pm.irqs_enabled = true; |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 4911 | dev_priv->drm.driver->irq_preinstall(&dev_priv->drm); |
| 4912 | dev_priv->drm.driver->irq_postinstall(&dev_priv->drm); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4913 | } |