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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
Paul Mackerras14cf11a2005-09-26 16:04:21 +10002 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
Paul Mackerras14cf11a2005-09-26 16:04:21 +100017#include <linux/errno.h>
18#include <linux/sched.h>
Ingo Molnarb17b0152017-02-08 18:51:35 +010019#include <linux/sched/debug.h>
Ingo Molnar29930022017-02-08 18:51:36 +010020#include <linux/sched/task.h>
Ingo Molnar68db0cf2017-02-08 18:51:37 +010021#include <linux/sched/task_stack.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100022#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/smp.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100025#include <linux/stddef.h>
26#include <linux/unistd.h>
27#include <linux/ptrace.h>
28#include <linux/slab.h>
29#include <linux/user.h>
30#include <linux/elf.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100031#include <linux/prctl.h>
32#include <linux/init_task.h>
Paul Gortmaker4b16f8e2011-07-22 18:24:23 -040033#include <linux/export.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100034#include <linux/kallsyms.h>
35#include <linux/mqueue.h>
36#include <linux/hardirq.h>
Paul Mackerras06d67d52005-10-10 22:29:05 +100037#include <linux/utsname.h>
Steven Rostedt6794c782009-02-09 21:10:27 -080038#include <linux/ftrace.h>
Martin Schwidefsky79741dd2008-12-31 15:11:38 +010039#include <linux/kernel_stat.h>
Anton Blanchardd8390882009-02-22 01:50:03 +000040#include <linux/personality.h>
41#include <linux/random.h>
K.Prasad5aae8a52010-06-15 11:35:19 +053042#include <linux/hw_breakpoint.h>
Anton Blanchard7b051f62014-10-13 20:27:15 +110043#include <linux/uaccess.h>
Daniel Axtens7f92bc52016-01-06 11:45:51 +110044#include <linux/elf-randomize.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100045
46#include <asm/pgtable.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100047#include <asm/io.h>
48#include <asm/processor.h>
49#include <asm/mmu.h>
50#include <asm/prom.h>
Michael Ellerman76032de2005-11-07 13:12:03 +110051#include <asm/machdep.h>
Paul Mackerrasc6622f62006-02-24 10:06:59 +110052#include <asm/time.h>
David Howellsae3a1972012-03-28 18:30:02 +010053#include <asm/runlatch.h>
Arnd Bergmanna7f31842006-03-23 00:00:08 +010054#include <asm/syscalls.h>
David Howellsae3a1972012-03-28 18:30:02 +010055#include <asm/switch_to.h>
Michael Neulingfb096922013-02-13 16:21:37 +000056#include <asm/tm.h>
David Howellsae3a1972012-03-28 18:30:02 +010057#include <asm/debug.h>
Paul Mackerras06d67d52005-10-10 22:29:05 +100058#ifdef CONFIG_PPC64
59#include <asm/firmware.h>
Paul Mackerras06d67d52005-10-10 22:29:05 +100060#endif
Anton Blanchard7cedd602014-02-04 16:08:51 +110061#include <asm/code-patching.h>
Daniel Axtens7f92bc52016-01-06 11:45:51 +110062#include <asm/exec.h>
Michael Ellerman5d31a962016-03-24 22:04:04 +110063#include <asm/livepatch.h>
Kevin Haob92a2262016-07-23 14:42:40 +053064#include <asm/cpu_has_feature.h>
Daniel Axtens0545d542016-09-06 15:32:43 +100065#include <asm/asm-prototypes.h>
Michael Ellerman5d31a962016-03-24 22:04:04 +110066
Luis Machadod6a61bf2008-07-24 02:10:41 +100067#include <linux/kprobes.h>
68#include <linux/kdebug.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100069
Michael Neuling8b3c34c2013-02-13 16:21:32 +000070/* Transactional Memory debug */
71#ifdef TM_DEBUG_SW
72#define TM_DEBUG(x...) printk(KERN_INFO x)
73#else
74#define TM_DEBUG(x...) do { } while(0)
75#endif
76
Paul Mackerras14cf11a2005-09-26 16:04:21 +100077extern unsigned long _get_SP(void);
78
Paul Mackerrasd31626f2014-01-13 15:56:29 +110079#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Anton Blanchardb86fd2b2015-10-29 11:43:58 +110080static void check_if_tm_restore_required(struct task_struct *tsk)
Paul Mackerrasd31626f2014-01-13 15:56:29 +110081{
82 /*
83 * If we are saving the current thread's registers, and the
84 * thread is in a transactional state, set the TIF_RESTORE_TM
85 * bit so that we know to restore the registers before
86 * returning to userspace.
87 */
88 if (tsk == current && tsk->thread.regs &&
89 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
90 !test_thread_flag(TIF_RESTORE_TM)) {
Anshuman Khandual829023d2015-07-06 16:24:10 +053091 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
Paul Mackerrasd31626f2014-01-13 15:56:29 +110092 set_thread_flag(TIF_RESTORE_TM);
93 }
Paul Mackerrasd31626f2014-01-13 15:56:29 +110094}
Cyril Burdc16b552016-09-23 16:18:08 +100095
96static inline bool msr_tm_active(unsigned long msr)
97{
98 return MSR_TM_ACTIVE(msr);
99}
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100100#else
Cyril Burdc16b552016-09-23 16:18:08 +1000101static inline bool msr_tm_active(unsigned long msr) { return false; }
Anton Blanchardb86fd2b2015-10-29 11:43:58 +1100102static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100103#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
104
Anton Blanchard3eb5d582015-10-29 11:44:06 +1100105bool strict_msr_control;
106EXPORT_SYMBOL(strict_msr_control);
107
108static int __init enable_strict_msr_control(char *str)
109{
110 strict_msr_control = true;
111 pr_info("Enabling strict facility control\n");
112
113 return 0;
114}
115early_param("ppc_strict_facility_enable", enable_strict_msr_control);
116
Cyril Bur3cee0702016-09-23 16:18:10 +1000117unsigned long msr_check_and_set(unsigned long bits)
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100118{
119 unsigned long oldmsr = mfmsr();
120 unsigned long newmsr;
121
122 newmsr = oldmsr | bits;
123
124#ifdef CONFIG_VSX
125 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
126 newmsr |= MSR_VSX;
127#endif
128
129 if (oldmsr != newmsr)
130 mtmsr_isync(newmsr);
Cyril Bur3cee0702016-09-23 16:18:10 +1000131
132 return newmsr;
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100133}
134
Anton Blanchard3eb5d582015-10-29 11:44:06 +1100135void __msr_check_and_clear(unsigned long bits)
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100136{
137 unsigned long oldmsr = mfmsr();
138 unsigned long newmsr;
139
140 newmsr = oldmsr & ~bits;
141
142#ifdef CONFIG_VSX
143 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
144 newmsr &= ~MSR_VSX;
145#endif
146
147 if (oldmsr != newmsr)
148 mtmsr_isync(newmsr);
149}
Anton Blanchard3eb5d582015-10-29 11:44:06 +1100150EXPORT_SYMBOL(__msr_check_and_clear);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100151
Kevin Hao037f0ee2013-07-14 17:02:05 +0800152#ifdef CONFIG_PPC_FPU
Cyril Bur87924682016-02-29 17:53:49 +1100153void __giveup_fpu(struct task_struct *tsk)
154{
Anton Blanchard8eb98032016-05-29 22:03:50 +1000155 unsigned long msr;
156
Cyril Bur87924682016-02-29 17:53:49 +1100157 save_fpu(tsk);
Anton Blanchard8eb98032016-05-29 22:03:50 +1000158 msr = tsk->thread.regs->msr;
159 msr &= ~MSR_FP;
Cyril Bur87924682016-02-29 17:53:49 +1100160#ifdef CONFIG_VSX
161 if (cpu_has_feature(CPU_FTR_VSX))
Anton Blanchard8eb98032016-05-29 22:03:50 +1000162 msr &= ~MSR_VSX;
Cyril Bur87924682016-02-29 17:53:49 +1100163#endif
Anton Blanchard8eb98032016-05-29 22:03:50 +1000164 tsk->thread.regs->msr = msr;
Cyril Bur87924682016-02-29 17:53:49 +1100165}
166
Anton Blanchard98da5812015-10-29 11:44:01 +1100167void giveup_fpu(struct task_struct *tsk)
168{
Anton Blanchard98da5812015-10-29 11:44:01 +1100169 check_if_tm_restore_required(tsk);
170
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100171 msr_check_and_set(MSR_FP);
Anton Blanchard98da5812015-10-29 11:44:01 +1100172 __giveup_fpu(tsk);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100173 msr_check_and_clear(MSR_FP);
Anton Blanchard98da5812015-10-29 11:44:01 +1100174}
175EXPORT_SYMBOL(giveup_fpu);
176
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000177/*
178 * Make sure the floating-point register state in the
179 * the thread_struct is up to date for task tsk.
180 */
181void flush_fp_to_thread(struct task_struct *tsk)
182{
183 if (tsk->thread.regs) {
184 /*
185 * We need to disable preemption here because if we didn't,
186 * another process could get scheduled after the regs->msr
187 * test but before we have finished saving the FP registers
188 * to the thread_struct. That process could take over the
189 * FPU, and then when we get scheduled again we would store
190 * bogus values for the remaining FP registers.
191 */
192 preempt_disable();
193 if (tsk->thread.regs->msr & MSR_FP) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000194 /*
195 * This should only ever be called for current or
196 * for a stopped child process. Since we save away
Anton Blanchardaf1bbc32015-10-29 11:43:57 +1100197 * the FP register state on context switch,
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000198 * there is something wrong if a stopped child appears
199 * to still have its FP state in the CPU registers.
200 */
201 BUG_ON(tsk != current);
Anton Blanchardb86fd2b2015-10-29 11:43:58 +1100202 giveup_fpu(tsk);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000203 }
204 preempt_enable();
205 }
206}
Paul Mackerrasde56a942011-06-29 00:21:34 +0000207EXPORT_SYMBOL_GPL(flush_fp_to_thread);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000208
209void enable_kernel_fp(void)
210{
Cyril Bure909fb82016-09-23 16:18:11 +1000211 unsigned long cpumsr;
212
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000213 WARN_ON(preemptible());
214
Cyril Bure909fb82016-09-23 16:18:11 +1000215 cpumsr = msr_check_and_set(MSR_FP);
Anton Blanchard611b0e52015-10-29 11:43:59 +1100216
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100217 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
218 check_if_tm_restore_required(current);
Cyril Bure909fb82016-09-23 16:18:11 +1000219 /*
220 * If a thread has already been reclaimed then the
221 * checkpointed registers are on the CPU but have definitely
222 * been saved by the reclaim code. Don't need to and *cannot*
223 * giveup as this would save to the 'live' structure not the
224 * checkpointed structure.
225 */
226 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
227 return;
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100228 __giveup_fpu(current);
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100229 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000230}
231EXPORT_SYMBOL(enable_kernel_fp);
Cyril Bur70fe3d92016-02-29 17:53:47 +1100232
Benjamin Herrenschmidt6a303832017-08-16 16:01:15 +1000233static int restore_fp(struct task_struct *tsk)
234{
Cyril Burdc16b552016-09-23 16:18:08 +1000235 if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
Cyril Bur70fe3d92016-02-29 17:53:47 +1100236 load_fp_state(&current->thread.fp_state);
237 current->thread.load_fp++;
238 return 1;
239 }
240 return 0;
241}
242#else
243static int restore_fp(struct task_struct *tsk) { return 0; }
Anton Blanchardd1e1cf22015-10-29 11:44:11 +1100244#endif /* CONFIG_PPC_FPU */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000245
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000246#ifdef CONFIG_ALTIVEC
Cyril Bur70fe3d92016-02-29 17:53:47 +1100247#define loadvec(thr) ((thr).load_vec)
248
Cyril Bur6f515d82016-02-29 17:53:50 +1100249static void __giveup_altivec(struct task_struct *tsk)
250{
Anton Blanchard8eb98032016-05-29 22:03:50 +1000251 unsigned long msr;
252
Cyril Bur6f515d82016-02-29 17:53:50 +1100253 save_altivec(tsk);
Anton Blanchard8eb98032016-05-29 22:03:50 +1000254 msr = tsk->thread.regs->msr;
255 msr &= ~MSR_VEC;
Cyril Bur6f515d82016-02-29 17:53:50 +1100256#ifdef CONFIG_VSX
257 if (cpu_has_feature(CPU_FTR_VSX))
Anton Blanchard8eb98032016-05-29 22:03:50 +1000258 msr &= ~MSR_VSX;
Cyril Bur6f515d82016-02-29 17:53:50 +1100259#endif
Anton Blanchard8eb98032016-05-29 22:03:50 +1000260 tsk->thread.regs->msr = msr;
Cyril Bur6f515d82016-02-29 17:53:50 +1100261}
262
Anton Blanchard98da5812015-10-29 11:44:01 +1100263void giveup_altivec(struct task_struct *tsk)
264{
Anton Blanchard98da5812015-10-29 11:44:01 +1100265 check_if_tm_restore_required(tsk);
266
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100267 msr_check_and_set(MSR_VEC);
Anton Blanchard98da5812015-10-29 11:44:01 +1100268 __giveup_altivec(tsk);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100269 msr_check_and_clear(MSR_VEC);
Anton Blanchard98da5812015-10-29 11:44:01 +1100270}
271EXPORT_SYMBOL(giveup_altivec);
272
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000273void enable_kernel_altivec(void)
274{
Cyril Bure909fb82016-09-23 16:18:11 +1000275 unsigned long cpumsr;
276
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000277 WARN_ON(preemptible());
278
Cyril Bure909fb82016-09-23 16:18:11 +1000279 cpumsr = msr_check_and_set(MSR_VEC);
Anton Blanchard611b0e52015-10-29 11:43:59 +1100280
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100281 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
282 check_if_tm_restore_required(current);
Cyril Bure909fb82016-09-23 16:18:11 +1000283 /*
284 * If a thread has already been reclaimed then the
285 * checkpointed registers are on the CPU but have definitely
286 * been saved by the reclaim code. Don't need to and *cannot*
287 * giveup as this would save to the 'live' structure not the
288 * checkpointed structure.
289 */
290 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
291 return;
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100292 __giveup_altivec(current);
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100293 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000294}
295EXPORT_SYMBOL(enable_kernel_altivec);
296
297/*
298 * Make sure the VMX/Altivec register state in the
299 * the thread_struct is up to date for task tsk.
300 */
301void flush_altivec_to_thread(struct task_struct *tsk)
302{
303 if (tsk->thread.regs) {
304 preempt_disable();
305 if (tsk->thread.regs->msr & MSR_VEC) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000306 BUG_ON(tsk != current);
Anton Blanchardb86fd2b2015-10-29 11:43:58 +1100307 giveup_altivec(tsk);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000308 }
309 preempt_enable();
310 }
311}
Paul Mackerrasde56a942011-06-29 00:21:34 +0000312EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
Cyril Bur70fe3d92016-02-29 17:53:47 +1100313
314static int restore_altivec(struct task_struct *tsk)
315{
Cyril Burdc16b552016-09-23 16:18:08 +1000316 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
317 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
Cyril Bur70fe3d92016-02-29 17:53:47 +1100318 load_vr_state(&tsk->thread.vr_state);
319 tsk->thread.used_vr = 1;
320 tsk->thread.load_vec++;
321
322 return 1;
323 }
324 return 0;
325}
326#else
327#define loadvec(thr) 0
328static inline int restore_altivec(struct task_struct *tsk) { return 0; }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000329#endif /* CONFIG_ALTIVEC */
330
Michael Neulingce48b212008-06-25 14:07:18 +1000331#ifdef CONFIG_VSX
Cyril Burbf6a4d52016-02-29 17:53:51 +1100332static void __giveup_vsx(struct task_struct *tsk)
Anton Blancharda7d623d2015-10-29 11:44:02 +1100333{
Anton Blancharda7d623d2015-10-29 11:44:02 +1100334 if (tsk->thread.regs->msr & MSR_FP)
335 __giveup_fpu(tsk);
336 if (tsk->thread.regs->msr & MSR_VEC)
337 __giveup_altivec(tsk);
Cyril Burbf6a4d52016-02-29 17:53:51 +1100338 tsk->thread.regs->msr &= ~MSR_VSX;
339}
340
341static void giveup_vsx(struct task_struct *tsk)
342{
343 check_if_tm_restore_required(tsk);
344
345 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
Anton Blancharda7d623d2015-10-29 11:44:02 +1100346 __giveup_vsx(tsk);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100347 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
Anton Blancharda7d623d2015-10-29 11:44:02 +1100348}
Cyril Burbf6a4d52016-02-29 17:53:51 +1100349
350static void save_vsx(struct task_struct *tsk)
351{
352 if (tsk->thread.regs->msr & MSR_FP)
353 save_fpu(tsk);
354 if (tsk->thread.regs->msr & MSR_VEC)
355 save_altivec(tsk);
356}
Anton Blancharda7d623d2015-10-29 11:44:02 +1100357
Michael Neulingce48b212008-06-25 14:07:18 +1000358void enable_kernel_vsx(void)
359{
Cyril Bure909fb82016-09-23 16:18:11 +1000360 unsigned long cpumsr;
361
Michael Neulingce48b212008-06-25 14:07:18 +1000362 WARN_ON(preemptible());
363
Cyril Bure909fb82016-09-23 16:18:11 +1000364 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
Anton Blanchard611b0e52015-10-29 11:43:59 +1100365
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100366 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100367 check_if_tm_restore_required(current);
Cyril Bure909fb82016-09-23 16:18:11 +1000368 /*
369 * If a thread has already been reclaimed then the
370 * checkpointed registers are on the CPU but have definitely
371 * been saved by the reclaim code. Don't need to and *cannot*
372 * giveup as this would save to the 'live' structure not the
373 * checkpointed structure.
374 */
375 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
376 return;
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100377 if (current->thread.regs->msr & MSR_FP)
378 __giveup_fpu(current);
379 if (current->thread.regs->msr & MSR_VEC)
380 __giveup_altivec(current);
381 __giveup_vsx(current);
Anton Blanchard611b0e52015-10-29 11:43:59 +1100382 }
Michael Neulingce48b212008-06-25 14:07:18 +1000383}
384EXPORT_SYMBOL(enable_kernel_vsx);
Michael Neulingce48b212008-06-25 14:07:18 +1000385
386void flush_vsx_to_thread(struct task_struct *tsk)
387{
388 if (tsk->thread.regs) {
389 preempt_disable();
390 if (tsk->thread.regs->msr & MSR_VSX) {
Michael Neulingce48b212008-06-25 14:07:18 +1000391 BUG_ON(tsk != current);
Michael Neulingce48b212008-06-25 14:07:18 +1000392 giveup_vsx(tsk);
393 }
394 preempt_enable();
395 }
396}
Paul Mackerrasde56a942011-06-29 00:21:34 +0000397EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
Cyril Bur70fe3d92016-02-29 17:53:47 +1100398
399static int restore_vsx(struct task_struct *tsk)
400{
401 if (cpu_has_feature(CPU_FTR_VSX)) {
402 tsk->thread.used_vsr = 1;
403 return 1;
404 }
405
406 return 0;
407}
408#else
409static inline int restore_vsx(struct task_struct *tsk) { return 0; }
Cyril Burbf6a4d52016-02-29 17:53:51 +1100410static inline void save_vsx(struct task_struct *tsk) { }
Michael Neulingce48b212008-06-25 14:07:18 +1000411#endif /* CONFIG_VSX */
412
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000413#ifdef CONFIG_SPE
Anton Blanchard98da5812015-10-29 11:44:01 +1100414void giveup_spe(struct task_struct *tsk)
415{
Anton Blanchard98da5812015-10-29 11:44:01 +1100416 check_if_tm_restore_required(tsk);
417
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100418 msr_check_and_set(MSR_SPE);
Anton Blanchard98da5812015-10-29 11:44:01 +1100419 __giveup_spe(tsk);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100420 msr_check_and_clear(MSR_SPE);
Anton Blanchard98da5812015-10-29 11:44:01 +1100421}
422EXPORT_SYMBOL(giveup_spe);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000423
424void enable_kernel_spe(void)
425{
426 WARN_ON(preemptible());
427
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100428 msr_check_and_set(MSR_SPE);
Anton Blanchard611b0e52015-10-29 11:43:59 +1100429
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100430 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
431 check_if_tm_restore_required(current);
Anton Blancharda0e72cf2015-10-29 11:44:04 +1100432 __giveup_spe(current);
Anton Blanchardd64d02c2015-12-10 20:04:05 +1100433 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000434}
435EXPORT_SYMBOL(enable_kernel_spe);
436
437void flush_spe_to_thread(struct task_struct *tsk)
438{
439 if (tsk->thread.regs) {
440 preempt_disable();
441 if (tsk->thread.regs->msr & MSR_SPE) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000442 BUG_ON(tsk != current);
yu liu685659e2011-06-14 18:34:25 -0500443 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
Kumar Gala0ee6c152007-08-28 21:15:53 -0500444 giveup_spe(tsk);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000445 }
446 preempt_enable();
447 }
448}
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000449#endif /* CONFIG_SPE */
450
Anton Blanchardc2085052015-10-29 11:44:08 +1100451static unsigned long msr_all_available;
452
453static int __init init_msr_all_available(void)
454{
455#ifdef CONFIG_PPC_FPU
456 msr_all_available |= MSR_FP;
457#endif
458#ifdef CONFIG_ALTIVEC
459 if (cpu_has_feature(CPU_FTR_ALTIVEC))
460 msr_all_available |= MSR_VEC;
461#endif
462#ifdef CONFIG_VSX
463 if (cpu_has_feature(CPU_FTR_VSX))
464 msr_all_available |= MSR_VSX;
465#endif
466#ifdef CONFIG_SPE
467 if (cpu_has_feature(CPU_FTR_SPE))
468 msr_all_available |= MSR_SPE;
469#endif
470
471 return 0;
472}
473early_initcall(init_msr_all_available);
474
475void giveup_all(struct task_struct *tsk)
476{
477 unsigned long usermsr;
478
479 if (!tsk->thread.regs)
480 return;
481
482 usermsr = tsk->thread.regs->msr;
483
484 if ((usermsr & msr_all_available) == 0)
485 return;
486
487 msr_check_and_set(msr_all_available);
Cyril Burb0f16b42016-09-23 16:18:09 +1000488 check_if_tm_restore_required(tsk);
Anton Blanchardc2085052015-10-29 11:44:08 +1100489
490#ifdef CONFIG_PPC_FPU
491 if (usermsr & MSR_FP)
492 __giveup_fpu(tsk);
493#endif
494#ifdef CONFIG_ALTIVEC
495 if (usermsr & MSR_VEC)
496 __giveup_altivec(tsk);
497#endif
498#ifdef CONFIG_VSX
499 if (usermsr & MSR_VSX)
500 __giveup_vsx(tsk);
501#endif
502#ifdef CONFIG_SPE
503 if (usermsr & MSR_SPE)
504 __giveup_spe(tsk);
505#endif
506
507 msr_check_and_clear(msr_all_available);
508}
509EXPORT_SYMBOL(giveup_all);
510
Cyril Bur70fe3d92016-02-29 17:53:47 +1100511void restore_math(struct pt_regs *regs)
512{
513 unsigned long msr;
514
Nicholas Pigginbc4f65e2017-06-09 01:35:05 +1000515 /*
516 * Syscall exit makes a similar initial check before branching
517 * to restore_math. Keep them in synch.
518 */
Cyril Burdc16b552016-09-23 16:18:08 +1000519 if (!msr_tm_active(regs->msr) &&
520 !current->thread.load_fp && !loadvec(current->thread))
Cyril Bur70fe3d92016-02-29 17:53:47 +1100521 return;
522
523 msr = regs->msr;
524 msr_check_and_set(msr_all_available);
525
526 /*
527 * Only reload if the bit is not set in the user MSR, the bit BEING set
528 * indicates that the registers are hot
529 */
530 if ((!(msr & MSR_FP)) && restore_fp(current))
531 msr |= MSR_FP | current->thread.fpexc_mode;
532
533 if ((!(msr & MSR_VEC)) && restore_altivec(current))
534 msr |= MSR_VEC;
535
536 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
537 restore_vsx(current)) {
538 msr |= MSR_VSX;
539 }
540
541 msr_check_and_clear(msr_all_available);
542
543 regs->msr = msr;
544}
545
Cyril Burde2a20a2016-02-29 17:53:48 +1100546void save_all(struct task_struct *tsk)
547{
548 unsigned long usermsr;
549
550 if (!tsk->thread.regs)
551 return;
552
553 usermsr = tsk->thread.regs->msr;
554
555 if ((usermsr & msr_all_available) == 0)
556 return;
557
558 msr_check_and_set(msr_all_available);
559
Cyril Burbf6a4d52016-02-29 17:53:51 +1100560 /*
561 * Saving the way the register space is in hardware, save_vsx boils
562 * down to a save_fpu() and save_altivec()
563 */
564 if (usermsr & MSR_VSX) {
565 save_vsx(tsk);
566 } else {
567 if (usermsr & MSR_FP)
568 save_fpu(tsk);
Cyril Burde2a20a2016-02-29 17:53:48 +1100569
Cyril Burbf6a4d52016-02-29 17:53:51 +1100570 if (usermsr & MSR_VEC)
571 save_altivec(tsk);
572 }
Cyril Burde2a20a2016-02-29 17:53:48 +1100573
574 if (usermsr & MSR_SPE)
575 __giveup_spe(tsk);
576
577 msr_check_and_clear(msr_all_available);
578}
579
Anton Blanchard579e6332015-10-29 11:44:09 +1100580void flush_all_to_thread(struct task_struct *tsk)
581{
582 if (tsk->thread.regs) {
583 preempt_disable();
584 BUG_ON(tsk != current);
Cyril Burde2a20a2016-02-29 17:53:48 +1100585 save_all(tsk);
Anton Blanchard579e6332015-10-29 11:44:09 +1100586
587#ifdef CONFIG_SPE
588 if (tsk->thread.regs->msr & MSR_SPE)
589 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
590#endif
591
592 preempt_enable();
593 }
594}
595EXPORT_SYMBOL(flush_all_to_thread);
596
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000597#ifdef CONFIG_PPC_ADV_DEBUG_REGS
598void do_send_trap(struct pt_regs *regs, unsigned long address,
599 unsigned long error_code, int signal_code, int breakpt)
600{
601 siginfo_t info;
602
Ananth N Mavinakayanahalli41ab5262012-08-23 21:27:09 +0000603 current->thread.trap_nr = signal_code;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000604 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
605 11, SIGSEGV) == NOTIFY_STOP)
606 return;
607
608 /* Deliver the signal to userspace */
609 info.si_signo = SIGTRAP;
610 info.si_errno = breakpt; /* breakpoint or watchpoint id */
611 info.si_code = signal_code;
612 info.si_addr = (void __user *)address;
613 force_sig_info(SIGTRAP, &info, current);
614}
615#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
Michael Neuling9422de32012-12-20 14:06:44 +0000616void do_break (struct pt_regs *regs, unsigned long address,
Luis Machadod6a61bf2008-07-24 02:10:41 +1000617 unsigned long error_code)
618{
619 siginfo_t info;
620
Ananth N Mavinakayanahalli41ab5262012-08-23 21:27:09 +0000621 current->thread.trap_nr = TRAP_HWBKPT;
Luis Machadod6a61bf2008-07-24 02:10:41 +1000622 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
623 11, SIGSEGV) == NOTIFY_STOP)
624 return;
625
Michael Neuling9422de32012-12-20 14:06:44 +0000626 if (debugger_break_match(regs))
Luis Machadod6a61bf2008-07-24 02:10:41 +1000627 return;
628
Michael Neuling9422de32012-12-20 14:06:44 +0000629 /* Clear the breakpoint */
630 hw_breakpoint_disable();
Luis Machadod6a61bf2008-07-24 02:10:41 +1000631
632 /* Deliver the signal to userspace */
633 info.si_signo = SIGTRAP;
634 info.si_errno = 0;
635 info.si_code = TRAP_HWBKPT;
636 info.si_addr = (void __user *)address;
637 force_sig_info(SIGTRAP, &info, current);
638}
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000639#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
Luis Machadod6a61bf2008-07-24 02:10:41 +1000640
Michael Neuling9422de32012-12-20 14:06:44 +0000641static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
Michael Ellermana2ceff52008-03-28 19:11:48 +1100642
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000643#ifdef CONFIG_PPC_ADV_DEBUG_REGS
644/*
645 * Set the debug registers back to their default "safe" values.
646 */
647static void set_debug_reg_defaults(struct thread_struct *thread)
648{
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530649 thread->debug.iac1 = thread->debug.iac2 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000650#if CONFIG_PPC_ADV_DEBUG_IACS > 2
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530651 thread->debug.iac3 = thread->debug.iac4 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000652#endif
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530653 thread->debug.dac1 = thread->debug.dac2 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000654#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530655 thread->debug.dvc1 = thread->debug.dvc2 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000656#endif
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530657 thread->debug.dbcr0 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000658#ifdef CONFIG_BOOKE
659 /*
660 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
661 */
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530662 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000663 DBCR1_IAC3US | DBCR1_IAC4US;
664 /*
665 * Force Data Address Compare User/Supervisor bits to be User-only
666 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
667 */
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530668 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000669#else
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530670 thread->debug.dbcr1 = 0;
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000671#endif
672}
673
Scott Woodf5f97212013-11-22 15:52:29 -0600674static void prime_debug_regs(struct debug_reg *debug)
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000675{
Scott Wood6cecf762013-05-13 14:14:53 +0000676 /*
677 * We could have inherited MSR_DE from userspace, since
678 * it doesn't get cleared on exception entry. Make sure
679 * MSR_DE is clear before we enable any debug events.
680 */
681 mtmsr(mfmsr() & ~MSR_DE);
682
Scott Woodf5f97212013-11-22 15:52:29 -0600683 mtspr(SPRN_IAC1, debug->iac1);
684 mtspr(SPRN_IAC2, debug->iac2);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000685#if CONFIG_PPC_ADV_DEBUG_IACS > 2
Scott Woodf5f97212013-11-22 15:52:29 -0600686 mtspr(SPRN_IAC3, debug->iac3);
687 mtspr(SPRN_IAC4, debug->iac4);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000688#endif
Scott Woodf5f97212013-11-22 15:52:29 -0600689 mtspr(SPRN_DAC1, debug->dac1);
690 mtspr(SPRN_DAC2, debug->dac2);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000691#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
Scott Woodf5f97212013-11-22 15:52:29 -0600692 mtspr(SPRN_DVC1, debug->dvc1);
693 mtspr(SPRN_DVC2, debug->dvc2);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000694#endif
Scott Woodf5f97212013-11-22 15:52:29 -0600695 mtspr(SPRN_DBCR0, debug->dbcr0);
696 mtspr(SPRN_DBCR1, debug->dbcr1);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000697#ifdef CONFIG_BOOKE
Scott Woodf5f97212013-11-22 15:52:29 -0600698 mtspr(SPRN_DBCR2, debug->dbcr2);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000699#endif
700}
701/*
702 * Unless neither the old or new thread are making use of the
703 * debug registers, set the debug registers from the values
704 * stored in the new thread.
705 */
Scott Woodf5f97212013-11-22 15:52:29 -0600706void switch_booke_debug_regs(struct debug_reg *new_debug)
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000707{
Bharat Bhushan51ae8d42013-07-04 11:45:46 +0530708 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
Scott Woodf5f97212013-11-22 15:52:29 -0600709 || (new_debug->dbcr0 & DBCR0_IDM))
710 prime_debug_regs(new_debug);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000711}
Bharat Bhushan3743c9b2013-07-04 12:27:44 +0530712EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000713#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
K.Prasade0780b72011-02-10 04:44:35 +0000714#ifndef CONFIG_HAVE_HW_BREAKPOINT
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000715static void set_debug_reg_defaults(struct thread_struct *thread)
716{
Michael Neuling9422de32012-12-20 14:06:44 +0000717 thread->hw_brk.address = 0;
718 thread->hw_brk.type = 0;
Michael Neulingb9818c32013-01-10 14:25:34 +0000719 set_breakpoint(&thread->hw_brk);
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000720}
K.Prasade0780b72011-02-10 04:44:35 +0000721#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
Dave Kleikamp3bffb652010-02-08 11:51:18 +0000722#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
723
Dave Kleikamp172ae2e2010-02-08 11:50:57 +0000724#ifdef CONFIG_PPC_ADV_DEBUG_REGS
Michael Neuling9422de32012-12-20 14:06:44 +0000725static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
726{
Benjamin Herrenschmidtc6c9eac2009-09-08 14:16:58 +0000727 mtspr(SPRN_DAC1, dabr);
Dave Kleikamp221c1852010-03-05 10:43:24 +0000728#ifdef CONFIG_PPC_47x
729 isync();
730#endif
Michael Neuling9422de32012-12-20 14:06:44 +0000731 return 0;
732}
Benjamin Herrenschmidtc6c9eac2009-09-08 14:16:58 +0000733#elif defined(CONFIG_PPC_BOOK3S)
Michael Neuling9422de32012-12-20 14:06:44 +0000734static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
735{
Michael Ellermancab0af92005-11-03 15:30:49 +1100736 mtspr(SPRN_DABR, dabr);
Michael Neuling82a9f162013-05-16 20:27:31 +0000737 if (cpu_has_feature(CPU_FTR_DABRX))
738 mtspr(SPRN_DABRX, dabrx);
Michael Ellermancab0af92005-11-03 15:30:49 +1100739 return 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000740}
Christophe Leroy4ad86222016-11-29 09:52:15 +0100741#elif defined(CONFIG_PPC_8xx)
742static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
743{
744 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
745 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
746 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
747
748 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
749 lctrl1 |= 0xa0000;
750 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
751 lctrl1 |= 0xf0000;
752 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
753 lctrl2 = 0;
754
755 mtspr(SPRN_LCTRL2, 0);
756 mtspr(SPRN_CMPE, addr);
757 mtspr(SPRN_CMPF, addr + 4);
758 mtspr(SPRN_LCTRL1, lctrl1);
759 mtspr(SPRN_LCTRL2, lctrl2);
760
761 return 0;
762}
Michael Neuling9422de32012-12-20 14:06:44 +0000763#else
764static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
765{
766 return -EINVAL;
767}
768#endif
769
770static inline int set_dabr(struct arch_hw_breakpoint *brk)
771{
772 unsigned long dabr, dabrx;
773
774 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
775 dabrx = ((brk->type >> 3) & 0x7);
776
777 if (ppc_md.set_dabr)
778 return ppc_md.set_dabr(dabr, dabrx);
779
780 return __set_dabr(dabr, dabrx);
781}
782
Michael Neulingbf99de32012-12-20 14:06:45 +0000783static inline int set_dawr(struct arch_hw_breakpoint *brk)
784{
Michael Neuling05d694e2013-01-24 15:02:58 +0000785 unsigned long dawr, dawrx, mrd;
Michael Neulingbf99de32012-12-20 14:06:45 +0000786
787 dawr = brk->address;
788
789 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
790 << (63 - 58); //* read/write bits */
791 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
792 << (63 - 59); //* translate */
793 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
794 >> 3; //* PRIM bits */
Michael Neuling05d694e2013-01-24 15:02:58 +0000795 /* dawr length is stored in field MDR bits 48:53. Matches range in
796 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
797 0b111111=64DW.
798 brk->len is in bytes.
799 This aligns up to double word size, shifts and does the bias.
800 */
801 mrd = ((brk->len + 7) >> 3) - 1;
802 dawrx |= (mrd & 0x3f) << (63 - 53);
Michael Neulingbf99de32012-12-20 14:06:45 +0000803
804 if (ppc_md.set_dawr)
805 return ppc_md.set_dawr(dawr, dawrx);
806 mtspr(SPRN_DAWR, dawr);
807 mtspr(SPRN_DAWRX, dawrx);
808 return 0;
809}
810
Paul Gortmaker21f58502014-04-29 15:25:17 -0400811void __set_breakpoint(struct arch_hw_breakpoint *brk)
Michael Neuling9422de32012-12-20 14:06:44 +0000812{
Christoph Lameter69111ba2014-10-21 15:23:25 -0500813 memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
Michael Neuling9422de32012-12-20 14:06:44 +0000814
Michael Neulingbf99de32012-12-20 14:06:45 +0000815 if (cpu_has_feature(CPU_FTR_DAWR))
Paul Gortmaker04c32a52014-04-29 15:25:16 -0400816 set_dawr(brk);
817 else
818 set_dabr(brk);
Michael Neuling9422de32012-12-20 14:06:44 +0000819}
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000820
Paul Gortmaker21f58502014-04-29 15:25:17 -0400821void set_breakpoint(struct arch_hw_breakpoint *brk)
822{
823 preempt_disable();
824 __set_breakpoint(brk);
825 preempt_enable();
826}
827
Paul Mackerras06d67d52005-10-10 22:29:05 +1000828#ifdef CONFIG_PPC64
829DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
Paul Mackerras06d67d52005-10-10 22:29:05 +1000830#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000831
Michael Neuling9422de32012-12-20 14:06:44 +0000832static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
833 struct arch_hw_breakpoint *b)
834{
835 if (a->address != b->address)
836 return false;
837 if (a->type != b->type)
838 return false;
839 if (a->len != b->len)
840 return false;
841 return true;
842}
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100843
Michael Neulingfb096922013-02-13 16:21:37 +0000844#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Cyril Bur5d176f72016-09-14 18:02:16 +1000845
846static inline bool tm_enabled(struct task_struct *tsk)
847{
848 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
849}
850
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100851static void tm_reclaim_thread(struct thread_struct *thr,
852 struct thread_info *ti, uint8_t cause)
853{
Michael Neuling7f821fc2015-11-19 15:44:45 +1100854 /*
855 * Use the current MSR TM suspended bit to track if we have
856 * checkpointed state outstanding.
857 * On signal delivery, we'd normally reclaim the checkpointed
858 * state to obtain stack pointer (see:get_tm_stackpointer()).
859 * This will then directly return to userspace without going
860 * through __switch_to(). However, if the stack frame is bad,
861 * we need to exit this thread which calls __switch_to() which
862 * will again attempt to reclaim the already saved tm state.
863 * Hence we need to check that we've not already reclaimed
864 * this state.
865 * We do this using the current MSR, rather tracking it in
866 * some specific thread_struct bit, as it has the additional
Michael Ellerman027dfac2016-06-01 16:34:37 +1000867 * benefit of checking for a potential TM bad thing exception.
Michael Neuling7f821fc2015-11-19 15:44:45 +1100868 */
869 if (!MSR_TM_SUSPENDED(mfmsr()))
870 return;
871
Michael Neulingf48e91e2017-05-08 17:16:26 +1000872 /*
873 * If we are in a transaction and FP is off then we can't have
874 * used FP inside that transaction. Hence the checkpointed
875 * state is the same as the live state. We need to copy the
876 * live state to the checkpointed state so that when the
877 * transaction is restored, the checkpointed state is correct
878 * and the aborted transaction sees the correct state. We use
879 * ckpt_regs.msr here as that's what tm_reclaim will use to
880 * determine if it's going to write the checkpointed state or
881 * not. So either this will write the checkpointed registers,
882 * or reclaim will. Similarly for VMX.
883 */
884 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
885 memcpy(&thr->ckfp_state, &thr->fp_state,
886 sizeof(struct thread_fp_state));
887 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
888 memcpy(&thr->ckvr_state, &thr->vr_state,
889 sizeof(struct thread_vr_state));
890
Cyril Burdc310662016-09-23 16:18:24 +1000891 giveup_all(container_of(thr, struct task_struct, thread));
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100892
Cyril Burdc310662016-09-23 16:18:24 +1000893 tm_reclaim(thr, thr->ckpt_regs.msr, cause);
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100894}
895
896void tm_reclaim_current(uint8_t cause)
897{
898 tm_enable();
899 tm_reclaim_thread(&current->thread, current_thread_info(), cause);
900}
901
Michael Neulingfb096922013-02-13 16:21:37 +0000902static inline void tm_reclaim_task(struct task_struct *tsk)
903{
904 /* We have to work out if we're switching from/to a task that's in the
905 * middle of a transaction.
906 *
907 * In switching we need to maintain a 2nd register state as
908 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
Cyril Bur000ec282016-09-23 16:18:25 +1000909 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
910 * ckvr_state
Michael Neulingfb096922013-02-13 16:21:37 +0000911 *
912 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
913 */
914 struct thread_struct *thr = &tsk->thread;
915
916 if (!thr->regs)
917 return;
918
919 if (!MSR_TM_ACTIVE(thr->regs->msr))
920 goto out_and_saveregs;
921
Michael Neulingfb096922013-02-13 16:21:37 +0000922 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
923 "ccr=%lx, msr=%lx, trap=%lx)\n",
924 tsk->pid, thr->regs->nip,
925 thr->regs->ccr, thr->regs->msr,
926 thr->regs->trap);
927
Paul Mackerrasd31626f2014-01-13 15:56:29 +1100928 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
Michael Neulingfb096922013-02-13 16:21:37 +0000929
930 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
931 tsk->pid);
932
933out_and_saveregs:
934 /* Always save the regs here, even if a transaction's not active.
935 * This context-switches a thread's TM info SPRs. We do it here to
936 * be consistent with the restore path (in recheckpoint) which
937 * cannot happen later in _switch().
938 */
939 tm_save_sprs(thr);
940}
941
Michael Neulinge6b8fd02014-04-04 20:19:48 +1100942extern void __tm_recheckpoint(struct thread_struct *thread,
943 unsigned long orig_msr);
944
945void tm_recheckpoint(struct thread_struct *thread,
946 unsigned long orig_msr)
947{
948 unsigned long flags;
949
Cyril Bur5d176f72016-09-14 18:02:16 +1000950 if (!(thread->regs->msr & MSR_TM))
951 return;
952
Michael Neulinge6b8fd02014-04-04 20:19:48 +1100953 /* We really can't be interrupted here as the TEXASR registers can't
954 * change and later in the trecheckpoint code, we have a userspace R1.
955 * So let's hard disable over this region.
956 */
957 local_irq_save(flags);
958 hard_irq_disable();
959
960 /* The TM SPRs are restored here, so that TEXASR.FS can be set
961 * before the trecheckpoint and no explosion occurs.
962 */
963 tm_restore_sprs(thread);
964
965 __tm_recheckpoint(thread, orig_msr);
966
967 local_irq_restore(flags);
968}
969
Michael Neulingbc2a9402013-02-13 16:21:40 +0000970static inline void tm_recheckpoint_new_task(struct task_struct *new)
Michael Neulingfb096922013-02-13 16:21:37 +0000971{
972 unsigned long msr;
973
974 if (!cpu_has_feature(CPU_FTR_TM))
975 return;
976
977 /* Recheckpoint the registers of the thread we're about to switch to.
978 *
979 * If the task was using FP, we non-lazily reload both the original and
980 * the speculative FP register states. This is because the kernel
981 * doesn't see if/when a TM rollback occurs, so if we take an FP
Cyril Burdc310662016-09-23 16:18:24 +1000982 * unavailable later, we are unable to determine which set of FP regs
Michael Neulingfb096922013-02-13 16:21:37 +0000983 * need to be restored.
984 */
Cyril Bur5d176f72016-09-14 18:02:16 +1000985 if (!tm_enabled(new))
Michael Neulingfb096922013-02-13 16:21:37 +0000986 return;
987
Michael Neulinge6b8fd02014-04-04 20:19:48 +1100988 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
989 tm_restore_sprs(&new->thread);
Michael Neulingfb096922013-02-13 16:21:37 +0000990 return;
Michael Neulinge6b8fd02014-04-04 20:19:48 +1100991 }
Anshuman Khandual829023d2015-07-06 16:24:10 +0530992 msr = new->thread.ckpt_regs.msr;
Michael Neulingfb096922013-02-13 16:21:37 +0000993 /* Recheckpoint to restore original checkpointed register state. */
994 TM_DEBUG("*** tm_recheckpoint of pid %d "
995 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
996 new->pid, new->thread.regs->msr, msr);
997
Michael Neulingfb096922013-02-13 16:21:37 +0000998 tm_recheckpoint(&new->thread, msr);
999
Cyril Burdc310662016-09-23 16:18:24 +10001000 /*
1001 * The checkpointed state has been restored but the live state has
1002 * not, ensure all the math functionality is turned off to trigger
1003 * restore_math() to reload.
1004 */
1005 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
Michael Neulingfb096922013-02-13 16:21:37 +00001006
1007 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1008 "(kernel msr 0x%lx)\n",
1009 new->pid, mfmsr());
1010}
1011
Cyril Burdc310662016-09-23 16:18:24 +10001012static inline void __switch_to_tm(struct task_struct *prev,
1013 struct task_struct *new)
Michael Neulingfb096922013-02-13 16:21:37 +00001014{
1015 if (cpu_has_feature(CPU_FTR_TM)) {
Cyril Bur5d176f72016-09-14 18:02:16 +10001016 if (tm_enabled(prev) || tm_enabled(new))
1017 tm_enable();
1018
1019 if (tm_enabled(prev)) {
1020 prev->thread.load_tm++;
1021 tm_reclaim_task(prev);
1022 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1023 prev->thread.regs->msr &= ~MSR_TM;
1024 }
1025
Cyril Burdc310662016-09-23 16:18:24 +10001026 tm_recheckpoint_new_task(new);
Michael Neulingfb096922013-02-13 16:21:37 +00001027 }
1028}
Paul Mackerrasd31626f2014-01-13 15:56:29 +11001029
1030/*
1031 * This is called if we are on the way out to userspace and the
1032 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1033 * FP and/or vector state and does so if necessary.
1034 * If userspace is inside a transaction (whether active or
1035 * suspended) and FP/VMX/VSX instructions have ever been enabled
1036 * inside that transaction, then we have to keep them enabled
1037 * and keep the FP/VMX/VSX state loaded while ever the transaction
1038 * continues. The reason is that if we didn't, and subsequently
1039 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1040 * we don't know whether it's the same transaction, and thus we
1041 * don't know which of the checkpointed state and the transactional
1042 * state to use.
1043 */
1044void restore_tm_state(struct pt_regs *regs)
1045{
1046 unsigned long msr_diff;
1047
Cyril Burdc310662016-09-23 16:18:24 +10001048 /*
1049 * This is the only moment we should clear TIF_RESTORE_TM as
1050 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1051 * again, anything else could lead to an incorrect ckpt_msr being
1052 * saved and therefore incorrect signal contexts.
1053 */
Paul Mackerrasd31626f2014-01-13 15:56:29 +11001054 clear_thread_flag(TIF_RESTORE_TM);
1055 if (!MSR_TM_ACTIVE(regs->msr))
1056 return;
1057
Anshuman Khandual829023d2015-07-06 16:24:10 +05301058 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
Paul Mackerrasd31626f2014-01-13 15:56:29 +11001059 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
Cyril Bur70fe3d92016-02-29 17:53:47 +11001060
Cyril Burdc16b552016-09-23 16:18:08 +10001061 /* Ensure that restore_math() will restore */
1062 if (msr_diff & MSR_FP)
1063 current->thread.load_fp = 1;
Valentin Rothberg39715bf2016-10-05 07:57:26 +02001064#ifdef CONFIG_ALTIVEC
Cyril Burdc16b552016-09-23 16:18:08 +10001065 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1066 current->thread.load_vec = 1;
1067#endif
Cyril Bur70fe3d92016-02-29 17:53:47 +11001068 restore_math(regs);
1069
Paul Mackerrasd31626f2014-01-13 15:56:29 +11001070 regs->msr |= msr_diff;
1071}
1072
Michael Neulingfb096922013-02-13 16:21:37 +00001073#else
1074#define tm_recheckpoint_new_task(new)
Cyril Burdc310662016-09-23 16:18:24 +10001075#define __switch_to_tm(prev, new)
Michael Neulingfb096922013-02-13 16:21:37 +00001076#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
Michael Neuling9422de32012-12-20 14:06:44 +00001077
Anton Blanchard152d5232015-10-29 11:43:55 +11001078static inline void save_sprs(struct thread_struct *t)
1079{
1080#ifdef CONFIG_ALTIVEC
Oliver O'Halloran01d7c2a22016-03-08 09:08:47 +11001081 if (cpu_has_feature(CPU_FTR_ALTIVEC))
Anton Blanchard152d5232015-10-29 11:43:55 +11001082 t->vrsave = mfspr(SPRN_VRSAVE);
1083#endif
1084#ifdef CONFIG_PPC_BOOK3S_64
1085 if (cpu_has_feature(CPU_FTR_DSCR))
1086 t->dscr = mfspr(SPRN_DSCR);
1087
1088 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1089 t->bescr = mfspr(SPRN_BESCR);
1090 t->ebbhr = mfspr(SPRN_EBBHR);
1091 t->ebbrr = mfspr(SPRN_EBBRR);
1092
1093 t->fscr = mfspr(SPRN_FSCR);
1094
1095 /*
1096 * Note that the TAR is not available for use in the kernel.
1097 * (To provide this, the TAR should be backed up/restored on
1098 * exception entry/exit instead, and be in pt_regs. FIXME,
1099 * this should be in pt_regs anyway (for debug).)
1100 */
1101 t->tar = mfspr(SPRN_TAR);
1102 }
1103#endif
1104}
1105
1106static inline void restore_sprs(struct thread_struct *old_thread,
1107 struct thread_struct *new_thread)
1108{
1109#ifdef CONFIG_ALTIVEC
1110 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1111 old_thread->vrsave != new_thread->vrsave)
1112 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1113#endif
1114#ifdef CONFIG_PPC_BOOK3S_64
1115 if (cpu_has_feature(CPU_FTR_DSCR)) {
1116 u64 dscr = get_paca()->dscr_default;
Michael Neulingb57bd2d2016-06-09 12:31:08 +10001117 if (new_thread->dscr_inherit)
Anton Blanchard152d5232015-10-29 11:43:55 +11001118 dscr = new_thread->dscr;
Anton Blanchard152d5232015-10-29 11:43:55 +11001119
1120 if (old_thread->dscr != dscr)
1121 mtspr(SPRN_DSCR, dscr);
Anton Blanchard152d5232015-10-29 11:43:55 +11001122 }
1123
1124 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1125 if (old_thread->bescr != new_thread->bescr)
1126 mtspr(SPRN_BESCR, new_thread->bescr);
1127 if (old_thread->ebbhr != new_thread->ebbhr)
1128 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1129 if (old_thread->ebbrr != new_thread->ebbrr)
1130 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1131
Michael Neulingb57bd2d2016-06-09 12:31:08 +10001132 if (old_thread->fscr != new_thread->fscr)
1133 mtspr(SPRN_FSCR, new_thread->fscr);
1134
Anton Blanchard152d5232015-10-29 11:43:55 +11001135 if (old_thread->tar != new_thread->tar)
1136 mtspr(SPRN_TAR, new_thread->tar);
1137 }
1138#endif
1139}
1140
Nicholas Piggin07d2a622017-06-09 01:36:09 +10001141#ifdef CONFIG_PPC_BOOK3S_64
1142#define CP_SIZE 128
1143static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1144#endif
1145
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001146struct task_struct *__switch_to(struct task_struct *prev,
1147 struct task_struct *new)
1148{
1149 struct thread_struct *new_thread, *old_thread;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001150 struct task_struct *last;
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001151#ifdef CONFIG_PPC_BOOK3S_64
1152 struct ppc64_tlb_batch *batch;
1153#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001154
Anton Blanchard152d5232015-10-29 11:43:55 +11001155 new_thread = &new->thread;
1156 old_thread = &current->thread;
1157
Michael Neuling7ba5fef2013-10-02 17:15:14 +10001158 WARN_ON(!irqs_disabled());
1159
Paul Mackerras06d67d52005-10-10 22:29:05 +10001160#ifdef CONFIG_PPC64
1161 /*
1162 * Collect processor utilization data per process
1163 */
1164 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
Christoph Lameter69111ba2014-10-21 15:23:25 -05001165 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001166 long unsigned start_tb, current_tb;
1167 start_tb = old_thread->start_tb;
1168 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1169 old_thread->accum_tb += (current_tb - start_tb);
1170 new_thread->start_tb = current_tb;
1171 }
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001172#endif /* CONFIG_PPC64 */
1173
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10001174#ifdef CONFIG_PPC_STD_MMU_64
Christoph Lameter69111ba2014-10-21 15:23:25 -05001175 batch = this_cpu_ptr(&ppc64_tlb_batch);
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001176 if (batch->active) {
1177 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1178 if (batch->index)
1179 __flush_tlb_pending(batch);
1180 batch->active = 0;
1181 }
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10001182#endif /* CONFIG_PPC_STD_MMU_64 */
Paul Mackerras06d67d52005-10-10 22:29:05 +10001183
Anton Blanchardf3d885c2015-10-29 11:44:10 +11001184#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1185 switch_booke_debug_regs(&new->thread.debug);
1186#else
1187/*
1188 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1189 * schedule DABR
1190 */
1191#ifndef CONFIG_HAVE_HW_BREAKPOINT
1192 if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1193 __set_breakpoint(&new->thread.hw_brk);
1194#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1195#endif
1196
1197 /*
1198 * We need to save SPRs before treclaim/trecheckpoint as these will
1199 * change a number of them.
1200 */
1201 save_sprs(&prev->thread);
1202
Anton Blanchardf3d885c2015-10-29 11:44:10 +11001203 /* Save FPU, Altivec, VSX and SPE state */
1204 giveup_all(prev);
1205
Cyril Burdc310662016-09-23 16:18:24 +10001206 __switch_to_tm(prev, new);
1207
Nicholas Piggine4c0fc52017-06-09 01:36:06 +10001208 if (!radix_enabled()) {
1209 /*
1210 * We can't take a PMU exception inside _switch() since there
1211 * is a window where the kernel stack SLB and the kernel stack
1212 * are out of sync. Hard disable here.
1213 */
1214 hard_irq_disable();
1215 }
Michael Neulingbc2a9402013-02-13 16:21:40 +00001216
Anton Blanchard20dbe672015-12-10 20:44:39 +11001217 /*
1218 * Call restore_sprs() before calling _switch(). If we move it after
1219 * _switch() then we miss out on calling it for new tasks. The reason
1220 * for this is we manually create a stack frame for new tasks that
1221 * directly returns through ret_from_fork() or
1222 * ret_from_kernel_thread(). See copy_thread() for details.
1223 */
Anton Blanchardf3d885c2015-10-29 11:44:10 +11001224 restore_sprs(old_thread, new_thread);
1225
Anton Blanchard20dbe672015-12-10 20:44:39 +11001226 last = _switch(old_thread, new_thread);
1227
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10001228#ifdef CONFIG_PPC_STD_MMU_64
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001229 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1230 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
Christoph Lameter69111ba2014-10-21 15:23:25 -05001231 batch = this_cpu_ptr(&ppc64_tlb_batch);
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001232 batch->active = 1;
1233 }
Cyril Bur70fe3d92016-02-29 17:53:47 +11001234
Nicholas Piggin07d2a622017-06-09 01:36:09 +10001235 if (current_thread_info()->task->thread.regs) {
Cyril Bur70fe3d92016-02-29 17:53:47 +11001236 restore_math(current_thread_info()->task->thread.regs);
Nicholas Piggin07d2a622017-06-09 01:36:09 +10001237
1238 /*
1239 * The copy-paste buffer can only store into foreign real
1240 * addresses, so unprivileged processes can not see the
1241 * data or use it in any way unless they have foreign real
1242 * mappings. We don't have a VAS driver that allocates those
1243 * yet, so no cpabort is required.
1244 */
1245 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
1246 /*
1247 * DD1 allows paste into normal system memory, so we
1248 * do an unpaired copy here to clear the buffer and
1249 * prevent a covert channel being set up.
1250 *
1251 * cpabort is not used because it is quite expensive.
1252 */
1253 asm volatile(PPC_COPY(%0, %1)
1254 : : "r"(dummy_copy_buffer), "r"(0));
1255 }
1256 }
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10001257#endif /* CONFIG_PPC_STD_MMU_64 */
Peter Zijlstrad6bf29b2011-05-24 17:11:48 -07001258
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001259 return last;
1260}
1261
Paul Mackerras06d67d52005-10-10 22:29:05 +10001262static int instructions_to_print = 16;
1263
Paul Mackerras06d67d52005-10-10 22:29:05 +10001264static void show_instructions(struct pt_regs *regs)
1265{
1266 int i;
1267 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1268 sizeof(int));
1269
1270 printk("Instruction dump:");
1271
1272 for (i = 0; i < instructions_to_print; i++) {
1273 int instr;
1274
1275 if (!(i % 8))
Andrew Donnellan2ffd04d2016-11-04 17:20:40 +11001276 pr_cont("\n");
Paul Mackerras06d67d52005-10-10 22:29:05 +10001277
Scott Wood0de2d822007-09-28 04:38:55 +10001278#if !defined(CONFIG_BOOKE)
1279 /* If executing with the IMMU off, adjust pc rather
1280 * than print XXXXXXXX.
1281 */
1282 if (!(regs->msr & MSR_IR))
1283 pc = (unsigned long)phys_to_virt(pc);
1284#endif
1285
Anton Blanchard00ae36d2006-10-13 12:17:16 +10001286 if (!__kernel_text_address(pc) ||
Anton Blanchard7b051f62014-10-13 20:27:15 +11001287 probe_kernel_address((unsigned int __user *)pc, instr)) {
Andrew Donnellan2ffd04d2016-11-04 17:20:40 +11001288 pr_cont("XXXXXXXX ");
Paul Mackerras06d67d52005-10-10 22:29:05 +10001289 } else {
1290 if (regs->nip == pc)
Andrew Donnellan2ffd04d2016-11-04 17:20:40 +11001291 pr_cont("<%08x> ", instr);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001292 else
Andrew Donnellan2ffd04d2016-11-04 17:20:40 +11001293 pr_cont("%08x ", instr);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001294 }
1295
1296 pc += sizeof(int);
1297 }
1298
Andrew Donnellan2ffd04d2016-11-04 17:20:40 +11001299 pr_cont("\n");
Paul Mackerras06d67d52005-10-10 22:29:05 +10001300}
1301
Michael Neuling801c0b22015-11-20 15:15:32 +11001302struct regbit {
Paul Mackerras06d67d52005-10-10 22:29:05 +10001303 unsigned long bit;
1304 const char *name;
Michael Neuling801c0b22015-11-20 15:15:32 +11001305};
1306
1307static struct regbit msr_bits[] = {
Anton Blanchard3bfd0c9c2011-11-24 19:35:57 +00001308#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1309 {MSR_SF, "SF"},
1310 {MSR_HV, "HV"},
1311#endif
1312 {MSR_VEC, "VEC"},
1313 {MSR_VSX, "VSX"},
1314#ifdef CONFIG_BOOKE
1315 {MSR_CE, "CE"},
1316#endif
Paul Mackerras06d67d52005-10-10 22:29:05 +10001317 {MSR_EE, "EE"},
1318 {MSR_PR, "PR"},
1319 {MSR_FP, "FP"},
1320 {MSR_ME, "ME"},
Anton Blanchard3bfd0c9c2011-11-24 19:35:57 +00001321#ifdef CONFIG_BOOKE
Kumar Gala1b983262008-11-19 04:39:53 +00001322 {MSR_DE, "DE"},
Anton Blanchard3bfd0c9c2011-11-24 19:35:57 +00001323#else
1324 {MSR_SE, "SE"},
1325 {MSR_BE, "BE"},
1326#endif
Paul Mackerras06d67d52005-10-10 22:29:05 +10001327 {MSR_IR, "IR"},
1328 {MSR_DR, "DR"},
Anton Blanchard3bfd0c9c2011-11-24 19:35:57 +00001329 {MSR_PMM, "PMM"},
1330#ifndef CONFIG_BOOKE
1331 {MSR_RI, "RI"},
1332 {MSR_LE, "LE"},
1333#endif
Paul Mackerras06d67d52005-10-10 22:29:05 +10001334 {0, NULL}
1335};
1336
Michael Neuling801c0b22015-11-20 15:15:32 +11001337static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
Paul Mackerras06d67d52005-10-10 22:29:05 +10001338{
Michael Neuling801c0b22015-11-20 15:15:32 +11001339 const char *s = "";
Paul Mackerras06d67d52005-10-10 22:29:05 +10001340
Paul Mackerras06d67d52005-10-10 22:29:05 +10001341 for (; bits->bit; ++bits)
1342 if (val & bits->bit) {
Michael Ellermandb5ba5a2016-11-02 22:20:47 +11001343 pr_cont("%s%s", s, bits->name);
Michael Neuling801c0b22015-11-20 15:15:32 +11001344 s = sep;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001345 }
Michael Neuling801c0b22015-11-20 15:15:32 +11001346}
1347
1348#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349static struct regbit msr_tm_bits[] = {
1350 {MSR_TS_T, "T"},
1351 {MSR_TS_S, "S"},
1352 {MSR_TM, "E"},
1353 {0, NULL}
1354};
1355
1356static void print_tm_bits(unsigned long val)
1357{
1358/*
1359 * This only prints something if at least one of the TM bit is set.
1360 * Inside the TM[], the output means:
1361 * E: Enabled (bit 32)
1362 * S: Suspended (bit 33)
1363 * T: Transactional (bit 34)
1364 */
1365 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
Michael Ellermandb5ba5a2016-11-02 22:20:47 +11001366 pr_cont(",TM[");
Michael Neuling801c0b22015-11-20 15:15:32 +11001367 print_bits(val, msr_tm_bits, "");
Michael Ellermandb5ba5a2016-11-02 22:20:47 +11001368 pr_cont("]");
Michael Neuling801c0b22015-11-20 15:15:32 +11001369 }
1370}
1371#else
1372static void print_tm_bits(unsigned long val) {}
1373#endif
1374
1375static void print_msr_bits(unsigned long val)
1376{
Michael Ellermandb5ba5a2016-11-02 22:20:47 +11001377 pr_cont("<");
Michael Neuling801c0b22015-11-20 15:15:32 +11001378 print_bits(val, msr_bits, ",");
1379 print_tm_bits(val);
Michael Ellermandb5ba5a2016-11-02 22:20:47 +11001380 pr_cont(">");
Paul Mackerras06d67d52005-10-10 22:29:05 +10001381}
1382
1383#ifdef CONFIG_PPC64
anton@samba.orgf6f7dde2007-03-20 20:38:19 -05001384#define REG "%016lx"
Paul Mackerras06d67d52005-10-10 22:29:05 +10001385#define REGS_PER_LINE 4
1386#define LAST_VOLATILE 13
1387#else
anton@samba.orgf6f7dde2007-03-20 20:38:19 -05001388#define REG "%08lx"
Paul Mackerras06d67d52005-10-10 22:29:05 +10001389#define REGS_PER_LINE 8
1390#define LAST_VOLATILE 12
1391#endif
1392
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001393void show_regs(struct pt_regs * regs)
1394{
1395 int i, trap;
1396
Tejun Heoa43cb952013-04-30 15:27:17 -07001397 show_regs_print_info(KERN_DEFAULT);
1398
Paul Mackerras06d67d52005-10-10 22:29:05 +10001399 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1400 regs->nip, regs->link, regs->ctr);
1401 printk("REGS: %p TRAP: %04lx %s (%s)\n",
Serge E. Hallyn96b644b2006-10-02 02:18:13 -07001402 regs, regs->trap, print_tainted(), init_utsname()->release);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001403 printk("MSR: "REG" ", regs->msr);
Michael Neuling801c0b22015-11-20 15:15:32 +11001404 print_msr_bits(regs->msr);
anton@samba.orgf6f7dde2007-03-20 20:38:19 -05001405 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001406 trap = TRAP(regs);
Michael Neuling5115a022011-07-14 19:25:12 +00001407 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
Michael Ellerman7dae8652016-11-03 20:45:26 +11001408 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
Anton Blanchardc5400642013-11-15 15:41:19 +11001409 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
Kumar Galaba28c9a2011-10-06 02:53:38 +00001410#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
Michael Ellerman7dae8652016-11-03 20:45:26 +11001411 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
Kumar Gala14170782007-07-26 00:46:15 -05001412#else
Michael Ellerman7dae8652016-11-03 20:45:26 +11001413 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
Anton Blanchard9db8bcf2013-11-15 15:48:38 +11001414#endif
1415#ifdef CONFIG_PPC64
Michael Ellerman7dae8652016-11-03 20:45:26 +11001416 pr_cont("SOFTE: %ld ", regs->softe);
Anton Blanchard9db8bcf2013-11-15 15:48:38 +11001417#endif
1418#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Anton Blanchard6d888d12013-11-18 13:19:17 +11001419 if (MSR_TM_ACTIVE(regs->msr))
Michael Ellerman7dae8652016-11-03 20:45:26 +11001420 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
Kumar Gala14170782007-07-26 00:46:15 -05001421#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001422
1423 for (i = 0; i < 32; i++) {
Paul Mackerras06d67d52005-10-10 22:29:05 +10001424 if ((i % REGS_PER_LINE) == 0)
Michael Ellerman7dae8652016-11-03 20:45:26 +11001425 pr_cont("\nGPR%02d: ", i);
1426 pr_cont(REG " ", regs->gpr[i]);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001427 if (i == LAST_VOLATILE && !FULL_REGS(regs))
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001428 break;
1429 }
Michael Ellerman7dae8652016-11-03 20:45:26 +11001430 pr_cont("\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001431#ifdef CONFIG_KALLSYMS
1432 /*
1433 * Lookup NIP late so we have the best change of getting the
1434 * above info out without failing
1435 */
Benjamin Herrenschmidt058c78f2008-07-07 13:44:31 +10001436 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1437 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001438#endif
1439 show_stack(current, (unsigned long *) regs->gpr[1]);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001440 if (!user_mode(regs))
1441 show_instructions(regs);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001442}
1443
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001444void flush_thread(void)
1445{
K.Prasade0780b72011-02-10 04:44:35 +00001446#ifdef CONFIG_HAVE_HW_BREAKPOINT
K.Prasad5aae8a52010-06-15 11:35:19 +05301447 flush_ptrace_hw_breakpoint(current);
K.Prasade0780b72011-02-10 04:44:35 +00001448#else /* CONFIG_HAVE_HW_BREAKPOINT */
Dave Kleikamp3bffb652010-02-08 11:51:18 +00001449 set_debug_reg_defaults(&current->thread);
K.Prasade0780b72011-02-10 04:44:35 +00001450#endif /* CONFIG_HAVE_HW_BREAKPOINT */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001451}
1452
1453void
1454release_thread(struct task_struct *t)
1455{
1456}
1457
1458/*
Suresh Siddha55ccf3f2012-05-16 15:03:51 -07001459 * this gets called so that we can store coprocessor state into memory and
1460 * copy the current task into the new thread.
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001461 */
Suresh Siddha55ccf3f2012-05-16 15:03:51 -07001462int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001463{
Anton Blanchard579e6332015-10-29 11:44:09 +11001464 flush_all_to_thread(src);
Michael Neuling621b5062014-03-03 14:21:40 +11001465 /*
1466 * Flush TM state out so we can copy it. __switch_to_tm() does this
1467 * flush but it removes the checkpointed state from the current CPU and
1468 * transitions the CPU out of TM mode. Hence we need to call
1469 * tm_recheckpoint_new_task() (on the same task) to restore the
1470 * checkpointed state back and the TM mode.
Cyril Bur5d176f72016-09-14 18:02:16 +10001471 *
1472 * Can't pass dst because it isn't ready. Doesn't matter, passing
1473 * dst is only important for __switch_to()
Michael Neuling621b5062014-03-03 14:21:40 +11001474 */
Cyril Burdc310662016-09-23 16:18:24 +10001475 __switch_to_tm(src, src);
Michael Ellerman330a1eb2013-06-28 18:15:16 +10001476
Suresh Siddha55ccf3f2012-05-16 15:03:51 -07001477 *dst = *src;
Michael Ellerman330a1eb2013-06-28 18:15:16 +10001478
1479 clear_task_ebb(dst);
1480
Suresh Siddha55ccf3f2012-05-16 15:03:51 -07001481 return 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001482}
1483
Michael Ellermancec15482014-07-10 12:29:21 +10001484static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1485{
1486#ifdef CONFIG_PPC_STD_MMU_64
1487 unsigned long sp_vsid;
1488 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1489
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10001490 if (radix_enabled())
1491 return;
1492
Michael Ellermancec15482014-07-10 12:29:21 +10001493 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1494 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1495 << SLB_VSID_SHIFT_1T;
1496 else
1497 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1498 << SLB_VSID_SHIFT;
1499 sp_vsid |= SLB_VSID_KERNEL | llp;
1500 p->thread.ksp_vsid = sp_vsid;
1501#endif
1502}
1503
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001504/*
1505 * Copy a thread..
1506 */
Alexey Kardashevskiyefcac652011-03-02 15:18:48 +00001507
Alex Dowad6eca8932015-03-13 20:14:46 +02001508/*
1509 * Copy architecture-specific thread state
1510 */
Alexey Dobriyan6f2c55b2009-04-02 16:56:59 -07001511int copy_thread(unsigned long clone_flags, unsigned long usp,
Alex Dowad6eca8932015-03-13 20:14:46 +02001512 unsigned long kthread_arg, struct task_struct *p)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001513{
1514 struct pt_regs *childregs, *kregs;
1515 extern void ret_from_fork(void);
Al Viro58254e12012-09-12 18:32:42 -04001516 extern void ret_from_kernel_thread(void);
1517 void (*f)(void);
Al Viro0cec6fd2006-01-12 01:06:02 -08001518 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
Michael Ellerman5d31a962016-03-24 22:04:04 +11001519 struct thread_info *ti = task_thread_info(p);
1520
1521 klp_init_thread_info(ti);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001522
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001523 /* Copy registers */
1524 sp -= sizeof(struct pt_regs);
1525 childregs = (struct pt_regs *) sp;
Al Viroab758192012-10-21 22:33:39 -04001526 if (unlikely(p->flags & PF_KTHREAD)) {
Alex Dowad6eca8932015-03-13 20:14:46 +02001527 /* kernel thread */
Al Viro58254e12012-09-12 18:32:42 -04001528 memset(childregs, 0, sizeof(struct pt_regs));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001529 childregs->gpr[1] = sp + sizeof(struct pt_regs);
Anton Blanchard7cedd602014-02-04 16:08:51 +11001530 /* function */
1531 if (usp)
1532 childregs->gpr[14] = ppc_function_entry((void *)usp);
Al Viro58254e12012-09-12 18:32:42 -04001533#ifdef CONFIG_PPC64
Al Virob5e2fc12006-01-12 01:06:01 -08001534 clear_tsk_thread_flag(p, TIF_32BIT);
Al Viro138d1ce2012-10-11 08:41:43 -04001535 childregs->softe = 1;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001536#endif
Alex Dowad6eca8932015-03-13 20:14:46 +02001537 childregs->gpr[15] = kthread_arg;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001538 p->thread.regs = NULL; /* no user register state */
Al Viro138d1ce2012-10-11 08:41:43 -04001539 ti->flags |= _TIF_RESTOREALL;
Al Viro58254e12012-09-12 18:32:42 -04001540 f = ret_from_kernel_thread;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001541 } else {
Alex Dowad6eca8932015-03-13 20:14:46 +02001542 /* user thread */
Al Viroafa86fc2012-10-22 22:51:14 -04001543 struct pt_regs *regs = current_pt_regs();
Al Viro58254e12012-09-12 18:32:42 -04001544 CHECK_FULL_REGS(regs);
1545 *childregs = *regs;
Al Viroea516b12012-10-21 22:28:43 -04001546 if (usp)
1547 childregs->gpr[1] = usp;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001548 p->thread.regs = childregs;
Al Viro58254e12012-09-12 18:32:42 -04001549 childregs->gpr[3] = 0; /* Result from fork() */
Paul Mackerras06d67d52005-10-10 22:29:05 +10001550 if (clone_flags & CLONE_SETTLS) {
1551#ifdef CONFIG_PPC64
Denis Kirjanov9904b002010-07-29 22:04:39 +00001552 if (!is_32bit_task())
Paul Mackerras06d67d52005-10-10 22:29:05 +10001553 childregs->gpr[13] = childregs->gpr[6];
1554 else
1555#endif
1556 childregs->gpr[2] = childregs->gpr[6];
1557 }
Al Viro58254e12012-09-12 18:32:42 -04001558
1559 f = ret_from_fork;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001560 }
Cyril Burd272f662016-02-29 17:53:46 +11001561 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001562 sp -= STACK_FRAME_OVERHEAD;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001563
1564 /*
1565 * The way this works is that at some point in the future
1566 * some task will call _switch to switch to the new task.
1567 * That will pop off the stack frame created below and start
1568 * the new task running at ret_from_fork. The new task will
1569 * do some house keeping and then return from the fork or clone
1570 * system call, using the stack frame created above.
1571 */
Li Zhongaf945cf2013-05-06 22:44:41 +00001572 ((unsigned long *)sp)[0] = 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001573 sp -= sizeof(struct pt_regs);
1574 kregs = (struct pt_regs *) sp;
1575 sp -= STACK_FRAME_OVERHEAD;
1576 p->thread.ksp = sp;
Benjamin Herrenschmidtcbc95652013-09-24 15:17:21 +10001577#ifdef CONFIG_PPC32
Kumar Gala85218822008-04-28 16:21:22 +10001578 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1579 _ALIGN_UP(sizeof(struct thread_info), 16);
Benjamin Herrenschmidtcbc95652013-09-24 15:17:21 +10001580#endif
Oleg Nesterov28d170ab2013-04-21 06:47:59 +00001581#ifdef CONFIG_HAVE_HW_BREAKPOINT
1582 p->thread.ptrace_bps[0] = NULL;
1583#endif
1584
Paul Mackerras18461962013-09-10 20:21:10 +10001585 p->thread.fp_save_area = NULL;
1586#ifdef CONFIG_ALTIVEC
1587 p->thread.vr_save_area = NULL;
1588#endif
1589
Michael Ellermancec15482014-07-10 12:29:21 +10001590 setup_ksp_vsid(p, sp);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001591
Alexey Kardashevskiyefcac652011-03-02 15:18:48 +00001592#ifdef CONFIG_PPC64
1593 if (cpu_has_feature(CPU_FTR_DSCR)) {
Anton Blanchard1021cb22012-09-03 16:49:47 +00001594 p->thread.dscr_inherit = current->thread.dscr_inherit;
Anton Blancharddb1231dc2015-12-09 20:11:47 +11001595 p->thread.dscr = mfspr(SPRN_DSCR);
Alexey Kardashevskiyefcac652011-03-02 15:18:48 +00001596 }
Haren Myneni92779242012-12-06 21:49:56 +00001597 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1598 p->thread.ppr = INIT_PPR;
Alexey Kardashevskiyefcac652011-03-02 15:18:48 +00001599#endif
Anton Blanchard7cedd602014-02-04 16:08:51 +11001600 kregs->nip = ppc_function_entry(f);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001601 return 0;
1602}
1603
1604/*
1605 * Set up a thread for executing a new program
1606 */
Paul Mackerras06d67d52005-10-10 22:29:05 +10001607void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001608{
Michael Ellerman90eac722005-10-21 16:01:33 +10001609#ifdef CONFIG_PPC64
1610 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1611#endif
1612
Paul Mackerras06d67d52005-10-10 22:29:05 +10001613 /*
1614 * If we exec out of a kernel thread then thread.regs will not be
1615 * set. Do it now.
1616 */
1617 if (!current->thread.regs) {
Al Viro0cec6fd2006-01-12 01:06:02 -08001618 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1619 current->thread.regs = regs - 1;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001620 }
1621
Cyril Bur8e96a872016-06-17 14:58:34 +10001622#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1623 /*
1624 * Clear any transactional state, we're exec()ing. The cause is
1625 * not important as there will never be a recheckpoint so it's not
1626 * user visible.
1627 */
1628 if (MSR_TM_SUSPENDED(mfmsr()))
1629 tm_reclaim_current(0);
1630#endif
1631
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001632 memset(regs->gpr, 0, sizeof(regs->gpr));
1633 regs->ctr = 0;
1634 regs->link = 0;
1635 regs->xer = 0;
1636 regs->ccr = 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001637 regs->gpr[1] = sp;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001638
Roland McGrath474f8192007-09-24 16:52:44 -07001639 /*
1640 * We have just cleared all the nonvolatile GPRs, so make
1641 * FULL_REGS(regs) return true. This is necessary to allow
1642 * ptrace to examine the thread immediately after exec.
1643 */
1644 regs->trap &= ~1UL;
1645
Paul Mackerras06d67d52005-10-10 22:29:05 +10001646#ifdef CONFIG_PPC32
1647 regs->mq = 0;
1648 regs->nip = start;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001649 regs->msr = MSR_USER;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001650#else
Denis Kirjanov9904b002010-07-29 22:04:39 +00001651 if (!is_32bit_task()) {
Rusty Russell94af3ab2013-11-20 22:15:02 +11001652 unsigned long entry;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001653
Rusty Russell94af3ab2013-11-20 22:15:02 +11001654 if (is_elf2_task()) {
1655 /* Look ma, no function descriptors! */
1656 entry = start;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001657
Rusty Russell94af3ab2013-11-20 22:15:02 +11001658 /*
1659 * Ulrich says:
1660 * The latest iteration of the ABI requires that when
1661 * calling a function (at its global entry point),
1662 * the caller must ensure r12 holds the entry point
1663 * address (so that the function can quickly
1664 * establish addressability).
1665 */
1666 regs->gpr[12] = start;
1667 /* Make sure that's restored on entry to userspace. */
1668 set_thread_flag(TIF_RESTOREALL);
1669 } else {
1670 unsigned long toc;
1671
1672 /* start is a relocated pointer to the function
1673 * descriptor for the elf _start routine. The first
1674 * entry in the function descriptor is the entry
1675 * address of _start and the second entry is the TOC
1676 * value we need to use.
1677 */
1678 __get_user(entry, (unsigned long __user *)start);
1679 __get_user(toc, (unsigned long __user *)start+1);
1680
1681 /* Check whether the e_entry function descriptor entries
1682 * need to be relocated before we can use them.
1683 */
1684 if (load_addr != 0) {
1685 entry += load_addr;
1686 toc += load_addr;
1687 }
1688 regs->gpr[2] = toc;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001689 }
1690 regs->nip = entry;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001691 regs->msr = MSR_USER64;
Stephen Rothwelld4bf9a72005-10-13 13:40:54 +10001692 } else {
1693 regs->nip = start;
1694 regs->gpr[2] = 0;
1695 regs->msr = MSR_USER32;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001696 }
1697#endif
Michael Neulingce48b212008-06-25 14:07:18 +10001698#ifdef CONFIG_VSX
1699 current->thread.used_vsr = 0;
1700#endif
Breno Leitao11958922017-06-02 18:43:30 -03001701 current->thread.load_fp = 0;
Paul Mackerrasde79f7b2013-09-10 20:20:42 +10001702 memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
Paul Mackerras18461962013-09-10 20:21:10 +10001703 current->thread.fp_save_area = NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001704#ifdef CONFIG_ALTIVEC
Paul Mackerrasde79f7b2013-09-10 20:20:42 +10001705 memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1706 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
Paul Mackerras18461962013-09-10 20:21:10 +10001707 current->thread.vr_save_area = NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001708 current->thread.vrsave = 0;
1709 current->thread.used_vr = 0;
Breno Leitao11958922017-06-02 18:43:30 -03001710 current->thread.load_vec = 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001711#endif /* CONFIG_ALTIVEC */
1712#ifdef CONFIG_SPE
1713 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1714 current->thread.acc = 0;
1715 current->thread.spefscr = 0;
1716 current->thread.used_spe = 0;
1717#endif /* CONFIG_SPE */
Michael Neulingbc2a9402013-02-13 16:21:40 +00001718#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Michael Neulingbc2a9402013-02-13 16:21:40 +00001719 current->thread.tm_tfhar = 0;
1720 current->thread.tm_texasr = 0;
1721 current->thread.tm_tfiar = 0;
Breno Leitao7f22ced2017-06-05 11:40:59 -03001722 current->thread.load_tm = 0;
Michael Neulingbc2a9402013-02-13 16:21:40 +00001723#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001724}
Anton Blancharde1802b02014-08-20 08:00:02 +10001725EXPORT_SYMBOL(start_thread);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001726
1727#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1728 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1729
1730int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1731{
1732 struct pt_regs *regs = tsk->thread.regs;
1733
1734 /* This is a bit hairy. If we are an SPE enabled processor
1735 * (have embedded fp) we store the IEEE exception enable flags in
1736 * fpexc_mode. fpexc_mode is also used for setting FP exception
1737 * mode (asyn, precise, disabled) for 'Classic' FP. */
1738 if (val & PR_FP_EXC_SW_ENABLE) {
1739#ifdef CONFIG_SPE
Kumar Gala5e14d212007-09-13 01:44:20 -05001740 if (cpu_has_feature(CPU_FTR_SPE)) {
Joseph Myers640e9222013-12-10 23:07:45 +00001741 /*
1742 * When the sticky exception bits are set
1743 * directly by userspace, it must call prctl
1744 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1745 * in the existing prctl settings) or
1746 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1747 * the bits being set). <fenv.h> functions
1748 * saving and restoring the whole
1749 * floating-point environment need to do so
1750 * anyway to restore the prctl settings from
1751 * the saved environment.
1752 */
1753 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
Kumar Gala5e14d212007-09-13 01:44:20 -05001754 tsk->thread.fpexc_mode = val &
1755 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1756 return 0;
1757 } else {
1758 return -EINVAL;
1759 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001760#else
1761 return -EINVAL;
1762#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001763 }
Paul Mackerras06d67d52005-10-10 22:29:05 +10001764
1765 /* on a CONFIG_SPE this does not hurt us. The bits that
1766 * __pack_fe01 use do not overlap with bits used for
1767 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1768 * on CONFIG_SPE implementations are reserved so writing to
1769 * them does not change anything */
1770 if (val > PR_FP_EXC_PRECISE)
1771 return -EINVAL;
1772 tsk->thread.fpexc_mode = __pack_fe01(val);
1773 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1774 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1775 | tsk->thread.fpexc_mode;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001776 return 0;
1777}
1778
1779int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1780{
1781 unsigned int val;
1782
1783 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1784#ifdef CONFIG_SPE
Joseph Myers640e9222013-12-10 23:07:45 +00001785 if (cpu_has_feature(CPU_FTR_SPE)) {
1786 /*
1787 * When the sticky exception bits are set
1788 * directly by userspace, it must call prctl
1789 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1790 * in the existing prctl settings) or
1791 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1792 * the bits being set). <fenv.h> functions
1793 * saving and restoring the whole
1794 * floating-point environment need to do so
1795 * anyway to restore the prctl settings from
1796 * the saved environment.
1797 */
1798 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
Kumar Gala5e14d212007-09-13 01:44:20 -05001799 val = tsk->thread.fpexc_mode;
Joseph Myers640e9222013-12-10 23:07:45 +00001800 } else
Kumar Gala5e14d212007-09-13 01:44:20 -05001801 return -EINVAL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001802#else
1803 return -EINVAL;
1804#endif
1805 else
1806 val = __unpack_fe01(tsk->thread.fpexc_mode);
1807 return put_user(val, (unsigned int __user *) adr);
1808}
1809
Paul Mackerrasfab5db92006-06-07 16:14:40 +10001810int set_endian(struct task_struct *tsk, unsigned int val)
1811{
1812 struct pt_regs *regs = tsk->thread.regs;
1813
1814 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1815 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1816 return -EINVAL;
1817
1818 if (regs == NULL)
1819 return -EINVAL;
1820
1821 if (val == PR_ENDIAN_BIG)
1822 regs->msr &= ~MSR_LE;
1823 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1824 regs->msr |= MSR_LE;
1825 else
1826 return -EINVAL;
1827
1828 return 0;
1829}
1830
1831int get_endian(struct task_struct *tsk, unsigned long adr)
1832{
1833 struct pt_regs *regs = tsk->thread.regs;
1834 unsigned int val;
1835
1836 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1837 !cpu_has_feature(CPU_FTR_REAL_LE))
1838 return -EINVAL;
1839
1840 if (regs == NULL)
1841 return -EINVAL;
1842
1843 if (regs->msr & MSR_LE) {
1844 if (cpu_has_feature(CPU_FTR_REAL_LE))
1845 val = PR_ENDIAN_LITTLE;
1846 else
1847 val = PR_ENDIAN_PPC_LITTLE;
1848 } else
1849 val = PR_ENDIAN_BIG;
1850
1851 return put_user(val, (unsigned int __user *)adr);
1852}
1853
Paul Mackerrase9370ae2006-06-07 16:15:39 +10001854int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1855{
1856 tsk->thread.align_ctl = val;
1857 return 0;
1858}
1859
1860int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1861{
1862 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1863}
1864
Paul Mackerrasbb72c482007-02-19 11:42:42 +11001865static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1866 unsigned long nbytes)
1867{
1868 unsigned long stack_page;
1869 unsigned long cpu = task_cpu(p);
1870
1871 /*
1872 * Avoid crashing if the stack has overflowed and corrupted
1873 * task_cpu(p), which is in the thread_info struct.
1874 */
1875 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1876 stack_page = (unsigned long) hardirq_ctx[cpu];
1877 if (sp >= stack_page + sizeof(struct thread_struct)
1878 && sp <= stack_page + THREAD_SIZE - nbytes)
1879 return 1;
1880
1881 stack_page = (unsigned long) softirq_ctx[cpu];
1882 if (sp >= stack_page + sizeof(struct thread_struct)
1883 && sp <= stack_page + THREAD_SIZE - nbytes)
1884 return 1;
1885 }
1886 return 0;
1887}
1888
Anton Blanchard2f251942006-03-27 11:46:18 +11001889int validate_sp(unsigned long sp, struct task_struct *p,
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001890 unsigned long nbytes)
1891{
Al Viro0cec6fd2006-01-12 01:06:02 -08001892 unsigned long stack_page = (unsigned long)task_stack_page(p);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001893
1894 if (sp >= stack_page + sizeof(struct thread_struct)
1895 && sp <= stack_page + THREAD_SIZE - nbytes)
1896 return 1;
1897
Paul Mackerrasbb72c482007-02-19 11:42:42 +11001898 return valid_irq_stack(sp, p, nbytes);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001899}
1900
Anton Blanchard2f251942006-03-27 11:46:18 +11001901EXPORT_SYMBOL(validate_sp);
1902
Paul Mackerras06d67d52005-10-10 22:29:05 +10001903unsigned long get_wchan(struct task_struct *p)
1904{
1905 unsigned long ip, sp;
1906 int count = 0;
1907
1908 if (!p || p == current || p->state == TASK_RUNNING)
1909 return 0;
1910
1911 sp = p->thread.ksp;
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001912 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
Paul Mackerras06d67d52005-10-10 22:29:05 +10001913 return 0;
1914
1915 do {
1916 sp = *(unsigned long *)sp;
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001917 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
Paul Mackerras06d67d52005-10-10 22:29:05 +10001918 return 0;
1919 if (count > 0) {
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001920 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
Paul Mackerras06d67d52005-10-10 22:29:05 +10001921 if (!in_sched_functions(ip))
1922 return ip;
1923 }
1924 } while (count++ < 16);
1925 return 0;
1926}
Paul Mackerras06d67d52005-10-10 22:29:05 +10001927
Johannes Bergc4d04be2008-11-20 03:24:07 +00001928static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001929
1930void show_stack(struct task_struct *tsk, unsigned long *stack)
1931{
Paul Mackerras06d67d52005-10-10 22:29:05 +10001932 unsigned long sp, ip, lr, newsp;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001933 int count = 0;
Paul Mackerras06d67d52005-10-10 22:29:05 +10001934 int firstframe = 1;
Steven Rostedt6794c782009-02-09 21:10:27 -08001935#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1936 int curr_frame = current->curr_ret_stack;
1937 extern void return_to_handler(void);
Steven Rostedt9135c3c2009-09-15 08:20:15 -07001938 unsigned long rth = (unsigned long)return_to_handler;
Steven Rostedt6794c782009-02-09 21:10:27 -08001939#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001940
1941 sp = (unsigned long) stack;
1942 if (tsk == NULL)
1943 tsk = current;
1944 if (sp == 0) {
1945 if (tsk == current)
Anton Blanchardacf620e2014-10-13 19:41:39 +11001946 sp = current_stack_pointer();
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001947 else
1948 sp = tsk->thread.ksp;
1949 }
1950
Paul Mackerras06d67d52005-10-10 22:29:05 +10001951 lr = 0;
1952 printk("Call Trace:\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001953 do {
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001954 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
Paul Mackerras06d67d52005-10-10 22:29:05 +10001955 return;
1956
1957 stack = (unsigned long *) sp;
1958 newsp = stack[0];
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001959 ip = stack[STACK_FRAME_LR_SAVE];
Paul Mackerras06d67d52005-10-10 22:29:05 +10001960 if (!firstframe || ip != lr) {
Benjamin Herrenschmidt058c78f2008-07-07 13:44:31 +10001961 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
Steven Rostedt6794c782009-02-09 21:10:27 -08001962#ifdef CONFIG_FUNCTION_GRAPH_TRACER
Anton Blanchard7d56c652014-09-17 17:07:03 +10001963 if ((ip == rth) && curr_frame >= 0) {
Michael Ellerman9a1f4902016-11-02 22:20:46 +11001964 pr_cont(" (%pS)",
Steven Rostedt6794c782009-02-09 21:10:27 -08001965 (void *)current->ret_stack[curr_frame].ret);
1966 curr_frame--;
1967 }
1968#endif
Paul Mackerras06d67d52005-10-10 22:29:05 +10001969 if (firstframe)
Michael Ellerman9a1f4902016-11-02 22:20:46 +11001970 pr_cont(" (unreliable)");
1971 pr_cont("\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001972 }
Paul Mackerras06d67d52005-10-10 22:29:05 +10001973 firstframe = 0;
1974
1975 /*
1976 * See if this is an exception frame.
1977 * We look for the "regshere" marker in the current frame.
1978 */
Benjamin Herrenschmidtec2b36b2008-04-17 14:34:59 +10001979 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1980 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
Paul Mackerras06d67d52005-10-10 22:29:05 +10001981 struct pt_regs *regs = (struct pt_regs *)
1982 (sp + STACK_FRAME_OVERHEAD);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001983 lr = regs->link;
Paul Mackerras9be9be22014-06-12 16:53:08 +10001984 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
Benjamin Herrenschmidt058c78f2008-07-07 13:44:31 +10001985 regs->trap, (void *)regs->nip, (void *)lr);
Paul Mackerras06d67d52005-10-10 22:29:05 +10001986 firstframe = 1;
1987 }
1988
1989 sp = newsp;
1990 } while (count++ < kstack_depth_to_print);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001991}
Paul Mackerras06d67d52005-10-10 22:29:05 +10001992
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11001993#ifdef CONFIG_PPC64
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11001994/* Called with hard IRQs off */
Michael Ellerman0e377392013-06-13 21:04:56 +10001995void notrace __ppc64_runlatch_on(void)
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11001996{
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11001997 struct thread_info *ti = current_thread_info();
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11001998 unsigned long ctrl;
1999
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11002000 ctrl = mfspr(SPRN_CTRLF);
2001 ctrl |= CTRL_RUNLATCH;
2002 mtspr(SPRN_CTRLT, ctrl);
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002003
Benjamin Herrenschmidtfae2e0f2012-04-11 10:42:15 +10002004 ti->local_flags |= _TLF_RUNLATCH;
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002005}
2006
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11002007/* Called with hard IRQs off */
Michael Ellerman0e377392013-06-13 21:04:56 +10002008void notrace __ppc64_runlatch_off(void)
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002009{
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11002010 struct thread_info *ti = current_thread_info();
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002011 unsigned long ctrl;
2012
Benjamin Herrenschmidtfae2e0f2012-04-11 10:42:15 +10002013 ti->local_flags &= ~_TLF_RUNLATCH;
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002014
Anton Blanchard4138d652010-08-06 03:28:19 +00002015 ctrl = mfspr(SPRN_CTRLF);
2016 ctrl &= ~CTRL_RUNLATCH;
2017 mtspr(SPRN_CTRLT, ctrl);
Anton Blanchardcb2c9b22006-02-13 14:48:35 +11002018}
Benjamin Herrenschmidtfe1952f2012-03-01 12:45:27 +11002019#endif /* CONFIG_PPC64 */
Benjamin Herrenschmidtf6a61682008-04-18 16:56:17 +10002020
Anton Blanchardd8390882009-02-22 01:50:03 +00002021unsigned long arch_align_stack(unsigned long sp)
2022{
2023 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2024 sp -= get_random_int() & ~PAGE_MASK;
2025 return sp & ~0xf;
2026}
Anton Blanchard912f9ee2009-02-22 01:50:04 +00002027
2028static inline unsigned long brk_rnd(void)
2029{
2030 unsigned long rnd = 0;
2031
2032 /* 8MB for 32bit, 1GB for 64bit */
2033 if (is_32bit_task())
Daniel Cashman5ef11c32016-02-26 15:19:37 -08002034 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
Anton Blanchard912f9ee2009-02-22 01:50:04 +00002035 else
Daniel Cashman5ef11c32016-02-26 15:19:37 -08002036 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
Anton Blanchard912f9ee2009-02-22 01:50:04 +00002037
2038 return rnd << PAGE_SHIFT;
2039}
2040
2041unsigned long arch_randomize_brk(struct mm_struct *mm)
2042{
Anton Blanchard8bbde7a2009-09-21 16:52:35 +00002043 unsigned long base = mm->brk;
2044 unsigned long ret;
2045
Kumar Galace7a35c2009-10-16 07:05:17 +00002046#ifdef CONFIG_PPC_STD_MMU_64
Anton Blanchard8bbde7a2009-09-21 16:52:35 +00002047 /*
2048 * If we are using 1TB segments and we are allowed to randomise
2049 * the heap, we can put it above 1TB so it is backed by a 1TB
2050 * segment. Otherwise the heap will be in the bottom 1TB
2051 * which always uses 256MB segments and this may result in a
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +10002052 * performance penalty. We don't need to worry about radix. For
2053 * radix, mmu_highuser_ssize remains unchanged from 256MB.
Anton Blanchard8bbde7a2009-09-21 16:52:35 +00002054 */
2055 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2056 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2057#endif
2058
2059 ret = PAGE_ALIGN(base + brk_rnd());
Anton Blanchard912f9ee2009-02-22 01:50:04 +00002060
2061 if (ret < mm->brk)
2062 return mm->brk;
2063
2064 return ret;
2065}
Anton Blanchard501cb162009-02-22 01:50:07 +00002066