Paul Walmsley | 7b9487a | 2019-04-30 13:50:58 -0700 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 2 | |
Stephen Boyd | bc8c945 | 2020-04-08 23:44:16 -0700 | [diff] [blame] | 3 | config HAVE_CLK |
| 4 | bool |
| 5 | help |
| 6 | The <linux/clk.h> calls support software clock gating and |
| 7 | thus are a key power management tool on many systems. |
| 8 | |
Shawn Guo | 5c77f56 | 2011-12-20 14:46:38 +0800 | [diff] [blame] | 9 | config HAVE_CLK_PREPARE |
| 10 | bool |
| 11 | |
Stephen Boyd | bbd7ffd | 2020-04-08 23:44:13 -0700 | [diff] [blame] | 12 | config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 13 | bool |
Stephen Boyd | bbd7ffd | 2020-04-08 23:44:13 -0700 | [diff] [blame] | 14 | select HAVE_CLK |
| 15 | help |
| 16 | Select this option when the clock API in <linux/clk.h> is implemented |
| 17 | by platform/architecture code. This method is deprecated. Modern |
| 18 | code should select COMMON_CLK instead and not define a custom |
| 19 | 'struct clk'. |
| 20 | |
| 21 | menuconfig COMMON_CLK |
| 22 | bool "Common Clock Framework" |
| 23 | depends on !HAVE_LEGACY_CLK |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 24 | select HAVE_CLK_PREPARE |
Arnd Bergmann | 2f4574d | 2021-05-31 11:48:49 +0200 | [diff] [blame] | 25 | select HAVE_CLK |
Pranith Kumar | 83fe27e | 2014-12-05 11:24:45 -0500 | [diff] [blame] | 26 | select SRCU |
Andy Shevchenko | 0777591 | 2015-09-22 18:54:11 +0300 | [diff] [blame] | 27 | select RATIONAL |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 28 | help |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 29 | The common clock framework is a single definition of struct |
| 30 | clk, useful across many platforms, as well as an |
| 31 | implementation of the clock API in include/linux/clk.h. |
| 32 | Architectures utilizing the common struct clk should select |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 33 | this option. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 34 | |
Stephen Boyd | bbd7ffd | 2020-04-08 23:44:13 -0700 | [diff] [blame] | 35 | if COMMON_CLK |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 36 | |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 37 | config COMMON_CLK_WM831X |
| 38 | tristate "Clock driver for WM831x/2x PMICs" |
| 39 | depends on MFD_WM831X |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 40 | help |
Krzysztof Kozlowski | 333d2d1 | 2019-11-21 04:18:55 +0100 | [diff] [blame] | 41 | Supports the clocking subsystem of the WM831x/2x series of |
Masanari Iida | fe4e437 | 2014-10-17 00:09:24 +0900 | [diff] [blame] | 42 | PMICs from Wolfson Microelectronics. |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 43 | |
Pawel Moll | 5ee2b87 | 2013-09-17 17:16:15 +0100 | [diff] [blame] | 44 | source "drivers/clk/versatile/Kconfig" |
Linus Walleij | f9a6aa4 | 2012-08-06 18:32:08 +0200 | [diff] [blame] | 45 | |
Eugeniy Paltsev | daeeb43 | 2017-08-25 20:39:14 +0300 | [diff] [blame] | 46 | config CLK_HSDK |
| 47 | bool "PLL Driver for HSDK platform" |
Geert Uytterhoeven | f6bade6 | 2020-08-07 11:43:51 +0200 | [diff] [blame] | 48 | depends on ARC_SOC_HSDK || COMPILE_TEST |
Geert Uytterhoeven | bd8548d | 2020-08-03 10:48:35 +0200 | [diff] [blame] | 49 | depends on HAS_IOMEM |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 50 | help |
Eugeniy Paltsev | daeeb43 | 2017-08-25 20:39:14 +0300 | [diff] [blame] | 51 | This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs |
| 52 | control. |
| 53 | |
Liam Beguin | 3bc61cf | 2021-04-22 20:40:55 -0400 | [diff] [blame] | 54 | config LMK04832 |
| 55 | tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner" |
Stephen Boyd | 97a1c5c | 2021-06-28 23:07:50 -0700 | [diff] [blame] | 56 | depends on SPI |
Liam Beguin | 3bc61cf | 2021-04-22 20:40:55 -0400 | [diff] [blame] | 57 | select REGMAP_SPI |
| 58 | help |
| 59 | Say yes here to build support for Texas Instruments' LMK04832 Ultra |
| 60 | Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs |
| 61 | |
Jonghwa Lee | 73118e6 | 2012-08-28 17:54:28 +0900 | [diff] [blame] | 62 | config COMMON_CLK_MAX77686 |
Laxman Dewangan | 5a227cd | 2016-06-17 16:21:07 +0530 | [diff] [blame] | 63 | tristate "Clock driver for Maxim 77620/77686/77802 MFD" |
Krzysztof Kozlowski | 9c1b305 | 2016-10-02 22:58:14 +0200 | [diff] [blame] | 64 | depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 65 | help |
Laxman Dewangan | 5a227cd | 2016-06-17 16:21:07 +0530 | [diff] [blame] | 66 | This driver supports Maxim 77620/77686/77802 crystal oscillator |
| 67 | clock. |
Javier Martinez Canillas | 83ccf16 | 2014-08-18 10:33:03 +0200 | [diff] [blame] | 68 | |
Daniel Mack | 33f5104 | 2018-07-06 20:53:03 +0200 | [diff] [blame] | 69 | config COMMON_CLK_MAX9485 |
| 70 | tristate "Maxim 9485 Programmable Clock Generator" |
| 71 | depends on I2C |
| 72 | help |
| 73 | This driver supports Maxim 9485 Programmable Audio Clock Generator |
| 74 | |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 75 | config COMMON_CLK_RK808 |
Tony Xie | 8ed14401 | 2019-06-21 06:34:55 -0400 | [diff] [blame] | 76 | tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 77 | depends on MFD_RK808 |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 78 | help |
Tony Xie | 8ed14401 | 2019-06-21 06:34:55 -0400 | [diff] [blame] | 79 | This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. |
| 80 | These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. |
| 81 | Clkout1 is always on, Clkout2 can off by control register. |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 82 | |
Daniel Lezcano | b68adc2 | 2017-04-17 19:19:25 +0200 | [diff] [blame] | 83 | config COMMON_CLK_HI655X |
Riku Voipio | 3a49afb | 2018-03-12 12:49:45 +0200 | [diff] [blame] | 84 | tristate "Clock driver for Hi655x" if EXPERT |
| 85 | depends on (MFD_HI655X_PMIC || COMPILE_TEST) |
| 86 | depends on REGMAP |
| 87 | default MFD_HI655X_PMIC |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 88 | help |
Daniel Lezcano | b68adc2 | 2017-04-17 19:19:25 +0200 | [diff] [blame] | 89 | This driver supports the hi655x PMIC clock. This |
| 90 | multi-function device has one fixed-rate oscillator, clocked |
| 91 | at 32KHz. |
| 92 | |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 93 | config COMMON_CLK_SCMI |
| 94 | tristate "Clock driver controlled via SCMI interface" |
| 95 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 96 | help |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 97 | This driver provides support for clocks that are controlled |
| 98 | by firmware that implements the SCMI interface. |
| 99 | |
| 100 | This driver uses SCMI Message Protocol to interact with the |
| 101 | firmware providing all the clock controls. |
| 102 | |
Sudeep Holla | cd52c2a | 2015-03-30 10:59:52 +0100 | [diff] [blame] | 103 | config COMMON_CLK_SCPI |
| 104 | tristate "Clock driver controlled via SCPI interface" |
| 105 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 106 | help |
Sudeep Holla | cd52c2a | 2015-03-30 10:59:52 +0100 | [diff] [blame] | 107 | This driver provides support for clocks that are controlled |
| 108 | by firmware that implements the SCPI interface. |
| 109 | |
| 110 | This driver uses SCPI Message Protocol to interact with the |
| 111 | firmware providing all the clock controls. |
| 112 | |
Mike Looijmans | 3044a86 | 2019-05-17 15:23:52 +0200 | [diff] [blame] | 113 | config COMMON_CLK_SI5341 |
| 114 | tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices" |
| 115 | depends on I2C |
| 116 | select REGMAP_I2C |
| 117 | help |
| 118 | This driver supports Silicon Labs Si5341 and Si5340 programmable clock |
| 119 | generators. Not all features of these chips are currently supported |
| 120 | by the driver, in particular it only supports XTAL input. The chip can |
| 121 | be pre-programmed to support other configurations and features not yet |
| 122 | implemented in the driver. |
| 123 | |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 124 | config COMMON_CLK_SI5351 |
| 125 | tristate "Clock driver for SiLabs 5351A/B/C" |
| 126 | depends on I2C |
| 127 | select REGMAP_I2C |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 128 | help |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 129 | This driver supports Silicon Labs 5351A/B/C programmable clock |
| 130 | generators. |
| 131 | |
Mike Looijmans | 8ce20e6 | 2015-10-02 09:15:29 +0200 | [diff] [blame] | 132 | config COMMON_CLK_SI514 |
| 133 | tristate "Clock driver for SiLabs 514 devices" |
| 134 | depends on I2C |
| 135 | depends on OF |
| 136 | select REGMAP_I2C |
| 137 | help |
Mike Looijmans | 8ce20e6 | 2015-10-02 09:15:29 +0200 | [diff] [blame] | 138 | This driver supports the Silicon Labs 514 programmable clock |
| 139 | generator. |
| 140 | |
Mike Looijmans | 953cc3e | 2018-03-20 09:15:41 +0100 | [diff] [blame] | 141 | config COMMON_CLK_SI544 |
| 142 | tristate "Clock driver for SiLabs 544 devices" |
| 143 | depends on I2C |
| 144 | select REGMAP_I2C |
| 145 | help |
Mike Looijmans | 953cc3e | 2018-03-20 09:15:41 +0100 | [diff] [blame] | 146 | This driver supports the Silicon Labs 544 programmable clock |
| 147 | generator. |
| 148 | |
Soren Brinkmann | 1459c83 | 2013-09-21 16:40:39 -0700 | [diff] [blame] | 149 | config COMMON_CLK_SI570 |
| 150 | tristate "Clock driver for SiLabs 570 and compatible devices" |
| 151 | depends on I2C |
| 152 | depends on OF |
| 153 | select REGMAP_I2C |
| 154 | help |
Soren Brinkmann | 1459c83 | 2013-09-21 16:40:39 -0700 | [diff] [blame] | 155 | This driver supports Silicon Labs 570/571/598/599 programmable |
| 156 | clock generators. |
| 157 | |
Manivannan Sadhasivam | 1ab4601 | 2019-11-15 21:59:00 +0530 | [diff] [blame] | 158 | config COMMON_CLK_BM1880 |
| 159 | bool "Clock driver for Bitmain BM1880 SoC" |
| 160 | depends on ARCH_BITMAIN || COMPILE_TEST |
| 161 | default ARCH_BITMAIN |
| 162 | help |
| 163 | This driver supports the clocks on Bitmain BM1880 SoC. |
| 164 | |
Mike Looijmans | c7d5a46b | 2015-11-03 12:55:54 +0100 | [diff] [blame] | 165 | config COMMON_CLK_CDCE706 |
| 166 | tristate "Clock driver for TI CDCE706 clock synthesizer" |
| 167 | depends on I2C |
| 168 | select REGMAP_I2C |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 169 | help |
Mike Looijmans | c7d5a46b | 2015-11-03 12:55:54 +0100 | [diff] [blame] | 170 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
| 171 | |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 172 | config COMMON_CLK_CDCE925 |
Akinobu Mita | 5508124 | 2017-01-01 03:04:36 +0900 | [diff] [blame] | 173 | tristate "Clock driver for TI CDCE913/925/937/949 devices" |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 174 | depends on I2C |
| 175 | depends on OF |
| 176 | select REGMAP_I2C |
| 177 | help |
Akinobu Mita | 5508124 | 2017-01-01 03:04:36 +0900 | [diff] [blame] | 178 | This driver supports the TI CDCE913/925/937/949 programmable clock |
| 179 | synthesizer. Each chip has different number of PLLs and outputs. |
| 180 | For example, the CDCE925 contains two PLLs with spread-spectrum |
| 181 | clocking support and five output dividers. The driver only supports |
| 182 | the following setup, and uses a fixed setting for the output muxes. |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 183 | Y1 is derived from the input clock |
| 184 | Y2 and Y3 derive from PLL1 |
| 185 | Y4 and Y5 derive from PLL2 |
| 186 | Given a target output frequency, the driver will set the PLL and |
| 187 | divider to best approximate the desired output. |
| 188 | |
Kuninori Morimoto | 64dfbe2 | 2015-11-10 01:15:09 +0000 | [diff] [blame] | 189 | config COMMON_CLK_CS2000_CP |
| 190 | tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" |
| 191 | depends on I2C |
| 192 | help |
| 193 | If you say yes here you get support for the CS2000 clock multiplier. |
| 194 | |
Michael Walle | fcf77be | 2020-11-08 19:51:11 +0100 | [diff] [blame] | 195 | config COMMON_CLK_FSL_FLEXSPI |
| 196 | tristate "Clock driver for FlexSPI on Layerscape SoCs" |
| 197 | depends on ARCH_LAYERSCAPE || COMPILE_TEST |
| 198 | default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI |
| 199 | help |
| 200 | On Layerscape SoCs there is a special clock for the FlexSPI |
| 201 | interface. |
| 202 | |
Michael Walle | 9cd1020 | 2020-01-03 00:11:01 +0100 | [diff] [blame] | 203 | config COMMON_CLK_FSL_SAI |
| 204 | bool "Clock driver for BCLK of Freescale SAI cores" |
| 205 | depends on ARCH_LAYERSCAPE || COMPILE_TEST |
| 206 | help |
| 207 | This driver supports the Freescale SAI (Synchronous Audio Interface) |
| 208 | to be used as a generic clock output. Some SoCs have restrictions |
| 209 | regarding the possible pin multiplexer settings. Eg. on some SoCs |
| 210 | two SAI interfaces can only be enabled together. If just one is |
| 211 | needed, the BCLK pin of the second one can be used as general |
| 212 | purpose clock output. Ideally, it can be used to drive an audio |
| 213 | codec (sometimes known as MCLK). |
| 214 | |
Linus Walleij | 846423f | 2017-06-21 09:59:52 +0200 | [diff] [blame] | 215 | config COMMON_CLK_GEMINI |
| 216 | bool "Clock driver for Cortina Systems Gemini SoC" |
| 217 | depends on ARCH_GEMINI || COMPILE_TEST |
| 218 | select MFD_SYSCON |
| 219 | select RESET_CONTROLLER |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 220 | help |
Linus Walleij | 846423f | 2017-06-21 09:59:52 +0200 | [diff] [blame] | 221 | This driver supports the SoC clocks on the Cortina Systems Gemini |
| 222 | platform, also known as SL3516 or CS3516. |
| 223 | |
Joel Stanley | 5eda5d7 | 2017-12-22 13:15:18 +1030 | [diff] [blame] | 224 | config COMMON_CLK_ASPEED |
| 225 | bool "Clock driver for Aspeed BMC SoCs" |
| 226 | depends on ARCH_ASPEED || COMPILE_TEST |
| 227 | default ARCH_ASPEED |
| 228 | select MFD_SYSCON |
| 229 | select RESET_CONTROLLER |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 230 | help |
Joel Stanley | 5eda5d7 | 2017-12-22 13:15:18 +1030 | [diff] [blame] | 231 | This driver supports the SoC clocks on the Aspeed BMC platforms. |
| 232 | |
| 233 | The G4 and G5 series, including the ast2400 and ast2500, are supported |
| 234 | by this driver. |
| 235 | |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 236 | config COMMON_CLK_S2MPS11 |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 237 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
Krzysztof Kozlowski | 9c1b305 | 2016-10-02 22:58:14 +0200 | [diff] [blame] | 238 | depends on MFD_SEC_CORE || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 239 | help |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 240 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
| 241 | clock. These multi-function devices have two (S2MPS14) or three |
| 242 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 243 | |
Peter Ujfalusi | f9f8c04 | 2012-09-14 17:30:27 +0300 | [diff] [blame] | 244 | config CLK_TWL6040 |
| 245 | tristate "External McPDM functional clock from twl6040" |
| 246 | depends on TWL6040_CORE |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 247 | help |
Peter Ujfalusi | f9f8c04 | 2012-09-14 17:30:27 +0300 | [diff] [blame] | 248 | Enable the external functional clock support on OMAP4+ platforms for |
| 249 | McPDM. McPDM module is using the external bit clock on the McPDM bus |
| 250 | as functional clock. |
| 251 | |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 252 | config COMMON_CLK_AXI_CLKGEN |
| 253 | tristate "AXI clkgen driver" |
Alexandru Ardelean | 324a810 | 2021-02-01 17:12:42 +0200 | [diff] [blame] | 254 | depends on HAS_IOMEM || COMPILE_TEST |
| 255 | depends on OF |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 256 | help |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 257 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
| 258 | FPGAs. It is commonly used in Analog Devices' reference designs. |
| 259 | |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 260 | config CLK_QORIQ |
| 261 | bool "Clock driver for Freescale QorIQ platforms" |
Geert Uytterhoeven | b8bcece | 2020-11-10 16:47:50 +0100 | [diff] [blame] | 262 | depends on OF |
| 263 | depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 264 | help |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 265 | This adds the clock driver support for Freescale QorIQ platforms |
| 266 | using common clock framework. |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 267 | |
Wen He | d37010a | 2019-12-13 16:34:02 +0800 | [diff] [blame] | 268 | config CLK_LS1028A_PLLDIG |
| 269 | tristate "Clock driver for LS1028A Display output" |
| 270 | depends on ARCH_LAYERSCAPE || COMPILE_TEST |
| 271 | default ARCH_LAYERSCAPE |
| 272 | help |
| 273 | This driver support the Display output interfaces(LCD, DPHY) pixel clocks |
| 274 | of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all |
| 275 | features of the PLL are currently supported by the driver. By default, |
| 276 | configured bypass mode with this PLL. |
| 277 | |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 278 | config COMMON_CLK_XGENE |
| 279 | bool "Clock driver for APM XGene SoC" |
Marc Gonzalez | ce9a104 | 2019-06-12 17:03:56 +0200 | [diff] [blame] | 280 | default ARCH_XGENE |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 281 | depends on ARM64 || COMPILE_TEST |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 282 | help |
Christophe JAILLET | 4fe02fe | 2020-05-03 21:03:27 +0200 | [diff] [blame] | 283 | Support for the APM X-Gene SoC reference, PLL, and device clocks. |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 284 | |
Charles Keepax | 76c5478 | 2019-03-19 13:37:00 +0000 | [diff] [blame] | 285 | config COMMON_CLK_LOCHNAGAR |
| 286 | tristate "Cirrus Logic Lochnagar clock driver" |
| 287 | depends on MFD_LOCHNAGAR |
| 288 | help |
| 289 | This driver supports the clocking features of the Cirrus Logic |
| 290 | Lochnagar audio development board. |
| 291 | |
Vladimir Zapolskiy | f7c82a6 | 2015-12-06 12:45:57 +0200 | [diff] [blame] | 292 | config COMMON_CLK_NXP |
| 293 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) |
| 294 | select REGMAP_MMIO if ARCH_LPC32XX |
Ezequiel Garcia | 72ad679 | 2016-05-16 12:45:36 -0300 | [diff] [blame] | 295 | select MFD_SYSCON if ARCH_LPC18XX |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 296 | help |
Vladimir Zapolskiy | f7c82a6 | 2015-12-06 12:45:57 +0200 | [diff] [blame] | 297 | Support for clock providers on NXP platforms. |
| 298 | |
Peter Ujfalusi | 942d1d6 | 2014-06-27 09:01:11 +0300 | [diff] [blame] | 299 | config COMMON_CLK_PALMAS |
| 300 | tristate "Clock driver for TI Palmas devices" |
| 301 | depends on MFD_PALMAS |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 302 | help |
Peter Ujfalusi | 942d1d6 | 2014-06-27 09:01:11 +0300 | [diff] [blame] | 303 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
| 304 | using common clock framework. |
| 305 | |
Philipp Zabel | 9a74ccd | 2015-02-13 20:18:52 +0100 | [diff] [blame] | 306 | config COMMON_CLK_PWM |
| 307 | tristate "Clock driver for PWMs used as clock outputs" |
| 308 | depends on PWM |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 309 | help |
Philipp Zabel | 9a74ccd | 2015-02-13 20:18:52 +0100 | [diff] [blame] | 310 | Adapter driver so that any PWM output can be (mis)used as clock signal |
| 311 | at 50% duty cycle. |
| 312 | |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 313 | config COMMON_CLK_PXA |
| 314 | def_bool COMMON_CLK && ARCH_PXA |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 315 | help |
Mike Looijmans | 048c58b | 2015-11-03 12:55:53 +0100 | [diff] [blame] | 316 | Support for the Marvell PXA SoC. |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 317 | |
Purna Chandra Mandal | ce6e118 | 2016-05-13 13:22:40 +0530 | [diff] [blame] | 318 | config COMMON_CLK_PIC32 |
| 319 | def_bool COMMON_CLK && MACH_PIC32 |
| 320 | |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 321 | config COMMON_CLK_OXNAS |
| 322 | bool "Clock driver for the OXNAS SoC Family" |
Jean Delvare | 821f994 | 2016-07-07 09:18:44 +0200 | [diff] [blame] | 323 | depends on ARCH_OXNAS || COMPILE_TEST |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 324 | select MFD_SYSCON |
Masahiro Yamada | a7f7f62 | 2020-06-14 01:50:22 +0900 | [diff] [blame] | 325 | help |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 326 | Support for the OXNAS SoC Family clocks. |
| 327 | |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 328 | config COMMON_CLK_VC5 |
Marek Vasut | dbf6b16 | 2017-07-09 15:28:14 +0200 | [diff] [blame] | 329 | tristate "Clock driver for IDT VersaClock 5,6 devices" |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 330 | depends on I2C |
| 331 | depends on OF |
| 332 | select REGMAP_I2C |
| 333 | help |
Marek Vasut | dbf6b16 | 2017-07-09 15:28:14 +0200 | [diff] [blame] | 334 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
| 335 | programmable clock generators. |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 336 | |
Gabriel Fernandez | 9bee94e | 2018-03-08 17:53:55 +0100 | [diff] [blame] | 337 | config COMMON_CLK_STM32MP157 |
| 338 | def_bool COMMON_CLK && MACH_STM32MP157 |
| 339 | help |
Gabriel Fernandez | 9bee94e | 2018-03-08 17:53:55 +0100 | [diff] [blame] | 340 | Support for stm32mp157 SoC family clocks |
| 341 | |
Gabriel Fernandez | 21e7433 | 2021-06-17 07:18:14 +0200 | [diff] [blame] | 342 | config COMMON_CLK_STM32MP157_SCMI |
| 343 | bool "stm32mp157 Clock driver with Trusted Firmware" |
| 344 | depends on COMMON_CLK_STM32MP157 |
| 345 | select COMMON_CLK_SCMI |
| 346 | select ARM_SCMI_PROTOCOL |
| 347 | default y |
| 348 | help |
| 349 | Support for stm32mp157 SoC family clocks with Trusted Firmware using |
| 350 | SCMI protocol. |
| 351 | |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 352 | config COMMON_CLK_STM32F |
Gabriel Fernandez | 9a16060 | 2018-05-03 08:40:09 +0200 | [diff] [blame] | 353 | def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 354 | help |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 355 | Support for stm32f4 and stm32f7 SoC families clocks |
| 356 | |
| 357 | config COMMON_CLK_STM32H7 |
Gabriel Fernandez | 9a16060 | 2018-05-03 08:40:09 +0200 | [diff] [blame] | 358 | def_bool COMMON_CLK && MACH_STM32H743 |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 359 | help |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 360 | Support for stm32h7 SoC family clocks |
| 361 | |
Lubomir Rintel | a9372a5 | 2019-05-16 08:19:37 +0200 | [diff] [blame] | 362 | config COMMON_CLK_MMP2 |
| 363 | def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) |
| 364 | help |
| 365 | Support for Marvell MMP2 and MMP3 SoC clocks |
| 366 | |
Lubomir Rintel | 725262d | 2020-05-20 00:41:51 +0200 | [diff] [blame] | 367 | config COMMON_CLK_MMP2_AUDIO |
| 368 | tristate "Clock driver for MMP2 Audio subsystem" |
| 369 | depends on COMMON_CLK_MMP2 || COMPILE_TEST |
| 370 | help |
| 371 | This driver supports clocks for Audio subsystem on MMP2 SoC. |
| 372 | |
Matti Vaittinen | 2e62246 | 2018-12-07 12:01:44 +0200 | [diff] [blame] | 373 | config COMMON_CLK_BD718XX |
Matti Vaittinen | ae866de | 2020-01-20 15:44:19 +0200 | [diff] [blame] | 374 | tristate "Clock driver for 32K clk gates on ROHM PMICs" |
Matti Vaittinen | fa5b654 | 2021-05-25 13:15:10 +0300 | [diff] [blame] | 375 | depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828 |
Matti Vaittinen | 2e62246 | 2018-12-07 12:01:44 +0200 | [diff] [blame] | 376 | help |
Matti Vaittinen | fa5b654 | 2021-05-25 13:15:10 +0300 | [diff] [blame] | 377 | This driver supports ROHM BD71837, BD71847, BD71850, BD71815 |
| 378 | and BD71828 PMICs clock gates. |
Matti Vaittinen | 2e62246 | 2018-12-07 12:01:44 +0200 | [diff] [blame] | 379 | |
Jan Kotas | 50cc4ca | 2018-12-13 12:49:29 +0000 | [diff] [blame] | 380 | config COMMON_CLK_FIXED_MMIO |
| 381 | bool "Clock driver for Memory Mapped Fixed values" |
| 382 | depends on COMMON_CLK && OF |
| 383 | help |
| 384 | Support for Memory Mapped IO Fixed clocks |
| 385 | |
Damien Le Moal | c6ca761 | 2021-02-10 14:02:14 +0900 | [diff] [blame] | 386 | config COMMON_CLK_K210 |
| 387 | bool "Clock driver for the Canaan Kendryte K210 SoC" |
| 388 | depends on OF && RISCV && SOC_CANAAN |
| 389 | default SOC_CANAAN |
| 390 | help |
| 391 | Support for the Canaan Kendryte K210 RISC-V SoC clocks. |
| 392 | |
Manivannan Sadhasivam | 3495e29 | 2018-03-26 23:08:57 +0530 | [diff] [blame] | 393 | source "drivers/clk/actions/Kconfig" |
Paul Walmsley | 7b9487a | 2019-04-30 13:50:58 -0700 | [diff] [blame] | 394 | source "drivers/clk/analogbits/Kconfig" |
Serge Semin | b7d950b | 2020-05-27 01:20:55 +0300 | [diff] [blame] | 395 | source "drivers/clk/baikal-t1/Kconfig" |
Stephen Boyd | 64a12c5 | 2015-05-14 17:38:21 -0700 | [diff] [blame] | 396 | source "drivers/clk/bcm/Kconfig" |
Bintian Wang | 72ea486 | 2015-05-29 10:08:38 +0800 | [diff] [blame] | 397 | source "drivers/clk/hisilicon/Kconfig" |
Paul Burton | 6b0fd6c | 2017-06-17 13:52:47 -0700 | [diff] [blame] | 398 | source "drivers/clk/imgtec/Kconfig" |
Aisheng Dong | 3a48d91 | 2018-12-13 15:42:50 +0000 | [diff] [blame] | 399 | source "drivers/clk/imx/Kconfig" |
Paul Cercueil | 0880fb8 | 2018-08-23 15:17:41 +0200 | [diff] [blame] | 400 | source "drivers/clk/ingenic/Kconfig" |
Tero Kristo | b745c07 | 2017-06-13 10:09:27 +0300 | [diff] [blame] | 401 | source "drivers/clk/keystone/Kconfig" |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 402 | source "drivers/clk/mediatek/Kconfig" |
Michael Turquette | cb7c47d | 2016-05-23 14:29:13 -0700 | [diff] [blame] | 403 | source "drivers/clk/meson/Kconfig" |
Daniel Palmer | bef7a78 | 2021-02-11 14:22:03 +0900 | [diff] [blame] | 404 | source "drivers/clk/mstar/Kconfig" |
Sebastian Hesselbarth | 97fa4cf | 2012-11-17 15:22:22 +0100 | [diff] [blame] | 405 | source "drivers/clk/mvebu/Kconfig" |
Jiaxun Yang | 9042920 | 2021-07-23 10:25:37 +0800 | [diff] [blame] | 406 | source "drivers/clk/pistachio/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 407 | source "drivers/clk/qcom/Kconfig" |
Sergio Paracuellos | 48df7a2 | 2021-04-10 07:50:56 +0200 | [diff] [blame] | 408 | source "drivers/clk/ralink/Kconfig" |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 409 | source "drivers/clk/renesas/Kconfig" |
Elaine Zhang | 4d98ed1 | 2020-09-14 10:23:04 +0800 | [diff] [blame] | 410 | source "drivers/clk/rockchip/Kconfig" |
Pankaj Dubey | 4ce9b85e | 2014-05-08 13:07:08 +0900 | [diff] [blame] | 411 | source "drivers/clk/samsung/Kconfig" |
Paul Walmsley | 30b8e27 | 2019-04-30 13:51:00 -0700 | [diff] [blame] | 412 | source "drivers/clk/sifive/Kconfig" |
Krzysztof Kozlowski | 3b218ba | 2021-03-11 16:25:31 +0100 | [diff] [blame] | 413 | source "drivers/clk/socfpga/Kconfig" |
Chunyan Zhang | d41f59f | 2017-12-07 20:57:05 +0800 | [diff] [blame] | 414 | source "drivers/clk/sprd/Kconfig" |
Maxime Ripard | 49c726d | 2019-03-19 15:37:59 +0100 | [diff] [blame] | 415 | source "drivers/clk/sunxi/Kconfig" |
Maxime Ripard | 1d80c14 | 2016-06-29 21:05:23 +0200 | [diff] [blame] | 416 | source "drivers/clk/sunxi-ng/Kconfig" |
Thierry Reding | 31b52ba | 2015-04-01 09:10:58 +0200 | [diff] [blame] | 417 | source "drivers/clk/tegra/Kconfig" |
Tony Lindgren | 2133049 | 2016-02-26 09:35:05 -0800 | [diff] [blame] | 418 | source "drivers/clk/ti/Kconfig" |
Masahiro Yamada | 734d82f | 2016-09-16 16:40:03 +0900 | [diff] [blame] | 419 | source "drivers/clk/uniphier/Kconfig" |
Rahul Tanwar | d058fd9 | 2020-04-17 13:54:47 +0800 | [diff] [blame] | 420 | source "drivers/clk/x86/Kconfig" |
Michael Tretter | a2fe7ba | 2021-01-21 08:16:59 +0100 | [diff] [blame] | 421 | source "drivers/clk/xilinx/Kconfig" |
Jolly Shah | 3fde0e1 | 2018-10-08 11:21:46 -0700 | [diff] [blame] | 422 | source "drivers/clk/zynqmp/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 423 | |
Stephen Boyd | bbd7ffd | 2020-04-08 23:44:13 -0700 | [diff] [blame] | 424 | endif |