Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 1 | |
| 2 | config CLKDEV_LOOKUP |
| 3 | bool |
| 4 | select HAVE_CLK |
Kyungmin Park | aa3831c | 2011-07-18 16:34:54 +0900 | [diff] [blame] | 5 | |
Shawn Guo | 5c77f56 | 2011-12-20 14:46:38 +0800 | [diff] [blame] | 6 | config HAVE_CLK_PREPARE |
| 7 | bool |
| 8 | |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 9 | config COMMON_CLK |
| 10 | bool |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 11 | select HAVE_CLK_PREPARE |
Rob Herring | 01033be | 2012-04-09 15:24:58 -0500 | [diff] [blame] | 12 | select CLKDEV_LOOKUP |
Pranith Kumar | 83fe27e | 2014-12-05 11:24:45 -0500 | [diff] [blame] | 13 | select SRCU |
Andy Shevchenko | 0777591 | 2015-09-22 18:54:11 +0300 | [diff] [blame] | 14 | select RATIONAL |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 15 | ---help--- |
| 16 | The common clock framework is a single definition of struct |
| 17 | clk, useful across many platforms, as well as an |
| 18 | implementation of the clock API in include/linux/clk.h. |
| 19 | Architectures utilizing the common struct clk should select |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 20 | this option. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 21 | |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 22 | menu "Common Clock Framework" |
| 23 | depends on COMMON_CLK |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 24 | |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 25 | config COMMON_CLK_WM831X |
| 26 | tristate "Clock driver for WM831x/2x PMICs" |
| 27 | depends on MFD_WM831X |
| 28 | ---help--- |
| 29 | Supports the clocking subsystem of the WM831x/2x series of |
Masanari Iida | fe4e437 | 2014-10-17 00:09:24 +0900 | [diff] [blame] | 30 | PMICs from Wolfson Microelectronics. |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 31 | |
Pawel Moll | 5ee2b87 | 2013-09-17 17:16:15 +0100 | [diff] [blame] | 32 | source "drivers/clk/versatile/Kconfig" |
Linus Walleij | f9a6aa4 | 2012-08-06 18:32:08 +0200 | [diff] [blame] | 33 | |
Eugeniy Paltsev | daeeb43 | 2017-08-25 20:39:14 +0300 | [diff] [blame] | 34 | config CLK_HSDK |
| 35 | bool "PLL Driver for HSDK platform" |
| 36 | depends on OF || COMPILE_TEST |
| 37 | ---help--- |
| 38 | This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs |
| 39 | control. |
| 40 | |
Jonghwa Lee | 73118e6 | 2012-08-28 17:54:28 +0900 | [diff] [blame] | 41 | config COMMON_CLK_MAX77686 |
Laxman Dewangan | 5a227cd | 2016-06-17 16:21:07 +0530 | [diff] [blame] | 42 | tristate "Clock driver for Maxim 77620/77686/77802 MFD" |
Krzysztof Kozlowski | 9c1b305 | 2016-10-02 22:58:14 +0200 | [diff] [blame] | 43 | depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |
Jonghwa Lee | 73118e6 | 2012-08-28 17:54:28 +0900 | [diff] [blame] | 44 | ---help--- |
Laxman Dewangan | 5a227cd | 2016-06-17 16:21:07 +0530 | [diff] [blame] | 45 | This driver supports Maxim 77620/77686/77802 crystal oscillator |
| 46 | clock. |
Javier Martinez Canillas | 83ccf16 | 2014-08-18 10:33:03 +0200 | [diff] [blame] | 47 | |
Daniel Mack | 33f5104 | 2018-07-06 20:53:03 +0200 | [diff] [blame] | 48 | config COMMON_CLK_MAX9485 |
| 49 | tristate "Maxim 9485 Programmable Clock Generator" |
| 50 | depends on I2C |
| 51 | help |
| 52 | This driver supports Maxim 9485 Programmable Audio Clock Generator |
| 53 | |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 54 | config COMMON_CLK_RK808 |
Elaine Zhang | 65bc9d7 | 2017-08-16 10:00:03 +0800 | [diff] [blame] | 55 | tristate "Clock driver for RK805/RK808/RK818" |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 56 | depends on MFD_RK808 |
| 57 | ---help--- |
Elaine Zhang | 65bc9d7 | 2017-08-16 10:00:03 +0800 | [diff] [blame] | 58 | This driver supports RK805, RK808 and RK818 crystal oscillator clock. These |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 59 | multi-function devices have two fixed-rate oscillators, |
| 60 | clocked at 32KHz each. Clkout1 is always on, Clkout2 can off |
| 61 | by control register. |
| 62 | |
Daniel Lezcano | b68adc2 | 2017-04-17 19:19:25 +0200 | [diff] [blame] | 63 | config COMMON_CLK_HI655X |
Riku Voipio | 3a49afb | 2018-03-12 12:49:45 +0200 | [diff] [blame] | 64 | tristate "Clock driver for Hi655x" if EXPERT |
| 65 | depends on (MFD_HI655X_PMIC || COMPILE_TEST) |
| 66 | depends on REGMAP |
| 67 | default MFD_HI655X_PMIC |
Daniel Lezcano | b68adc2 | 2017-04-17 19:19:25 +0200 | [diff] [blame] | 68 | ---help--- |
| 69 | This driver supports the hi655x PMIC clock. This |
| 70 | multi-function device has one fixed-rate oscillator, clocked |
| 71 | at 32KHz. |
| 72 | |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 73 | config COMMON_CLK_SCMI |
| 74 | tristate "Clock driver controlled via SCMI interface" |
| 75 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST |
| 76 | ---help--- |
| 77 | This driver provides support for clocks that are controlled |
| 78 | by firmware that implements the SCMI interface. |
| 79 | |
| 80 | This driver uses SCMI Message Protocol to interact with the |
| 81 | firmware providing all the clock controls. |
| 82 | |
Sudeep Holla | cd52c2a | 2015-03-30 10:59:52 +0100 | [diff] [blame] | 83 | config COMMON_CLK_SCPI |
| 84 | tristate "Clock driver controlled via SCPI interface" |
| 85 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST |
| 86 | ---help--- |
| 87 | This driver provides support for clocks that are controlled |
| 88 | by firmware that implements the SCPI interface. |
| 89 | |
| 90 | This driver uses SCPI Message Protocol to interact with the |
| 91 | firmware providing all the clock controls. |
| 92 | |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 93 | config COMMON_CLK_SI5351 |
| 94 | tristate "Clock driver for SiLabs 5351A/B/C" |
| 95 | depends on I2C |
| 96 | select REGMAP_I2C |
| 97 | select RATIONAL |
| 98 | ---help--- |
| 99 | This driver supports Silicon Labs 5351A/B/C programmable clock |
| 100 | generators. |
| 101 | |
Mike Looijmans | 8ce20e6 | 2015-10-02 09:15:29 +0200 | [diff] [blame] | 102 | config COMMON_CLK_SI514 |
| 103 | tristate "Clock driver for SiLabs 514 devices" |
| 104 | depends on I2C |
| 105 | depends on OF |
| 106 | select REGMAP_I2C |
| 107 | help |
| 108 | ---help--- |
| 109 | This driver supports the Silicon Labs 514 programmable clock |
| 110 | generator. |
| 111 | |
Mike Looijmans | 953cc3e | 2018-03-20 09:15:41 +0100 | [diff] [blame] | 112 | config COMMON_CLK_SI544 |
| 113 | tristate "Clock driver for SiLabs 544 devices" |
| 114 | depends on I2C |
| 115 | select REGMAP_I2C |
| 116 | help |
| 117 | ---help--- |
| 118 | This driver supports the Silicon Labs 544 programmable clock |
| 119 | generator. |
| 120 | |
Soren Brinkmann | 1459c83 | 2013-09-21 16:40:39 -0700 | [diff] [blame] | 121 | config COMMON_CLK_SI570 |
| 122 | tristate "Clock driver for SiLabs 570 and compatible devices" |
| 123 | depends on I2C |
| 124 | depends on OF |
| 125 | select REGMAP_I2C |
| 126 | help |
| 127 | ---help--- |
| 128 | This driver supports Silicon Labs 570/571/598/599 programmable |
| 129 | clock generators. |
| 130 | |
Mike Looijmans | c7d5a46b | 2015-11-03 12:55:54 +0100 | [diff] [blame] | 131 | config COMMON_CLK_CDCE706 |
| 132 | tristate "Clock driver for TI CDCE706 clock synthesizer" |
| 133 | depends on I2C |
| 134 | select REGMAP_I2C |
| 135 | select RATIONAL |
| 136 | ---help--- |
| 137 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
| 138 | |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 139 | config COMMON_CLK_CDCE925 |
Akinobu Mita | 5508124 | 2017-01-01 03:04:36 +0900 | [diff] [blame] | 140 | tristate "Clock driver for TI CDCE913/925/937/949 devices" |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 141 | depends on I2C |
| 142 | depends on OF |
| 143 | select REGMAP_I2C |
| 144 | help |
| 145 | ---help--- |
Akinobu Mita | 5508124 | 2017-01-01 03:04:36 +0900 | [diff] [blame] | 146 | This driver supports the TI CDCE913/925/937/949 programmable clock |
| 147 | synthesizer. Each chip has different number of PLLs and outputs. |
| 148 | For example, the CDCE925 contains two PLLs with spread-spectrum |
| 149 | clocking support and five output dividers. The driver only supports |
| 150 | the following setup, and uses a fixed setting for the output muxes. |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 151 | Y1 is derived from the input clock |
| 152 | Y2 and Y3 derive from PLL1 |
| 153 | Y4 and Y5 derive from PLL2 |
| 154 | Given a target output frequency, the driver will set the PLL and |
| 155 | divider to best approximate the desired output. |
| 156 | |
Kuninori Morimoto | 64dfbe2 | 2015-11-10 01:15:09 +0000 | [diff] [blame] | 157 | config COMMON_CLK_CS2000_CP |
| 158 | tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" |
| 159 | depends on I2C |
| 160 | help |
| 161 | If you say yes here you get support for the CS2000 clock multiplier. |
| 162 | |
Linus Walleij | 846423f | 2017-06-21 09:59:52 +0200 | [diff] [blame] | 163 | config COMMON_CLK_GEMINI |
| 164 | bool "Clock driver for Cortina Systems Gemini SoC" |
| 165 | depends on ARCH_GEMINI || COMPILE_TEST |
| 166 | select MFD_SYSCON |
| 167 | select RESET_CONTROLLER |
| 168 | ---help--- |
| 169 | This driver supports the SoC clocks on the Cortina Systems Gemini |
| 170 | platform, also known as SL3516 or CS3516. |
| 171 | |
Joel Stanley | 5eda5d7 | 2017-12-22 13:15:18 +1030 | [diff] [blame] | 172 | config COMMON_CLK_ASPEED |
| 173 | bool "Clock driver for Aspeed BMC SoCs" |
| 174 | depends on ARCH_ASPEED || COMPILE_TEST |
| 175 | default ARCH_ASPEED |
| 176 | select MFD_SYSCON |
| 177 | select RESET_CONTROLLER |
| 178 | ---help--- |
| 179 | This driver supports the SoC clocks on the Aspeed BMC platforms. |
| 180 | |
| 181 | The G4 and G5 series, including the ast2400 and ast2500, are supported |
| 182 | by this driver. |
| 183 | |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 184 | config COMMON_CLK_S2MPS11 |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 185 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
Krzysztof Kozlowski | 9c1b305 | 2016-10-02 22:58:14 +0200 | [diff] [blame] | 186 | depends on MFD_SEC_CORE || COMPILE_TEST |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 187 | ---help--- |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 188 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
| 189 | clock. These multi-function devices have two (S2MPS14) or three |
| 190 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 191 | |
Peter Ujfalusi | f9f8c04 | 2012-09-14 17:30:27 +0300 | [diff] [blame] | 192 | config CLK_TWL6040 |
| 193 | tristate "External McPDM functional clock from twl6040" |
| 194 | depends on TWL6040_CORE |
| 195 | ---help--- |
| 196 | Enable the external functional clock support on OMAP4+ platforms for |
| 197 | McPDM. McPDM module is using the external bit clock on the McPDM bus |
| 198 | as functional clock. |
| 199 | |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 200 | config COMMON_CLK_AXI_CLKGEN |
| 201 | tristate "AXI clkgen driver" |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 202 | depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 203 | help |
| 204 | ---help--- |
| 205 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
| 206 | FPGAs. It is commonly used in Analog Devices' reference designs. |
| 207 | |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 208 | config CLK_QORIQ |
| 209 | bool "Clock driver for Freescale QorIQ platforms" |
Linus Torvalds | 2f4bf52 | 2015-11-05 23:38:43 -0800 | [diff] [blame] | 210 | depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 211 | ---help--- |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 212 | This adds the clock driver support for Freescale QorIQ platforms |
| 213 | using common clock framework. |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 214 | |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 215 | config COMMON_CLK_XGENE |
| 216 | bool "Clock driver for APM XGene SoC" |
| 217 | default y |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 218 | depends on ARM64 || COMPILE_TEST |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 219 | ---help--- |
| 220 | Sypport for the APM X-Gene SoC reference, PLL, and device clocks. |
| 221 | |
Vladimir Zapolskiy | f7c82a6 | 2015-12-06 12:45:57 +0200 | [diff] [blame] | 222 | config COMMON_CLK_NXP |
| 223 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) |
| 224 | select REGMAP_MMIO if ARCH_LPC32XX |
Ezequiel Garcia | 72ad679 | 2016-05-16 12:45:36 -0300 | [diff] [blame] | 225 | select MFD_SYSCON if ARCH_LPC18XX |
Vladimir Zapolskiy | f7c82a6 | 2015-12-06 12:45:57 +0200 | [diff] [blame] | 226 | ---help--- |
| 227 | Support for clock providers on NXP platforms. |
| 228 | |
Peter Ujfalusi | 942d1d6 | 2014-06-27 09:01:11 +0300 | [diff] [blame] | 229 | config COMMON_CLK_PALMAS |
| 230 | tristate "Clock driver for TI Palmas devices" |
| 231 | depends on MFD_PALMAS |
| 232 | ---help--- |
| 233 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
| 234 | using common clock framework. |
| 235 | |
Philipp Zabel | 9a74ccd | 2015-02-13 20:18:52 +0100 | [diff] [blame] | 236 | config COMMON_CLK_PWM |
| 237 | tristate "Clock driver for PWMs used as clock outputs" |
| 238 | depends on PWM |
| 239 | ---help--- |
| 240 | Adapter driver so that any PWM output can be (mis)used as clock signal |
| 241 | at 50% duty cycle. |
| 242 | |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 243 | config COMMON_CLK_PXA |
| 244 | def_bool COMMON_CLK && ARCH_PXA |
| 245 | ---help--- |
Mike Looijmans | 048c58b | 2015-11-03 12:55:53 +0100 | [diff] [blame] | 246 | Support for the Marvell PXA SoC. |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 247 | |
Purna Chandra Mandal | ce6e118 | 2016-05-13 13:22:40 +0530 | [diff] [blame] | 248 | config COMMON_CLK_PIC32 |
| 249 | def_bool COMMON_CLK && MACH_PIC32 |
| 250 | |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 251 | config COMMON_CLK_OXNAS |
| 252 | bool "Clock driver for the OXNAS SoC Family" |
Jean Delvare | 821f994 | 2016-07-07 09:18:44 +0200 | [diff] [blame] | 253 | depends on ARCH_OXNAS || COMPILE_TEST |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 254 | select MFD_SYSCON |
| 255 | ---help--- |
| 256 | Support for the OXNAS SoC Family clocks. |
| 257 | |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 258 | config COMMON_CLK_VC5 |
Marek Vasut | dbf6b16 | 2017-07-09 15:28:14 +0200 | [diff] [blame] | 259 | tristate "Clock driver for IDT VersaClock 5,6 devices" |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 260 | depends on I2C |
| 261 | depends on OF |
| 262 | select REGMAP_I2C |
| 263 | help |
| 264 | ---help--- |
Marek Vasut | dbf6b16 | 2017-07-09 15:28:14 +0200 | [diff] [blame] | 265 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
| 266 | programmable clock generators. |
Marek Vasut | 3e1aec4e | 2017-01-12 02:03:24 +0100 | [diff] [blame] | 267 | |
Gabriel Fernandez | 9bee94e | 2018-03-08 17:53:55 +0100 | [diff] [blame] | 268 | config COMMON_CLK_STM32MP157 |
| 269 | def_bool COMMON_CLK && MACH_STM32MP157 |
| 270 | help |
| 271 | ---help--- |
| 272 | Support for stm32mp157 SoC family clocks |
| 273 | |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 274 | config COMMON_CLK_STM32F |
Gabriel Fernandez | 9a16060 | 2018-05-03 08:40:09 +0200 | [diff] [blame] | 275 | def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 276 | help |
| 277 | ---help--- |
| 278 | Support for stm32f4 and stm32f7 SoC families clocks |
| 279 | |
| 280 | config COMMON_CLK_STM32H7 |
Gabriel Fernandez | 9a16060 | 2018-05-03 08:40:09 +0200 | [diff] [blame] | 281 | def_bool COMMON_CLK && MACH_STM32H743 |
Benjamin Gaignard | da32d35 | 2018-03-12 10:32:48 +0100 | [diff] [blame] | 282 | help |
| 283 | ---help--- |
| 284 | Support for stm32h7 SoC family clocks |
| 285 | |
Manivannan Sadhasivam | 3495e29 | 2018-03-26 23:08:57 +0530 | [diff] [blame] | 286 | source "drivers/clk/actions/Kconfig" |
Stephen Boyd | 64a12c5 | 2015-05-14 17:38:21 -0700 | [diff] [blame] | 287 | source "drivers/clk/bcm/Kconfig" |
Bintian Wang | 72ea486 | 2015-05-29 10:08:38 +0800 | [diff] [blame] | 288 | source "drivers/clk/hisilicon/Kconfig" |
Paul Burton | 6b0fd6c | 2017-06-17 13:52:47 -0700 | [diff] [blame] | 289 | source "drivers/clk/imgtec/Kconfig" |
Tero Kristo | b745c07 | 2017-06-13 10:09:27 +0300 | [diff] [blame] | 290 | source "drivers/clk/keystone/Kconfig" |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 291 | source "drivers/clk/mediatek/Kconfig" |
Michael Turquette | cb7c47d | 2016-05-23 14:29:13 -0700 | [diff] [blame] | 292 | source "drivers/clk/meson/Kconfig" |
Sebastian Hesselbarth | 97fa4cf | 2012-11-17 15:22:22 +0100 | [diff] [blame] | 293 | source "drivers/clk/mvebu/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 294 | source "drivers/clk/qcom/Kconfig" |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 295 | source "drivers/clk/renesas/Kconfig" |
Pankaj Dubey | 4ce9b85e | 2014-05-08 13:07:08 +0900 | [diff] [blame] | 296 | source "drivers/clk/samsung/Kconfig" |
Chunyan Zhang | d41f59f | 2017-12-07 20:57:05 +0800 | [diff] [blame] | 297 | source "drivers/clk/sprd/Kconfig" |
Maxime Ripard | 1d80c14 | 2016-06-29 21:05:23 +0200 | [diff] [blame] | 298 | source "drivers/clk/sunxi-ng/Kconfig" |
Thierry Reding | 31b52ba | 2015-04-01 09:10:58 +0200 | [diff] [blame] | 299 | source "drivers/clk/tegra/Kconfig" |
Tony Lindgren | 2133049 | 2016-02-26 09:35:05 -0800 | [diff] [blame] | 300 | source "drivers/clk/ti/Kconfig" |
Masahiro Yamada | 734d82f | 2016-09-16 16:40:03 +0900 | [diff] [blame] | 301 | source "drivers/clk/uniphier/Kconfig" |
Jolly Shah | 3fde0e1 | 2018-10-08 11:21:46 -0700 | [diff] [blame^] | 302 | source "drivers/clk/zynqmp/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 303 | |
| 304 | endmenu |