blob: cee1d4e657bccdd7769fdffbbce666ef239add79 [file] [log] [blame]
Paul Walmsley7b9487a2019-04-30 13:50:58 -07001# SPDX-License-Identifier: GPL-2.0
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +01002
Stephen Boydbc8c9452020-04-08 23:44:16 -07003config HAVE_CLK
4 bool
5 help
6 The <linux/clk.h> calls support software clock gating and
7 thus are a key power management tool on many systems.
8
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +01009config CLKDEV_LOOKUP
10 bool
11 select HAVE_CLK
Kyungmin Parkaa3831c2011-07-18 16:34:54 +090012
Shawn Guo5c77f562011-12-20 14:46:38 +080013config HAVE_CLK_PREPARE
14 bool
15
Stephen Boydbbd7ffd2020-04-08 23:44:13 -070016config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
Arnd Bergmann8fb61e32012-03-17 21:10:51 +000017 bool
Stephen Boydbbd7ffd2020-04-08 23:44:13 -070018 select HAVE_CLK
19 help
20 Select this option when the clock API in <linux/clk.h> is implemented
21 by platform/architecture code. This method is deprecated. Modern
22 code should select COMMON_CLK instead and not define a custom
23 'struct clk'.
24
25menuconfig COMMON_CLK
26 bool "Common Clock Framework"
27 depends on !HAVE_LEGACY_CLK
Mike Turquetteb24764902012-03-15 23:11:19 -070028 select HAVE_CLK_PREPARE
Rob Herring01033be2012-04-09 15:24:58 -050029 select CLKDEV_LOOKUP
Pranith Kumar83fe27e2014-12-05 11:24:45 -050030 select SRCU
Andy Shevchenko07775912015-09-22 18:54:11 +030031 select RATIONAL
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090032 help
Mike Turquetteb24764902012-03-15 23:11:19 -070033 The common clock framework is a single definition of struct
34 clk, useful across many platforms, as well as an
35 implementation of the clock API in include/linux/clk.h.
36 Architectures utilizing the common struct clk should select
Arnd Bergmann8fb61e32012-03-17 21:10:51 +000037 this option.
Mike Turquetteb24764902012-03-15 23:11:19 -070038
Stephen Boydbbd7ffd2020-04-08 23:44:13 -070039if COMMON_CLK
Mike Turquetteb24764902012-03-15 23:11:19 -070040
Mark Brownf05259a2012-05-17 10:04:57 +010041config COMMON_CLK_WM831X
42 tristate "Clock driver for WM831x/2x PMICs"
43 depends on MFD_WM831X
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090044 help
Krzysztof Kozlowski333d2d12019-11-21 04:18:55 +010045 Supports the clocking subsystem of the WM831x/2x series of
Masanari Iidafe4e4372014-10-17 00:09:24 +090046 PMICs from Wolfson Microelectronics.
Mark Brownf05259a2012-05-17 10:04:57 +010047
Pawel Moll5ee2b872013-09-17 17:16:15 +010048source "drivers/clk/versatile/Kconfig"
Linus Walleijf9a6aa42012-08-06 18:32:08 +020049
Eugeniy Paltsevdaeeb432017-08-25 20:39:14 +030050config CLK_HSDK
51 bool "PLL Driver for HSDK platform"
Geert Uytterhoevenf6bade62020-08-07 11:43:51 +020052 depends on ARC_SOC_HSDK || COMPILE_TEST
Geert Uytterhoevenbd8548d2020-08-03 10:48:35 +020053 depends on HAS_IOMEM
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090054 help
Eugeniy Paltsevdaeeb432017-08-25 20:39:14 +030055 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
56 control.
57
Jonghwa Lee73118e62012-08-28 17:54:28 +090058config COMMON_CLK_MAX77686
Laxman Dewangan5a227cd2016-06-17 16:21:07 +053059 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
Krzysztof Kozlowski9c1b3052016-10-02 22:58:14 +020060 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090061 help
Laxman Dewangan5a227cd2016-06-17 16:21:07 +053062 This driver supports Maxim 77620/77686/77802 crystal oscillator
63 clock.
Javier Martinez Canillas83ccf162014-08-18 10:33:03 +020064
Daniel Mack33f51042018-07-06 20:53:03 +020065config COMMON_CLK_MAX9485
66 tristate "Maxim 9485 Programmable Clock Generator"
67 depends on I2C
68 help
69 This driver supports Maxim 9485 Programmable Audio Clock Generator
70
Chris Zhong038b8922014-10-13 15:52:44 -070071config COMMON_CLK_RK808
Tony Xie8ed144012019-06-21 06:34:55 -040072 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
Chris Zhong038b8922014-10-13 15:52:44 -070073 depends on MFD_RK808
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090074 help
Tony Xie8ed144012019-06-21 06:34:55 -040075 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
76 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
77 Clkout1 is always on, Clkout2 can off by control register.
Chris Zhong038b8922014-10-13 15:52:44 -070078
Daniel Lezcanob68adc22017-04-17 19:19:25 +020079config COMMON_CLK_HI655X
Riku Voipio3a49afb2018-03-12 12:49:45 +020080 tristate "Clock driver for Hi655x" if EXPERT
81 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
82 depends on REGMAP
83 default MFD_HI655X_PMIC
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090084 help
Daniel Lezcanob68adc22017-04-17 19:19:25 +020085 This driver supports the hi655x PMIC clock. This
86 multi-function device has one fixed-rate oscillator, clocked
87 at 32KHz.
88
Sudeep Holla6d6a1d82017-06-13 17:19:36 +010089config COMMON_CLK_SCMI
90 tristate "Clock driver controlled via SCMI interface"
91 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090092 help
Sudeep Holla6d6a1d82017-06-13 17:19:36 +010093 This driver provides support for clocks that are controlled
94 by firmware that implements the SCMI interface.
95
96 This driver uses SCMI Message Protocol to interact with the
97 firmware providing all the clock controls.
98
Sudeep Hollacd52c2a2015-03-30 10:59:52 +010099config COMMON_CLK_SCPI
100 tristate "Clock driver controlled via SCPI interface"
101 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900102 help
Sudeep Hollacd52c2a2015-03-30 10:59:52 +0100103 This driver provides support for clocks that are controlled
104 by firmware that implements the SCPI interface.
105
106 This driver uses SCPI Message Protocol to interact with the
107 firmware providing all the clock controls.
108
Mike Looijmans3044a862019-05-17 15:23:52 +0200109config COMMON_CLK_SI5341
110 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
111 depends on I2C
112 select REGMAP_I2C
113 help
114 This driver supports Silicon Labs Si5341 and Si5340 programmable clock
115 generators. Not all features of these chips are currently supported
116 by the driver, in particular it only supports XTAL input. The chip can
117 be pre-programmed to support other configurations and features not yet
118 implemented in the driver.
119
Sebastian Hesselbarth9abd5f02013-04-11 21:42:29 +0200120config COMMON_CLK_SI5351
121 tristate "Clock driver for SiLabs 5351A/B/C"
122 depends on I2C
123 select REGMAP_I2C
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900124 help
Sebastian Hesselbarth9abd5f02013-04-11 21:42:29 +0200125 This driver supports Silicon Labs 5351A/B/C programmable clock
126 generators.
127
Mike Looijmans8ce20e62015-10-02 09:15:29 +0200128config COMMON_CLK_SI514
129 tristate "Clock driver for SiLabs 514 devices"
130 depends on I2C
131 depends on OF
132 select REGMAP_I2C
133 help
Mike Looijmans8ce20e62015-10-02 09:15:29 +0200134 This driver supports the Silicon Labs 514 programmable clock
135 generator.
136
Mike Looijmans953cc3e2018-03-20 09:15:41 +0100137config COMMON_CLK_SI544
138 tristate "Clock driver for SiLabs 544 devices"
139 depends on I2C
140 select REGMAP_I2C
141 help
Mike Looijmans953cc3e2018-03-20 09:15:41 +0100142 This driver supports the Silicon Labs 544 programmable clock
143 generator.
144
Soren Brinkmann1459c832013-09-21 16:40:39 -0700145config COMMON_CLK_SI570
146 tristate "Clock driver for SiLabs 570 and compatible devices"
147 depends on I2C
148 depends on OF
149 select REGMAP_I2C
150 help
Soren Brinkmann1459c832013-09-21 16:40:39 -0700151 This driver supports Silicon Labs 570/571/598/599 programmable
152 clock generators.
153
Manivannan Sadhasivam1ab46012019-11-15 21:59:00 +0530154config COMMON_CLK_BM1880
155 bool "Clock driver for Bitmain BM1880 SoC"
156 depends on ARCH_BITMAIN || COMPILE_TEST
157 default ARCH_BITMAIN
158 help
159 This driver supports the clocks on Bitmain BM1880 SoC.
160
Mike Looijmansc7d5a46b2015-11-03 12:55:54 +0100161config COMMON_CLK_CDCE706
162 tristate "Clock driver for TI CDCE706 clock synthesizer"
163 depends on I2C
164 select REGMAP_I2C
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900165 help
Mike Looijmansc7d5a46b2015-11-03 12:55:54 +0100166 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
167
Mike Looijmans19fbbbb2015-06-03 07:25:19 +0200168config COMMON_CLK_CDCE925
Akinobu Mita55081242017-01-01 03:04:36 +0900169 tristate "Clock driver for TI CDCE913/925/937/949 devices"
Mike Looijmans19fbbbb2015-06-03 07:25:19 +0200170 depends on I2C
171 depends on OF
172 select REGMAP_I2C
173 help
Akinobu Mita55081242017-01-01 03:04:36 +0900174 This driver supports the TI CDCE913/925/937/949 programmable clock
175 synthesizer. Each chip has different number of PLLs and outputs.
176 For example, the CDCE925 contains two PLLs with spread-spectrum
177 clocking support and five output dividers. The driver only supports
178 the following setup, and uses a fixed setting for the output muxes.
Mike Looijmans19fbbbb2015-06-03 07:25:19 +0200179 Y1 is derived from the input clock
180 Y2 and Y3 derive from PLL1
181 Y4 and Y5 derive from PLL2
182 Given a target output frequency, the driver will set the PLL and
183 divider to best approximate the desired output.
184
Kuninori Morimoto64dfbe22015-11-10 01:15:09 +0000185config COMMON_CLK_CS2000_CP
186 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
187 depends on I2C
188 help
189 If you say yes here you get support for the CS2000 clock multiplier.
190
Michael Wallefcf77be2020-11-08 19:51:11 +0100191config COMMON_CLK_FSL_FLEXSPI
192 tristate "Clock driver for FlexSPI on Layerscape SoCs"
193 depends on ARCH_LAYERSCAPE || COMPILE_TEST
194 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
195 help
196 On Layerscape SoCs there is a special clock for the FlexSPI
197 interface.
198
Michael Walle9cd10202020-01-03 00:11:01 +0100199config COMMON_CLK_FSL_SAI
200 bool "Clock driver for BCLK of Freescale SAI cores"
201 depends on ARCH_LAYERSCAPE || COMPILE_TEST
202 help
203 This driver supports the Freescale SAI (Synchronous Audio Interface)
204 to be used as a generic clock output. Some SoCs have restrictions
205 regarding the possible pin multiplexer settings. Eg. on some SoCs
206 two SAI interfaces can only be enabled together. If just one is
207 needed, the BCLK pin of the second one can be used as general
208 purpose clock output. Ideally, it can be used to drive an audio
209 codec (sometimes known as MCLK).
210
Linus Walleij846423f2017-06-21 09:59:52 +0200211config COMMON_CLK_GEMINI
212 bool "Clock driver for Cortina Systems Gemini SoC"
213 depends on ARCH_GEMINI || COMPILE_TEST
214 select MFD_SYSCON
215 select RESET_CONTROLLER
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900216 help
Linus Walleij846423f2017-06-21 09:59:52 +0200217 This driver supports the SoC clocks on the Cortina Systems Gemini
218 platform, also known as SL3516 or CS3516.
219
Joel Stanley5eda5d72017-12-22 13:15:18 +1030220config COMMON_CLK_ASPEED
221 bool "Clock driver for Aspeed BMC SoCs"
222 depends on ARCH_ASPEED || COMPILE_TEST
223 default ARCH_ASPEED
224 select MFD_SYSCON
225 select RESET_CONTROLLER
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900226 help
Joel Stanley5eda5d72017-12-22 13:15:18 +1030227 This driver supports the SoC clocks on the Aspeed BMC platforms.
228
229 The G4 and G5 series, including the ast2400 and ast2500, are supported
230 by this driver.
231
Yadwinder Singh Brar7cc560d2013-07-07 17:14:20 +0530232config COMMON_CLK_S2MPS11
Krzysztof Kozlowskie8b60a42014-05-21 13:23:01 +0200233 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
Krzysztof Kozlowski9c1b3052016-10-02 22:58:14 +0200234 depends on MFD_SEC_CORE || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900235 help
Krzysztof Kozlowskie8b60a42014-05-21 13:23:01 +0200236 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
237 clock. These multi-function devices have two (S2MPS14) or three
238 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
Yadwinder Singh Brar7cc560d2013-07-07 17:14:20 +0530239
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300240config CLK_TWL6040
241 tristate "External McPDM functional clock from twl6040"
242 depends on TWL6040_CORE
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900243 help
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300244 Enable the external functional clock support on OMAP4+ platforms for
245 McPDM. McPDM module is using the external bit clock on the McPDM bus
246 as functional clock.
247
Lars-Peter Clausen0e646c52013-03-11 16:22:29 +0100248config COMMON_CLK_AXI_CLKGEN
249 tristate "AXI clkgen driver"
Alexandru Ardelean324a8102021-02-01 17:12:42 +0200250 depends on HAS_IOMEM || COMPILE_TEST
251 depends on OF
Lars-Peter Clausen0e646c52013-03-11 16:22:29 +0100252 help
Lars-Peter Clausen0e646c52013-03-11 16:22:29 +0100253 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
254 FPGAs. It is commonly used in Analog Devices' reference designs.
255
Tang Yuantian93a17c02015-01-15 14:03:41 +0800256config CLK_QORIQ
257 bool "Clock driver for Freescale QorIQ platforms"
Geert Uytterhoevenb8bcece2020-11-10 16:47:50 +0100258 depends on OF
259 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900260 help
Tang Yuantian93a17c02015-01-15 14:03:41 +0800261 This adds the clock driver support for Freescale QorIQ platforms
262 using common clock framework.
Tang Yuantian555eae92013-04-09 16:46:26 +0800263
Wen Hed37010a2019-12-13 16:34:02 +0800264config CLK_LS1028A_PLLDIG
265 tristate "Clock driver for LS1028A Display output"
266 depends on ARCH_LAYERSCAPE || COMPILE_TEST
267 default ARCH_LAYERSCAPE
268 help
269 This driver support the Display output interfaces(LCD, DPHY) pixel clocks
270 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
271 features of the PLL are currently supported by the driver. By default,
272 configured bypass mode with this PLL.
273
Loc Ho308964c2013-06-26 11:56:09 -0600274config COMMON_CLK_XGENE
275 bool "Clock driver for APM XGene SoC"
Marc Gonzalezce9a1042019-06-12 17:03:56 +0200276 default ARCH_XGENE
Javier Martinez Canillas4a7748c2015-10-13 16:18:18 +0200277 depends on ARM64 || COMPILE_TEST
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900278 help
Christophe JAILLET4fe02fe2020-05-03 21:03:27 +0200279 Support for the APM X-Gene SoC reference, PLL, and device clocks.
Loc Ho308964c2013-06-26 11:56:09 -0600280
Charles Keepax76c54782019-03-19 13:37:00 +0000281config COMMON_CLK_LOCHNAGAR
282 tristate "Cirrus Logic Lochnagar clock driver"
283 depends on MFD_LOCHNAGAR
284 help
285 This driver supports the clocking features of the Cirrus Logic
286 Lochnagar audio development board.
287
Vladimir Zapolskiyf7c82a62015-12-06 12:45:57 +0200288config COMMON_CLK_NXP
289 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
290 select REGMAP_MMIO if ARCH_LPC32XX
Ezequiel Garcia72ad6792016-05-16 12:45:36 -0300291 select MFD_SYSCON if ARCH_LPC18XX
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900292 help
Vladimir Zapolskiyf7c82a62015-12-06 12:45:57 +0200293 Support for clock providers on NXP platforms.
294
Peter Ujfalusi942d1d62014-06-27 09:01:11 +0300295config COMMON_CLK_PALMAS
296 tristate "Clock driver for TI Palmas devices"
297 depends on MFD_PALMAS
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900298 help
Peter Ujfalusi942d1d62014-06-27 09:01:11 +0300299 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
300 using common clock framework.
301
Philipp Zabel9a74ccd2015-02-13 20:18:52 +0100302config COMMON_CLK_PWM
303 tristate "Clock driver for PWMs used as clock outputs"
304 depends on PWM
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900305 help
Philipp Zabel9a74ccd2015-02-13 20:18:52 +0100306 Adapter driver so that any PWM output can be (mis)used as clock signal
307 at 50% duty cycle.
308
Robert Jarzmik98d147f2014-10-01 23:39:29 +0200309config COMMON_CLK_PXA
310 def_bool COMMON_CLK && ARCH_PXA
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900311 help
Mike Looijmans048c58b2015-11-03 12:55:53 +0100312 Support for the Marvell PXA SoC.
Robert Jarzmik98d147f2014-10-01 23:39:29 +0200313
Purna Chandra Mandalce6e1182016-05-13 13:22:40 +0530314config COMMON_CLK_PIC32
315 def_bool COMMON_CLK && MACH_PIC32
316
Neil Armstrong0bbd72b2016-04-18 12:01:35 +0200317config COMMON_CLK_OXNAS
318 bool "Clock driver for the OXNAS SoC Family"
Jean Delvare821f9942016-07-07 09:18:44 +0200319 depends on ARCH_OXNAS || COMPILE_TEST
Neil Armstrong0bbd72b2016-04-18 12:01:35 +0200320 select MFD_SYSCON
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +0900321 help
Neil Armstrong0bbd72b2016-04-18 12:01:35 +0200322 Support for the OXNAS SoC Family clocks.
323
Marek Vasut3e1aec4e2017-01-12 02:03:24 +0100324config COMMON_CLK_VC5
Marek Vasutdbf6b162017-07-09 15:28:14 +0200325 tristate "Clock driver for IDT VersaClock 5,6 devices"
Marek Vasut3e1aec4e2017-01-12 02:03:24 +0100326 depends on I2C
327 depends on OF
328 select REGMAP_I2C
329 help
Marek Vasutdbf6b162017-07-09 15:28:14 +0200330 This driver supports the IDT VersaClock 5 and VersaClock 6
331 programmable clock generators.
Marek Vasut3e1aec4e2017-01-12 02:03:24 +0100332
Gabriel Fernandez9bee94e2018-03-08 17:53:55 +0100333config COMMON_CLK_STM32MP157
334 def_bool COMMON_CLK && MACH_STM32MP157
335 help
Gabriel Fernandez9bee94e2018-03-08 17:53:55 +0100336 Support for stm32mp157 SoC family clocks
337
Benjamin Gaignardda32d352018-03-12 10:32:48 +0100338config COMMON_CLK_STM32F
Gabriel Fernandez9a160602018-05-03 08:40:09 +0200339 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
Benjamin Gaignardda32d352018-03-12 10:32:48 +0100340 help
Benjamin Gaignardda32d352018-03-12 10:32:48 +0100341 Support for stm32f4 and stm32f7 SoC families clocks
342
343config COMMON_CLK_STM32H7
Gabriel Fernandez9a160602018-05-03 08:40:09 +0200344 def_bool COMMON_CLK && MACH_STM32H743
Benjamin Gaignardda32d352018-03-12 10:32:48 +0100345 help
Benjamin Gaignardda32d352018-03-12 10:32:48 +0100346 Support for stm32h7 SoC family clocks
347
Lubomir Rintela9372a52019-05-16 08:19:37 +0200348config COMMON_CLK_MMP2
349 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
350 help
351 Support for Marvell MMP2 and MMP3 SoC clocks
352
Lubomir Rintel725262d2020-05-20 00:41:51 +0200353config COMMON_CLK_MMP2_AUDIO
354 tristate "Clock driver for MMP2 Audio subsystem"
355 depends on COMMON_CLK_MMP2 || COMPILE_TEST
356 help
357 This driver supports clocks for Audio subsystem on MMP2 SoC.
358
Matti Vaittinen2e622462018-12-07 12:01:44 +0200359config COMMON_CLK_BD718XX
Matti Vaittinenae866de2020-01-20 15:44:19 +0200360 tristate "Clock driver for 32K clk gates on ROHM PMICs"
361 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
Matti Vaittinen2e622462018-12-07 12:01:44 +0200362 help
Matti Vaittinenae866de2020-01-20 15:44:19 +0200363 This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
Matti Vaittinen0dae7f52019-06-03 10:25:39 +0300364 ROHM BD70528 PMICs clock gates.
Matti Vaittinen2e622462018-12-07 12:01:44 +0200365
Jan Kotas50cc4ca2018-12-13 12:49:29 +0000366config COMMON_CLK_FIXED_MMIO
367 bool "Clock driver for Memory Mapped Fixed values"
368 depends on COMMON_CLK && OF
369 help
370 Support for Memory Mapped IO Fixed clocks
371
Manivannan Sadhasivam3495e292018-03-26 23:08:57 +0530372source "drivers/clk/actions/Kconfig"
Paul Walmsley7b9487a2019-04-30 13:50:58 -0700373source "drivers/clk/analogbits/Kconfig"
Serge Seminb7d950b2020-05-27 01:20:55 +0300374source "drivers/clk/baikal-t1/Kconfig"
Stephen Boyd64a12c52015-05-14 17:38:21 -0700375source "drivers/clk/bcm/Kconfig"
Bintian Wang72ea4862015-05-29 10:08:38 +0800376source "drivers/clk/hisilicon/Kconfig"
Paul Burton6b0fd6c2017-06-17 13:52:47 -0700377source "drivers/clk/imgtec/Kconfig"
Aisheng Dong3a48d912018-12-13 15:42:50 +0000378source "drivers/clk/imx/Kconfig"
Paul Cercueil0880fb82018-08-23 15:17:41 +0200379source "drivers/clk/ingenic/Kconfig"
Tero Kristob745c072017-06-13 10:09:27 +0300380source "drivers/clk/keystone/Kconfig"
James Liao2886c842016-08-19 13:34:49 +0800381source "drivers/clk/mediatek/Kconfig"
Michael Turquettecb7c47d2016-05-23 14:29:13 -0700382source "drivers/clk/meson/Kconfig"
Sebastian Hesselbarth97fa4cf2012-11-17 15:22:22 +0100383source "drivers/clk/mvebu/Kconfig"
James Liaob9e65eb2016-01-28 16:58:57 +0800384source "drivers/clk/qcom/Kconfig"
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200385source "drivers/clk/renesas/Kconfig"
Elaine Zhang4d98ed12020-09-14 10:23:04 +0800386source "drivers/clk/rockchip/Kconfig"
Pankaj Dubey4ce9b85e2014-05-08 13:07:08 +0900387source "drivers/clk/samsung/Kconfig"
Paul Walmsley30b8e272019-04-30 13:51:00 -0700388source "drivers/clk/sifive/Kconfig"
Chunyan Zhangd41f59f2017-12-07 20:57:05 +0800389source "drivers/clk/sprd/Kconfig"
Maxime Ripard49c726d2019-03-19 15:37:59 +0100390source "drivers/clk/sunxi/Kconfig"
Maxime Ripard1d80c142016-06-29 21:05:23 +0200391source "drivers/clk/sunxi-ng/Kconfig"
Thierry Reding31b52ba2015-04-01 09:10:58 +0200392source "drivers/clk/tegra/Kconfig"
Tony Lindgren21330492016-02-26 09:35:05 -0800393source "drivers/clk/ti/Kconfig"
Masahiro Yamada734d82f2016-09-16 16:40:03 +0900394source "drivers/clk/uniphier/Kconfig"
Rahul Tanward058fd92020-04-17 13:54:47 +0800395source "drivers/clk/x86/Kconfig"
Jolly Shah3fde0e12018-10-08 11:21:46 -0700396source "drivers/clk/zynqmp/Kconfig"
James Liaob9e65eb2016-01-28 16:58:57 +0800397
Stephen Boydbbd7ffd2020-04-08 23:44:13 -0700398endif