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Maxime Ripardf73100c2020-09-03 10:01:11 +02001#ifndef _VC4_HDMI_H_
2#define _VC4_HDMI_H_
3
4#include <drm/drm_connector.h>
5#include <media/cec.h>
6#include <sound/dmaengine_pcm.h>
7#include <sound/soc.h>
8
9#include "vc4_drv.h"
10
Maxime Ripardf73100c2020-09-03 10:01:11 +020011/* VC4 HDMI encoder KMS struct */
12struct vc4_hdmi_encoder {
13 struct vc4_encoder base;
14 bool hdmi_monitor;
15 bool limited_rgb_range;
16};
17
18static inline struct vc4_hdmi_encoder *
19to_vc4_hdmi_encoder(struct drm_encoder *encoder)
20{
21 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
22}
23
Maxime Ripardc457b8a2020-09-03 10:01:25 +020024struct drm_display_mode;
25
Maxime Ripard33c773e2020-09-03 10:01:22 +020026struct vc4_hdmi;
Maxime Ripard311e3052020-09-03 10:01:23 +020027struct vc4_hdmi_register;
Maxime Ripard33c773e2020-09-03 10:01:22 +020028
Maxime Ripard83239892020-09-03 10:01:48 +020029enum vc4_hdmi_phy_channel {
30 PHY_LANE_0 = 0,
31 PHY_LANE_1,
32 PHY_LANE_2,
33 PHY_LANE_CK,
34};
35
Maxime Ripard33c773e2020-09-03 10:01:22 +020036struct vc4_hdmi_variant {
Maxime Ripard7d732992020-09-03 10:01:29 +020037 /* Encoder Type for that controller */
38 enum vc4_encoder_type encoder_type;
39
Maxime Ripard9be43a52020-09-03 10:01:41 +020040 /* ALSA card name */
41 const char *card_name;
42
Maxime Ripardb2405c92020-09-03 10:01:30 +020043 /* Filename to expose the registers in debugfs */
44 const char *debugfs_name;
45
Maxime Ripard234f4212020-09-03 10:01:32 +020046 /* Set to true when the CEC support is available */
47 bool cec_available;
48
Maxime Ripardcd4cb492020-09-03 10:01:35 +020049 /* Maximum pixel clock supported by the controller (in Hz) */
50 unsigned long long max_pixel_clock;
51
Maxime Ripard311e3052020-09-03 10:01:23 +020052 /* List of the registers available on that variant */
53 const struct vc4_hdmi_register *registers;
54
55 /* Number of registers on that variant */
56 unsigned int num_registers;
57
Maxime Ripard83239892020-09-03 10:01:48 +020058 /* BCM2711 Only.
59 * The variants don't map the lane in the same order in the
60 * PHY, so this is an array mapping the HDMI channel (index)
61 * to the PHY lane (value).
62 */
63 enum vc4_hdmi_phy_channel phy_lane_mapping[4];
64
Maxime Ripard57fb32e2020-10-29 13:25:22 +010065 /* The BCM2711 cannot deal with odd horizontal pixel timings */
66 bool unsupported_odd_h_timings;
67
Maxime Ripard33c773e2020-09-03 10:01:22 +020068 /* Callback to get the resources (memory region, interrupts,
69 * clocks, etc) for that variant.
70 */
71 int (*init_resources)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard9045e912020-09-03 10:01:24 +020072
73 /* Callback to reset the HDMI block */
74 void (*reset)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +020075
Maxime Ripard89f31a22020-09-03 10:01:27 +020076 /* Callback to enable / disable the CSC */
77 void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
78
Maxime Ripard904f6682020-09-03 10:01:28 +020079 /* Callback to configure the video timings in the HDMI block */
80 void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
81 struct drm_display_mode *mode);
82
Maxime Ripardc457b8a2020-09-03 10:01:25 +020083 /* Callback to initialize the PHY according to the mode */
84 void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
85 struct drm_display_mode *mode);
86
87 /* Callback to disable the PHY */
88 void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +020089
90 /* Callback to enable the RNG in the PHY */
91 void (*phy_rng_enable)(struct vc4_hdmi *vc4_hdmi);
92
93 /* Callback to disable the RNG in the PHY */
94 void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);
Dave Stevenson632ee3a2020-09-03 10:01:40 +020095
96 /* Callback to get channel map */
97 u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
Maxime Ripard33c773e2020-09-03 10:01:22 +020098};
99
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200100/* HDMI audio information */
101struct vc4_hdmi_audio {
102 struct snd_soc_card card;
103 struct snd_soc_dai_link link;
104 struct snd_soc_dai_link_component cpu;
105 struct snd_soc_dai_link_component codec;
106 struct snd_soc_dai_link_component platform;
107 int samplerate;
108 int channels;
109 struct snd_dmaengine_dai_dma_data dma_data;
110 struct snd_pcm_substream *substream;
Dave Stevenson6ac1c752020-09-03 10:01:38 +0200111
112 bool streaming;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200113};
114
115/* General HDMI hardware state. */
116struct vc4_hdmi {
Maxime Ripard47c167b2020-09-03 10:01:19 +0200117 struct vc4_hdmi_audio audio;
118
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200119 struct platform_device *pdev;
Maxime Ripard33c773e2020-09-03 10:01:22 +0200120 const struct vc4_hdmi_variant *variant;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200121
122 struct vc4_hdmi_encoder encoder;
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200123 struct drm_connector connector;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200124
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200125 struct i2c_adapter *ddc;
126 void __iomem *hdmicore_regs;
127 void __iomem *hd_regs;
Maxime Ripard83239892020-09-03 10:01:48 +0200128
129 /* VC5 Only */
130 void __iomem *cec_regs;
131 /* VC5 Only */
132 void __iomem *csc_regs;
133 /* VC5 Only */
134 void __iomem *dvp_regs;
135 /* VC5 Only */
136 void __iomem *phy_regs;
137 /* VC5 Only */
138 void __iomem *ram_regs;
139 /* VC5 Only */
140 void __iomem *rm_regs;
141
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200142 int hpd_gpio;
143 bool hpd_active_low;
144
145 struct cec_adapter *cec_adap;
146 struct cec_msg cec_rx_msg;
147 bool cec_tx_ok;
148 bool cec_irq_was_rx;
149
150 struct clk *pixel_clock;
151 struct clk *hsm_clock;
Dave Stevenson632ee3a2020-09-03 10:01:40 +0200152 struct clk *audio_clock;
Hoegeun Kwon37387422020-09-03 10:01:47 +0200153 struct clk *pixel_bvb_clock;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200154
Maxime Ripard83239892020-09-03 10:01:48 +0200155 struct reset_control *reset;
156
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200157 struct debugfs_regset32 hdmi_regset;
158 struct debugfs_regset32 hd_regset;
159};
160
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200161static inline struct vc4_hdmi *
162connector_to_vc4_hdmi(struct drm_connector *connector)
163{
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200164 return container_of(connector, struct vc4_hdmi, connector);
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200165}
166
167static inline struct vc4_hdmi *
168encoder_to_vc4_hdmi(struct drm_encoder *encoder)
169{
170 struct vc4_hdmi_encoder *_encoder = to_vc4_hdmi_encoder(encoder);
171
172 return container_of(_encoder, struct vc4_hdmi, encoder);
173}
174
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200175void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
176 struct drm_display_mode *mode);
177void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +0200178void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
179void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200180
Maxime Ripard83239892020-09-03 10:01:48 +0200181void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
182 struct drm_display_mode *mode);
183void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
184void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
185void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
186
Maxime Ripardf73100c2020-09-03 10:01:11 +0200187#endif /* _VC4_HDMI_H_ */