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Maxime Ripardf73100c2020-09-03 10:01:11 +02001#ifndef _VC4_HDMI_H_
2#define _VC4_HDMI_H_
3
4#include <drm/drm_connector.h>
5#include <media/cec.h>
6#include <sound/dmaengine_pcm.h>
7#include <sound/soc.h>
8
9#include "vc4_drv.h"
10
Maxime Ripardf73100c2020-09-03 10:01:11 +020011/* VC4 HDMI encoder KMS struct */
12struct vc4_hdmi_encoder {
13 struct vc4_encoder base;
14 bool hdmi_monitor;
15 bool limited_rgb_range;
16};
17
18static inline struct vc4_hdmi_encoder *
19to_vc4_hdmi_encoder(struct drm_encoder *encoder)
20{
21 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
22}
23
Maxime Ripardc457b8a2020-09-03 10:01:25 +020024struct drm_display_mode;
25
Maxime Ripard33c773e2020-09-03 10:01:22 +020026struct vc4_hdmi;
Maxime Ripard311e3052020-09-03 10:01:23 +020027struct vc4_hdmi_register;
Maxime Ripard33c773e2020-09-03 10:01:22 +020028
Maxime Ripard83239892020-09-03 10:01:48 +020029enum vc4_hdmi_phy_channel {
30 PHY_LANE_0 = 0,
31 PHY_LANE_1,
32 PHY_LANE_2,
33 PHY_LANE_CK,
34};
35
Maxime Ripard33c773e2020-09-03 10:01:22 +020036struct vc4_hdmi_variant {
Maxime Ripard7d732992020-09-03 10:01:29 +020037 /* Encoder Type for that controller */
38 enum vc4_encoder_type encoder_type;
39
Maxime Ripard9be43a52020-09-03 10:01:41 +020040 /* ALSA card name */
41 const char *card_name;
42
Maxime Ripardb2405c92020-09-03 10:01:30 +020043 /* Filename to expose the registers in debugfs */
44 const char *debugfs_name;
45
Maxime Ripard234f4212020-09-03 10:01:32 +020046 /* Set to true when the CEC support is available */
47 bool cec_available;
48
Maxime Ripardcd4cb492020-09-03 10:01:35 +020049 /* Maximum pixel clock supported by the controller (in Hz) */
50 unsigned long long max_pixel_clock;
51
Maxime Ripard311e3052020-09-03 10:01:23 +020052 /* List of the registers available on that variant */
53 const struct vc4_hdmi_register *registers;
54
55 /* Number of registers on that variant */
56 unsigned int num_registers;
57
Maxime Ripard83239892020-09-03 10:01:48 +020058 /* BCM2711 Only.
59 * The variants don't map the lane in the same order in the
60 * PHY, so this is an array mapping the HDMI channel (index)
61 * to the PHY lane (value).
62 */
63 enum vc4_hdmi_phy_channel phy_lane_mapping[4];
64
Maxime Ripard33c773e2020-09-03 10:01:22 +020065 /* Callback to get the resources (memory region, interrupts,
66 * clocks, etc) for that variant.
67 */
68 int (*init_resources)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard9045e912020-09-03 10:01:24 +020069
70 /* Callback to reset the HDMI block */
71 void (*reset)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +020072
Maxime Ripard89f31a22020-09-03 10:01:27 +020073 /* Callback to enable / disable the CSC */
74 void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
75
Maxime Ripard904f6682020-09-03 10:01:28 +020076 /* Callback to configure the video timings in the HDMI block */
77 void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
78 struct drm_display_mode *mode);
79
Maxime Ripardc457b8a2020-09-03 10:01:25 +020080 /* Callback to initialize the PHY according to the mode */
81 void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
82 struct drm_display_mode *mode);
83
84 /* Callback to disable the PHY */
85 void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +020086
87 /* Callback to enable the RNG in the PHY */
88 void (*phy_rng_enable)(struct vc4_hdmi *vc4_hdmi);
89
90 /* Callback to disable the RNG in the PHY */
91 void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);
Dave Stevenson632ee3a2020-09-03 10:01:40 +020092
93 /* Callback to get channel map */
94 u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
Maxime Ripard33c773e2020-09-03 10:01:22 +020095};
96
Maxime Ripardc98c85b2020-09-03 10:01:12 +020097/* HDMI audio information */
98struct vc4_hdmi_audio {
99 struct snd_soc_card card;
100 struct snd_soc_dai_link link;
101 struct snd_soc_dai_link_component cpu;
102 struct snd_soc_dai_link_component codec;
103 struct snd_soc_dai_link_component platform;
104 int samplerate;
105 int channels;
106 struct snd_dmaengine_dai_dma_data dma_data;
107 struct snd_pcm_substream *substream;
Dave Stevenson6ac1c752020-09-03 10:01:38 +0200108
109 bool streaming;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200110};
111
112/* General HDMI hardware state. */
113struct vc4_hdmi {
Maxime Ripard47c167b2020-09-03 10:01:19 +0200114 struct vc4_hdmi_audio audio;
115
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200116 struct platform_device *pdev;
Maxime Ripard33c773e2020-09-03 10:01:22 +0200117 const struct vc4_hdmi_variant *variant;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200118
119 struct vc4_hdmi_encoder encoder;
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200120 struct drm_connector connector;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200121
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200122 struct i2c_adapter *ddc;
123 void __iomem *hdmicore_regs;
124 void __iomem *hd_regs;
Maxime Ripard83239892020-09-03 10:01:48 +0200125
126 /* VC5 Only */
127 void __iomem *cec_regs;
128 /* VC5 Only */
129 void __iomem *csc_regs;
130 /* VC5 Only */
131 void __iomem *dvp_regs;
132 /* VC5 Only */
133 void __iomem *phy_regs;
134 /* VC5 Only */
135 void __iomem *ram_regs;
136 /* VC5 Only */
137 void __iomem *rm_regs;
138
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200139 int hpd_gpio;
140 bool hpd_active_low;
141
142 struct cec_adapter *cec_adap;
143 struct cec_msg cec_rx_msg;
144 bool cec_tx_ok;
145 bool cec_irq_was_rx;
146
147 struct clk *pixel_clock;
148 struct clk *hsm_clock;
Dave Stevenson632ee3a2020-09-03 10:01:40 +0200149 struct clk *audio_clock;
Hoegeun Kwon37387422020-09-03 10:01:47 +0200150 struct clk *pixel_bvb_clock;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200151
Maxime Ripard83239892020-09-03 10:01:48 +0200152 struct reset_control *reset;
153
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200154 struct debugfs_regset32 hdmi_regset;
155 struct debugfs_regset32 hd_regset;
156};
157
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200158static inline struct vc4_hdmi *
159connector_to_vc4_hdmi(struct drm_connector *connector)
160{
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200161 return container_of(connector, struct vc4_hdmi, connector);
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200162}
163
164static inline struct vc4_hdmi *
165encoder_to_vc4_hdmi(struct drm_encoder *encoder)
166{
167 struct vc4_hdmi_encoder *_encoder = to_vc4_hdmi_encoder(encoder);
168
169 return container_of(_encoder, struct vc4_hdmi, encoder);
170}
171
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200172void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
173 struct drm_display_mode *mode);
174void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +0200175void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
176void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200177
Maxime Ripard83239892020-09-03 10:01:48 +0200178void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
179 struct drm_display_mode *mode);
180void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
181void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
182void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
183
Maxime Ripardf73100c2020-09-03 10:01:11 +0200184#endif /* _VC4_HDMI_H_ */