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Maxime Ripardf73100c2020-09-03 10:01:11 +02001#ifndef _VC4_HDMI_H_
2#define _VC4_HDMI_H_
3
4#include <drm/drm_connector.h>
5#include <media/cec.h>
6#include <sound/dmaengine_pcm.h>
7#include <sound/soc.h>
8
9#include "vc4_drv.h"
10
Maxime Ripardf73100c2020-09-03 10:01:11 +020011/* VC4 HDMI encoder KMS struct */
12struct vc4_hdmi_encoder {
13 struct vc4_encoder base;
14 bool hdmi_monitor;
15 bool limited_rgb_range;
16};
17
18static inline struct vc4_hdmi_encoder *
19to_vc4_hdmi_encoder(struct drm_encoder *encoder)
20{
21 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
22}
23
Maxime Ripardc457b8a2020-09-03 10:01:25 +020024struct drm_display_mode;
25
Maxime Ripard33c773e2020-09-03 10:01:22 +020026struct vc4_hdmi;
Maxime Ripard311e3052020-09-03 10:01:23 +020027struct vc4_hdmi_register;
Maxime Ripard33c773e2020-09-03 10:01:22 +020028
29struct vc4_hdmi_variant {
Maxime Ripard7d732992020-09-03 10:01:29 +020030 /* Encoder Type for that controller */
31 enum vc4_encoder_type encoder_type;
32
Maxime Ripard9be43a52020-09-03 10:01:41 +020033 /* ALSA card name */
34 const char *card_name;
35
Maxime Ripardb2405c92020-09-03 10:01:30 +020036 /* Filename to expose the registers in debugfs */
37 const char *debugfs_name;
38
Maxime Ripard234f4212020-09-03 10:01:32 +020039 /* Set to true when the CEC support is available */
40 bool cec_available;
41
Maxime Ripardcd4cb492020-09-03 10:01:35 +020042 /* Maximum pixel clock supported by the controller (in Hz) */
43 unsigned long long max_pixel_clock;
44
Maxime Ripard311e3052020-09-03 10:01:23 +020045 /* List of the registers available on that variant */
46 const struct vc4_hdmi_register *registers;
47
48 /* Number of registers on that variant */
49 unsigned int num_registers;
50
Maxime Ripard33c773e2020-09-03 10:01:22 +020051 /* Callback to get the resources (memory region, interrupts,
52 * clocks, etc) for that variant.
53 */
54 int (*init_resources)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard9045e912020-09-03 10:01:24 +020055
56 /* Callback to reset the HDMI block */
57 void (*reset)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +020058
Maxime Ripard89f31a22020-09-03 10:01:27 +020059 /* Callback to enable / disable the CSC */
60 void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
61
Maxime Ripard904f6682020-09-03 10:01:28 +020062 /* Callback to configure the video timings in the HDMI block */
63 void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
64 struct drm_display_mode *mode);
65
Maxime Ripardc457b8a2020-09-03 10:01:25 +020066 /* Callback to initialize the PHY according to the mode */
67 void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
68 struct drm_display_mode *mode);
69
70 /* Callback to disable the PHY */
71 void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +020072
73 /* Callback to enable the RNG in the PHY */
74 void (*phy_rng_enable)(struct vc4_hdmi *vc4_hdmi);
75
76 /* Callback to disable the RNG in the PHY */
77 void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);
Dave Stevenson632ee3a2020-09-03 10:01:40 +020078
79 /* Callback to get channel map */
80 u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
Maxime Ripard33c773e2020-09-03 10:01:22 +020081};
82
Maxime Ripardc98c85b2020-09-03 10:01:12 +020083/* HDMI audio information */
84struct vc4_hdmi_audio {
85 struct snd_soc_card card;
86 struct snd_soc_dai_link link;
87 struct snd_soc_dai_link_component cpu;
88 struct snd_soc_dai_link_component codec;
89 struct snd_soc_dai_link_component platform;
90 int samplerate;
91 int channels;
92 struct snd_dmaengine_dai_dma_data dma_data;
93 struct snd_pcm_substream *substream;
Dave Stevenson6ac1c752020-09-03 10:01:38 +020094
95 bool streaming;
Maxime Ripardc98c85b2020-09-03 10:01:12 +020096};
97
98/* General HDMI hardware state. */
99struct vc4_hdmi {
Maxime Ripard47c167b2020-09-03 10:01:19 +0200100 struct vc4_hdmi_audio audio;
101
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200102 struct platform_device *pdev;
Maxime Ripard33c773e2020-09-03 10:01:22 +0200103 const struct vc4_hdmi_variant *variant;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200104
105 struct vc4_hdmi_encoder encoder;
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200106 struct drm_connector connector;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200107
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200108 struct i2c_adapter *ddc;
109 void __iomem *hdmicore_regs;
110 void __iomem *hd_regs;
111 int hpd_gpio;
112 bool hpd_active_low;
113
114 struct cec_adapter *cec_adap;
115 struct cec_msg cec_rx_msg;
116 bool cec_tx_ok;
117 bool cec_irq_was_rx;
118
119 struct clk *pixel_clock;
120 struct clk *hsm_clock;
Dave Stevenson632ee3a2020-09-03 10:01:40 +0200121 struct clk *audio_clock;
Hoegeun Kwon37387422020-09-03 10:01:47 +0200122 struct clk *pixel_bvb_clock;
Maxime Ripardc98c85b2020-09-03 10:01:12 +0200123
124 struct debugfs_regset32 hdmi_regset;
125 struct debugfs_regset32 hd_regset;
126};
127
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200128static inline struct vc4_hdmi *
129connector_to_vc4_hdmi(struct drm_connector *connector)
130{
Maxime Ripard0532e5e2020-09-03 10:01:21 +0200131 return container_of(connector, struct vc4_hdmi, connector);
Maxime Ripard5dfbcae2020-09-03 10:01:17 +0200132}
133
134static inline struct vc4_hdmi *
135encoder_to_vc4_hdmi(struct drm_encoder *encoder)
136{
137 struct vc4_hdmi_encoder *_encoder = to_vc4_hdmi_encoder(encoder);
138
139 return container_of(_encoder, struct vc4_hdmi, encoder);
140}
141
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200142void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
143 struct drm_display_mode *mode);
144void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripard647b9652020-09-03 10:01:26 +0200145void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
146void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
Maxime Ripardc457b8a2020-09-03 10:01:25 +0200147
Maxime Ripardf73100c2020-09-03 10:01:11 +0200148#endif /* _VC4_HDMI_H_ */