Blame - drivers/pinctrl/sh-pfc/pfc-r8a7795.c - SHIFTPHONES/mainline/linux

blob: 18aeee592fdcf24694909230c15974696f8b4a43 [file] [log] [blame]

Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1	/*
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	2	* R8A7795 ES2.0+ processor support - PFC hardware block.
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	3	*
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4	* Copyright (C) 2015-2016 Renesas Electronics Corporation
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5	*
				6	* This program is free software; you can redistribute it and/or modify
				7	* it under the terms of the GNU General Public License as published by
				8	* the Free Software Foundation; version 2 of the License.
				9	*/
				10
				11	#include <linux/kernel.h>
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	12	#include <linux/sys_soc.h>
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	13
				14	#include "core.h"
				15	#include "sh_pfc.h"
				16
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	17	#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH \| \
				18	SH_PFC_PIN_CFG_PULL_UP \| \
				19	SH_PFC_PIN_CFG_PULL_DOWN)
				20
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	21	#define CPU_ALL_PORT(fn, sfx) \
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	22	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	23	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	24	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
				25	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE), \
				26	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
				27	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
				28	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
				29	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
				30	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE), \
				31	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
				32	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
				33	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	34	/*
				35	* F_() : just information
				36	* FM() : macro for FN_xxx / xxx_MARK
				37	*/
				38
				39	/* GPSR0 */
				40	#define GPSR0_15 F_(D15, IP7_11_8)
				41	#define GPSR0_14 F_(D14, IP7_7_4)
				42	#define GPSR0_13 F_(D13, IP7_3_0)
				43	#define GPSR0_12 F_(D12, IP6_31_28)
				44	#define GPSR0_11 F_(D11, IP6_27_24)
				45	#define GPSR0_10 F_(D10, IP6_23_20)
				46	#define GPSR0_9 F_(D9, IP6_19_16)
				47	#define GPSR0_8 F_(D8, IP6_15_12)
				48	#define GPSR0_7 F_(D7, IP6_11_8)
				49	#define GPSR0_6 F_(D6, IP6_7_4)
				50	#define GPSR0_5 F_(D5, IP6_3_0)
				51	#define GPSR0_4 F_(D4, IP5_31_28)
				52	#define GPSR0_3 F_(D3, IP5_27_24)
				53	#define GPSR0_2 F_(D2, IP5_23_20)
				54	#define GPSR0_1 F_(D1, IP5_19_16)
				55	#define GPSR0_0 F_(D0, IP5_15_12)
				56
				57	/* GPSR1 */
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	58	#define GPSR1_28 FM(CLKOUT)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	59	#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
				60	#define GPSR1_26 F_(WE1_N, IP5_7_4)
				61	#define GPSR1_25 F_(WE0_N, IP5_3_0)
				62	#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
				63	#define GPSR1_23 F_(RD_N, IP4_27_24)
				64	#define GPSR1_22 F_(BS_N, IP4_23_20)
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	65	#define GPSR1_21 F_(CS1_N, IP4_19_16)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	66	#define GPSR1_20 F_(CS0_N, IP4_15_12)
				67	#define GPSR1_19 F_(A19, IP4_11_8)
				68	#define GPSR1_18 F_(A18, IP4_7_4)
				69	#define GPSR1_17 F_(A17, IP4_3_0)
				70	#define GPSR1_16 F_(A16, IP3_31_28)
				71	#define GPSR1_15 F_(A15, IP3_27_24)
				72	#define GPSR1_14 F_(A14, IP3_23_20)
				73	#define GPSR1_13 F_(A13, IP3_19_16)
				74	#define GPSR1_12 F_(A12, IP3_15_12)
				75	#define GPSR1_11 F_(A11, IP3_11_8)
				76	#define GPSR1_10 F_(A10, IP3_7_4)
				77	#define GPSR1_9 F_(A9, IP3_3_0)
				78	#define GPSR1_8 F_(A8, IP2_31_28)
				79	#define GPSR1_7 F_(A7, IP2_27_24)
				80	#define GPSR1_6 F_(A6, IP2_23_20)
				81	#define GPSR1_5 F_(A5, IP2_19_16)
				82	#define GPSR1_4 F_(A4, IP2_15_12)
				83	#define GPSR1_3 F_(A3, IP2_11_8)
				84	#define GPSR1_2 F_(A2, IP2_7_4)
				85	#define GPSR1_1 F_(A1, IP2_3_0)
				86	#define GPSR1_0 F_(A0, IP1_31_28)
				87
				88	/* GPSR2 */
				89	#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
				90	#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
				91	#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
				92	#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
				93	#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
				94	#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
				95	#define GPSR2_8 F_(PWM2_A, IP1_27_24)
				96	#define GPSR2_7 F_(PWM1_A, IP1_23_20)
				97	#define GPSR2_6 F_(PWM0, IP1_19_16)
				98	#define GPSR2_5 F_(IRQ5, IP1_15_12)
				99	#define GPSR2_4 F_(IRQ4, IP1_11_8)
				100	#define GPSR2_3 F_(IRQ3, IP1_7_4)
				101	#define GPSR2_2 F_(IRQ2, IP1_3_0)
				102	#define GPSR2_1 F_(IRQ1, IP0_31_28)
				103	#define GPSR2_0 F_(IRQ0, IP0_27_24)
				104
				105	/* GPSR3 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	106	#define GPSR3_15 F_(SD1_WP, IP11_23_20)
				107	#define GPSR3_14 F_(SD1_CD, IP11_19_16)
				108	#define GPSR3_13 F_(SD0_WP, IP11_15_12)
				109	#define GPSR3_12 F_(SD0_CD, IP11_11_8)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	110	#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
				111	#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
				112	#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
				113	#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
				114	#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
				115	#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
				116	#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
				117	#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
				118	#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
				119	#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
				120	#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
				121	#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
				122
				123	/* GPSR4 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	124	#define GPSR4_17 F_(SD3_DS, IP11_7_4)
				125	#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
				126	#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
				127	#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
				128	#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
				129	#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
				130	#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
				131	#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
				132	#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
				133	#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
				134	#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
				135	#define GPSR4_6 F_(SD2_DS, IP9_27_24)
				136	#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
				137	#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
				138	#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
				139	#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
				140	#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	141	#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
				142
				143	/* GPSR5 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	144	#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
				145	#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
				146	#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	147	#define GPSR5_22 FM(MSIOF0_RXD)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	148	#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	149	#define GPSR5_20 FM(MSIOF0_TXD)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	150	#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
				151	#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	152	#define GPSR5_17 FM(MSIOF0_SCK)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	153	#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
				154	#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
				155	#define GPSR5_14 F_(HTX0, IP13_19_16)
				156	#define GPSR5_13 F_(HRX0, IP13_15_12)
				157	#define GPSR5_12 F_(HSCK0, IP13_11_8)
				158	#define GPSR5_11 F_(RX2_A, IP13_7_4)
				159	#define GPSR5_10 F_(TX2_A, IP13_3_0)
				160	#define GPSR5_9 F_(SCK2, IP12_31_28)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	161	#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	162	#define GPSR5_7 F_(CTS1_N, IP12_23_20)
				163	#define GPSR5_6 F_(TX1_A, IP12_19_16)
				164	#define GPSR5_5 F_(RX1_A, IP12_15_12)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	165	#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	166	#define GPSR5_3 F_(CTS0_N, IP12_7_4)
				167	#define GPSR5_2 F_(TX0, IP12_3_0)
				168	#define GPSR5_1 F_(RX0, IP11_31_28)
				169	#define GPSR5_0 F_(SCK0, IP11_27_24)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	170
				171	/* GPSR6 */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	172	#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
				173	#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	174	#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
				175	#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
				176	#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
				177	#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
				178	#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
				179	#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
				180	#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
				181	#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
				182	#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
				183	#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
				184	#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
				185	#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
				186	#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
				187	#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
				188	#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
				189	#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	190	#define GPSR6_13 FM(SSI_SDATA5)
				191	#define GPSR6_12 FM(SSI_WS5)
				192	#define GPSR6_11 FM(SSI_SCK5)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	193	#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
				194	#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
				195	#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
				196	#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	197	#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
				198	#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	199	#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
				200	#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
				201	#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
				202	#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
				203	#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	204
				205	/* GPSR7 */
				206	#define GPSR7_3 FM(HDMI1_CEC)
				207	#define GPSR7_2 FM(HDMI0_CEC)
				208	#define GPSR7_1 FM(AVS2)
				209	#define GPSR7_0 FM(AVS1)
				210
				211
				212	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				213	#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				214	#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				215	#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				216	#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	217	#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	218	#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	e2ab177	2017-05-30 20:15:18 +0900	[diff] [blame]	219	#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				220	#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	221	#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	7716c51	2017-11-16 12:16:48 +0900	[diff] [blame]	222	#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				223	#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				224	#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				225	#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				226	#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				227	#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	228	#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				229	#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				230	#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				231	#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				232
				233	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				234	#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				235	#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				236	#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				237	#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				238	#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				239	#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	240	#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	241	#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				242	#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				243	#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				244	#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				245	#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				246	#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				247	#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				248	#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				249	#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				250	#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	251	#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	252	#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				253	#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				254	#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				255	#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	256	#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	257	#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				258	#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				259	#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				260	#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				261	#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				262	#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				263	#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				264	#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				265	#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				266	#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				267	#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				268	#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	269	#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	270	#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				271	#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				272	#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				273	#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	274	#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				275
				276	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				277	#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				278	#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				279	#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				280	#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				281	#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				282	#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	283	#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				284	#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				285	#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				286	#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				287	#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	67c836b	2017-07-28 20:41:17 +0900	[diff] [blame]	288	#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				289	#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				290	#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				291	#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				292	#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				293	#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				294	#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				295	#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				296	#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				297	#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				298	#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				299	#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				300	#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				301	#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				302	#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				303	#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				304	#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				305	#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	306	#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	307
				308	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	309	#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				310	#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				311	#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				312	#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				313	#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				314	#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				315	#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	316	#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	317	#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				318	#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				319	#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	320	#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	321	#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				322	#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				323	#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				324	#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				325	#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				326	#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				327	#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				328	#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				329	#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
				330	#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				331	#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				332	#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				333	#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				334	#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				335	#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				336	#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				337
				338	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				339	#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				340	#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				341	#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	342	#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				343	#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	344	#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				345	#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				346	#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				347	#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				348	#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				349	#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				350	#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				351	#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				352	#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				353	#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				354	#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				355	#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				356	#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				357	#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				358	#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
				359	#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
				360	#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
				361	#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
				362	#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
				363	#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	bad7cc1	2017-07-28 20:41:16 +0900	[diff] [blame]	364	#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
				365	#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	366
				367	#define PINMUX_GPSR \
				368	\
				369	GPSR6_31 \
				370	GPSR6_30 \
				371	GPSR6_29 \
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	372	GPSR1_28 GPSR6_28 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	373	GPSR1_27 GPSR6_27 \
				374	GPSR1_26 GPSR6_26 \
				375	GPSR1_25 GPSR5_25 GPSR6_25 \
				376	GPSR1_24 GPSR5_24 GPSR6_24 \
				377	GPSR1_23 GPSR5_23 GPSR6_23 \
				378	GPSR1_22 GPSR5_22 GPSR6_22 \
				379	GPSR1_21 GPSR5_21 GPSR6_21 \
				380	GPSR1_20 GPSR5_20 GPSR6_20 \
				381	GPSR1_19 GPSR5_19 GPSR6_19 \
				382	GPSR1_18 GPSR5_18 GPSR6_18 \
				383	GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
				384	GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
				385	GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
				386	GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
				387	GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
				388	GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
				389	GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
				390	GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
				391	GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
				392	GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
				393	GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
				394	GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
				395	GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
				396	GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
				397	GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
				398	GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
				399	GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
				400	GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
				401
				402	#define PINMUX_IPSR \
				403	\
				404	FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
				405	FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
				406	FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
				407	FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
				408	FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
				409	FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
				410	FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
				411	FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
				412	\
				413	FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
				414	FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
				415	FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
Takeshi Kihara	30cd1c4	2017-07-28 20:41:19 +0900	[diff] [blame]	416	FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	417	FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
				418	FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
				419	FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
				420	FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
				421	\
				422	FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
				423	FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
				424	FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
				425	FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
				426	FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
				427	FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
				428	FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
				429	FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
				430	\
				431	FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
				432	FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
				433	FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
				434	FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
				435	FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
				436	FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
				437	FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
				438	FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
				439	\
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	440	FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
				441	FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
				442	FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
				443	FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
				444	FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
				445	FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
				446	FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
				447	FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	448
				449	/* MOD_SEL0 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	450	#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	451	#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
				452	#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
				453	#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
				454	#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	455	#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
				456	#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
				457	#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
				458	#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
				459	#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
				460	#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
				461	#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
				462	#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
				463	#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
				464	#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
				465	#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
				466	#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
				467	#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	468
				469	/* MOD_SEL1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 */
				470	#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
				471	#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	472	#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	473	#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
				474	#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
				475	#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
				476	#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
				477	#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
				478	#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
				479	#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
				480	#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
				481	#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
				482	#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	483	#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	484	#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
				485	#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
				486	#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
				487	#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
				488	#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
				489	#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
				490	#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
				491	#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
				492
				493	/* MOD_SEL2 / / 0 / / 1 / / 2 / / 3 */
				494	#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
				495	#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
				496	#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	497	#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
				498	#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
				499	#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	500	#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
				501	#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
				502	#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
				503	#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
				504	#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	505	#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
				506
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	507	#define PINMUX_MOD_SELS \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	508	\
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	509	MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
				510	MOD_SEL2_30 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	511	MOD_SEL1_29_28_27 MOD_SEL2_29 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	512	MOD_SEL0_28_27 MOD_SEL2_28_27 \
				513	MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
				514	MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	515	MOD_SEL0_23 MOD_SEL1_23_22_21 \
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	516	MOD_SEL0_22 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	517	MOD_SEL0_21 MOD_SEL2_21 \
				518	MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
				519	MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
				520	MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
				521	MOD_SEL2_17 \
				522	MOD_SEL0_16 MOD_SEL1_16 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	523	MOD_SEL1_15_14 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	524	MOD_SEL0_14_13 \
				525	MOD_SEL1_13 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	526	MOD_SEL0_12 MOD_SEL1_12 \
				527	MOD_SEL0_11 MOD_SEL1_11 \
				528	MOD_SEL0_10 MOD_SEL1_10 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	529	MOD_SEL0_9_8 MOD_SEL1_9 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	530	MOD_SEL0_7_6 \
				531	MOD_SEL1_6 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	532	MOD_SEL0_5 MOD_SEL1_5 \
				533	MOD_SEL0_4_3 MOD_SEL1_4 \
				534	MOD_SEL1_3 \
				535	MOD_SEL1_2 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	536	MOD_SEL1_1 \
				537	MOD_SEL1_0 MOD_SEL2_0
				538
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	539	/*
				540	* These pins are not able to be muxed but have other properties
				541	* that can be set, such as drive-strength or pull-up/pull-down enable.
				542	*/
				543	#define PINMUX_STATIC \
				544	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
				545	FM(QSPI0_IO2) FM(QSPI0_IO3) \
				546	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
				547	FM(QSPI1_IO2) FM(QSPI1_IO3) \
				548	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
				549	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
				550	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
				551	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	552	FM(PRESETOUT) \
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	553	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	554	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	555
				556	enum {
				557	PINMUX_RESERVED = 0,
				558
				559	PINMUX_DATA_BEGIN,
				560	GP_ALL(DATA),
				561	PINMUX_DATA_END,
				562
				563	#define F_(x, y)
				564	#define FM(x) FN_##x,
				565	PINMUX_FUNCTION_BEGIN,
				566	GP_ALL(FN),
				567	PINMUX_GPSR
				568	PINMUX_IPSR
				569	PINMUX_MOD_SELS
				570	PINMUX_FUNCTION_END,
				571	#undef F_
				572	#undef FM
				573
				574	#define F_(x, y)
				575	#define FM(x) x##_MARK,
				576	PINMUX_MARK_BEGIN,
				577	PINMUX_GPSR
				578	PINMUX_IPSR
				579	PINMUX_MOD_SELS
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	580	PINMUX_STATIC
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	581	PINMUX_MARK_END,
				582	#undef F_
				583	#undef FM
				584	};
				585
				586	static const u16 pinmux_data[] = {
				587	PINMUX_DATA_GP_ALL(),
				588
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	589	PINMUX_SINGLE(AVS1),
				590	PINMUX_SINGLE(AVS2),
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	591	PINMUX_SINGLE(CLKOUT),
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	592	PINMUX_SINGLE(HDMI0_CEC),
				593	PINMUX_SINGLE(HDMI1_CEC),
Kuninori Morimoto	d07640f	2016-06-21 02:46:55 +0000	[diff] [blame]	594	PINMUX_SINGLE(I2C_SEL_0_1),
				595	PINMUX_SINGLE(I2C_SEL_3_1),
				596	PINMUX_SINGLE(I2C_SEL_5_1),
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	597	PINMUX_SINGLE(MSIOF0_RXD),
				598	PINMUX_SINGLE(MSIOF0_SCK),
				599	PINMUX_SINGLE(MSIOF0_TXD),
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	600	PINMUX_SINGLE(SSI_SCK5),
				601	PINMUX_SINGLE(SSI_SDATA5),
				602	PINMUX_SINGLE(SSI_WS5),
				603
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	604	/* IPSR0 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	605	PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	606	PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
				607
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	608	PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	609	PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
				610	PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
				611
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	612	PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	613	PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
				614	PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
				615
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	616	PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	617	PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
				618	PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
				619
				620	PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
				621	PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
				622	PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	623	PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	624
				625	PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
				626	PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	627	PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	628
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	629	PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
				630	PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
				631	PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	632	PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
				633	PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
				634	PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	635	PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	636
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	637	PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
				638	PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
				639	PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	640	PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
				641	PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
				642	PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	643	PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	644
				645	/* IPSR1 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	646	PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
				647	PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
				648	PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	649	PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
				650	PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	651	PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	652
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	653	PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
				654	PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	655	PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	656	PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
				657	PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	658	PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	659
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	660	PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
				661	PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	662	PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	663	PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
				664	PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	665	PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	666
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	667	PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
				668	PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	669	PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	670	PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
				671	PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	672	PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
				673	PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	674
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	675	PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
				676	PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	677	PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
				678	PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
				679
				680	PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	681	PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
				682	PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
				683	PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
				684
				685	PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	686	PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
				687	PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
				688
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	689	PINMUX_IPSR_GPSR(IP1_31_28, A0),
				690	PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	691	PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	692	PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
				693	PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	694	PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
				695
				696	/* IPSR2 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	697	PINMUX_IPSR_GPSR(IP2_3_0, A1),
				698	PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	699	PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	700	PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
				701	PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	702	PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
				703
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	704	PINMUX_IPSR_GPSR(IP2_7_4, A2),
				705	PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	706	PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	707	PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
				708	PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	709	PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
				710
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	711	PINMUX_IPSR_GPSR(IP2_11_8, A3),
				712	PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	713	PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	714	PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
				715	PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	716	PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
				717
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	718	PINMUX_IPSR_GPSR(IP2_15_12, A4),
				719	PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	720	PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	721	PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
				722	PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
				723	PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	724
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	725	PINMUX_IPSR_GPSR(IP2_19_16, A5),
				726	PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	727	PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
				728	PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	729	PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
				730	PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
				731	PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	732
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	733	PINMUX_IPSR_GPSR(IP2_23_20, A6),
				734	PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	735	PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
				736	PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	737	PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
				738	PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
				739	PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	740
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	741	PINMUX_IPSR_GPSR(IP2_27_24, A7),
				742	PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	743	PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
				744	PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	745	PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
				746	PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
				747	PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	748
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	749	PINMUX_IPSR_GPSR(IP2_31_28, A8),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	750	PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
				751	PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
				752	PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
				753	PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
				754	PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
				755	PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
				756
				757	/* IPSR3 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	758	PINMUX_IPSR_GPSR(IP3_3_0, A9),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	759	PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
				760	PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	761	PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	762
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	763	PINMUX_IPSR_GPSR(IP3_7_4, A10),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	764	PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	765	PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	766	PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	767
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	768	PINMUX_IPSR_GPSR(IP3_11_8, A11),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	769	PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
				770	PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
				771	PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	772	PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
				773	PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	774	PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
				775	PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
				776	PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
				777
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	778	PINMUX_IPSR_GPSR(IP3_15_12, A12),
				779	PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	780	PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
				781	PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	782	PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
				783	PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	784
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	785	PINMUX_IPSR_GPSR(IP3_19_16, A13),
				786	PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	787	PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
				788	PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	789	PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
				790	PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	791
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	792	PINMUX_IPSR_GPSR(IP3_23_20, A14),
				793	PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	794	PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	795	PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
				796	PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
				797	PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	798
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	799	PINMUX_IPSR_GPSR(IP3_27_24, A15),
				800	PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	801	PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	802	PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
				803	PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
				804	PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	805
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	806	PINMUX_IPSR_GPSR(IP3_31_28, A16),
				807	PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
				808	PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
				809	PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	810
				811	/* IPSR4 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	812	PINMUX_IPSR_GPSR(IP4_3_0, A17),
				813	PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
				814	PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
				815	PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	816
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	817	PINMUX_IPSR_GPSR(IP4_7_4, A18),
				818	PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
				819	PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
				820	PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	821
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	822	PINMUX_IPSR_GPSR(IP4_11_8, A19),
				823	PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
				824	PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
				825	PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	826
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	827	PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
				828	PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	829
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	830	PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	831	PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	832	PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
				833
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	834	PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
				835	PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	836	PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	837	PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
				838	PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
				839	PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
				840	PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	841	PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
				842
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	843	PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	844	PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
				845	PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
				846	PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
				847	PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
				848	PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
				849
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	850	PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	851	PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
				852	PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
				853	PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
				854	PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
				855	PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
				856
				857	/* IPSR5 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	858	PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	859	PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	860	PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
				861	PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	862	PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	863	PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	864	PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
				865
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	866	PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	867	PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	868	PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	869	PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	870	PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	871	PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
				872	PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	873	PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
				874
				875	PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	876	PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
				877	PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
				878	PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	879
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	880	PINMUX_IPSR_GPSR(IP5_15_12, D0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	881	PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
				882	PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	883	PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
				884	PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	885
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	886	PINMUX_IPSR_GPSR(IP5_19_16, D1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	887	PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
				888	PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	889	PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
				890	PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	891
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	892	PINMUX_IPSR_GPSR(IP5_23_20, D2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	893	PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	894	PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
				895	PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	896
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	897	PINMUX_IPSR_GPSR(IP5_27_24, D3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	898	PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	899	PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
				900	PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	901
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	902	PINMUX_IPSR_GPSR(IP5_31_28, D4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	903	PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	904	PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
				905	PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	906
				907	/* IPSR6 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	908	PINMUX_IPSR_GPSR(IP6_3_0, D5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	909	PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	910	PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
				911	PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	912
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	913	PINMUX_IPSR_GPSR(IP6_7_4, D6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	914	PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	915	PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
				916	PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	917
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	918	PINMUX_IPSR_GPSR(IP6_11_8, D7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	919	PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	920	PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
				921	PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	922
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	923	PINMUX_IPSR_GPSR(IP6_15_12, D8),
				924	PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	925	PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
				926	PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
				927	PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	928	PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	929
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	930	PINMUX_IPSR_GPSR(IP6_19_16, D9),
				931	PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	932	PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
				933	PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	934	PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	935
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	936	PINMUX_IPSR_GPSR(IP6_23_20, D10),
				937	PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	938	PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
				939	PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
				940	PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
				941	PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	942	PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	943
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	944	PINMUX_IPSR_GPSR(IP6_27_24, D11),
				945	PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	946	PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
				947	PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
				948	PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	949	PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	950	PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	951
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	952	PINMUX_IPSR_GPSR(IP6_31_28, D12),
				953	PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	954	PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
				955	PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
				956	PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	957	PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	958
				959	/* IPSR7 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	960	PINMUX_IPSR_GPSR(IP7_3_0, D13),
				961	PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	962	PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
				963	PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
				964	PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	965	PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	966
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	967	PINMUX_IPSR_GPSR(IP7_7_4, D14),
				968	PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	969	PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
				970	PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
				971	PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	972	PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	973	PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
				974
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	975	PINMUX_IPSR_GPSR(IP7_11_8, D15),
				976	PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	977	PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
				978	PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
				979	PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	980	PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	981	PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
				982
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	983	PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	984	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
				985	PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
				986
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	987	PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	988	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
				989	PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
				990
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	991	PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	992	PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
				993	PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
				994	PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
				995
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	996	PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	997	PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
				998	PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
				999	PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
				1000
				1001	/* IPSR8 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1002	PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1003	PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
				1004	PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
				1005	PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
				1006
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1007	PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1008	PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
				1009	PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
				1010	PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
				1011
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1012	PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1013	PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
				1014	PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
				1015
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1016	PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1017	PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1018	PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1019	PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
				1020	PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
				1021
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1022	PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
				1023	PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1024	PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1025	PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1026	PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
				1027	PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
				1028
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1029	PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
				1030	PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1031	PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1032	PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1033	PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
				1034	PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
				1035
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1036	PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
				1037	PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1038	PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1039	PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1040	PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
				1041	PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
				1042
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1043	PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
				1044	PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1045	PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1046	PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1047	PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
				1048	PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
				1049
				1050	/* IPSR9 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1051	PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1052	PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1053
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1054	PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
				1055	PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1056
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1057	PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
				1058	PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1059
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1060	PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
				1061	PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1062
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1063	PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
				1064	PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1065
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1066	PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
				1067	PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1068
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1069	PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
				1070	PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
				1071	PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1072
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1073	PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
				1074	PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1075
				1076	/* IPSR10 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1077	PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
				1078	PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1079
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1080	PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
				1081	PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1082
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1083	PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
				1084	PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1085
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1086	PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
				1087	PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1088
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1089	PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
				1090	PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1091
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1092	PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
				1093	PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
				1094	PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1095
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1096	PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
				1097	PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
				1098	PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1099
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1100	PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
				1101	PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
				1102	PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1103
				1104	/* IPSR11 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1105	PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
				1106	PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
				1107	PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1108
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1109	PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
				1110	PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1111
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1112	PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
				1113	PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
				1114	PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1115
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1116	PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
				1117	PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1118
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1119	PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
				1120	PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1121
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1122	PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
				1123	PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1124
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1125	PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
				1126	PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
				1127	PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
				1128	PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
				1129	PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
				1130	PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
				1131	PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
				1132	PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
				1133	PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
				1134	PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1135
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1136	PINMUX_IPSR_GPSR(IP11_31_28, RX0),
				1137	PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
				1138	PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
				1139	PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
				1140	PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1141
				1142	/* IPSR12 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1143	PINMUX_IPSR_GPSR(IP12_3_0, TX0),
				1144	PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
				1145	PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
				1146	PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
				1147	PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1148
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1149	PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
				1150	PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
				1151	PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
				1152	PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
				1153	PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
				1154	PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
				1155	PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
				1156	PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1157
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	1158	PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1159	PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
				1160	PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
				1161	PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
				1162	PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
				1163	PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
				1164	PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
				1165	PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1166
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1167	PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
				1168	PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
				1169	PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
				1170	PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
				1171	PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1172
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1173	PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
				1174	PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
				1175	PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
				1176	PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
				1177	PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1178
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1179	PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
				1180	PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
				1181	PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
				1182	PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
				1183	PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
				1184	PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
				1185	PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1186
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	1187	PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1188	PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
				1189	PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
				1190	PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
				1191	PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
				1192	PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
				1193	PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1194
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1195	PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	1196	PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1197	PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
				1198	PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
				1199	PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
				1200	PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
				1201	PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1202
				1203	/* IPSR13 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1204	PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
				1205	PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
				1206	PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
				1207	PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
				1208	PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
				1209	PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1210
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1211	PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
				1212	PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
				1213	PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
				1214	PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
				1215	PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
				1216	PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1217
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1218	PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
				1219	PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
				1220	PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
				1221	PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
				1222	PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
				1223	PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
				1224	PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
				1225	PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1226
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1227	PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
				1228	PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
				1229	PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
				1230	PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
				1231	PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
				1232	PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1233
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1234	PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
				1235	PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
				1236	PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
				1237	PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
				1238	PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
				1239	PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1240
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1241	PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
				1242	PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
				1243	PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
				1244	PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
				1245	PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
				1246	PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
				1247	PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
				1248	PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1249
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1250	PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
				1251	PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
				1252	PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
				1253	PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
				1254	PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
				1255	PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
				1256	PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1257
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1258	PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
				1259	PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
				1260	PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
				1261	PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1262
				1263	/* IPSR14 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1264	PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
				1265	PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1266	PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1267	PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
				1268	PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
				1269	PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
				1270	PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1271	PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1272
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1273	PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
				1274	PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
				1275	PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
				1276	PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
				1277	PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
				1278	PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
				1279	PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
				1280	PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1281
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1282	PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
				1283	PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
				1284	PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1285
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1286	PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
				1287	PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
				1288	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
				1289	PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1290
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1291	PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
				1292	PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
				1293	PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1294
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1295	PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
				1296	PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1297
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1298	PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
				1299	PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1300
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1301	PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
				1302	PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1303
				1304	/* IPSR15 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1305	PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1306
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1307	PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
				1308	PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1309
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	1310	PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1311	PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
				1312	PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1313
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	1314	PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1315	PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
				1316	PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
				1317	PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1318
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1319	PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
				1320	PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
				1321	PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
				1322	PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
				1323	PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
				1324	PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
				1325	PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1326
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1327	PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
				1328	PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
				1329	PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
				1330	PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
				1331	PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
				1332	PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
				1333	PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1334
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1335	PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
				1336	PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
				1337	PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
				1338	PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
				1339	PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
				1340	PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
				1341	PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1342
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1343	PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
				1344	PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
				1345	PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
				1346	PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
				1347	PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
				1348	PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
				1349	PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1350
				1351	/* IPSR16 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1352	PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
				1353	PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
				1354	PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1355
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1356	PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
				1357	PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
				1358	PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1359
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1360	PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
				1361	PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
				1362	PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1363
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1364	PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
				1365	PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
				1366	PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
				1367	PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
				1368	PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
				1369	PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
				1370	PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1371
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1372	PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
				1373	PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
				1374	PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
				1375	PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
				1376	PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
				1377	PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
				1378	PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1379
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1380	PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
				1381	PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
				1382	PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
				1383	PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
				1384	PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
				1385	PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
				1386	PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1387	PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1388
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1389	PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
				1390	PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
				1391	PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
				1392	PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
				1393	PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
				1394	PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
				1395	PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1396
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1397	PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
				1398	PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
				1399	PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
				1400	PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
				1401	PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
				1402	PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
				1403	PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
Takeshi Kihara	712f36f	2017-07-28 20:41:14 +0900	[diff] [blame]	1404	PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1405
				1406	/* IPSR17 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1407	PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
				1408	PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1409
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1410	PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	1411	PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1412	PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
				1413	PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1414	PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1415
				1416	PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
				1417	PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
				1418	PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
				1419	PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
				1420	PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
				1421	PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
				1422	PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
				1423
				1424	PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
				1425	PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
				1426	PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
				1427	PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
				1428	PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
				1429	PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
				1430
				1431	PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
				1432	PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
				1433	PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
				1434	PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
				1435	PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
				1436	PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
				1437	PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
				1438	PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
				1439	PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
				1440
				1441	PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
				1442	PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
				1443	PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
				1444	PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
				1445	PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
				1446	PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
				1447	PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
				1448	PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
				1449	PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
				1450
				1451	PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
				1452	PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
				1453	PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
				1454	PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
Takeshi Kihara	50d8315	2017-07-28 20:41:13 +0900	[diff] [blame]	1455	PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1456	PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
				1457	PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1458	PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1459	PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
				1460	PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
				1461	PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
				1462
				1463	PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
				1464	PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
				1465	PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
				1466	PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
				1467	PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
				1468	PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
				1469	PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
				1470	PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
				1471	PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
				1472
				1473	/* IPSR18 */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	1474	PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1475	PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
				1476	PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
				1477	PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
				1478	PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
				1479	PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
				1480	PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
				1481	PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
				1482	PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
				1483
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	1484	PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1485	PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
				1486	PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
				1487	PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
				1488	PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
				1489	PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
				1490	PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
				1491	PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
				1492	PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1493
				1494	/*
				1495	* Static pins can not be muxed between different functions but
				1496	* still needs a mark entry in the pinmux list. Add each static
				1497	* pin to the list without an associated function. The sh-pfc
				1498	* core will do the right thing and skip trying to mux then pin
				1499	* while still applying configuration to it
				1500	*/
				1501	#define FM(x) PINMUX_DATA(x##_MARK, 0),
				1502	PINMUX_STATIC
				1503	#undef FM
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1504	};
				1505
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1506	/*
Wolfram Sang	ecd5450	2017-10-09 10:37:24 +0200	[diff] [blame]	1507	* R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1508	* Physical layout rows: A - AW, cols: 1 - 39.
				1509	*/
				1510	#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
				1511	#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
				1512	#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	1513	#define PIN_NONE U16_MAX
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1514
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1515	static const struct sh_pfc_pin pinmux_pins[] = {
				1516	PINMUX_GPIO_GP_ALL(),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1517
				1518	/*
				1519	* Pins not associated with a GPIO port.
				1520	*
				1521	* The pin positions are different between different r8a7795
				1522	* packages, all that is needed for the pfc driver is a unique
				1523	* number for each pin. To this end use the pin layout from
				1524	* R-Car H3SiP to calculate a unique number for each pin.
				1525	*/
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	1526	SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
				1527	SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
				1528	SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
				1529	SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
				1530	SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
				1531	SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
				1532	SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
				1533	SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
				1534	SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
				1535	SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
				1536	SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
				1537	SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
				1538	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
				1539	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
				1540	SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
				1541	SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
				1542	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
				1543	SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
				1544	SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
				1545	SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
				1546	SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
				1547	SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
				1548	SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
				1549	SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
				1550	SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
				1551	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
				1552	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
				1553	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
				1554	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
				1555	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
				1556	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
				1557	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1558	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
				1559	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
				1560	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
				1561	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
				1562	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
				1563	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
				1564	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1565	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1566	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
				1567	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1568	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	1569	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1570	};
				1571
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	1572	/* - AUDIO CLOCK ------------------------------------------------------------ */
				1573	static const unsigned int audio_clk_a_a_pins[] = {
				1574	/* CLK A */
				1575	RCAR_GP_PIN(6, 22),
				1576	};
				1577	static const unsigned int audio_clk_a_a_mux[] = {
				1578	AUDIO_CLKA_A_MARK,
				1579	};
				1580	static const unsigned int audio_clk_a_b_pins[] = {
				1581	/* CLK A */
				1582	RCAR_GP_PIN(5, 4),
				1583	};
				1584	static const unsigned int audio_clk_a_b_mux[] = {
				1585	AUDIO_CLKA_B_MARK,
				1586	};
				1587	static const unsigned int audio_clk_a_c_pins[] = {
				1588	/* CLK A */
				1589	RCAR_GP_PIN(5, 19),
				1590	};
				1591	static const unsigned int audio_clk_a_c_mux[] = {
				1592	AUDIO_CLKA_C_MARK,
				1593	};
				1594	static const unsigned int audio_clk_b_a_pins[] = {
				1595	/* CLK B */
				1596	RCAR_GP_PIN(5, 12),
				1597	};
				1598	static const unsigned int audio_clk_b_a_mux[] = {
				1599	AUDIO_CLKB_A_MARK,
				1600	};
				1601	static const unsigned int audio_clk_b_b_pins[] = {
				1602	/* CLK B */
				1603	RCAR_GP_PIN(6, 23),
				1604	};
				1605	static const unsigned int audio_clk_b_b_mux[] = {
				1606	AUDIO_CLKB_B_MARK,
				1607	};
				1608	static const unsigned int audio_clk_c_a_pins[] = {
				1609	/* CLK C */
				1610	RCAR_GP_PIN(5, 21),
				1611	};
				1612	static const unsigned int audio_clk_c_a_mux[] = {
				1613	AUDIO_CLKC_A_MARK,
				1614	};
				1615	static const unsigned int audio_clk_c_b_pins[] = {
				1616	/* CLK C */
				1617	RCAR_GP_PIN(5, 0),
				1618	};
				1619	static const unsigned int audio_clk_c_b_mux[] = {
				1620	AUDIO_CLKC_B_MARK,
				1621	};
				1622	static const unsigned int audio_clkout_a_pins[] = {
				1623	/* CLKOUT */
				1624	RCAR_GP_PIN(5, 18),
				1625	};
				1626	static const unsigned int audio_clkout_a_mux[] = {
				1627	AUDIO_CLKOUT_A_MARK,
				1628	};
				1629	static const unsigned int audio_clkout_b_pins[] = {
				1630	/* CLKOUT */
				1631	RCAR_GP_PIN(6, 28),
				1632	};
				1633	static const unsigned int audio_clkout_b_mux[] = {
				1634	AUDIO_CLKOUT_B_MARK,
				1635	};
				1636	static const unsigned int audio_clkout_c_pins[] = {
				1637	/* CLKOUT */
				1638	RCAR_GP_PIN(5, 3),
				1639	};
				1640	static const unsigned int audio_clkout_c_mux[] = {
				1641	AUDIO_CLKOUT_C_MARK,
				1642	};
				1643	static const unsigned int audio_clkout_d_pins[] = {
				1644	/* CLKOUT */
				1645	RCAR_GP_PIN(5, 21),
				1646	};
				1647	static const unsigned int audio_clkout_d_mux[] = {
				1648	AUDIO_CLKOUT_D_MARK,
				1649	};
				1650	static const unsigned int audio_clkout1_a_pins[] = {
				1651	/* CLKOUT1 */
				1652	RCAR_GP_PIN(5, 15),
				1653	};
				1654	static const unsigned int audio_clkout1_a_mux[] = {
				1655	AUDIO_CLKOUT1_A_MARK,
				1656	};
				1657	static const unsigned int audio_clkout1_b_pins[] = {
				1658	/* CLKOUT1 */
				1659	RCAR_GP_PIN(6, 29),
				1660	};
				1661	static const unsigned int audio_clkout1_b_mux[] = {
				1662	AUDIO_CLKOUT1_B_MARK,
				1663	};
				1664	static const unsigned int audio_clkout2_a_pins[] = {
				1665	/* CLKOUT2 */
				1666	RCAR_GP_PIN(5, 16),
				1667	};
				1668	static const unsigned int audio_clkout2_a_mux[] = {
				1669	AUDIO_CLKOUT2_A_MARK,
				1670	};
				1671	static const unsigned int audio_clkout2_b_pins[] = {
				1672	/* CLKOUT2 */
				1673	RCAR_GP_PIN(6, 30),
				1674	};
				1675	static const unsigned int audio_clkout2_b_mux[] = {
				1676	AUDIO_CLKOUT2_B_MARK,
				1677	};
				1678	static const unsigned int audio_clkout3_a_pins[] = {
				1679	/* CLKOUT3 */
				1680	RCAR_GP_PIN(5, 19),
				1681	};
				1682	static const unsigned int audio_clkout3_a_mux[] = {
				1683	AUDIO_CLKOUT3_A_MARK,
				1684	};
				1685	static const unsigned int audio_clkout3_b_pins[] = {
				1686	/* CLKOUT3 */
				1687	RCAR_GP_PIN(6, 31),
				1688	};
				1689	static const unsigned int audio_clkout3_b_mux[] = {
				1690	AUDIO_CLKOUT3_B_MARK,
				1691	};
				1692
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	1693	/* - EtherAVB --------------------------------------------------------------- */
				1694	static const unsigned int avb_link_pins[] = {
				1695	/* AVB_LINK */
				1696	RCAR_GP_PIN(2, 12),
				1697	};
				1698	static const unsigned int avb_link_mux[] = {
				1699	AVB_LINK_MARK,
				1700	};
				1701	static const unsigned int avb_magic_pins[] = {
				1702	/* AVB_MAGIC_ */
				1703	RCAR_GP_PIN(2, 10),
				1704	};
				1705	static const unsigned int avb_magic_mux[] = {
				1706	AVB_MAGIC_MARK,
				1707	};
				1708	static const unsigned int avb_phy_int_pins[] = {
				1709	/* AVB_PHY_INT */
				1710	RCAR_GP_PIN(2, 11),
				1711	};
				1712	static const unsigned int avb_phy_int_mux[] = {
				1713	AVB_PHY_INT_MARK,
				1714	};
				1715	static const unsigned int avb_mdc_pins[] = {
				1716	/* AVB_MDC, AVB_MDIO */
				1717	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
				1718	};
				1719	static const unsigned int avb_mdc_mux[] = {
				1720	AVB_MDC_MARK, AVB_MDIO_MARK,
				1721	};
				1722	static const unsigned int avb_mii_pins[] = {
				1723	/*
				1724	* AVB_TX_CTL, AVB_TXC, AVB_TD0,
				1725	* AVB_TD1, AVB_TD2, AVB_TD3,
				1726	* AVB_RX_CTL, AVB_RXC, AVB_RD0,
				1727	* AVB_RD1, AVB_RD2, AVB_RD3,
				1728	* AVB_TXCREFCLK
				1729	*/
				1730	PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
				1731	PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
				1732	PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
				1733	PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
				1734	PIN_NUMBER('A', 12),
				1735
				1736	};
				1737	static const unsigned int avb_mii_mux[] = {
				1738	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
				1739	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
				1740	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
				1741	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
				1742	AVB_TXCREFCLK_MARK,
				1743	};
				1744	static const unsigned int avb_avtp_pps_pins[] = {
				1745	/* AVB_AVTP_PPS */
				1746	RCAR_GP_PIN(2, 6),
				1747	};
				1748	static const unsigned int avb_avtp_pps_mux[] = {
				1749	AVB_AVTP_PPS_MARK,
				1750	};
				1751	static const unsigned int avb_avtp_match_a_pins[] = {
				1752	/* AVB_AVTP_MATCH_A */
				1753	RCAR_GP_PIN(2, 13),
				1754	};
				1755	static const unsigned int avb_avtp_match_a_mux[] = {
				1756	AVB_AVTP_MATCH_A_MARK,
				1757	};
				1758	static const unsigned int avb_avtp_capture_a_pins[] = {
				1759	/* AVB_AVTP_CAPTURE_A */
				1760	RCAR_GP_PIN(2, 14),
				1761	};
				1762	static const unsigned int avb_avtp_capture_a_mux[] = {
				1763	AVB_AVTP_CAPTURE_A_MARK,
				1764	};
				1765	static const unsigned int avb_avtp_match_b_pins[] = {
				1766	/* AVB_AVTP_MATCH_B */
				1767	RCAR_GP_PIN(1, 8),
				1768	};
				1769	static const unsigned int avb_avtp_match_b_mux[] = {
				1770	AVB_AVTP_MATCH_B_MARK,
				1771	};
				1772	static const unsigned int avb_avtp_capture_b_pins[] = {
				1773	/* AVB_AVTP_CAPTURE_B */
				1774	RCAR_GP_PIN(1, 11),
				1775	};
				1776	static const unsigned int avb_avtp_capture_b_mux[] = {
				1777	AVB_AVTP_CAPTURE_B_MARK,
				1778	};
				1779
Ramesh Shanmugasundaram	a678abf	2017-11-10 13:58:49 +0000	[diff] [blame]	1780	/* - CAN ------------------------------------------------------------------ */
				1781	static const unsigned int can0_data_a_pins[] = {
				1782	/* TX, RX */
				1783	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
				1784	};
				1785	static const unsigned int can0_data_a_mux[] = {
				1786	CAN0_TX_A_MARK, CAN0_RX_A_MARK,
				1787	};
				1788	static const unsigned int can0_data_b_pins[] = {
				1789	/* TX, RX */
				1790	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
				1791	};
				1792	static const unsigned int can0_data_b_mux[] = {
				1793	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
				1794	};
				1795	static const unsigned int can1_data_pins[] = {
				1796	/* TX, RX */
				1797	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
				1798	};
				1799	static const unsigned int can1_data_mux[] = {
				1800	CAN1_TX_MARK, CAN1_RX_MARK,
				1801	};
				1802
				1803	/* - CAN Clock -------------------------------------------------------------- */
				1804	static const unsigned int can_clk_pins[] = {
				1805	/* CLK */
				1806	RCAR_GP_PIN(1, 25),
				1807	};
				1808	static const unsigned int can_clk_mux[] = {
				1809	CAN_CLK_MARK,
				1810	};
				1811
Ramesh Shanmugasundaram	0e1c7a9	2017-11-10 13:58:50 +0000	[diff] [blame]	1812	/* - CAN FD --------------------------------------------------------------- */
				1813	static const unsigned int canfd0_data_a_pins[] = {
				1814	/* TX, RX */
				1815	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
				1816	};
				1817	static const unsigned int canfd0_data_a_mux[] = {
				1818	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
				1819	};
				1820	static const unsigned int canfd0_data_b_pins[] = {
				1821	/* TX, RX */
				1822	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
				1823	};
				1824	static const unsigned int canfd0_data_b_mux[] = {
				1825	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
				1826	};
				1827	static const unsigned int canfd1_data_pins[] = {
				1828	/* TX, RX */
				1829	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
				1830	};
				1831	static const unsigned int canfd1_data_mux[] = {
				1832	CANFD1_TX_MARK, CANFD1_RX_MARK,
				1833	};
				1834
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	1835	/* - DRIF0 --------------------------------------------------------------- */
				1836	static const unsigned int drif0_ctrl_a_pins[] = {
				1837	/* CLK, SYNC */
				1838	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				1839	};
				1840	static const unsigned int drif0_ctrl_a_mux[] = {
				1841	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
				1842	};
				1843	static const unsigned int drif0_data0_a_pins[] = {
				1844	/* D0 */
				1845	RCAR_GP_PIN(6, 10),
				1846	};
				1847	static const unsigned int drif0_data0_a_mux[] = {
				1848	RIF0_D0_A_MARK,
				1849	};
				1850	static const unsigned int drif0_data1_a_pins[] = {
				1851	/* D1 */
				1852	RCAR_GP_PIN(6, 7),
				1853	};
				1854	static const unsigned int drif0_data1_a_mux[] = {
				1855	RIF0_D1_A_MARK,
				1856	};
				1857	static const unsigned int drif0_ctrl_b_pins[] = {
				1858	/* CLK, SYNC */
				1859	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
				1860	};
				1861	static const unsigned int drif0_ctrl_b_mux[] = {
				1862	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
				1863	};
				1864	static const unsigned int drif0_data0_b_pins[] = {
				1865	/* D0 */
				1866	RCAR_GP_PIN(5, 1),
				1867	};
				1868	static const unsigned int drif0_data0_b_mux[] = {
				1869	RIF0_D0_B_MARK,
				1870	};
				1871	static const unsigned int drif0_data1_b_pins[] = {
				1872	/* D1 */
				1873	RCAR_GP_PIN(5, 2),
				1874	};
				1875	static const unsigned int drif0_data1_b_mux[] = {
				1876	RIF0_D1_B_MARK,
				1877	};
				1878	static const unsigned int drif0_ctrl_c_pins[] = {
				1879	/* CLK, SYNC */
				1880	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
				1881	};
				1882	static const unsigned int drif0_ctrl_c_mux[] = {
				1883	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
				1884	};
				1885	static const unsigned int drif0_data0_c_pins[] = {
				1886	/* D0 */
				1887	RCAR_GP_PIN(5, 13),
				1888	};
				1889	static const unsigned int drif0_data0_c_mux[] = {
				1890	RIF0_D0_C_MARK,
				1891	};
				1892	static const unsigned int drif0_data1_c_pins[] = {
				1893	/* D1 */
				1894	RCAR_GP_PIN(5, 14),
				1895	};
				1896	static const unsigned int drif0_data1_c_mux[] = {
				1897	RIF0_D1_C_MARK,
				1898	};
				1899	/* - DRIF1 --------------------------------------------------------------- */
				1900	static const unsigned int drif1_ctrl_a_pins[] = {
				1901	/* CLK, SYNC */
				1902	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				1903	};
				1904	static const unsigned int drif1_ctrl_a_mux[] = {
				1905	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
				1906	};
				1907	static const unsigned int drif1_data0_a_pins[] = {
				1908	/* D0 */
				1909	RCAR_GP_PIN(6, 19),
				1910	};
				1911	static const unsigned int drif1_data0_a_mux[] = {
				1912	RIF1_D0_A_MARK,
				1913	};
				1914	static const unsigned int drif1_data1_a_pins[] = {
				1915	/* D1 */
				1916	RCAR_GP_PIN(6, 20),
				1917	};
				1918	static const unsigned int drif1_data1_a_mux[] = {
				1919	RIF1_D1_A_MARK,
				1920	};
				1921	static const unsigned int drif1_ctrl_b_pins[] = {
				1922	/* CLK, SYNC */
				1923	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
				1924	};
				1925	static const unsigned int drif1_ctrl_b_mux[] = {
				1926	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
				1927	};
				1928	static const unsigned int drif1_data0_b_pins[] = {
				1929	/* D0 */
				1930	RCAR_GP_PIN(5, 7),
				1931	};
				1932	static const unsigned int drif1_data0_b_mux[] = {
				1933	RIF1_D0_B_MARK,
				1934	};
				1935	static const unsigned int drif1_data1_b_pins[] = {
				1936	/* D1 */
				1937	RCAR_GP_PIN(5, 8),
				1938	};
				1939	static const unsigned int drif1_data1_b_mux[] = {
				1940	RIF1_D1_B_MARK,
				1941	};
				1942	static const unsigned int drif1_ctrl_c_pins[] = {
				1943	/* CLK, SYNC */
				1944	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
				1945	};
				1946	static const unsigned int drif1_ctrl_c_mux[] = {
				1947	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
				1948	};
				1949	static const unsigned int drif1_data0_c_pins[] = {
				1950	/* D0 */
				1951	RCAR_GP_PIN(5, 6),
				1952	};
				1953	static const unsigned int drif1_data0_c_mux[] = {
				1954	RIF1_D0_C_MARK,
				1955	};
				1956	static const unsigned int drif1_data1_c_pins[] = {
				1957	/* D1 */
				1958	RCAR_GP_PIN(5, 10),
				1959	};
				1960	static const unsigned int drif1_data1_c_mux[] = {
				1961	RIF1_D1_C_MARK,
				1962	};
				1963	/* - DRIF2 --------------------------------------------------------------- */
				1964	static const unsigned int drif2_ctrl_a_pins[] = {
				1965	/* CLK, SYNC */
				1966	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				1967	};
				1968	static const unsigned int drif2_ctrl_a_mux[] = {
				1969	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
				1970	};
				1971	static const unsigned int drif2_data0_a_pins[] = {
				1972	/* D0 */
				1973	RCAR_GP_PIN(6, 7),
				1974	};
				1975	static const unsigned int drif2_data0_a_mux[] = {
				1976	RIF2_D0_A_MARK,
				1977	};
				1978	static const unsigned int drif2_data1_a_pins[] = {
				1979	/* D1 */
				1980	RCAR_GP_PIN(6, 10),
				1981	};
				1982	static const unsigned int drif2_data1_a_mux[] = {
				1983	RIF2_D1_A_MARK,
				1984	};
				1985	static const unsigned int drif2_ctrl_b_pins[] = {
				1986	/* CLK, SYNC */
				1987	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				1988	};
				1989	static const unsigned int drif2_ctrl_b_mux[] = {
				1990	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
				1991	};
				1992	static const unsigned int drif2_data0_b_pins[] = {
				1993	/* D0 */
				1994	RCAR_GP_PIN(6, 30),
				1995	};
				1996	static const unsigned int drif2_data0_b_mux[] = {
				1997	RIF2_D0_B_MARK,
				1998	};
				1999	static const unsigned int drif2_data1_b_pins[] = {
				2000	/* D1 */
				2001	RCAR_GP_PIN(6, 31),
				2002	};
				2003	static const unsigned int drif2_data1_b_mux[] = {
				2004	RIF2_D1_B_MARK,
				2005	};
				2006	/* - DRIF3 --------------------------------------------------------------- */
				2007	static const unsigned int drif3_ctrl_a_pins[] = {
				2008	/* CLK, SYNC */
				2009	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				2010	};
				2011	static const unsigned int drif3_ctrl_a_mux[] = {
				2012	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
				2013	};
				2014	static const unsigned int drif3_data0_a_pins[] = {
				2015	/* D0 */
				2016	RCAR_GP_PIN(6, 19),
				2017	};
				2018	static const unsigned int drif3_data0_a_mux[] = {
				2019	RIF3_D0_A_MARK,
				2020	};
				2021	static const unsigned int drif3_data1_a_pins[] = {
				2022	/* D1 */
				2023	RCAR_GP_PIN(6, 20),
				2024	};
				2025	static const unsigned int drif3_data1_a_mux[] = {
				2026	RIF3_D1_A_MARK,
				2027	};
				2028	static const unsigned int drif3_ctrl_b_pins[] = {
				2029	/* CLK, SYNC */
				2030	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
				2031	};
				2032	static const unsigned int drif3_ctrl_b_mux[] = {
				2033	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
				2034	};
				2035	static const unsigned int drif3_data0_b_pins[] = {
				2036	/* D0 */
				2037	RCAR_GP_PIN(6, 28),
				2038	};
				2039	static const unsigned int drif3_data0_b_mux[] = {
				2040	RIF3_D0_B_MARK,
				2041	};
				2042	static const unsigned int drif3_data1_b_pins[] = {
				2043	/* D1 */
				2044	RCAR_GP_PIN(6, 29),
				2045	};
				2046	static const unsigned int drif3_data1_b_mux[] = {
				2047	RIF3_D1_B_MARK,
				2048	};
				2049
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	2050	/* - DU --------------------------------------------------------------------- */
				2051	static const unsigned int du_rgb666_pins[] = {
				2052	/* R[7:2], G[7:2], B[7:2] */
				2053	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
				2054	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				2055	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
				2056	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
				2057	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
				2058	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
				2059	};
				2060	static const unsigned int du_rgb666_mux[] = {
				2061	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
				2062	DU_DR3_MARK, DU_DR2_MARK,
				2063	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
				2064	DU_DG3_MARK, DU_DG2_MARK,
				2065	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
				2066	DU_DB3_MARK, DU_DB2_MARK,
				2067	};
				2068	static const unsigned int du_rgb888_pins[] = {
				2069	/* R[7:0], G[7:0], B[7:0] */
				2070	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
				2071	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				2072	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
				2073	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
				2074	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
				2075	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
				2076	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
				2077	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
				2078	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
				2079	};
				2080	static const unsigned int du_rgb888_mux[] = {
				2081	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
				2082	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
				2083	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
				2084	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
				2085	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
				2086	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
				2087	};
				2088	static const unsigned int du_clk_out_0_pins[] = {
				2089	/* CLKOUT */
				2090	RCAR_GP_PIN(1, 27),
				2091	};
				2092	static const unsigned int du_clk_out_0_mux[] = {
				2093	DU_DOTCLKOUT0_MARK
				2094	};
				2095	static const unsigned int du_clk_out_1_pins[] = {
				2096	/* CLKOUT */
				2097	RCAR_GP_PIN(2, 3),
				2098	};
				2099	static const unsigned int du_clk_out_1_mux[] = {
				2100	DU_DOTCLKOUT1_MARK
				2101	};
				2102	static const unsigned int du_sync_pins[] = {
				2103	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
				2104	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
				2105	};
				2106	static const unsigned int du_sync_mux[] = {
				2107	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
				2108	};
				2109	static const unsigned int du_oddf_pins[] = {
				2110	/* EXDISP/EXODDF/EXCDE */
				2111	RCAR_GP_PIN(2, 2),
				2112	};
				2113	static const unsigned int du_oddf_mux[] = {
				2114	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
				2115	};
				2116	static const unsigned int du_cde_pins[] = {
				2117	/* CDE */
				2118	RCAR_GP_PIN(2, 0),
				2119	};
				2120	static const unsigned int du_cde_mux[] = {
				2121	DU_CDE_MARK,
				2122	};
				2123	static const unsigned int du_disp_pins[] = {
				2124	/* DISP */
				2125	RCAR_GP_PIN(2, 1),
				2126	};
				2127	static const unsigned int du_disp_mux[] = {
				2128	DU_DISP_MARK,
				2129	};
				2130
Wolfram Sang	7a362e3	2017-10-09 10:20:53 +0200	[diff] [blame]	2131	/* - HSCIF0 ----------------------------------------------------------------- */
				2132	static const unsigned int hscif0_data_pins[] = {
				2133	/* RX, TX */
				2134	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
				2135	};
				2136	static const unsigned int hscif0_data_mux[] = {
				2137	HRX0_MARK, HTX0_MARK,
				2138	};
				2139	static const unsigned int hscif0_clk_pins[] = {
				2140	/* SCK */
				2141	RCAR_GP_PIN(5, 12),
				2142	};
				2143	static const unsigned int hscif0_clk_mux[] = {
				2144	HSCK0_MARK,
				2145	};
				2146	static const unsigned int hscif0_ctrl_pins[] = {
				2147	/* RTS, CTS */
				2148	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
				2149	};
				2150	static const unsigned int hscif0_ctrl_mux[] = {
				2151	HRTS0_N_MARK, HCTS0_N_MARK,
				2152	};
				2153	/* - HSCIF1 ----------------------------------------------------------------- */
				2154	static const unsigned int hscif1_data_a_pins[] = {
				2155	/* RX, TX */
				2156	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
				2157	};
				2158	static const unsigned int hscif1_data_a_mux[] = {
				2159	HRX1_A_MARK, HTX1_A_MARK,
				2160	};
				2161	static const unsigned int hscif1_clk_a_pins[] = {
				2162	/* SCK */
				2163	RCAR_GP_PIN(6, 21),
				2164	};
				2165	static const unsigned int hscif1_clk_a_mux[] = {
				2166	HSCK1_A_MARK,
				2167	};
				2168	static const unsigned int hscif1_ctrl_a_pins[] = {
				2169	/* RTS, CTS */
				2170	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
				2171	};
				2172	static const unsigned int hscif1_ctrl_a_mux[] = {
				2173	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
				2174	};
				2175
				2176	static const unsigned int hscif1_data_b_pins[] = {
				2177	/* RX, TX */
				2178	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
				2179	};
				2180	static const unsigned int hscif1_data_b_mux[] = {
				2181	HRX1_B_MARK, HTX1_B_MARK,
				2182	};
				2183	static const unsigned int hscif1_clk_b_pins[] = {
				2184	/* SCK */
				2185	RCAR_GP_PIN(5, 0),
				2186	};
				2187	static const unsigned int hscif1_clk_b_mux[] = {
				2188	HSCK1_B_MARK,
				2189	};
				2190	static const unsigned int hscif1_ctrl_b_pins[] = {
				2191	/* RTS, CTS */
				2192	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
				2193	};
				2194	static const unsigned int hscif1_ctrl_b_mux[] = {
				2195	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
				2196	};
				2197	/* - HSCIF2 ----------------------------------------------------------------- */
				2198	static const unsigned int hscif2_data_a_pins[] = {
				2199	/* RX, TX */
				2200	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				2201	};
				2202	static const unsigned int hscif2_data_a_mux[] = {
				2203	HRX2_A_MARK, HTX2_A_MARK,
				2204	};
				2205	static const unsigned int hscif2_clk_a_pins[] = {
				2206	/* SCK */
				2207	RCAR_GP_PIN(6, 10),
				2208	};
				2209	static const unsigned int hscif2_clk_a_mux[] = {
				2210	HSCK2_A_MARK,
				2211	};
				2212	static const unsigned int hscif2_ctrl_a_pins[] = {
				2213	/* RTS, CTS */
				2214	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
				2215	};
				2216	static const unsigned int hscif2_ctrl_a_mux[] = {
				2217	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
				2218	};
				2219
				2220	static const unsigned int hscif2_data_b_pins[] = {
				2221	/* RX, TX */
				2222	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				2223	};
				2224	static const unsigned int hscif2_data_b_mux[] = {
				2225	HRX2_B_MARK, HTX2_B_MARK,
				2226	};
				2227	static const unsigned int hscif2_clk_b_pins[] = {
				2228	/* SCK */
				2229	RCAR_GP_PIN(6, 21),
				2230	};
				2231	static const unsigned int hscif2_clk_b_mux[] = {
				2232	HSCK2_B_MARK,
				2233	};
				2234	static const unsigned int hscif2_ctrl_b_pins[] = {
				2235	/* RTS, CTS */
				2236	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
				2237	};
				2238	static const unsigned int hscif2_ctrl_b_mux[] = {
				2239	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
				2240	};
				2241
				2242	static const unsigned int hscif2_data_c_pins[] = {
				2243	/* RX, TX */
				2244	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
				2245	};
				2246	static const unsigned int hscif2_data_c_mux[] = {
				2247	HRX2_C_MARK, HTX2_C_MARK,
				2248	};
				2249	static const unsigned int hscif2_clk_c_pins[] = {
				2250	/* SCK */
				2251	RCAR_GP_PIN(6, 24),
				2252	};
				2253	static const unsigned int hscif2_clk_c_mux[] = {
				2254	HSCK2_C_MARK,
				2255	};
				2256	static const unsigned int hscif2_ctrl_c_pins[] = {
				2257	/* RTS, CTS */
				2258	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
				2259	};
				2260	static const unsigned int hscif2_ctrl_c_mux[] = {
				2261	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
				2262	};
				2263	/* - HSCIF3 ----------------------------------------------------------------- */
				2264	static const unsigned int hscif3_data_a_pins[] = {
				2265	/* RX, TX */
				2266	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
				2267	};
				2268	static const unsigned int hscif3_data_a_mux[] = {
				2269	HRX3_A_MARK, HTX3_A_MARK,
				2270	};
				2271	static const unsigned int hscif3_clk_pins[] = {
				2272	/* SCK */
				2273	RCAR_GP_PIN(1, 22),
				2274	};
				2275	static const unsigned int hscif3_clk_mux[] = {
				2276	HSCK3_MARK,
				2277	};
				2278	static const unsigned int hscif3_ctrl_pins[] = {
				2279	/* RTS, CTS */
				2280	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
				2281	};
				2282	static const unsigned int hscif3_ctrl_mux[] = {
				2283	HRTS3_N_MARK, HCTS3_N_MARK,
				2284	};
				2285
				2286	static const unsigned int hscif3_data_b_pins[] = {
				2287	/* RX, TX */
				2288	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
				2289	};
				2290	static const unsigned int hscif3_data_b_mux[] = {
				2291	HRX3_B_MARK, HTX3_B_MARK,
				2292	};
				2293	static const unsigned int hscif3_data_c_pins[] = {
				2294	/* RX, TX */
				2295	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
				2296	};
				2297	static const unsigned int hscif3_data_c_mux[] = {
				2298	HRX3_C_MARK, HTX3_C_MARK,
				2299	};
				2300	static const unsigned int hscif3_data_d_pins[] = {
				2301	/* RX, TX */
				2302	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
				2303	};
				2304	static const unsigned int hscif3_data_d_mux[] = {
				2305	HRX3_D_MARK, HTX3_D_MARK,
				2306	};
				2307	/* - HSCIF4 ----------------------------------------------------------------- */
				2308	static const unsigned int hscif4_data_a_pins[] = {
				2309	/* RX, TX */
				2310	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
				2311	};
				2312	static const unsigned int hscif4_data_a_mux[] = {
				2313	HRX4_A_MARK, HTX4_A_MARK,
				2314	};
				2315	static const unsigned int hscif4_clk_pins[] = {
				2316	/* SCK */
				2317	RCAR_GP_PIN(1, 11),
				2318	};
				2319	static const unsigned int hscif4_clk_mux[] = {
				2320	HSCK4_MARK,
				2321	};
				2322	static const unsigned int hscif4_ctrl_pins[] = {
				2323	/* RTS, CTS */
				2324	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
				2325	};
				2326	static const unsigned int hscif4_ctrl_mux[] = {
				2327	HRTS4_N_MARK, HCTS4_N_MARK,
				2328	};
				2329
				2330	static const unsigned int hscif4_data_b_pins[] = {
				2331	/* RX, TX */
				2332	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
				2333	};
				2334	static const unsigned int hscif4_data_b_mux[] = {
				2335	HRX4_B_MARK, HTX4_B_MARK,
				2336	};
				2337
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	2338	/* - I2C -------------------------------------------------------------------- */
				2339	static const unsigned int i2c1_a_pins[] = {
				2340	/* SDA, SCL */
				2341	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
				2342	};
				2343	static const unsigned int i2c1_a_mux[] = {
				2344	SDA1_A_MARK, SCL1_A_MARK,
				2345	};
				2346	static const unsigned int i2c1_b_pins[] = {
				2347	/* SDA, SCL */
				2348	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
				2349	};
				2350	static const unsigned int i2c1_b_mux[] = {
				2351	SDA1_B_MARK, SCL1_B_MARK,
				2352	};
				2353	static const unsigned int i2c2_a_pins[] = {
				2354	/* SDA, SCL */
				2355	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
				2356	};
				2357	static const unsigned int i2c2_a_mux[] = {
				2358	SDA2_A_MARK, SCL2_A_MARK,
				2359	};
				2360	static const unsigned int i2c2_b_pins[] = {
				2361	/* SDA, SCL */
				2362	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
				2363	};
				2364	static const unsigned int i2c2_b_mux[] = {
				2365	SDA2_B_MARK, SCL2_B_MARK,
				2366	};
				2367	static const unsigned int i2c6_a_pins[] = {
				2368	/* SDA, SCL */
				2369	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
				2370	};
				2371	static const unsigned int i2c6_a_mux[] = {
				2372	SDA6_A_MARK, SCL6_A_MARK,
				2373	};
				2374	static const unsigned int i2c6_b_pins[] = {
				2375	/* SDA, SCL */
				2376	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
				2377	};
				2378	static const unsigned int i2c6_b_mux[] = {
				2379	SDA6_B_MARK, SCL6_B_MARK,
				2380	};
				2381	static const unsigned int i2c6_c_pins[] = {
				2382	/* SDA, SCL */
				2383	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
				2384	};
				2385	static const unsigned int i2c6_c_mux[] = {
				2386	SDA6_C_MARK, SCL6_C_MARK,
				2387	};
				2388
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame]	2389	/* - INTC-EX ---------------------------------------------------------------- */
				2390	static const unsigned int intc_ex_irq0_pins[] = {
				2391	/* IRQ0 */
				2392	RCAR_GP_PIN(2, 0),
				2393	};
				2394	static const unsigned int intc_ex_irq0_mux[] = {
				2395	IRQ0_MARK,
				2396	};
				2397	static const unsigned int intc_ex_irq1_pins[] = {
				2398	/* IRQ1 */
				2399	RCAR_GP_PIN(2, 1),
				2400	};
				2401	static const unsigned int intc_ex_irq1_mux[] = {
				2402	IRQ1_MARK,
				2403	};
				2404	static const unsigned int intc_ex_irq2_pins[] = {
				2405	/* IRQ2 */
				2406	RCAR_GP_PIN(2, 2),
				2407	};
				2408	static const unsigned int intc_ex_irq2_mux[] = {
				2409	IRQ2_MARK,
				2410	};
				2411	static const unsigned int intc_ex_irq3_pins[] = {
				2412	/* IRQ3 */
				2413	RCAR_GP_PIN(2, 3),
				2414	};
				2415	static const unsigned int intc_ex_irq3_mux[] = {
				2416	IRQ3_MARK,
				2417	};
				2418	static const unsigned int intc_ex_irq4_pins[] = {
				2419	/* IRQ4 */
				2420	RCAR_GP_PIN(2, 4),
				2421	};
				2422	static const unsigned int intc_ex_irq4_mux[] = {
				2423	IRQ4_MARK,
				2424	};
				2425	static const unsigned int intc_ex_irq5_pins[] = {
				2426	/* IRQ5 */
				2427	RCAR_GP_PIN(2, 5),
				2428	};
				2429	static const unsigned int intc_ex_irq5_mux[] = {
				2430	IRQ5_MARK,
				2431	};
				2432
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	2433	/* - MSIOF0 ----------------------------------------------------------------- */
				2434	static const unsigned int msiof0_clk_pins[] = {
				2435	/* SCK */
				2436	RCAR_GP_PIN(5, 17),
				2437	};
				2438	static const unsigned int msiof0_clk_mux[] = {
				2439	MSIOF0_SCK_MARK,
				2440	};
				2441	static const unsigned int msiof0_sync_pins[] = {
				2442	/* SYNC */
				2443	RCAR_GP_PIN(5, 18),
				2444	};
				2445	static const unsigned int msiof0_sync_mux[] = {
				2446	MSIOF0_SYNC_MARK,
				2447	};
				2448	static const unsigned int msiof0_ss1_pins[] = {
				2449	/* SS1 */
				2450	RCAR_GP_PIN(5, 19),
				2451	};
				2452	static const unsigned int msiof0_ss1_mux[] = {
				2453	MSIOF0_SS1_MARK,
				2454	};
				2455	static const unsigned int msiof0_ss2_pins[] = {
				2456	/* SS2 */
				2457	RCAR_GP_PIN(5, 21),
				2458	};
				2459	static const unsigned int msiof0_ss2_mux[] = {
				2460	MSIOF0_SS2_MARK,
				2461	};
				2462	static const unsigned int msiof0_txd_pins[] = {
				2463	/* TXD */
				2464	RCAR_GP_PIN(5, 20),
				2465	};
				2466	static const unsigned int msiof0_txd_mux[] = {
				2467	MSIOF0_TXD_MARK,
				2468	};
				2469	static const unsigned int msiof0_rxd_pins[] = {
				2470	/* RXD */
				2471	RCAR_GP_PIN(5, 22),
				2472	};
				2473	static const unsigned int msiof0_rxd_mux[] = {
				2474	MSIOF0_RXD_MARK,
				2475	};
				2476	/* - MSIOF1 ----------------------------------------------------------------- */
				2477	static const unsigned int msiof1_clk_a_pins[] = {
				2478	/* SCK */
				2479	RCAR_GP_PIN(6, 8),
				2480	};
				2481	static const unsigned int msiof1_clk_a_mux[] = {
				2482	MSIOF1_SCK_A_MARK,
				2483	};
				2484	static const unsigned int msiof1_sync_a_pins[] = {
				2485	/* SYNC */
				2486	RCAR_GP_PIN(6, 9),
				2487	};
				2488	static const unsigned int msiof1_sync_a_mux[] = {
				2489	MSIOF1_SYNC_A_MARK,
				2490	};
				2491	static const unsigned int msiof1_ss1_a_pins[] = {
				2492	/* SS1 */
				2493	RCAR_GP_PIN(6, 5),
				2494	};
				2495	static const unsigned int msiof1_ss1_a_mux[] = {
				2496	MSIOF1_SS1_A_MARK,
				2497	};
				2498	static const unsigned int msiof1_ss2_a_pins[] = {
				2499	/* SS2 */
				2500	RCAR_GP_PIN(6, 6),
				2501	};
				2502	static const unsigned int msiof1_ss2_a_mux[] = {
				2503	MSIOF1_SS2_A_MARK,
				2504	};
				2505	static const unsigned int msiof1_txd_a_pins[] = {
				2506	/* TXD */
				2507	RCAR_GP_PIN(6, 7),
				2508	};
				2509	static const unsigned int msiof1_txd_a_mux[] = {
				2510	MSIOF1_TXD_A_MARK,
				2511	};
				2512	static const unsigned int msiof1_rxd_a_pins[] = {
				2513	/* RXD */
				2514	RCAR_GP_PIN(6, 10),
				2515	};
				2516	static const unsigned int msiof1_rxd_a_mux[] = {
				2517	MSIOF1_RXD_A_MARK,
				2518	};
				2519	static const unsigned int msiof1_clk_b_pins[] = {
				2520	/* SCK */
				2521	RCAR_GP_PIN(5, 9),
				2522	};
				2523	static const unsigned int msiof1_clk_b_mux[] = {
				2524	MSIOF1_SCK_B_MARK,
				2525	};
				2526	static const unsigned int msiof1_sync_b_pins[] = {
				2527	/* SYNC */
				2528	RCAR_GP_PIN(5, 3),
				2529	};
				2530	static const unsigned int msiof1_sync_b_mux[] = {
				2531	MSIOF1_SYNC_B_MARK,
				2532	};
				2533	static const unsigned int msiof1_ss1_b_pins[] = {
				2534	/* SS1 */
				2535	RCAR_GP_PIN(5, 4),
				2536	};
				2537	static const unsigned int msiof1_ss1_b_mux[] = {
				2538	MSIOF1_SS1_B_MARK,
				2539	};
				2540	static const unsigned int msiof1_ss2_b_pins[] = {
				2541	/* SS2 */
				2542	RCAR_GP_PIN(5, 0),
				2543	};
				2544	static const unsigned int msiof1_ss2_b_mux[] = {
				2545	MSIOF1_SS2_B_MARK,
				2546	};
				2547	static const unsigned int msiof1_txd_b_pins[] = {
				2548	/* TXD */
				2549	RCAR_GP_PIN(5, 8),
				2550	};
				2551	static const unsigned int msiof1_txd_b_mux[] = {
				2552	MSIOF1_TXD_B_MARK,
				2553	};
				2554	static const unsigned int msiof1_rxd_b_pins[] = {
				2555	/* RXD */
				2556	RCAR_GP_PIN(5, 7),
				2557	};
				2558	static const unsigned int msiof1_rxd_b_mux[] = {
				2559	MSIOF1_RXD_B_MARK,
				2560	};
				2561	static const unsigned int msiof1_clk_c_pins[] = {
				2562	/* SCK */
				2563	RCAR_GP_PIN(6, 17),
				2564	};
				2565	static const unsigned int msiof1_clk_c_mux[] = {
				2566	MSIOF1_SCK_C_MARK,
				2567	};
				2568	static const unsigned int msiof1_sync_c_pins[] = {
				2569	/* SYNC */
				2570	RCAR_GP_PIN(6, 18),
				2571	};
				2572	static const unsigned int msiof1_sync_c_mux[] = {
				2573	MSIOF1_SYNC_C_MARK,
				2574	};
				2575	static const unsigned int msiof1_ss1_c_pins[] = {
				2576	/* SS1 */
				2577	RCAR_GP_PIN(6, 21),
				2578	};
				2579	static const unsigned int msiof1_ss1_c_mux[] = {
				2580	MSIOF1_SS1_C_MARK,
				2581	};
				2582	static const unsigned int msiof1_ss2_c_pins[] = {
				2583	/* SS2 */
				2584	RCAR_GP_PIN(6, 27),
				2585	};
				2586	static const unsigned int msiof1_ss2_c_mux[] = {
				2587	MSIOF1_SS2_C_MARK,
				2588	};
				2589	static const unsigned int msiof1_txd_c_pins[] = {
				2590	/* TXD */
				2591	RCAR_GP_PIN(6, 20),
				2592	};
				2593	static const unsigned int msiof1_txd_c_mux[] = {
				2594	MSIOF1_TXD_C_MARK,
				2595	};
				2596	static const unsigned int msiof1_rxd_c_pins[] = {
				2597	/* RXD */
				2598	RCAR_GP_PIN(6, 19),
				2599	};
				2600	static const unsigned int msiof1_rxd_c_mux[] = {
				2601	MSIOF1_RXD_C_MARK,
				2602	};
				2603	static const unsigned int msiof1_clk_d_pins[] = {
				2604	/* SCK */
				2605	RCAR_GP_PIN(5, 12),
				2606	};
				2607	static const unsigned int msiof1_clk_d_mux[] = {
				2608	MSIOF1_SCK_D_MARK,
				2609	};
				2610	static const unsigned int msiof1_sync_d_pins[] = {
				2611	/* SYNC */
				2612	RCAR_GP_PIN(5, 15),
				2613	};
				2614	static const unsigned int msiof1_sync_d_mux[] = {
				2615	MSIOF1_SYNC_D_MARK,
				2616	};
				2617	static const unsigned int msiof1_ss1_d_pins[] = {
				2618	/* SS1 */
				2619	RCAR_GP_PIN(5, 16),
				2620	};
				2621	static const unsigned int msiof1_ss1_d_mux[] = {
				2622	MSIOF1_SS1_D_MARK,
				2623	};
				2624	static const unsigned int msiof1_ss2_d_pins[] = {
				2625	/* SS2 */
				2626	RCAR_GP_PIN(5, 21),
				2627	};
				2628	static const unsigned int msiof1_ss2_d_mux[] = {
				2629	MSIOF1_SS2_D_MARK,
				2630	};
				2631	static const unsigned int msiof1_txd_d_pins[] = {
				2632	/* TXD */
				2633	RCAR_GP_PIN(5, 14),
				2634	};
				2635	static const unsigned int msiof1_txd_d_mux[] = {
				2636	MSIOF1_TXD_D_MARK,
				2637	};
				2638	static const unsigned int msiof1_rxd_d_pins[] = {
				2639	/* RXD */
				2640	RCAR_GP_PIN(5, 13),
				2641	};
				2642	static const unsigned int msiof1_rxd_d_mux[] = {
				2643	MSIOF1_RXD_D_MARK,
				2644	};
				2645	static const unsigned int msiof1_clk_e_pins[] = {
				2646	/* SCK */
				2647	RCAR_GP_PIN(3, 0),
				2648	};
				2649	static const unsigned int msiof1_clk_e_mux[] = {
				2650	MSIOF1_SCK_E_MARK,
				2651	};
				2652	static const unsigned int msiof1_sync_e_pins[] = {
				2653	/* SYNC */
				2654	RCAR_GP_PIN(3, 1),
				2655	};
				2656	static const unsigned int msiof1_sync_e_mux[] = {
				2657	MSIOF1_SYNC_E_MARK,
				2658	};
				2659	static const unsigned int msiof1_ss1_e_pins[] = {
				2660	/* SS1 */
				2661	RCAR_GP_PIN(3, 4),
				2662	};
				2663	static const unsigned int msiof1_ss1_e_mux[] = {
				2664	MSIOF1_SS1_E_MARK,
				2665	};
				2666	static const unsigned int msiof1_ss2_e_pins[] = {
				2667	/* SS2 */
				2668	RCAR_GP_PIN(3, 5),
				2669	};
				2670	static const unsigned int msiof1_ss2_e_mux[] = {
				2671	MSIOF1_SS2_E_MARK,
				2672	};
				2673	static const unsigned int msiof1_txd_e_pins[] = {
				2674	/* TXD */
				2675	RCAR_GP_PIN(3, 3),
				2676	};
				2677	static const unsigned int msiof1_txd_e_mux[] = {
				2678	MSIOF1_TXD_E_MARK,
				2679	};
				2680	static const unsigned int msiof1_rxd_e_pins[] = {
				2681	/* RXD */
				2682	RCAR_GP_PIN(3, 2),
				2683	};
				2684	static const unsigned int msiof1_rxd_e_mux[] = {
				2685	MSIOF1_RXD_E_MARK,
				2686	};
				2687	static const unsigned int msiof1_clk_f_pins[] = {
				2688	/* SCK */
				2689	RCAR_GP_PIN(5, 23),
				2690	};
				2691	static const unsigned int msiof1_clk_f_mux[] = {
				2692	MSIOF1_SCK_F_MARK,
				2693	};
				2694	static const unsigned int msiof1_sync_f_pins[] = {
				2695	/* SYNC */
				2696	RCAR_GP_PIN(5, 24),
				2697	};
				2698	static const unsigned int msiof1_sync_f_mux[] = {
				2699	MSIOF1_SYNC_F_MARK,
				2700	};
				2701	static const unsigned int msiof1_ss1_f_pins[] = {
				2702	/* SS1 */
				2703	RCAR_GP_PIN(6, 1),
				2704	};
				2705	static const unsigned int msiof1_ss1_f_mux[] = {
				2706	MSIOF1_SS1_F_MARK,
				2707	};
				2708	static const unsigned int msiof1_ss2_f_pins[] = {
				2709	/* SS2 */
				2710	RCAR_GP_PIN(6, 2),
				2711	};
				2712	static const unsigned int msiof1_ss2_f_mux[] = {
				2713	MSIOF1_SS2_F_MARK,
				2714	};
				2715	static const unsigned int msiof1_txd_f_pins[] = {
				2716	/* TXD */
				2717	RCAR_GP_PIN(6, 0),
				2718	};
				2719	static const unsigned int msiof1_txd_f_mux[] = {
				2720	MSIOF1_TXD_F_MARK,
				2721	};
				2722	static const unsigned int msiof1_rxd_f_pins[] = {
				2723	/* RXD */
				2724	RCAR_GP_PIN(5, 25),
				2725	};
				2726	static const unsigned int msiof1_rxd_f_mux[] = {
				2727	MSIOF1_RXD_F_MARK,
				2728	};
				2729	static const unsigned int msiof1_clk_g_pins[] = {
				2730	/* SCK */
				2731	RCAR_GP_PIN(3, 6),
				2732	};
				2733	static const unsigned int msiof1_clk_g_mux[] = {
				2734	MSIOF1_SCK_G_MARK,
				2735	};
				2736	static const unsigned int msiof1_sync_g_pins[] = {
				2737	/* SYNC */
				2738	RCAR_GP_PIN(3, 7),
				2739	};
				2740	static const unsigned int msiof1_sync_g_mux[] = {
				2741	MSIOF1_SYNC_G_MARK,
				2742	};
				2743	static const unsigned int msiof1_ss1_g_pins[] = {
				2744	/* SS1 */
				2745	RCAR_GP_PIN(3, 10),
				2746	};
				2747	static const unsigned int msiof1_ss1_g_mux[] = {
				2748	MSIOF1_SS1_G_MARK,
				2749	};
				2750	static const unsigned int msiof1_ss2_g_pins[] = {
				2751	/* SS2 */
				2752	RCAR_GP_PIN(3, 11),
				2753	};
				2754	static const unsigned int msiof1_ss2_g_mux[] = {
				2755	MSIOF1_SS2_G_MARK,
				2756	};
				2757	static const unsigned int msiof1_txd_g_pins[] = {
				2758	/* TXD */
				2759	RCAR_GP_PIN(3, 9),
				2760	};
				2761	static const unsigned int msiof1_txd_g_mux[] = {
				2762	MSIOF1_TXD_G_MARK,
				2763	};
				2764	static const unsigned int msiof1_rxd_g_pins[] = {
				2765	/* RXD */
				2766	RCAR_GP_PIN(3, 8),
				2767	};
				2768	static const unsigned int msiof1_rxd_g_mux[] = {
				2769	MSIOF1_RXD_G_MARK,
				2770	};
				2771	/* - MSIOF2 ----------------------------------------------------------------- */
				2772	static const unsigned int msiof2_clk_a_pins[] = {
				2773	/* SCK */
				2774	RCAR_GP_PIN(1, 9),
				2775	};
				2776	static const unsigned int msiof2_clk_a_mux[] = {
				2777	MSIOF2_SCK_A_MARK,
				2778	};
				2779	static const unsigned int msiof2_sync_a_pins[] = {
				2780	/* SYNC */
				2781	RCAR_GP_PIN(1, 8),
				2782	};
				2783	static const unsigned int msiof2_sync_a_mux[] = {
				2784	MSIOF2_SYNC_A_MARK,
				2785	};
				2786	static const unsigned int msiof2_ss1_a_pins[] = {
				2787	/* SS1 */
				2788	RCAR_GP_PIN(1, 6),
				2789	};
				2790	static const unsigned int msiof2_ss1_a_mux[] = {
				2791	MSIOF2_SS1_A_MARK,
				2792	};
				2793	static const unsigned int msiof2_ss2_a_pins[] = {
				2794	/* SS2 */
				2795	RCAR_GP_PIN(1, 7),
				2796	};
				2797	static const unsigned int msiof2_ss2_a_mux[] = {
				2798	MSIOF2_SS2_A_MARK,
				2799	};
				2800	static const unsigned int msiof2_txd_a_pins[] = {
				2801	/* TXD */
				2802	RCAR_GP_PIN(1, 11),
				2803	};
				2804	static const unsigned int msiof2_txd_a_mux[] = {
				2805	MSIOF2_TXD_A_MARK,
				2806	};
				2807	static const unsigned int msiof2_rxd_a_pins[] = {
				2808	/* RXD */
				2809	RCAR_GP_PIN(1, 10),
				2810	};
				2811	static const unsigned int msiof2_rxd_a_mux[] = {
				2812	MSIOF2_RXD_A_MARK,
				2813	};
				2814	static const unsigned int msiof2_clk_b_pins[] = {
				2815	/* SCK */
				2816	RCAR_GP_PIN(0, 4),
				2817	};
				2818	static const unsigned int msiof2_clk_b_mux[] = {
				2819	MSIOF2_SCK_B_MARK,
				2820	};
				2821	static const unsigned int msiof2_sync_b_pins[] = {
				2822	/* SYNC */
				2823	RCAR_GP_PIN(0, 5),
				2824	};
				2825	static const unsigned int msiof2_sync_b_mux[] = {
				2826	MSIOF2_SYNC_B_MARK,
				2827	};
				2828	static const unsigned int msiof2_ss1_b_pins[] = {
				2829	/* SS1 */
				2830	RCAR_GP_PIN(0, 0),
				2831	};
				2832	static const unsigned int msiof2_ss1_b_mux[] = {
				2833	MSIOF2_SS1_B_MARK,
				2834	};
				2835	static const unsigned int msiof2_ss2_b_pins[] = {
				2836	/* SS2 */
				2837	RCAR_GP_PIN(0, 1),
				2838	};
				2839	static const unsigned int msiof2_ss2_b_mux[] = {
				2840	MSIOF2_SS2_B_MARK,
				2841	};
				2842	static const unsigned int msiof2_txd_b_pins[] = {
				2843	/* TXD */
				2844	RCAR_GP_PIN(0, 7),
				2845	};
				2846	static const unsigned int msiof2_txd_b_mux[] = {
				2847	MSIOF2_TXD_B_MARK,
				2848	};
				2849	static const unsigned int msiof2_rxd_b_pins[] = {
				2850	/* RXD */
				2851	RCAR_GP_PIN(0, 6),
				2852	};
				2853	static const unsigned int msiof2_rxd_b_mux[] = {
				2854	MSIOF2_RXD_B_MARK,
				2855	};
				2856	static const unsigned int msiof2_clk_c_pins[] = {
				2857	/* SCK */
				2858	RCAR_GP_PIN(2, 12),
				2859	};
				2860	static const unsigned int msiof2_clk_c_mux[] = {
				2861	MSIOF2_SCK_C_MARK,
				2862	};
				2863	static const unsigned int msiof2_sync_c_pins[] = {
				2864	/* SYNC */
				2865	RCAR_GP_PIN(2, 11),
				2866	};
				2867	static const unsigned int msiof2_sync_c_mux[] = {
				2868	MSIOF2_SYNC_C_MARK,
				2869	};
				2870	static const unsigned int msiof2_ss1_c_pins[] = {
				2871	/* SS1 */
				2872	RCAR_GP_PIN(2, 10),
				2873	};
				2874	static const unsigned int msiof2_ss1_c_mux[] = {
				2875	MSIOF2_SS1_C_MARK,
				2876	};
				2877	static const unsigned int msiof2_ss2_c_pins[] = {
				2878	/* SS2 */
				2879	RCAR_GP_PIN(2, 9),
				2880	};
				2881	static const unsigned int msiof2_ss2_c_mux[] = {
				2882	MSIOF2_SS2_C_MARK,
				2883	};
				2884	static const unsigned int msiof2_txd_c_pins[] = {
				2885	/* TXD */
				2886	RCAR_GP_PIN(2, 14),
				2887	};
				2888	static const unsigned int msiof2_txd_c_mux[] = {
				2889	MSIOF2_TXD_C_MARK,
				2890	};
				2891	static const unsigned int msiof2_rxd_c_pins[] = {
				2892	/* RXD */
				2893	RCAR_GP_PIN(2, 13),
				2894	};
				2895	static const unsigned int msiof2_rxd_c_mux[] = {
				2896	MSIOF2_RXD_C_MARK,
				2897	};
				2898	static const unsigned int msiof2_clk_d_pins[] = {
				2899	/* SCK */
				2900	RCAR_GP_PIN(0, 8),
				2901	};
				2902	static const unsigned int msiof2_clk_d_mux[] = {
				2903	MSIOF2_SCK_D_MARK,
				2904	};
				2905	static const unsigned int msiof2_sync_d_pins[] = {
				2906	/* SYNC */
				2907	RCAR_GP_PIN(0, 9),
				2908	};
				2909	static const unsigned int msiof2_sync_d_mux[] = {
				2910	MSIOF2_SYNC_D_MARK,
				2911	};
				2912	static const unsigned int msiof2_ss1_d_pins[] = {
				2913	/* SS1 */
				2914	RCAR_GP_PIN(0, 12),
				2915	};
				2916	static const unsigned int msiof2_ss1_d_mux[] = {
				2917	MSIOF2_SS1_D_MARK,
				2918	};
				2919	static const unsigned int msiof2_ss2_d_pins[] = {
				2920	/* SS2 */
				2921	RCAR_GP_PIN(0, 13),
				2922	};
				2923	static const unsigned int msiof2_ss2_d_mux[] = {
				2924	MSIOF2_SS2_D_MARK,
				2925	};
				2926	static const unsigned int msiof2_txd_d_pins[] = {
				2927	/* TXD */
				2928	RCAR_GP_PIN(0, 11),
				2929	};
				2930	static const unsigned int msiof2_txd_d_mux[] = {
				2931	MSIOF2_TXD_D_MARK,
				2932	};
				2933	static const unsigned int msiof2_rxd_d_pins[] = {
				2934	/* RXD */
				2935	RCAR_GP_PIN(0, 10),
				2936	};
				2937	static const unsigned int msiof2_rxd_d_mux[] = {
				2938	MSIOF2_RXD_D_MARK,
				2939	};
				2940	/* - MSIOF3 ----------------------------------------------------------------- */
				2941	static const unsigned int msiof3_clk_a_pins[] = {
				2942	/* SCK */
				2943	RCAR_GP_PIN(0, 0),
				2944	};
				2945	static const unsigned int msiof3_clk_a_mux[] = {
				2946	MSIOF3_SCK_A_MARK,
				2947	};
				2948	static const unsigned int msiof3_sync_a_pins[] = {
				2949	/* SYNC */
				2950	RCAR_GP_PIN(0, 1),
				2951	};
				2952	static const unsigned int msiof3_sync_a_mux[] = {
				2953	MSIOF3_SYNC_A_MARK,
				2954	};
				2955	static const unsigned int msiof3_ss1_a_pins[] = {
				2956	/* SS1 */
				2957	RCAR_GP_PIN(0, 14),
				2958	};
				2959	static const unsigned int msiof3_ss1_a_mux[] = {
				2960	MSIOF3_SS1_A_MARK,
				2961	};
				2962	static const unsigned int msiof3_ss2_a_pins[] = {
				2963	/* SS2 */
				2964	RCAR_GP_PIN(0, 15),
				2965	};
				2966	static const unsigned int msiof3_ss2_a_mux[] = {
				2967	MSIOF3_SS2_A_MARK,
				2968	};
				2969	static const unsigned int msiof3_txd_a_pins[] = {
				2970	/* TXD */
				2971	RCAR_GP_PIN(0, 3),
				2972	};
				2973	static const unsigned int msiof3_txd_a_mux[] = {
				2974	MSIOF3_TXD_A_MARK,
				2975	};
				2976	static const unsigned int msiof3_rxd_a_pins[] = {
				2977	/* RXD */
				2978	RCAR_GP_PIN(0, 2),
				2979	};
				2980	static const unsigned int msiof3_rxd_a_mux[] = {
				2981	MSIOF3_RXD_A_MARK,
				2982	};
				2983	static const unsigned int msiof3_clk_b_pins[] = {
				2984	/* SCK */
				2985	RCAR_GP_PIN(1, 2),
				2986	};
				2987	static const unsigned int msiof3_clk_b_mux[] = {
				2988	MSIOF3_SCK_B_MARK,
				2989	};
				2990	static const unsigned int msiof3_sync_b_pins[] = {
				2991	/* SYNC */
				2992	RCAR_GP_PIN(1, 0),
				2993	};
				2994	static const unsigned int msiof3_sync_b_mux[] = {
				2995	MSIOF3_SYNC_B_MARK,
				2996	};
				2997	static const unsigned int msiof3_ss1_b_pins[] = {
				2998	/* SS1 */
				2999	RCAR_GP_PIN(1, 4),
				3000	};
				3001	static const unsigned int msiof3_ss1_b_mux[] = {
				3002	MSIOF3_SS1_B_MARK,
				3003	};
				3004	static const unsigned int msiof3_ss2_b_pins[] = {
				3005	/* SS2 */
				3006	RCAR_GP_PIN(1, 5),
				3007	};
				3008	static const unsigned int msiof3_ss2_b_mux[] = {
				3009	MSIOF3_SS2_B_MARK,
				3010	};
				3011	static const unsigned int msiof3_txd_b_pins[] = {
				3012	/* TXD */
				3013	RCAR_GP_PIN(1, 1),
				3014	};
				3015	static const unsigned int msiof3_txd_b_mux[] = {
				3016	MSIOF3_TXD_B_MARK,
				3017	};
				3018	static const unsigned int msiof3_rxd_b_pins[] = {
				3019	/* RXD */
				3020	RCAR_GP_PIN(1, 3),
				3021	};
				3022	static const unsigned int msiof3_rxd_b_mux[] = {
				3023	MSIOF3_RXD_B_MARK,
				3024	};
				3025	static const unsigned int msiof3_clk_c_pins[] = {
				3026	/* SCK */
				3027	RCAR_GP_PIN(1, 12),
				3028	};
				3029	static const unsigned int msiof3_clk_c_mux[] = {
				3030	MSIOF3_SCK_C_MARK,
				3031	};
				3032	static const unsigned int msiof3_sync_c_pins[] = {
				3033	/* SYNC */
				3034	RCAR_GP_PIN(1, 13),
				3035	};
				3036	static const unsigned int msiof3_sync_c_mux[] = {
				3037	MSIOF3_SYNC_C_MARK,
				3038	};
				3039	static const unsigned int msiof3_txd_c_pins[] = {
				3040	/* TXD */
				3041	RCAR_GP_PIN(1, 15),
				3042	};
				3043	static const unsigned int msiof3_txd_c_mux[] = {
				3044	MSIOF3_TXD_C_MARK,
				3045	};
				3046	static const unsigned int msiof3_rxd_c_pins[] = {
				3047	/* RXD */
				3048	RCAR_GP_PIN(1, 14),
				3049	};
				3050	static const unsigned int msiof3_rxd_c_mux[] = {
				3051	MSIOF3_RXD_C_MARK,
				3052	};
				3053	static const unsigned int msiof3_clk_d_pins[] = {
				3054	/* SCK */
				3055	RCAR_GP_PIN(1, 22),
				3056	};
				3057	static const unsigned int msiof3_clk_d_mux[] = {
				3058	MSIOF3_SCK_D_MARK,
				3059	};
				3060	static const unsigned int msiof3_sync_d_pins[] = {
				3061	/* SYNC */
				3062	RCAR_GP_PIN(1, 23),
				3063	};
				3064	static const unsigned int msiof3_sync_d_mux[] = {
				3065	MSIOF3_SYNC_D_MARK,
				3066	};
				3067	static const unsigned int msiof3_ss1_d_pins[] = {
				3068	/* SS1 */
				3069	RCAR_GP_PIN(1, 26),
				3070	};
				3071	static const unsigned int msiof3_ss1_d_mux[] = {
				3072	MSIOF3_SS1_D_MARK,
				3073	};
				3074	static const unsigned int msiof3_txd_d_pins[] = {
				3075	/* TXD */
				3076	RCAR_GP_PIN(1, 25),
				3077	};
				3078	static const unsigned int msiof3_txd_d_mux[] = {
				3079	MSIOF3_TXD_D_MARK,
				3080	};
				3081	static const unsigned int msiof3_rxd_d_pins[] = {
				3082	/* RXD */
				3083	RCAR_GP_PIN(1, 24),
				3084	};
				3085	static const unsigned int msiof3_rxd_d_mux[] = {
				3086	MSIOF3_RXD_D_MARK,
				3087	};
				3088	static const unsigned int msiof3_clk_e_pins[] = {
				3089	/* SCK */
				3090	RCAR_GP_PIN(2, 3),
				3091	};
				3092	static const unsigned int msiof3_clk_e_mux[] = {
				3093	MSIOF3_SCK_E_MARK,
				3094	};
				3095	static const unsigned int msiof3_sync_e_pins[] = {
				3096	/* SYNC */
				3097	RCAR_GP_PIN(2, 2),
				3098	};
				3099	static const unsigned int msiof3_sync_e_mux[] = {
				3100	MSIOF3_SYNC_E_MARK,
				3101	};
				3102	static const unsigned int msiof3_ss1_e_pins[] = {
				3103	/* SS1 */
				3104	RCAR_GP_PIN(2, 1),
				3105	};
				3106	static const unsigned int msiof3_ss1_e_mux[] = {
				3107	MSIOF3_SS1_E_MARK,
				3108	};
				3109	static const unsigned int msiof3_ss2_e_pins[] = {
				3110	/* SS1 */
				3111	RCAR_GP_PIN(2, 0),
				3112	};
				3113	static const unsigned int msiof3_ss2_e_mux[] = {
				3114	MSIOF3_SS2_E_MARK,
				3115	};
				3116	static const unsigned int msiof3_txd_e_pins[] = {
				3117	/* TXD */
				3118	RCAR_GP_PIN(2, 5),
				3119	};
				3120	static const unsigned int msiof3_txd_e_mux[] = {
				3121	MSIOF3_TXD_E_MARK,
				3122	};
				3123	static const unsigned int msiof3_rxd_e_pins[] = {
				3124	/* RXD */
				3125	RCAR_GP_PIN(2, 4),
				3126	};
				3127	static const unsigned int msiof3_rxd_e_mux[] = {
				3128	MSIOF3_RXD_E_MARK,
				3129	};
				3130
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	3131	/* - PWM0 --------------------------------------------------------------------*/
				3132	static const unsigned int pwm0_pins[] = {
				3133	/* PWM */
				3134	RCAR_GP_PIN(2, 6),
				3135	};
				3136	static const unsigned int pwm0_mux[] = {
				3137	PWM0_MARK,
				3138	};
				3139	/* - PWM1 --------------------------------------------------------------------*/
				3140	static const unsigned int pwm1_a_pins[] = {
				3141	/* PWM */
				3142	RCAR_GP_PIN(2, 7),
				3143	};
				3144	static const unsigned int pwm1_a_mux[] = {
				3145	PWM1_A_MARK,
				3146	};
				3147	static const unsigned int pwm1_b_pins[] = {
				3148	/* PWM */
				3149	RCAR_GP_PIN(1, 8),
				3150	};
				3151	static const unsigned int pwm1_b_mux[] = {
				3152	PWM1_B_MARK,
				3153	};
				3154	/* - PWM2 --------------------------------------------------------------------*/
				3155	static const unsigned int pwm2_a_pins[] = {
				3156	/* PWM */
				3157	RCAR_GP_PIN(2, 8),
				3158	};
				3159	static const unsigned int pwm2_a_mux[] = {
				3160	PWM2_A_MARK,
				3161	};
				3162	static const unsigned int pwm2_b_pins[] = {
				3163	/* PWM */
				3164	RCAR_GP_PIN(1, 11),
				3165	};
				3166	static const unsigned int pwm2_b_mux[] = {
				3167	PWM2_B_MARK,
				3168	};
				3169	/* - PWM3 --------------------------------------------------------------------*/
				3170	static const unsigned int pwm3_a_pins[] = {
				3171	/* PWM */
				3172	RCAR_GP_PIN(1, 0),
				3173	};
				3174	static const unsigned int pwm3_a_mux[] = {
				3175	PWM3_A_MARK,
				3176	};
				3177	static const unsigned int pwm3_b_pins[] = {
				3178	/* PWM */
				3179	RCAR_GP_PIN(2, 2),
				3180	};
				3181	static const unsigned int pwm3_b_mux[] = {
				3182	PWM3_B_MARK,
				3183	};
				3184	/* - PWM4 --------------------------------------------------------------------*/
				3185	static const unsigned int pwm4_a_pins[] = {
				3186	/* PWM */
				3187	RCAR_GP_PIN(1, 1),
				3188	};
				3189	static const unsigned int pwm4_a_mux[] = {
				3190	PWM4_A_MARK,
				3191	};
				3192	static const unsigned int pwm4_b_pins[] = {
				3193	/* PWM */
				3194	RCAR_GP_PIN(2, 3),
				3195	};
				3196	static const unsigned int pwm4_b_mux[] = {
				3197	PWM4_B_MARK,
				3198	};
				3199	/* - PWM5 --------------------------------------------------------------------*/
				3200	static const unsigned int pwm5_a_pins[] = {
				3201	/* PWM */
				3202	RCAR_GP_PIN(1, 2),
				3203	};
				3204	static const unsigned int pwm5_a_mux[] = {
				3205	PWM5_A_MARK,
				3206	};
				3207	static const unsigned int pwm5_b_pins[] = {
				3208	/* PWM */
				3209	RCAR_GP_PIN(2, 4),
				3210	};
				3211	static const unsigned int pwm5_b_mux[] = {
				3212	PWM5_B_MARK,
				3213	};
				3214	/* - PWM6 --------------------------------------------------------------------*/
				3215	static const unsigned int pwm6_a_pins[] = {
				3216	/* PWM */
				3217	RCAR_GP_PIN(1, 3),
				3218	};
				3219	static const unsigned int pwm6_a_mux[] = {
				3220	PWM6_A_MARK,
				3221	};
				3222	static const unsigned int pwm6_b_pins[] = {
				3223	/* PWM */
				3224	RCAR_GP_PIN(2, 5),
				3225	};
				3226	static const unsigned int pwm6_b_mux[] = {
				3227	PWM6_B_MARK,
				3228	};
				3229
Wolfram Sang	297e5b2	2017-12-20 22:59:22 +0100	[diff] [blame^]	3230	/* - SATA --------------------------------------------------------------------*/
				3231	static const unsigned int sata0_devslp_a_pins[] = {
				3232	/* DEVSLP */
				3233	RCAR_GP_PIN(6, 16),
				3234	};
				3235	static const unsigned int sata0_devslp_a_mux[] = {
				3236	SATA_DEVSLP_A_MARK,
				3237	};
				3238	static const unsigned int sata0_devslp_b_pins[] = {
				3239	/* DEVSLP */
				3240	RCAR_GP_PIN(4, 6),
				3241	};
				3242	static const unsigned int sata0_devslp_b_mux[] = {
				3243	SATA_DEVSLP_B_MARK,
				3244	};
				3245
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3246	/* - SCIF0 ------------------------------------------------------------------ */
				3247	static const unsigned int scif0_data_pins[] = {
				3248	/* RX, TX */
				3249	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
				3250	};
				3251	static const unsigned int scif0_data_mux[] = {
				3252	RX0_MARK, TX0_MARK,
				3253	};
				3254	static const unsigned int scif0_clk_pins[] = {
				3255	/* SCK */
				3256	RCAR_GP_PIN(5, 0),
				3257	};
				3258	static const unsigned int scif0_clk_mux[] = {
				3259	SCK0_MARK,
				3260	};
				3261	static const unsigned int scif0_ctrl_pins[] = {
				3262	/* RTS, CTS */
				3263	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
				3264	};
				3265	static const unsigned int scif0_ctrl_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3266	RTS0_N_MARK, CTS0_N_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3267	};
				3268	/* - SCIF1 ------------------------------------------------------------------ */
				3269	static const unsigned int scif1_data_a_pins[] = {
				3270	/* RX, TX */
				3271	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
				3272	};
				3273	static const unsigned int scif1_data_a_mux[] = {
				3274	RX1_A_MARK, TX1_A_MARK,
				3275	};
				3276	static const unsigned int scif1_clk_pins[] = {
				3277	/* SCK */
				3278	RCAR_GP_PIN(6, 21),
				3279	};
				3280	static const unsigned int scif1_clk_mux[] = {
				3281	SCK1_MARK,
				3282	};
				3283	static const unsigned int scif1_ctrl_pins[] = {
				3284	/* RTS, CTS */
				3285	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
				3286	};
				3287	static const unsigned int scif1_ctrl_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3288	RTS1_N_MARK, CTS1_N_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3289	};
				3290
				3291	static const unsigned int scif1_data_b_pins[] = {
				3292	/* RX, TX */
				3293	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
				3294	};
				3295	static const unsigned int scif1_data_b_mux[] = {
				3296	RX1_B_MARK, TX1_B_MARK,
				3297	};
				3298	/* - SCIF2 ------------------------------------------------------------------ */
				3299	static const unsigned int scif2_data_a_pins[] = {
				3300	/* RX, TX */
				3301	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
				3302	};
				3303	static const unsigned int scif2_data_a_mux[] = {
				3304	RX2_A_MARK, TX2_A_MARK,
				3305	};
				3306	static const unsigned int scif2_clk_pins[] = {
				3307	/* SCK */
				3308	RCAR_GP_PIN(5, 9),
				3309	};
				3310	static const unsigned int scif2_clk_mux[] = {
				3311	SCK2_MARK,
				3312	};
				3313	static const unsigned int scif2_data_b_pins[] = {
				3314	/* RX, TX */
				3315	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
				3316	};
				3317	static const unsigned int scif2_data_b_mux[] = {
				3318	RX2_B_MARK, TX2_B_MARK,
				3319	};
				3320	/* - SCIF3 ------------------------------------------------------------------ */
				3321	static const unsigned int scif3_data_a_pins[] = {
				3322	/* RX, TX */
				3323	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
				3324	};
				3325	static const unsigned int scif3_data_a_mux[] = {
				3326	RX3_A_MARK, TX3_A_MARK,
				3327	};
				3328	static const unsigned int scif3_clk_pins[] = {
				3329	/* SCK */
				3330	RCAR_GP_PIN(1, 22),
				3331	};
				3332	static const unsigned int scif3_clk_mux[] = {
				3333	SCK3_MARK,
				3334	};
				3335	static const unsigned int scif3_ctrl_pins[] = {
				3336	/* RTS, CTS */
				3337	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
				3338	};
				3339	static const unsigned int scif3_ctrl_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3340	RTS3_N_MARK, CTS3_N_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3341	};
				3342	static const unsigned int scif3_data_b_pins[] = {
				3343	/* RX, TX */
				3344	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
				3345	};
				3346	static const unsigned int scif3_data_b_mux[] = {
				3347	RX3_B_MARK, TX3_B_MARK,
				3348	};
				3349	/* - SCIF4 ------------------------------------------------------------------ */
				3350	static const unsigned int scif4_data_a_pins[] = {
				3351	/* RX, TX */
				3352	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
				3353	};
				3354	static const unsigned int scif4_data_a_mux[] = {
				3355	RX4_A_MARK, TX4_A_MARK,
				3356	};
				3357	static const unsigned int scif4_clk_a_pins[] = {
				3358	/* SCK */
				3359	RCAR_GP_PIN(2, 10),
				3360	};
				3361	static const unsigned int scif4_clk_a_mux[] = {
				3362	SCK4_A_MARK,
				3363	};
				3364	static const unsigned int scif4_ctrl_a_pins[] = {
				3365	/* RTS, CTS */
				3366	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
				3367	};
				3368	static const unsigned int scif4_ctrl_a_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3369	RTS4_N_A_MARK, CTS4_N_A_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3370	};
				3371	static const unsigned int scif4_data_b_pins[] = {
				3372	/* RX, TX */
				3373	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
				3374	};
				3375	static const unsigned int scif4_data_b_mux[] = {
				3376	RX4_B_MARK, TX4_B_MARK,
				3377	};
				3378	static const unsigned int scif4_clk_b_pins[] = {
				3379	/* SCK */
				3380	RCAR_GP_PIN(1, 5),
				3381	};
				3382	static const unsigned int scif4_clk_b_mux[] = {
				3383	SCK4_B_MARK,
				3384	};
				3385	static const unsigned int scif4_ctrl_b_pins[] = {
				3386	/* RTS, CTS */
				3387	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
				3388	};
				3389	static const unsigned int scif4_ctrl_b_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3390	RTS4_N_B_MARK, CTS4_N_B_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3391	};
				3392	static const unsigned int scif4_data_c_pins[] = {
				3393	/* RX, TX */
				3394	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
				3395	};
				3396	static const unsigned int scif4_data_c_mux[] = {
				3397	RX4_C_MARK, TX4_C_MARK,
				3398	};
				3399	static const unsigned int scif4_clk_c_pins[] = {
				3400	/* SCK */
				3401	RCAR_GP_PIN(0, 8),
				3402	};
				3403	static const unsigned int scif4_clk_c_mux[] = {
				3404	SCK4_C_MARK,
				3405	};
				3406	static const unsigned int scif4_ctrl_c_pins[] = {
				3407	/* RTS, CTS */
				3408	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				3409	};
				3410	static const unsigned int scif4_ctrl_c_mux[] = {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	3411	RTS4_N_C_MARK, CTS4_N_C_MARK,
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3412	};
				3413	/* - SCIF5 ------------------------------------------------------------------ */
				3414	static const unsigned int scif5_data_a_pins[] = {
				3415	/* RX, TX */
				3416	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
				3417	};
				3418	static const unsigned int scif5_data_a_mux[] = {
				3419	RX5_A_MARK, TX5_A_MARK,
				3420	};
				3421	static const unsigned int scif5_clk_a_pins[] = {
				3422	/* SCK */
				3423	RCAR_GP_PIN(6, 21),
				3424	};
				3425	static const unsigned int scif5_clk_a_mux[] = {
				3426	SCK5_A_MARK,
				3427	};
				3428	static const unsigned int scif5_data_b_pins[] = {
				3429	/* RX, TX */
				3430	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
				3431	};
				3432	static const unsigned int scif5_data_b_mux[] = {
				3433	RX5_B_MARK, TX5_B_MARK,
				3434	};
				3435	static const unsigned int scif5_clk_b_pins[] = {
				3436	/* SCK */
				3437	RCAR_GP_PIN(5, 0),
				3438	};
				3439	static const unsigned int scif5_clk_b_mux[] = {
				3440	SCK5_B_MARK,
				3441	};
				3442
Geert Uytterhoeven	b4062b4	2017-10-05 12:14:00 +0200	[diff] [blame]	3443	/* - SCIF Clock ------------------------------------------------------------- */
				3444	static const unsigned int scif_clk_a_pins[] = {
				3445	/* SCIF_CLK */
				3446	RCAR_GP_PIN(6, 23),
				3447	};
				3448	static const unsigned int scif_clk_a_mux[] = {
				3449	SCIF_CLK_A_MARK,
				3450	};
				3451	static const unsigned int scif_clk_b_pins[] = {
				3452	/* SCIF_CLK */
				3453	RCAR_GP_PIN(5, 9),
				3454	};
				3455	static const unsigned int scif_clk_b_mux[] = {
				3456	SCIF_CLK_B_MARK,
				3457	};
				3458
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	3459	/* - SDHI0 ------------------------------------------------------------------ */
				3460	static const unsigned int sdhi0_data1_pins[] = {
				3461	/* D0 */
				3462	RCAR_GP_PIN(3, 2),
				3463	};
				3464	static const unsigned int sdhi0_data1_mux[] = {
				3465	SD0_DAT0_MARK,
				3466	};
				3467	static const unsigned int sdhi0_data4_pins[] = {
				3468	/* D[0:3] */
				3469	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
				3470	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
				3471	};
				3472	static const unsigned int sdhi0_data4_mux[] = {
				3473	SD0_DAT0_MARK, SD0_DAT1_MARK,
				3474	SD0_DAT2_MARK, SD0_DAT3_MARK,
				3475	};
				3476	static const unsigned int sdhi0_ctrl_pins[] = {
				3477	/* CLK, CMD */
				3478	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
				3479	};
				3480	static const unsigned int sdhi0_ctrl_mux[] = {
				3481	SD0_CLK_MARK, SD0_CMD_MARK,
				3482	};
				3483	static const unsigned int sdhi0_cd_pins[] = {
				3484	/* CD */
				3485	RCAR_GP_PIN(3, 12),
				3486	};
				3487	static const unsigned int sdhi0_cd_mux[] = {
				3488	SD0_CD_MARK,
				3489	};
				3490	static const unsigned int sdhi0_wp_pins[] = {
				3491	/* WP */
				3492	RCAR_GP_PIN(3, 13),
				3493	};
				3494	static const unsigned int sdhi0_wp_mux[] = {
				3495	SD0_WP_MARK,
				3496	};
				3497	/* - SDHI1 ------------------------------------------------------------------ */
				3498	static const unsigned int sdhi1_data1_pins[] = {
				3499	/* D0 */
				3500	RCAR_GP_PIN(3, 8),
				3501	};
				3502	static const unsigned int sdhi1_data1_mux[] = {
				3503	SD1_DAT0_MARK,
				3504	};
				3505	static const unsigned int sdhi1_data4_pins[] = {
				3506	/* D[0:3] */
				3507	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
				3508	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
				3509	};
				3510	static const unsigned int sdhi1_data4_mux[] = {
				3511	SD1_DAT0_MARK, SD1_DAT1_MARK,
				3512	SD1_DAT2_MARK, SD1_DAT3_MARK,
				3513	};
				3514	static const unsigned int sdhi1_ctrl_pins[] = {
				3515	/* CLK, CMD */
				3516	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
				3517	};
				3518	static const unsigned int sdhi1_ctrl_mux[] = {
				3519	SD1_CLK_MARK, SD1_CMD_MARK,
				3520	};
				3521	static const unsigned int sdhi1_cd_pins[] = {
				3522	/* CD */
				3523	RCAR_GP_PIN(3, 14),
				3524	};
				3525	static const unsigned int sdhi1_cd_mux[] = {
				3526	SD1_CD_MARK,
				3527	};
				3528	static const unsigned int sdhi1_wp_pins[] = {
				3529	/* WP */
				3530	RCAR_GP_PIN(3, 15),
				3531	};
				3532	static const unsigned int sdhi1_wp_mux[] = {
				3533	SD1_WP_MARK,
				3534	};
				3535	/* - SDHI2 ------------------------------------------------------------------ */
				3536	static const unsigned int sdhi2_data1_pins[] = {
				3537	/* D0 */
				3538	RCAR_GP_PIN(4, 2),
				3539	};
				3540	static const unsigned int sdhi2_data1_mux[] = {
				3541	SD2_DAT0_MARK,
				3542	};
				3543	static const unsigned int sdhi2_data4_pins[] = {
				3544	/* D[0:3] */
				3545	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
				3546	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
				3547	};
				3548	static const unsigned int sdhi2_data4_mux[] = {
				3549	SD2_DAT0_MARK, SD2_DAT1_MARK,
				3550	SD2_DAT2_MARK, SD2_DAT3_MARK,
				3551	};
				3552	static const unsigned int sdhi2_data8_pins[] = {
				3553	/* D[0:7] */
				3554	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
				3555	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
				3556	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
				3557	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
				3558	};
				3559	static const unsigned int sdhi2_data8_mux[] = {
				3560	SD2_DAT0_MARK, SD2_DAT1_MARK,
				3561	SD2_DAT2_MARK, SD2_DAT3_MARK,
				3562	SD2_DAT4_MARK, SD2_DAT5_MARK,
				3563	SD2_DAT6_MARK, SD2_DAT7_MARK,
				3564	};
				3565	static const unsigned int sdhi2_ctrl_pins[] = {
				3566	/* CLK, CMD */
				3567	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
				3568	};
				3569	static const unsigned int sdhi2_ctrl_mux[] = {
				3570	SD2_CLK_MARK, SD2_CMD_MARK,
				3571	};
				3572	static const unsigned int sdhi2_cd_a_pins[] = {
				3573	/* CD */
				3574	RCAR_GP_PIN(4, 13),
				3575	};
				3576	static const unsigned int sdhi2_cd_a_mux[] = {
				3577	SD2_CD_A_MARK,
				3578	};
				3579	static const unsigned int sdhi2_cd_b_pins[] = {
				3580	/* CD */
				3581	RCAR_GP_PIN(5, 10),
				3582	};
				3583	static const unsigned int sdhi2_cd_b_mux[] = {
				3584	SD2_CD_B_MARK,
				3585	};
				3586	static const unsigned int sdhi2_wp_a_pins[] = {
				3587	/* WP */
				3588	RCAR_GP_PIN(4, 14),
				3589	};
				3590	static const unsigned int sdhi2_wp_a_mux[] = {
				3591	SD2_WP_A_MARK,
				3592	};
				3593	static const unsigned int sdhi2_wp_b_pins[] = {
				3594	/* WP */
				3595	RCAR_GP_PIN(5, 11),
				3596	};
				3597	static const unsigned int sdhi2_wp_b_mux[] = {
				3598	SD2_WP_B_MARK,
				3599	};
				3600	static const unsigned int sdhi2_ds_pins[] = {
				3601	/* DS */
				3602	RCAR_GP_PIN(4, 6),
				3603	};
				3604	static const unsigned int sdhi2_ds_mux[] = {
				3605	SD2_DS_MARK,
				3606	};
				3607	/* - SDHI3 ------------------------------------------------------------------ */
				3608	static const unsigned int sdhi3_data1_pins[] = {
				3609	/* D0 */
				3610	RCAR_GP_PIN(4, 9),
				3611	};
				3612	static const unsigned int sdhi3_data1_mux[] = {
				3613	SD3_DAT0_MARK,
				3614	};
				3615	static const unsigned int sdhi3_data4_pins[] = {
				3616	/* D[0:3] */
				3617	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
				3618	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
				3619	};
				3620	static const unsigned int sdhi3_data4_mux[] = {
				3621	SD3_DAT0_MARK, SD3_DAT1_MARK,
				3622	SD3_DAT2_MARK, SD3_DAT3_MARK,
				3623	};
				3624	static const unsigned int sdhi3_data8_pins[] = {
				3625	/* D[0:7] */
				3626	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
				3627	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
				3628	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
				3629	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
				3630	};
				3631	static const unsigned int sdhi3_data8_mux[] = {
				3632	SD3_DAT0_MARK, SD3_DAT1_MARK,
				3633	SD3_DAT2_MARK, SD3_DAT3_MARK,
				3634	SD3_DAT4_MARK, SD3_DAT5_MARK,
				3635	SD3_DAT6_MARK, SD3_DAT7_MARK,
				3636	};
				3637	static const unsigned int sdhi3_ctrl_pins[] = {
				3638	/* CLK, CMD */
				3639	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
				3640	};
				3641	static const unsigned int sdhi3_ctrl_mux[] = {
				3642	SD3_CLK_MARK, SD3_CMD_MARK,
				3643	};
				3644	static const unsigned int sdhi3_cd_pins[] = {
				3645	/* CD */
				3646	RCAR_GP_PIN(4, 15),
				3647	};
				3648	static const unsigned int sdhi3_cd_mux[] = {
				3649	SD3_CD_MARK,
				3650	};
				3651	static const unsigned int sdhi3_wp_pins[] = {
				3652	/* WP */
				3653	RCAR_GP_PIN(4, 16),
				3654	};
				3655	static const unsigned int sdhi3_wp_mux[] = {
				3656	SD3_WP_MARK,
				3657	};
				3658	static const unsigned int sdhi3_ds_pins[] = {
				3659	/* DS */
				3660	RCAR_GP_PIN(4, 17),
				3661	};
				3662	static const unsigned int sdhi3_ds_mux[] = {
				3663	SD3_DS_MARK,
				3664	};
				3665
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	3666	/* - SSI -------------------------------------------------------------------- */
				3667	static const unsigned int ssi0_data_pins[] = {
				3668	/* SDATA */
				3669	RCAR_GP_PIN(6, 2),
				3670	};
				3671	static const unsigned int ssi0_data_mux[] = {
				3672	SSI_SDATA0_MARK,
				3673	};
				3674	static const unsigned int ssi01239_ctrl_pins[] = {
				3675	/* SCK, WS */
				3676	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
				3677	};
				3678	static const unsigned int ssi01239_ctrl_mux[] = {
				3679	SSI_SCK01239_MARK, SSI_WS01239_MARK,
				3680	};
				3681	static const unsigned int ssi1_data_a_pins[] = {
				3682	/* SDATA */
				3683	RCAR_GP_PIN(6, 3),
				3684	};
				3685	static const unsigned int ssi1_data_a_mux[] = {
				3686	SSI_SDATA1_A_MARK,
				3687	};
				3688	static const unsigned int ssi1_data_b_pins[] = {
				3689	/* SDATA */
				3690	RCAR_GP_PIN(5, 12),
				3691	};
				3692	static const unsigned int ssi1_data_b_mux[] = {
				3693	SSI_SDATA1_B_MARK,
				3694	};
				3695	static const unsigned int ssi1_ctrl_a_pins[] = {
				3696	/* SCK, WS */
				3697	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				3698	};
				3699	static const unsigned int ssi1_ctrl_a_mux[] = {
				3700	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
				3701	};
				3702	static const unsigned int ssi1_ctrl_b_pins[] = {
				3703	/* SCK, WS */
				3704	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
				3705	};
				3706	static const unsigned int ssi1_ctrl_b_mux[] = {
				3707	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
				3708	};
				3709	static const unsigned int ssi2_data_a_pins[] = {
				3710	/* SDATA */
				3711	RCAR_GP_PIN(6, 4),
				3712	};
				3713	static const unsigned int ssi2_data_a_mux[] = {
				3714	SSI_SDATA2_A_MARK,
				3715	};
				3716	static const unsigned int ssi2_data_b_pins[] = {
				3717	/* SDATA */
				3718	RCAR_GP_PIN(5, 13),
				3719	};
				3720	static const unsigned int ssi2_data_b_mux[] = {
				3721	SSI_SDATA2_B_MARK,
				3722	};
				3723	static const unsigned int ssi2_ctrl_a_pins[] = {
				3724	/* SCK, WS */
				3725	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
				3726	};
				3727	static const unsigned int ssi2_ctrl_a_mux[] = {
				3728	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
				3729	};
				3730	static const unsigned int ssi2_ctrl_b_pins[] = {
				3731	/* SCK, WS */
				3732	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
				3733	};
				3734	static const unsigned int ssi2_ctrl_b_mux[] = {
				3735	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
				3736	};
				3737	static const unsigned int ssi3_data_pins[] = {
				3738	/* SDATA */
				3739	RCAR_GP_PIN(6, 7),
				3740	};
				3741	static const unsigned int ssi3_data_mux[] = {
				3742	SSI_SDATA3_MARK,
				3743	};
				3744	static const unsigned int ssi349_ctrl_pins[] = {
				3745	/* SCK, WS */
				3746	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
				3747	};
				3748	static const unsigned int ssi349_ctrl_mux[] = {
				3749	SSI_SCK349_MARK, SSI_WS349_MARK,
				3750	};
				3751	static const unsigned int ssi4_data_pins[] = {
				3752	/* SDATA */
				3753	RCAR_GP_PIN(6, 10),
				3754	};
				3755	static const unsigned int ssi4_data_mux[] = {
				3756	SSI_SDATA4_MARK,
				3757	};
				3758	static const unsigned int ssi4_ctrl_pins[] = {
				3759	/* SCK, WS */
				3760	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				3761	};
				3762	static const unsigned int ssi4_ctrl_mux[] = {
				3763	SSI_SCK4_MARK, SSI_WS4_MARK,
				3764	};
				3765	static const unsigned int ssi5_data_pins[] = {
				3766	/* SDATA */
				3767	RCAR_GP_PIN(6, 13),
				3768	};
				3769	static const unsigned int ssi5_data_mux[] = {
				3770	SSI_SDATA5_MARK,
				3771	};
				3772	static const unsigned int ssi5_ctrl_pins[] = {
				3773	/* SCK, WS */
				3774	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
				3775	};
				3776	static const unsigned int ssi5_ctrl_mux[] = {
				3777	SSI_SCK5_MARK, SSI_WS5_MARK,
				3778	};
				3779	static const unsigned int ssi6_data_pins[] = {
				3780	/* SDATA */
				3781	RCAR_GP_PIN(6, 16),
				3782	};
				3783	static const unsigned int ssi6_data_mux[] = {
				3784	SSI_SDATA6_MARK,
				3785	};
				3786	static const unsigned int ssi6_ctrl_pins[] = {
				3787	/* SCK, WS */
				3788	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
				3789	};
				3790	static const unsigned int ssi6_ctrl_mux[] = {
				3791	SSI_SCK6_MARK, SSI_WS6_MARK,
				3792	};
				3793	static const unsigned int ssi7_data_pins[] = {
				3794	/* SDATA */
				3795	RCAR_GP_PIN(6, 19),
				3796	};
				3797	static const unsigned int ssi7_data_mux[] = {
				3798	SSI_SDATA7_MARK,
				3799	};
				3800	static const unsigned int ssi78_ctrl_pins[] = {
				3801	/* SCK, WS */
				3802	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				3803	};
				3804	static const unsigned int ssi78_ctrl_mux[] = {
				3805	SSI_SCK78_MARK, SSI_WS78_MARK,
				3806	};
				3807	static const unsigned int ssi8_data_pins[] = {
				3808	/* SDATA */
				3809	RCAR_GP_PIN(6, 20),
				3810	};
				3811	static const unsigned int ssi8_data_mux[] = {
				3812	SSI_SDATA8_MARK,
				3813	};
				3814	static const unsigned int ssi9_data_a_pins[] = {
				3815	/* SDATA */
				3816	RCAR_GP_PIN(6, 21),
				3817	};
				3818	static const unsigned int ssi9_data_a_mux[] = {
				3819	SSI_SDATA9_A_MARK,
				3820	};
				3821	static const unsigned int ssi9_data_b_pins[] = {
				3822	/* SDATA */
				3823	RCAR_GP_PIN(5, 14),
				3824	};
				3825	static const unsigned int ssi9_data_b_mux[] = {
				3826	SSI_SDATA9_B_MARK,
				3827	};
				3828	static const unsigned int ssi9_ctrl_a_pins[] = {
				3829	/* SCK, WS */
				3830	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
				3831	};
				3832	static const unsigned int ssi9_ctrl_a_mux[] = {
				3833	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
				3834	};
				3835	static const unsigned int ssi9_ctrl_b_pins[] = {
				3836	/* SCK, WS */
				3837	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
				3838	};
				3839	static const unsigned int ssi9_ctrl_b_mux[] = {
				3840	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
				3841	};
				3842
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	3843	/* - USB0 ------------------------------------------------------------------- */
				3844	static const unsigned int usb0_pins[] = {
				3845	/* PWEN, OVC */
				3846	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
				3847	};
				3848	static const unsigned int usb0_mux[] = {
				3849	USB0_PWEN_MARK, USB0_OVC_MARK,
				3850	};
				3851	/* - USB1 ------------------------------------------------------------------- */
				3852	static const unsigned int usb1_pins[] = {
				3853	/* PWEN, OVC */
				3854	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				3855	};
				3856	static const unsigned int usb1_mux[] = {
				3857	USB1_PWEN_MARK, USB1_OVC_MARK,
				3858	};
				3859	/* - USB2 ------------------------------------------------------------------- */
				3860	static const unsigned int usb2_pins[] = {
				3861	/* PWEN, OVC */
				3862	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
				3863	};
				3864	static const unsigned int usb2_mux[] = {
				3865	USB2_PWEN_MARK, USB2_OVC_MARK,
				3866	};
				3867	/* - USB2_CH3 --------------------------------------------------------------- */
				3868	static const unsigned int usb2_ch3_pins[] = {
				3869	/* PWEN, OVC */
				3870	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
				3871	};
				3872	static const unsigned int usb2_ch3_mux[] = {
				3873	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
				3874	};
				3875
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	3876	/* - USB30 ------------------------------------------------------------------ */
				3877	static const unsigned int usb30_pins[] = {
				3878	/* PWEN, OVC */
				3879	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
				3880	};
				3881	static const unsigned int usb30_mux[] = {
				3882	USB30_PWEN_MARK, USB30_OVC_MARK,
				3883	};
				3884
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	3885	static const struct sh_pfc_pin_group pinmux_groups[] = {
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	3886	SH_PFC_PIN_GROUP(audio_clk_a_a),
				3887	SH_PFC_PIN_GROUP(audio_clk_a_b),
				3888	SH_PFC_PIN_GROUP(audio_clk_a_c),
				3889	SH_PFC_PIN_GROUP(audio_clk_b_a),
				3890	SH_PFC_PIN_GROUP(audio_clk_b_b),
				3891	SH_PFC_PIN_GROUP(audio_clk_c_a),
				3892	SH_PFC_PIN_GROUP(audio_clk_c_b),
				3893	SH_PFC_PIN_GROUP(audio_clkout_a),
				3894	SH_PFC_PIN_GROUP(audio_clkout_b),
				3895	SH_PFC_PIN_GROUP(audio_clkout_c),
				3896	SH_PFC_PIN_GROUP(audio_clkout_d),
				3897	SH_PFC_PIN_GROUP(audio_clkout1_a),
				3898	SH_PFC_PIN_GROUP(audio_clkout1_b),
				3899	SH_PFC_PIN_GROUP(audio_clkout2_a),
				3900	SH_PFC_PIN_GROUP(audio_clkout2_b),
				3901	SH_PFC_PIN_GROUP(audio_clkout3_a),
				3902	SH_PFC_PIN_GROUP(audio_clkout3_b),
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	3903	SH_PFC_PIN_GROUP(avb_link),
				3904	SH_PFC_PIN_GROUP(avb_magic),
				3905	SH_PFC_PIN_GROUP(avb_phy_int),
				3906	SH_PFC_PIN_GROUP(avb_mdc),
				3907	SH_PFC_PIN_GROUP(avb_mii),
				3908	SH_PFC_PIN_GROUP(avb_avtp_pps),
				3909	SH_PFC_PIN_GROUP(avb_avtp_match_a),
				3910	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
				3911	SH_PFC_PIN_GROUP(avb_avtp_match_b),
				3912	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Ramesh Shanmugasundaram	a678abf	2017-11-10 13:58:49 +0000	[diff] [blame]	3913	SH_PFC_PIN_GROUP(can0_data_a),
				3914	SH_PFC_PIN_GROUP(can0_data_b),
				3915	SH_PFC_PIN_GROUP(can1_data),
				3916	SH_PFC_PIN_GROUP(can_clk),
Ramesh Shanmugasundaram	0e1c7a9	2017-11-10 13:58:50 +0000	[diff] [blame]	3917	SH_PFC_PIN_GROUP(canfd0_data_a),
				3918	SH_PFC_PIN_GROUP(canfd0_data_b),
				3919	SH_PFC_PIN_GROUP(canfd1_data),
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	3920	SH_PFC_PIN_GROUP(drif0_ctrl_a),
				3921	SH_PFC_PIN_GROUP(drif0_data0_a),
				3922	SH_PFC_PIN_GROUP(drif0_data1_a),
				3923	SH_PFC_PIN_GROUP(drif0_ctrl_b),
				3924	SH_PFC_PIN_GROUP(drif0_data0_b),
				3925	SH_PFC_PIN_GROUP(drif0_data1_b),
				3926	SH_PFC_PIN_GROUP(drif0_ctrl_c),
				3927	SH_PFC_PIN_GROUP(drif0_data0_c),
				3928	SH_PFC_PIN_GROUP(drif0_data1_c),
				3929	SH_PFC_PIN_GROUP(drif1_ctrl_a),
				3930	SH_PFC_PIN_GROUP(drif1_data0_a),
				3931	SH_PFC_PIN_GROUP(drif1_data1_a),
				3932	SH_PFC_PIN_GROUP(drif1_ctrl_b),
				3933	SH_PFC_PIN_GROUP(drif1_data0_b),
				3934	SH_PFC_PIN_GROUP(drif1_data1_b),
				3935	SH_PFC_PIN_GROUP(drif1_ctrl_c),
				3936	SH_PFC_PIN_GROUP(drif1_data0_c),
				3937	SH_PFC_PIN_GROUP(drif1_data1_c),
				3938	SH_PFC_PIN_GROUP(drif2_ctrl_a),
				3939	SH_PFC_PIN_GROUP(drif2_data0_a),
				3940	SH_PFC_PIN_GROUP(drif2_data1_a),
				3941	SH_PFC_PIN_GROUP(drif2_ctrl_b),
				3942	SH_PFC_PIN_GROUP(drif2_data0_b),
				3943	SH_PFC_PIN_GROUP(drif2_data1_b),
				3944	SH_PFC_PIN_GROUP(drif3_ctrl_a),
				3945	SH_PFC_PIN_GROUP(drif3_data0_a),
				3946	SH_PFC_PIN_GROUP(drif3_data1_a),
				3947	SH_PFC_PIN_GROUP(drif3_ctrl_b),
				3948	SH_PFC_PIN_GROUP(drif3_data0_b),
				3949	SH_PFC_PIN_GROUP(drif3_data1_b),
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	3950	SH_PFC_PIN_GROUP(du_rgb666),
				3951	SH_PFC_PIN_GROUP(du_rgb888),
				3952	SH_PFC_PIN_GROUP(du_clk_out_0),
				3953	SH_PFC_PIN_GROUP(du_clk_out_1),
				3954	SH_PFC_PIN_GROUP(du_sync),
				3955	SH_PFC_PIN_GROUP(du_oddf),
				3956	SH_PFC_PIN_GROUP(du_cde),
				3957	SH_PFC_PIN_GROUP(du_disp),
Wolfram Sang	7a362e3	2017-10-09 10:20:53 +0200	[diff] [blame]	3958	SH_PFC_PIN_GROUP(hscif0_data),
				3959	SH_PFC_PIN_GROUP(hscif0_clk),
				3960	SH_PFC_PIN_GROUP(hscif0_ctrl),
				3961	SH_PFC_PIN_GROUP(hscif1_data_a),
				3962	SH_PFC_PIN_GROUP(hscif1_clk_a),
				3963	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
				3964	SH_PFC_PIN_GROUP(hscif1_data_b),
				3965	SH_PFC_PIN_GROUP(hscif1_clk_b),
				3966	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
				3967	SH_PFC_PIN_GROUP(hscif2_data_a),
				3968	SH_PFC_PIN_GROUP(hscif2_clk_a),
				3969	SH_PFC_PIN_GROUP(hscif2_ctrl_a),
				3970	SH_PFC_PIN_GROUP(hscif2_data_b),
				3971	SH_PFC_PIN_GROUP(hscif2_clk_b),
				3972	SH_PFC_PIN_GROUP(hscif2_ctrl_b),
				3973	SH_PFC_PIN_GROUP(hscif2_data_c),
				3974	SH_PFC_PIN_GROUP(hscif2_clk_c),
				3975	SH_PFC_PIN_GROUP(hscif2_ctrl_c),
				3976	SH_PFC_PIN_GROUP(hscif3_data_a),
				3977	SH_PFC_PIN_GROUP(hscif3_clk),
				3978	SH_PFC_PIN_GROUP(hscif3_ctrl),
				3979	SH_PFC_PIN_GROUP(hscif3_data_b),
				3980	SH_PFC_PIN_GROUP(hscif3_data_c),
				3981	SH_PFC_PIN_GROUP(hscif3_data_d),
				3982	SH_PFC_PIN_GROUP(hscif4_data_a),
				3983	SH_PFC_PIN_GROUP(hscif4_clk),
				3984	SH_PFC_PIN_GROUP(hscif4_ctrl),
				3985	SH_PFC_PIN_GROUP(hscif4_data_b),
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	3986	SH_PFC_PIN_GROUP(i2c1_a),
				3987	SH_PFC_PIN_GROUP(i2c1_b),
				3988	SH_PFC_PIN_GROUP(i2c2_a),
				3989	SH_PFC_PIN_GROUP(i2c2_b),
				3990	SH_PFC_PIN_GROUP(i2c6_a),
				3991	SH_PFC_PIN_GROUP(i2c6_b),
				3992	SH_PFC_PIN_GROUP(i2c6_c),
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame]	3993	SH_PFC_PIN_GROUP(intc_ex_irq0),
				3994	SH_PFC_PIN_GROUP(intc_ex_irq1),
				3995	SH_PFC_PIN_GROUP(intc_ex_irq2),
				3996	SH_PFC_PIN_GROUP(intc_ex_irq3),
				3997	SH_PFC_PIN_GROUP(intc_ex_irq4),
				3998	SH_PFC_PIN_GROUP(intc_ex_irq5),
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	3999	SH_PFC_PIN_GROUP(msiof0_clk),
				4000	SH_PFC_PIN_GROUP(msiof0_sync),
				4001	SH_PFC_PIN_GROUP(msiof0_ss1),
				4002	SH_PFC_PIN_GROUP(msiof0_ss2),
				4003	SH_PFC_PIN_GROUP(msiof0_txd),
				4004	SH_PFC_PIN_GROUP(msiof0_rxd),
				4005	SH_PFC_PIN_GROUP(msiof1_clk_a),
				4006	SH_PFC_PIN_GROUP(msiof1_sync_a),
				4007	SH_PFC_PIN_GROUP(msiof1_ss1_a),
				4008	SH_PFC_PIN_GROUP(msiof1_ss2_a),
				4009	SH_PFC_PIN_GROUP(msiof1_txd_a),
				4010	SH_PFC_PIN_GROUP(msiof1_rxd_a),
				4011	SH_PFC_PIN_GROUP(msiof1_clk_b),
				4012	SH_PFC_PIN_GROUP(msiof1_sync_b),
				4013	SH_PFC_PIN_GROUP(msiof1_ss1_b),
				4014	SH_PFC_PIN_GROUP(msiof1_ss2_b),
				4015	SH_PFC_PIN_GROUP(msiof1_txd_b),
				4016	SH_PFC_PIN_GROUP(msiof1_rxd_b),
				4017	SH_PFC_PIN_GROUP(msiof1_clk_c),
				4018	SH_PFC_PIN_GROUP(msiof1_sync_c),
				4019	SH_PFC_PIN_GROUP(msiof1_ss1_c),
				4020	SH_PFC_PIN_GROUP(msiof1_ss2_c),
				4021	SH_PFC_PIN_GROUP(msiof1_txd_c),
				4022	SH_PFC_PIN_GROUP(msiof1_rxd_c),
				4023	SH_PFC_PIN_GROUP(msiof1_clk_d),
				4024	SH_PFC_PIN_GROUP(msiof1_sync_d),
				4025	SH_PFC_PIN_GROUP(msiof1_ss1_d),
				4026	SH_PFC_PIN_GROUP(msiof1_ss2_d),
				4027	SH_PFC_PIN_GROUP(msiof1_txd_d),
				4028	SH_PFC_PIN_GROUP(msiof1_rxd_d),
				4029	SH_PFC_PIN_GROUP(msiof1_clk_e),
				4030	SH_PFC_PIN_GROUP(msiof1_sync_e),
				4031	SH_PFC_PIN_GROUP(msiof1_ss1_e),
				4032	SH_PFC_PIN_GROUP(msiof1_ss2_e),
				4033	SH_PFC_PIN_GROUP(msiof1_txd_e),
				4034	SH_PFC_PIN_GROUP(msiof1_rxd_e),
				4035	SH_PFC_PIN_GROUP(msiof1_clk_f),
				4036	SH_PFC_PIN_GROUP(msiof1_sync_f),
				4037	SH_PFC_PIN_GROUP(msiof1_ss1_f),
				4038	SH_PFC_PIN_GROUP(msiof1_ss2_f),
				4039	SH_PFC_PIN_GROUP(msiof1_txd_f),
				4040	SH_PFC_PIN_GROUP(msiof1_rxd_f),
				4041	SH_PFC_PIN_GROUP(msiof1_clk_g),
				4042	SH_PFC_PIN_GROUP(msiof1_sync_g),
				4043	SH_PFC_PIN_GROUP(msiof1_ss1_g),
				4044	SH_PFC_PIN_GROUP(msiof1_ss2_g),
				4045	SH_PFC_PIN_GROUP(msiof1_txd_g),
				4046	SH_PFC_PIN_GROUP(msiof1_rxd_g),
				4047	SH_PFC_PIN_GROUP(msiof2_clk_a),
				4048	SH_PFC_PIN_GROUP(msiof2_sync_a),
				4049	SH_PFC_PIN_GROUP(msiof2_ss1_a),
				4050	SH_PFC_PIN_GROUP(msiof2_ss2_a),
				4051	SH_PFC_PIN_GROUP(msiof2_txd_a),
				4052	SH_PFC_PIN_GROUP(msiof2_rxd_a),
				4053	SH_PFC_PIN_GROUP(msiof2_clk_b),
				4054	SH_PFC_PIN_GROUP(msiof2_sync_b),
				4055	SH_PFC_PIN_GROUP(msiof2_ss1_b),
				4056	SH_PFC_PIN_GROUP(msiof2_ss2_b),
				4057	SH_PFC_PIN_GROUP(msiof2_txd_b),
				4058	SH_PFC_PIN_GROUP(msiof2_rxd_b),
				4059	SH_PFC_PIN_GROUP(msiof2_clk_c),
				4060	SH_PFC_PIN_GROUP(msiof2_sync_c),
				4061	SH_PFC_PIN_GROUP(msiof2_ss1_c),
				4062	SH_PFC_PIN_GROUP(msiof2_ss2_c),
				4063	SH_PFC_PIN_GROUP(msiof2_txd_c),
				4064	SH_PFC_PIN_GROUP(msiof2_rxd_c),
				4065	SH_PFC_PIN_GROUP(msiof2_clk_d),
				4066	SH_PFC_PIN_GROUP(msiof2_sync_d),
				4067	SH_PFC_PIN_GROUP(msiof2_ss1_d),
				4068	SH_PFC_PIN_GROUP(msiof2_ss2_d),
				4069	SH_PFC_PIN_GROUP(msiof2_txd_d),
				4070	SH_PFC_PIN_GROUP(msiof2_rxd_d),
				4071	SH_PFC_PIN_GROUP(msiof3_clk_a),
				4072	SH_PFC_PIN_GROUP(msiof3_sync_a),
				4073	SH_PFC_PIN_GROUP(msiof3_ss1_a),
				4074	SH_PFC_PIN_GROUP(msiof3_ss2_a),
				4075	SH_PFC_PIN_GROUP(msiof3_txd_a),
				4076	SH_PFC_PIN_GROUP(msiof3_rxd_a),
				4077	SH_PFC_PIN_GROUP(msiof3_clk_b),
				4078	SH_PFC_PIN_GROUP(msiof3_sync_b),
				4079	SH_PFC_PIN_GROUP(msiof3_ss1_b),
				4080	SH_PFC_PIN_GROUP(msiof3_ss2_b),
				4081	SH_PFC_PIN_GROUP(msiof3_txd_b),
				4082	SH_PFC_PIN_GROUP(msiof3_rxd_b),
				4083	SH_PFC_PIN_GROUP(msiof3_clk_c),
				4084	SH_PFC_PIN_GROUP(msiof3_sync_c),
				4085	SH_PFC_PIN_GROUP(msiof3_txd_c),
				4086	SH_PFC_PIN_GROUP(msiof3_rxd_c),
				4087	SH_PFC_PIN_GROUP(msiof3_clk_d),
				4088	SH_PFC_PIN_GROUP(msiof3_sync_d),
				4089	SH_PFC_PIN_GROUP(msiof3_ss1_d),
				4090	SH_PFC_PIN_GROUP(msiof3_txd_d),
				4091	SH_PFC_PIN_GROUP(msiof3_rxd_d),
				4092	SH_PFC_PIN_GROUP(msiof3_clk_e),
				4093	SH_PFC_PIN_GROUP(msiof3_sync_e),
				4094	SH_PFC_PIN_GROUP(msiof3_ss1_e),
				4095	SH_PFC_PIN_GROUP(msiof3_ss2_e),
				4096	SH_PFC_PIN_GROUP(msiof3_txd_e),
				4097	SH_PFC_PIN_GROUP(msiof3_rxd_e),
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	4098	SH_PFC_PIN_GROUP(pwm0),
				4099	SH_PFC_PIN_GROUP(pwm1_a),
				4100	SH_PFC_PIN_GROUP(pwm1_b),
				4101	SH_PFC_PIN_GROUP(pwm2_a),
				4102	SH_PFC_PIN_GROUP(pwm2_b),
				4103	SH_PFC_PIN_GROUP(pwm3_a),
				4104	SH_PFC_PIN_GROUP(pwm3_b),
				4105	SH_PFC_PIN_GROUP(pwm4_a),
				4106	SH_PFC_PIN_GROUP(pwm4_b),
				4107	SH_PFC_PIN_GROUP(pwm5_a),
				4108	SH_PFC_PIN_GROUP(pwm5_b),
				4109	SH_PFC_PIN_GROUP(pwm6_a),
				4110	SH_PFC_PIN_GROUP(pwm6_b),
Wolfram Sang	297e5b2	2017-12-20 22:59:22 +0100	[diff] [blame^]	4111	SH_PFC_PIN_GROUP(sata0_devslp_a),
				4112	SH_PFC_PIN_GROUP(sata0_devslp_b),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4113	SH_PFC_PIN_GROUP(scif0_data),
				4114	SH_PFC_PIN_GROUP(scif0_clk),
				4115	SH_PFC_PIN_GROUP(scif0_ctrl),
				4116	SH_PFC_PIN_GROUP(scif1_data_a),
				4117	SH_PFC_PIN_GROUP(scif1_clk),
				4118	SH_PFC_PIN_GROUP(scif1_ctrl),
				4119	SH_PFC_PIN_GROUP(scif1_data_b),
				4120	SH_PFC_PIN_GROUP(scif2_data_a),
				4121	SH_PFC_PIN_GROUP(scif2_clk),
				4122	SH_PFC_PIN_GROUP(scif2_data_b),
				4123	SH_PFC_PIN_GROUP(scif3_data_a),
				4124	SH_PFC_PIN_GROUP(scif3_clk),
				4125	SH_PFC_PIN_GROUP(scif3_ctrl),
				4126	SH_PFC_PIN_GROUP(scif3_data_b),
				4127	SH_PFC_PIN_GROUP(scif4_data_a),
				4128	SH_PFC_PIN_GROUP(scif4_clk_a),
				4129	SH_PFC_PIN_GROUP(scif4_ctrl_a),
				4130	SH_PFC_PIN_GROUP(scif4_data_b),
				4131	SH_PFC_PIN_GROUP(scif4_clk_b),
				4132	SH_PFC_PIN_GROUP(scif4_ctrl_b),
				4133	SH_PFC_PIN_GROUP(scif4_data_c),
				4134	SH_PFC_PIN_GROUP(scif4_clk_c),
				4135	SH_PFC_PIN_GROUP(scif4_ctrl_c),
				4136	SH_PFC_PIN_GROUP(scif5_data_a),
				4137	SH_PFC_PIN_GROUP(scif5_clk_a),
				4138	SH_PFC_PIN_GROUP(scif5_data_b),
				4139	SH_PFC_PIN_GROUP(scif5_clk_b),
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	4140	SH_PFC_PIN_GROUP(scif_clk_a),
				4141	SH_PFC_PIN_GROUP(scif_clk_b),
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	4142	SH_PFC_PIN_GROUP(sdhi0_data1),
				4143	SH_PFC_PIN_GROUP(sdhi0_data4),
				4144	SH_PFC_PIN_GROUP(sdhi0_ctrl),
				4145	SH_PFC_PIN_GROUP(sdhi0_cd),
				4146	SH_PFC_PIN_GROUP(sdhi0_wp),
				4147	SH_PFC_PIN_GROUP(sdhi1_data1),
				4148	SH_PFC_PIN_GROUP(sdhi1_data4),
				4149	SH_PFC_PIN_GROUP(sdhi1_ctrl),
				4150	SH_PFC_PIN_GROUP(sdhi1_cd),
				4151	SH_PFC_PIN_GROUP(sdhi1_wp),
				4152	SH_PFC_PIN_GROUP(sdhi2_data1),
				4153	SH_PFC_PIN_GROUP(sdhi2_data4),
				4154	SH_PFC_PIN_GROUP(sdhi2_data8),
				4155	SH_PFC_PIN_GROUP(sdhi2_ctrl),
				4156	SH_PFC_PIN_GROUP(sdhi2_cd_a),
				4157	SH_PFC_PIN_GROUP(sdhi2_wp_a),
				4158	SH_PFC_PIN_GROUP(sdhi2_cd_b),
				4159	SH_PFC_PIN_GROUP(sdhi2_wp_b),
				4160	SH_PFC_PIN_GROUP(sdhi2_ds),
				4161	SH_PFC_PIN_GROUP(sdhi3_data1),
				4162	SH_PFC_PIN_GROUP(sdhi3_data4),
				4163	SH_PFC_PIN_GROUP(sdhi3_data8),
				4164	SH_PFC_PIN_GROUP(sdhi3_ctrl),
				4165	SH_PFC_PIN_GROUP(sdhi3_cd),
				4166	SH_PFC_PIN_GROUP(sdhi3_wp),
				4167	SH_PFC_PIN_GROUP(sdhi3_ds),
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	4168	SH_PFC_PIN_GROUP(ssi0_data),
				4169	SH_PFC_PIN_GROUP(ssi01239_ctrl),
				4170	SH_PFC_PIN_GROUP(ssi1_data_a),
				4171	SH_PFC_PIN_GROUP(ssi1_data_b),
				4172	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
				4173	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
				4174	SH_PFC_PIN_GROUP(ssi2_data_a),
				4175	SH_PFC_PIN_GROUP(ssi2_data_b),
				4176	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
				4177	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
				4178	SH_PFC_PIN_GROUP(ssi3_data),
				4179	SH_PFC_PIN_GROUP(ssi349_ctrl),
				4180	SH_PFC_PIN_GROUP(ssi4_data),
				4181	SH_PFC_PIN_GROUP(ssi4_ctrl),
				4182	SH_PFC_PIN_GROUP(ssi5_data),
				4183	SH_PFC_PIN_GROUP(ssi5_ctrl),
				4184	SH_PFC_PIN_GROUP(ssi6_data),
				4185	SH_PFC_PIN_GROUP(ssi6_ctrl),
				4186	SH_PFC_PIN_GROUP(ssi7_data),
				4187	SH_PFC_PIN_GROUP(ssi78_ctrl),
				4188	SH_PFC_PIN_GROUP(ssi8_data),
				4189	SH_PFC_PIN_GROUP(ssi9_data_a),
				4190	SH_PFC_PIN_GROUP(ssi9_data_b),
				4191	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
				4192	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	4193	SH_PFC_PIN_GROUP(usb0),
				4194	SH_PFC_PIN_GROUP(usb1),
				4195	SH_PFC_PIN_GROUP(usb2),
				4196	SH_PFC_PIN_GROUP(usb2_ch3),
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	4197	SH_PFC_PIN_GROUP(usb30),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4198	};
				4199
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	4200	static const char * const audio_clk_groups[] = {
				4201	"audio_clk_a_a",
				4202	"audio_clk_a_b",
				4203	"audio_clk_a_c",
				4204	"audio_clk_b_a",
				4205	"audio_clk_b_b",
				4206	"audio_clk_c_a",
				4207	"audio_clk_c_b",
				4208	"audio_clkout_a",
				4209	"audio_clkout_b",
				4210	"audio_clkout_c",
				4211	"audio_clkout_d",
				4212	"audio_clkout1_a",
				4213	"audio_clkout1_b",
				4214	"audio_clkout2_a",
				4215	"audio_clkout2_b",
				4216	"audio_clkout3_a",
				4217	"audio_clkout3_b",
				4218	};
				4219
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	4220	static const char * const avb_groups[] = {
				4221	"avb_link",
				4222	"avb_magic",
				4223	"avb_phy_int",
				4224	"avb_mdc",
				4225	"avb_mii",
				4226	"avb_avtp_pps",
				4227	"avb_avtp_match_a",
				4228	"avb_avtp_capture_a",
				4229	"avb_avtp_match_b",
				4230	"avb_avtp_capture_b",
				4231	};
				4232
Ramesh Shanmugasundaram	a678abf	2017-11-10 13:58:49 +0000	[diff] [blame]	4233	static const char * const can0_groups[] = {
				4234	"can0_data_a",
				4235	"can0_data_b",
				4236	};
				4237
				4238	static const char * const can1_groups[] = {
				4239	"can1_data",
				4240	};
				4241
				4242	static const char * const can_clk_groups[] = {
				4243	"can_clk",
				4244	};
				4245
Ramesh Shanmugasundaram	0e1c7a9	2017-11-10 13:58:50 +0000	[diff] [blame]	4246	static const char * const canfd0_groups[] = {
				4247	"canfd0_data_a",
				4248	"canfd0_data_b",
				4249	};
				4250
				4251	static const char * const canfd1_groups[] = {
				4252	"canfd1_data",
				4253	};
				4254
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	4255	static const char * const drif0_groups[] = {
				4256	"drif0_ctrl_a",
				4257	"drif0_data0_a",
				4258	"drif0_data1_a",
				4259	"drif0_ctrl_b",
				4260	"drif0_data0_b",
				4261	"drif0_data1_b",
				4262	"drif0_ctrl_c",
				4263	"drif0_data0_c",
				4264	"drif0_data1_c",
				4265	};
				4266
				4267	static const char * const drif1_groups[] = {
				4268	"drif1_ctrl_a",
				4269	"drif1_data0_a",
				4270	"drif1_data1_a",
				4271	"drif1_ctrl_b",
				4272	"drif1_data0_b",
				4273	"drif1_data1_b",
				4274	"drif1_ctrl_c",
				4275	"drif1_data0_c",
				4276	"drif1_data1_c",
				4277	};
				4278
				4279	static const char * const drif2_groups[] = {
				4280	"drif2_ctrl_a",
				4281	"drif2_data0_a",
				4282	"drif2_data1_a",
				4283	"drif2_ctrl_b",
				4284	"drif2_data0_b",
				4285	"drif2_data1_b",
				4286	};
				4287
				4288	static const char * const drif3_groups[] = {
				4289	"drif3_ctrl_a",
				4290	"drif3_data0_a",
				4291	"drif3_data1_a",
				4292	"drif3_ctrl_b",
				4293	"drif3_data0_b",
				4294	"drif3_data1_b",
				4295	};
				4296
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	4297	static const char * const du_groups[] = {
				4298	"du_rgb666",
				4299	"du_rgb888",
				4300	"du_clk_out_0",
				4301	"du_clk_out_1",
				4302	"du_sync",
				4303	"du_oddf",
				4304	"du_cde",
				4305	"du_disp",
				4306	};
				4307
Wolfram Sang	7a362e3	2017-10-09 10:20:53 +0200	[diff] [blame]	4308	static const char * const hscif0_groups[] = {
				4309	"hscif0_data",
				4310	"hscif0_clk",
				4311	"hscif0_ctrl",
				4312	};
				4313
				4314	static const char * const hscif1_groups[] = {
				4315	"hscif1_data_a",
				4316	"hscif1_clk_a",
				4317	"hscif1_ctrl_a",
				4318	"hscif1_data_b",
				4319	"hscif1_clk_b",
				4320	"hscif1_ctrl_b",
				4321	};
				4322
				4323	static const char * const hscif2_groups[] = {
				4324	"hscif2_data_a",
				4325	"hscif2_clk_a",
				4326	"hscif2_ctrl_a",
				4327	"hscif2_data_b",
				4328	"hscif2_clk_b",
				4329	"hscif2_ctrl_b",
				4330	"hscif2_data_c",
				4331	"hscif2_clk_c",
				4332	"hscif2_ctrl_c",
				4333	};
				4334
				4335	static const char * const hscif3_groups[] = {
				4336	"hscif3_data_a",
				4337	"hscif3_clk",
				4338	"hscif3_ctrl",
				4339	"hscif3_data_b",
				4340	"hscif3_data_c",
				4341	"hscif3_data_d",
				4342	};
				4343
				4344	static const char * const hscif4_groups[] = {
				4345	"hscif4_data_a",
				4346	"hscif4_clk",
				4347	"hscif4_ctrl",
				4348	"hscif4_data_b",
				4349	};
				4350
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	4351	static const char * const i2c1_groups[] = {
				4352	"i2c1_a",
				4353	"i2c1_b",
				4354	};
				4355
				4356	static const char * const i2c2_groups[] = {
				4357	"i2c2_a",
				4358	"i2c2_b",
				4359	};
				4360
				4361	static const char * const i2c6_groups[] = {
				4362	"i2c6_a",
				4363	"i2c6_b",
				4364	"i2c6_c",
				4365	};
				4366
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame]	4367	static const char * const intc_ex_groups[] = {
				4368	"intc_ex_irq0",
				4369	"intc_ex_irq1",
				4370	"intc_ex_irq2",
				4371	"intc_ex_irq3",
				4372	"intc_ex_irq4",
				4373	"intc_ex_irq5",
				4374	};
				4375
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	4376	static const char * const msiof0_groups[] = {
				4377	"msiof0_clk",
				4378	"msiof0_sync",
				4379	"msiof0_ss1",
				4380	"msiof0_ss2",
				4381	"msiof0_txd",
				4382	"msiof0_rxd",
				4383	};
				4384
				4385	static const char * const msiof1_groups[] = {
				4386	"msiof1_clk_a",
				4387	"msiof1_sync_a",
				4388	"msiof1_ss1_a",
				4389	"msiof1_ss2_a",
				4390	"msiof1_txd_a",
				4391	"msiof1_rxd_a",
				4392	"msiof1_clk_b",
				4393	"msiof1_sync_b",
				4394	"msiof1_ss1_b",
				4395	"msiof1_ss2_b",
				4396	"msiof1_txd_b",
				4397	"msiof1_rxd_b",
				4398	"msiof1_clk_c",
				4399	"msiof1_sync_c",
				4400	"msiof1_ss1_c",
				4401	"msiof1_ss2_c",
				4402	"msiof1_txd_c",
				4403	"msiof1_rxd_c",
				4404	"msiof1_clk_d",
				4405	"msiof1_sync_d",
				4406	"msiof1_ss1_d",
				4407	"msiof1_ss2_d",
				4408	"msiof1_txd_d",
				4409	"msiof1_rxd_d",
				4410	"msiof1_clk_e",
				4411	"msiof1_sync_e",
				4412	"msiof1_ss1_e",
				4413	"msiof1_ss2_e",
				4414	"msiof1_txd_e",
				4415	"msiof1_rxd_e",
				4416	"msiof1_clk_f",
				4417	"msiof1_sync_f",
				4418	"msiof1_ss1_f",
				4419	"msiof1_ss2_f",
				4420	"msiof1_txd_f",
				4421	"msiof1_rxd_f",
				4422	"msiof1_clk_g",
				4423	"msiof1_sync_g",
				4424	"msiof1_ss1_g",
				4425	"msiof1_ss2_g",
				4426	"msiof1_txd_g",
				4427	"msiof1_rxd_g",
				4428	};
				4429
				4430	static const char * const msiof2_groups[] = {
				4431	"msiof2_clk_a",
				4432	"msiof2_sync_a",
				4433	"msiof2_ss1_a",
				4434	"msiof2_ss2_a",
				4435	"msiof2_txd_a",
				4436	"msiof2_rxd_a",
				4437	"msiof2_clk_b",
				4438	"msiof2_sync_b",
				4439	"msiof2_ss1_b",
				4440	"msiof2_ss2_b",
				4441	"msiof2_txd_b",
				4442	"msiof2_rxd_b",
				4443	"msiof2_clk_c",
				4444	"msiof2_sync_c",
				4445	"msiof2_ss1_c",
				4446	"msiof2_ss2_c",
				4447	"msiof2_txd_c",
				4448	"msiof2_rxd_c",
				4449	"msiof2_clk_d",
				4450	"msiof2_sync_d",
				4451	"msiof2_ss1_d",
				4452	"msiof2_ss2_d",
				4453	"msiof2_txd_d",
				4454	"msiof2_rxd_d",
				4455	};
				4456
				4457	static const char * const msiof3_groups[] = {
				4458	"msiof3_clk_a",
				4459	"msiof3_sync_a",
				4460	"msiof3_ss1_a",
				4461	"msiof3_ss2_a",
				4462	"msiof3_txd_a",
				4463	"msiof3_rxd_a",
				4464	"msiof3_clk_b",
				4465	"msiof3_sync_b",
				4466	"msiof3_ss1_b",
				4467	"msiof3_ss2_b",
				4468	"msiof3_txd_b",
				4469	"msiof3_rxd_b",
				4470	"msiof3_clk_c",
				4471	"msiof3_sync_c",
				4472	"msiof3_txd_c",
				4473	"msiof3_rxd_c",
				4474	"msiof3_clk_d",
				4475	"msiof3_sync_d",
				4476	"msiof3_ss1_d",
				4477	"msiof3_txd_d",
				4478	"msiof3_rxd_d",
				4479	"msiof3_clk_e",
				4480	"msiof3_sync_e",
				4481	"msiof3_ss1_e",
				4482	"msiof3_ss2_e",
				4483	"msiof3_txd_e",
				4484	"msiof3_rxd_e",
				4485	};
				4486
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	4487	static const char * const pwm0_groups[] = {
				4488	"pwm0",
				4489	};
				4490
				4491	static const char * const pwm1_groups[] = {
				4492	"pwm1_a",
				4493	"pwm1_b",
				4494	};
				4495
				4496	static const char * const pwm2_groups[] = {
				4497	"pwm2_a",
				4498	"pwm2_b",
				4499	};
				4500
				4501	static const char * const pwm3_groups[] = {
				4502	"pwm3_a",
				4503	"pwm3_b",
				4504	};
				4505
				4506	static const char * const pwm4_groups[] = {
				4507	"pwm4_a",
				4508	"pwm4_b",
				4509	};
				4510
				4511	static const char * const pwm5_groups[] = {
				4512	"pwm5_a",
				4513	"pwm5_b",
				4514	};
				4515
				4516	static const char * const pwm6_groups[] = {
				4517	"pwm6_a",
				4518	"pwm6_b",
				4519	};
				4520
Wolfram Sang	297e5b2	2017-12-20 22:59:22 +0100	[diff] [blame^]	4521	static const char * const sata0_groups[] = {
				4522	"sata0_devslp_a",
				4523	"sata0_devslp_b",
				4524	};
				4525
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4526	static const char * const scif0_groups[] = {
				4527	"scif0_data",
				4528	"scif0_clk",
				4529	"scif0_ctrl",
				4530	};
				4531
				4532	static const char * const scif1_groups[] = {
				4533	"scif1_data_a",
				4534	"scif1_clk",
				4535	"scif1_ctrl",
				4536	"scif1_data_b",
				4537	};
				4538
				4539	static const char * const scif2_groups[] = {
				4540	"scif2_data_a",
				4541	"scif2_clk",
				4542	"scif2_data_b",
				4543	};
				4544
				4545	static const char * const scif3_groups[] = {
				4546	"scif3_data_a",
				4547	"scif3_clk",
				4548	"scif3_ctrl",
				4549	"scif3_data_b",
				4550	};
				4551
				4552	static const char * const scif4_groups[] = {
				4553	"scif4_data_a",
				4554	"scif4_clk_a",
				4555	"scif4_ctrl_a",
				4556	"scif4_data_b",
				4557	"scif4_clk_b",
				4558	"scif4_ctrl_b",
				4559	"scif4_data_c",
				4560	"scif4_clk_c",
				4561	"scif4_ctrl_c",
				4562	};
				4563
				4564	static const char * const scif5_groups[] = {
				4565	"scif5_data_a",
				4566	"scif5_clk_a",
				4567	"scif5_data_b",
				4568	"scif5_clk_b",
Takeshi Kihara	76250a6	2016-02-02 19:18:49 +0900	[diff] [blame]	4569	};
				4570
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	4571	static const char * const scif_clk_groups[] = {
				4572	"scif_clk_a",
				4573	"scif_clk_b",
				4574	};
				4575
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	4576	static const char * const sdhi0_groups[] = {
				4577	"sdhi0_data1",
				4578	"sdhi0_data4",
				4579	"sdhi0_ctrl",
				4580	"sdhi0_cd",
				4581	"sdhi0_wp",
				4582	};
				4583
				4584	static const char * const sdhi1_groups[] = {
				4585	"sdhi1_data1",
				4586	"sdhi1_data4",
				4587	"sdhi1_ctrl",
				4588	"sdhi1_cd",
				4589	"sdhi1_wp",
				4590	};
				4591
				4592	static const char * const sdhi2_groups[] = {
				4593	"sdhi2_data1",
				4594	"sdhi2_data4",
				4595	"sdhi2_data8",
				4596	"sdhi2_ctrl",
				4597	"sdhi2_cd_a",
				4598	"sdhi2_wp_a",
				4599	"sdhi2_cd_b",
				4600	"sdhi2_wp_b",
				4601	"sdhi2_ds",
				4602	};
				4603
				4604	static const char * const sdhi3_groups[] = {
				4605	"sdhi3_data1",
				4606	"sdhi3_data4",
				4607	"sdhi3_data8",
				4608	"sdhi3_ctrl",
				4609	"sdhi3_cd",
				4610	"sdhi3_wp",
				4611	"sdhi3_ds",
				4612	};
				4613
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	4614	static const char * const ssi_groups[] = {
				4615	"ssi0_data",
				4616	"ssi01239_ctrl",
				4617	"ssi1_data_a",
				4618	"ssi1_data_b",
				4619	"ssi1_ctrl_a",
				4620	"ssi1_ctrl_b",
				4621	"ssi2_data_a",
				4622	"ssi2_data_b",
				4623	"ssi2_ctrl_a",
				4624	"ssi2_ctrl_b",
				4625	"ssi3_data",
				4626	"ssi349_ctrl",
				4627	"ssi4_data",
				4628	"ssi4_ctrl",
				4629	"ssi5_data",
				4630	"ssi5_ctrl",
				4631	"ssi6_data",
				4632	"ssi6_ctrl",
				4633	"ssi7_data",
				4634	"ssi78_ctrl",
				4635	"ssi8_data",
				4636	"ssi9_data_a",
				4637	"ssi9_data_b",
				4638	"ssi9_ctrl_a",
				4639	"ssi9_ctrl_b",
				4640	};
				4641
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	4642	static const char * const usb0_groups[] = {
				4643	"usb0",
				4644	};
				4645
				4646	static const char * const usb1_groups[] = {
				4647	"usb1",
				4648	};
				4649
				4650	static const char * const usb2_groups[] = {
				4651	"usb2",
				4652	};
				4653
				4654	static const char * const usb2_ch3_groups[] = {
				4655	"usb2_ch3",
				4656	};
				4657
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	4658	static const char * const usb30_groups[] = {
				4659	"usb30",
				4660	};
				4661
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4662	static const struct sh_pfc_function pinmux_functions[] = {
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	4663	SH_PFC_FUNCTION(audio_clk),
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	4664	SH_PFC_FUNCTION(avb),
Ramesh Shanmugasundaram	a678abf	2017-11-10 13:58:49 +0000	[diff] [blame]	4665	SH_PFC_FUNCTION(can0),
				4666	SH_PFC_FUNCTION(can1),
				4667	SH_PFC_FUNCTION(can_clk),
Ramesh Shanmugasundaram	0e1c7a9	2017-11-10 13:58:50 +0000	[diff] [blame]	4668	SH_PFC_FUNCTION(canfd0),
				4669	SH_PFC_FUNCTION(canfd1),
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	4670	SH_PFC_FUNCTION(drif0),
				4671	SH_PFC_FUNCTION(drif1),
				4672	SH_PFC_FUNCTION(drif2),
				4673	SH_PFC_FUNCTION(drif3),
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	4674	SH_PFC_FUNCTION(du),
Wolfram Sang	7a362e3	2017-10-09 10:20:53 +0200	[diff] [blame]	4675	SH_PFC_FUNCTION(hscif0),
				4676	SH_PFC_FUNCTION(hscif1),
				4677	SH_PFC_FUNCTION(hscif2),
				4678	SH_PFC_FUNCTION(hscif3),
				4679	SH_PFC_FUNCTION(hscif4),
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	4680	SH_PFC_FUNCTION(i2c1),
				4681	SH_PFC_FUNCTION(i2c2),
				4682	SH_PFC_FUNCTION(i2c6),
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame]	4683	SH_PFC_FUNCTION(intc_ex),
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	4684	SH_PFC_FUNCTION(msiof0),
				4685	SH_PFC_FUNCTION(msiof1),
				4686	SH_PFC_FUNCTION(msiof2),
				4687	SH_PFC_FUNCTION(msiof3),
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	4688	SH_PFC_FUNCTION(pwm0),
				4689	SH_PFC_FUNCTION(pwm1),
				4690	SH_PFC_FUNCTION(pwm2),
				4691	SH_PFC_FUNCTION(pwm3),
				4692	SH_PFC_FUNCTION(pwm4),
				4693	SH_PFC_FUNCTION(pwm5),
				4694	SH_PFC_FUNCTION(pwm6),
Wolfram Sang	297e5b2	2017-12-20 22:59:22 +0100	[diff] [blame^]	4695	SH_PFC_FUNCTION(sata0),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4696	SH_PFC_FUNCTION(scif0),
				4697	SH_PFC_FUNCTION(scif1),
				4698	SH_PFC_FUNCTION(scif2),
				4699	SH_PFC_FUNCTION(scif3),
				4700	SH_PFC_FUNCTION(scif4),
				4701	SH_PFC_FUNCTION(scif5),
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	4702	SH_PFC_FUNCTION(scif_clk),
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	4703	SH_PFC_FUNCTION(sdhi0),
				4704	SH_PFC_FUNCTION(sdhi1),
				4705	SH_PFC_FUNCTION(sdhi2),
				4706	SH_PFC_FUNCTION(sdhi3),
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	4707	SH_PFC_FUNCTION(ssi),
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	4708	SH_PFC_FUNCTION(usb0),
				4709	SH_PFC_FUNCTION(usb1),
				4710	SH_PFC_FUNCTION(usb2),
				4711	SH_PFC_FUNCTION(usb2_ch3),
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	4712	SH_PFC_FUNCTION(usb30),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4713	};
				4714
				4715	static const struct pinmux_cfg_reg pinmux_config_regs[] = {
				4716	#define F_(x, y) FN_##y
				4717	#define FM(x) FN_##x
				4718	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
				4719	0, 0,
				4720	0, 0,
				4721	0, 0,
				4722	0, 0,
				4723	0, 0,
				4724	0, 0,
				4725	0, 0,
				4726	0, 0,
				4727	0, 0,
				4728	0, 0,
				4729	0, 0,
				4730	0, 0,
				4731	0, 0,
				4732	0, 0,
				4733	0, 0,
				4734	0, 0,
				4735	GP_0_15_FN, GPSR0_15,
				4736	GP_0_14_FN, GPSR0_14,
				4737	GP_0_13_FN, GPSR0_13,
				4738	GP_0_12_FN, GPSR0_12,
				4739	GP_0_11_FN, GPSR0_11,
				4740	GP_0_10_FN, GPSR0_10,
				4741	GP_0_9_FN, GPSR0_9,
				4742	GP_0_8_FN, GPSR0_8,
				4743	GP_0_7_FN, GPSR0_7,
				4744	GP_0_6_FN, GPSR0_6,
				4745	GP_0_5_FN, GPSR0_5,
				4746	GP_0_4_FN, GPSR0_4,
				4747	GP_0_3_FN, GPSR0_3,
				4748	GP_0_2_FN, GPSR0_2,
				4749	GP_0_1_FN, GPSR0_1,
				4750	GP_0_0_FN, GPSR0_0, }
				4751	},
				4752	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
				4753	0, 0,
				4754	0, 0,
				4755	0, 0,
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	4756	GP_1_28_FN, GPSR1_28,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4757	GP_1_27_FN, GPSR1_27,
				4758	GP_1_26_FN, GPSR1_26,
				4759	GP_1_25_FN, GPSR1_25,
				4760	GP_1_24_FN, GPSR1_24,
				4761	GP_1_23_FN, GPSR1_23,
				4762	GP_1_22_FN, GPSR1_22,
				4763	GP_1_21_FN, GPSR1_21,
				4764	GP_1_20_FN, GPSR1_20,
				4765	GP_1_19_FN, GPSR1_19,
				4766	GP_1_18_FN, GPSR1_18,
				4767	GP_1_17_FN, GPSR1_17,
				4768	GP_1_16_FN, GPSR1_16,
				4769	GP_1_15_FN, GPSR1_15,
				4770	GP_1_14_FN, GPSR1_14,
				4771	GP_1_13_FN, GPSR1_13,
				4772	GP_1_12_FN, GPSR1_12,
				4773	GP_1_11_FN, GPSR1_11,
				4774	GP_1_10_FN, GPSR1_10,
				4775	GP_1_9_FN, GPSR1_9,
				4776	GP_1_8_FN, GPSR1_8,
				4777	GP_1_7_FN, GPSR1_7,
				4778	GP_1_6_FN, GPSR1_6,
				4779	GP_1_5_FN, GPSR1_5,
				4780	GP_1_4_FN, GPSR1_4,
				4781	GP_1_3_FN, GPSR1_3,
				4782	GP_1_2_FN, GPSR1_2,
				4783	GP_1_1_FN, GPSR1_1,
				4784	GP_1_0_FN, GPSR1_0, }
				4785	},
				4786	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
				4787	0, 0,
				4788	0, 0,
				4789	0, 0,
				4790	0, 0,
				4791	0, 0,
				4792	0, 0,
				4793	0, 0,
				4794	0, 0,
				4795	0, 0,
				4796	0, 0,
				4797	0, 0,
				4798	0, 0,
				4799	0, 0,
				4800	0, 0,
				4801	0, 0,
				4802	0, 0,
				4803	0, 0,
				4804	GP_2_14_FN, GPSR2_14,
				4805	GP_2_13_FN, GPSR2_13,
				4806	GP_2_12_FN, GPSR2_12,
				4807	GP_2_11_FN, GPSR2_11,
				4808	GP_2_10_FN, GPSR2_10,
				4809	GP_2_9_FN, GPSR2_9,
				4810	GP_2_8_FN, GPSR2_8,
				4811	GP_2_7_FN, GPSR2_7,
				4812	GP_2_6_FN, GPSR2_6,
				4813	GP_2_5_FN, GPSR2_5,
				4814	GP_2_4_FN, GPSR2_4,
				4815	GP_2_3_FN, GPSR2_3,
				4816	GP_2_2_FN, GPSR2_2,
				4817	GP_2_1_FN, GPSR2_1,
				4818	GP_2_0_FN, GPSR2_0, }
				4819	},
				4820	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
				4821	0, 0,
				4822	0, 0,
				4823	0, 0,
				4824	0, 0,
				4825	0, 0,
				4826	0, 0,
				4827	0, 0,
				4828	0, 0,
				4829	0, 0,
				4830	0, 0,
				4831	0, 0,
				4832	0, 0,
				4833	0, 0,
				4834	0, 0,
				4835	0, 0,
				4836	0, 0,
				4837	GP_3_15_FN, GPSR3_15,
				4838	GP_3_14_FN, GPSR3_14,
				4839	GP_3_13_FN, GPSR3_13,
				4840	GP_3_12_FN, GPSR3_12,
				4841	GP_3_11_FN, GPSR3_11,
				4842	GP_3_10_FN, GPSR3_10,
				4843	GP_3_9_FN, GPSR3_9,
				4844	GP_3_8_FN, GPSR3_8,
				4845	GP_3_7_FN, GPSR3_7,
				4846	GP_3_6_FN, GPSR3_6,
				4847	GP_3_5_FN, GPSR3_5,
				4848	GP_3_4_FN, GPSR3_4,
				4849	GP_3_3_FN, GPSR3_3,
				4850	GP_3_2_FN, GPSR3_2,
				4851	GP_3_1_FN, GPSR3_1,
				4852	GP_3_0_FN, GPSR3_0, }
				4853	},
				4854	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
				4855	0, 0,
				4856	0, 0,
				4857	0, 0,
				4858	0, 0,
				4859	0, 0,
				4860	0, 0,
				4861	0, 0,
				4862	0, 0,
				4863	0, 0,
				4864	0, 0,
				4865	0, 0,
				4866	0, 0,
				4867	0, 0,
				4868	0, 0,
				4869	GP_4_17_FN, GPSR4_17,
				4870	GP_4_16_FN, GPSR4_16,
				4871	GP_4_15_FN, GPSR4_15,
				4872	GP_4_14_FN, GPSR4_14,
				4873	GP_4_13_FN, GPSR4_13,
				4874	GP_4_12_FN, GPSR4_12,
				4875	GP_4_11_FN, GPSR4_11,
				4876	GP_4_10_FN, GPSR4_10,
				4877	GP_4_9_FN, GPSR4_9,
				4878	GP_4_8_FN, GPSR4_8,
				4879	GP_4_7_FN, GPSR4_7,
				4880	GP_4_6_FN, GPSR4_6,
				4881	GP_4_5_FN, GPSR4_5,
				4882	GP_4_4_FN, GPSR4_4,
				4883	GP_4_3_FN, GPSR4_3,
				4884	GP_4_2_FN, GPSR4_2,
				4885	GP_4_1_FN, GPSR4_1,
				4886	GP_4_0_FN, GPSR4_0, }
				4887	},
				4888	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
				4889	0, 0,
				4890	0, 0,
				4891	0, 0,
				4892	0, 0,
				4893	0, 0,
				4894	0, 0,
				4895	GP_5_25_FN, GPSR5_25,
				4896	GP_5_24_FN, GPSR5_24,
				4897	GP_5_23_FN, GPSR5_23,
				4898	GP_5_22_FN, GPSR5_22,
				4899	GP_5_21_FN, GPSR5_21,
				4900	GP_5_20_FN, GPSR5_20,
				4901	GP_5_19_FN, GPSR5_19,
				4902	GP_5_18_FN, GPSR5_18,
				4903	GP_5_17_FN, GPSR5_17,
				4904	GP_5_16_FN, GPSR5_16,
				4905	GP_5_15_FN, GPSR5_15,
				4906	GP_5_14_FN, GPSR5_14,
				4907	GP_5_13_FN, GPSR5_13,
				4908	GP_5_12_FN, GPSR5_12,
				4909	GP_5_11_FN, GPSR5_11,
				4910	GP_5_10_FN, GPSR5_10,
				4911	GP_5_9_FN, GPSR5_9,
				4912	GP_5_8_FN, GPSR5_8,
				4913	GP_5_7_FN, GPSR5_7,
				4914	GP_5_6_FN, GPSR5_6,
				4915	GP_5_5_FN, GPSR5_5,
				4916	GP_5_4_FN, GPSR5_4,
				4917	GP_5_3_FN, GPSR5_3,
				4918	GP_5_2_FN, GPSR5_2,
				4919	GP_5_1_FN, GPSR5_1,
				4920	GP_5_0_FN, GPSR5_0, }
				4921	},
				4922	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
				4923	GP_6_31_FN, GPSR6_31,
				4924	GP_6_30_FN, GPSR6_30,
				4925	GP_6_29_FN, GPSR6_29,
				4926	GP_6_28_FN, GPSR6_28,
				4927	GP_6_27_FN, GPSR6_27,
				4928	GP_6_26_FN, GPSR6_26,
				4929	GP_6_25_FN, GPSR6_25,
				4930	GP_6_24_FN, GPSR6_24,
				4931	GP_6_23_FN, GPSR6_23,
				4932	GP_6_22_FN, GPSR6_22,
				4933	GP_6_21_FN, GPSR6_21,
				4934	GP_6_20_FN, GPSR6_20,
				4935	GP_6_19_FN, GPSR6_19,
				4936	GP_6_18_FN, GPSR6_18,
				4937	GP_6_17_FN, GPSR6_17,
				4938	GP_6_16_FN, GPSR6_16,
				4939	GP_6_15_FN, GPSR6_15,
				4940	GP_6_14_FN, GPSR6_14,
				4941	GP_6_13_FN, GPSR6_13,
				4942	GP_6_12_FN, GPSR6_12,
				4943	GP_6_11_FN, GPSR6_11,
				4944	GP_6_10_FN, GPSR6_10,
				4945	GP_6_9_FN, GPSR6_9,
				4946	GP_6_8_FN, GPSR6_8,
				4947	GP_6_7_FN, GPSR6_7,
				4948	GP_6_6_FN, GPSR6_6,
				4949	GP_6_5_FN, GPSR6_5,
				4950	GP_6_4_FN, GPSR6_4,
				4951	GP_6_3_FN, GPSR6_3,
				4952	GP_6_2_FN, GPSR6_2,
				4953	GP_6_1_FN, GPSR6_1,
				4954	GP_6_0_FN, GPSR6_0, }
				4955	},
				4956	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
				4957	0, 0,
				4958	0, 0,
				4959	0, 0,
				4960	0, 0,
				4961	0, 0,
				4962	0, 0,
				4963	0, 0,
				4964	0, 0,
				4965	0, 0,
				4966	0, 0,
				4967	0, 0,
				4968	0, 0,
				4969	0, 0,
				4970	0, 0,
				4971	0, 0,
				4972	0, 0,
				4973	0, 0,
				4974	0, 0,
				4975	0, 0,
				4976	0, 0,
				4977	0, 0,
				4978	0, 0,
				4979	0, 0,
				4980	0, 0,
				4981	0, 0,
				4982	0, 0,
				4983	0, 0,
				4984	0, 0,
				4985	GP_7_3_FN, GPSR7_3,
				4986	GP_7_2_FN, GPSR7_2,
				4987	GP_7_1_FN, GPSR7_1,
				4988	GP_7_0_FN, GPSR7_0, }
				4989	},
				4990	#undef F_
				4991	#undef FM
				4992
				4993	#define F_(x, y) x,
				4994	#define FM(x) FN_##x,
				4995	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
				4996	IP0_31_28
				4997	IP0_27_24
				4998	IP0_23_20
				4999	IP0_19_16
				5000	IP0_15_12
				5001	IP0_11_8
				5002	IP0_7_4
				5003	IP0_3_0 }
				5004	},
				5005	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
				5006	IP1_31_28
				5007	IP1_27_24
				5008	IP1_23_20
				5009	IP1_19_16
				5010	IP1_15_12
				5011	IP1_11_8
				5012	IP1_7_4
				5013	IP1_3_0 }
				5014	},
				5015	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
				5016	IP2_31_28
				5017	IP2_27_24
				5018	IP2_23_20
				5019	IP2_19_16
				5020	IP2_15_12
				5021	IP2_11_8
				5022	IP2_7_4
				5023	IP2_3_0 }
				5024	},
				5025	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
				5026	IP3_31_28
				5027	IP3_27_24
				5028	IP3_23_20
				5029	IP3_19_16
				5030	IP3_15_12
				5031	IP3_11_8
				5032	IP3_7_4
				5033	IP3_3_0 }
				5034	},
				5035	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
				5036	IP4_31_28
				5037	IP4_27_24
				5038	IP4_23_20
				5039	IP4_19_16
				5040	IP4_15_12
				5041	IP4_11_8
				5042	IP4_7_4
				5043	IP4_3_0 }
				5044	},
				5045	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
				5046	IP5_31_28
				5047	IP5_27_24
				5048	IP5_23_20
				5049	IP5_19_16
				5050	IP5_15_12
				5051	IP5_11_8
				5052	IP5_7_4
				5053	IP5_3_0 }
				5054	},
				5055	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
				5056	IP6_31_28
				5057	IP6_27_24
				5058	IP6_23_20
				5059	IP6_19_16
				5060	IP6_15_12
				5061	IP6_11_8
				5062	IP6_7_4
				5063	IP6_3_0 }
				5064	},
				5065	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
				5066	IP7_31_28
				5067	IP7_27_24
				5068	IP7_23_20
				5069	IP7_19_16
Takeshi Kihara	30cd1c4	2017-07-28 20:41:19 +0900	[diff] [blame]	5070	/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5071	IP7_11_8
				5072	IP7_7_4
				5073	IP7_3_0 }
				5074	},
				5075	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
				5076	IP8_31_28
				5077	IP8_27_24
				5078	IP8_23_20
				5079	IP8_19_16
				5080	IP8_15_12
				5081	IP8_11_8
				5082	IP8_7_4
				5083	IP8_3_0 }
				5084	},
				5085	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
				5086	IP9_31_28
				5087	IP9_27_24
				5088	IP9_23_20
				5089	IP9_19_16
				5090	IP9_15_12
				5091	IP9_11_8
				5092	IP9_7_4
				5093	IP9_3_0 }
				5094	},
				5095	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
				5096	IP10_31_28
				5097	IP10_27_24
				5098	IP10_23_20
				5099	IP10_19_16
				5100	IP10_15_12
				5101	IP10_11_8
				5102	IP10_7_4
				5103	IP10_3_0 }
				5104	},
				5105	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
				5106	IP11_31_28
				5107	IP11_27_24
				5108	IP11_23_20
				5109	IP11_19_16
				5110	IP11_15_12
				5111	IP11_11_8
				5112	IP11_7_4
				5113	IP11_3_0 }
				5114	},
				5115	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
				5116	IP12_31_28
				5117	IP12_27_24
				5118	IP12_23_20
				5119	IP12_19_16
				5120	IP12_15_12
				5121	IP12_11_8
				5122	IP12_7_4
				5123	IP12_3_0 }
				5124	},
				5125	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
				5126	IP13_31_28
				5127	IP13_27_24
				5128	IP13_23_20
				5129	IP13_19_16
				5130	IP13_15_12
				5131	IP13_11_8
				5132	IP13_7_4
				5133	IP13_3_0 }
				5134	},
				5135	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
				5136	IP14_31_28
				5137	IP14_27_24
				5138	IP14_23_20
				5139	IP14_19_16
				5140	IP14_15_12
				5141	IP14_11_8
				5142	IP14_7_4
				5143	IP14_3_0 }
				5144	},
				5145	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
				5146	IP15_31_28
				5147	IP15_27_24
				5148	IP15_23_20
				5149	IP15_19_16
				5150	IP15_15_12
				5151	IP15_11_8
				5152	IP15_7_4
				5153	IP15_3_0 }
				5154	},
				5155	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
				5156	IP16_31_28
				5157	IP16_27_24
				5158	IP16_23_20
				5159	IP16_19_16
				5160	IP16_15_12
				5161	IP16_11_8
				5162	IP16_7_4
				5163	IP16_3_0 }
				5164	},
				5165	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5166	IP17_31_28
				5167	IP17_27_24
				5168	IP17_23_20
				5169	IP17_19_16
				5170	IP17_15_12
				5171	IP17_11_8
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5172	IP17_7_4
				5173	IP17_3_0 }
				5174	},
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5175	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
				5176	/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5177	/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5178	/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5179	/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5180	/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5181	/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				5182	IP18_7_4
				5183	IP18_3_0 }
				5184	},
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5185	#undef F_
				5186	#undef FM
				5187
				5188	#define F_(x, y) x,
				5189	#define FM(x) FN_##x,
				5190	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5191	3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
				5192	1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
				5193	MOD_SEL0_31_30_29
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5194	MOD_SEL0_28_27
				5195	MOD_SEL0_26_25_24
				5196	MOD_SEL0_23
				5197	MOD_SEL0_22
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5198	MOD_SEL0_21
				5199	MOD_SEL0_20
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5200	MOD_SEL0_19
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5201	MOD_SEL0_18_17
				5202	MOD_SEL0_16
				5203	0, 0, /* RESERVED 15 */
				5204	MOD_SEL0_14_13
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5205	MOD_SEL0_12
				5206	MOD_SEL0_11
				5207	MOD_SEL0_10
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5208	MOD_SEL0_9_8
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5209	MOD_SEL0_7_6
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5210	MOD_SEL0_5
				5211	MOD_SEL0_4_3
				5212	/* RESERVED 2, 1, 0 */
				5213	0, 0, 0, 0, 0, 0, 0, 0 }
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5214	},
				5215	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
				5216	2, 3, 1, 2, 3, 1, 1, 2, 1,
				5217	2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
				5218	MOD_SEL1_31_30
				5219	MOD_SEL1_29_28_27
				5220	MOD_SEL1_26
				5221	MOD_SEL1_25_24
				5222	MOD_SEL1_23_22_21
				5223	MOD_SEL1_20
				5224	MOD_SEL1_19
				5225	MOD_SEL1_18_17
				5226	MOD_SEL1_16
				5227	MOD_SEL1_15_14
				5228	MOD_SEL1_13
				5229	MOD_SEL1_12
				5230	MOD_SEL1_11
				5231	MOD_SEL1_10
				5232	MOD_SEL1_9
				5233	0, 0, 0, 0, /* RESERVED 8, 7 */
				5234	MOD_SEL1_6
				5235	MOD_SEL1_5
				5236	MOD_SEL1_4
				5237	MOD_SEL1_3
				5238	MOD_SEL1_2
				5239	MOD_SEL1_1
				5240	MOD_SEL1_0 }
				5241	},
				5242	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5243	1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
				5244	4, 4, 4, 3, 1) {
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5245	MOD_SEL2_31
				5246	MOD_SEL2_30
				5247	MOD_SEL2_29
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5248	MOD_SEL2_28_27
				5249	MOD_SEL2_26
				5250	MOD_SEL2_25_24_23
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	5251	/* RESERVED 22 */
				5252	0, 0,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5253	MOD_SEL2_21
				5254	MOD_SEL2_20
				5255	MOD_SEL2_19
				5256	MOD_SEL2_18
				5257	MOD_SEL2_17
				5258	/* RESERVED 16 */
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5259	0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5260	/* RESERVED 15, 14, 13, 12 */
				5261	0, 0, 0, 0, 0, 0, 0, 0,
				5262	0, 0, 0, 0, 0, 0, 0, 0,
				5263	/* RESERVED 11, 10, 9, 8 */
				5264	0, 0, 0, 0, 0, 0, 0, 0,
				5265	0, 0, 0, 0, 0, 0, 0, 0,
				5266	/* RESERVED 7, 6, 5, 4 */
				5267	0, 0, 0, 0, 0, 0, 0, 0,
				5268	0, 0, 0, 0, 0, 0, 0, 0,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5269	/* RESERVED 3, 2, 1 */
				5270	0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5271	MOD_SEL2_0 }
				5272	},
				5273	{ },
				5274	};
				5275
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5276	static const struct pinmux_drive_reg pinmux_drive_regs[] = {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5277	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
				5278	{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
				5279	{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
				5280	{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
				5281	{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
				5282	{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
				5283	{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
				5284	{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
				5285	{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
				5286	} },
				5287	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
				5288	{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
				5289	{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
				5290	{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
				5291	{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
				5292	{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
				5293	{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
				5294	{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
				5295	{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
				5296	} },
				5297	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
				5298	{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
				5299	{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
				5300	{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
				5301	{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
				5302	{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
				5303	{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
				5304	{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
				5305	{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
				5306	} },
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5307	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5308	{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
				5309	{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
				5310	{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
				5311	{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
				5312	{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
				5313	{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
				5314	{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
				5315	{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5316	} },
				5317	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
				5318	{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
				5319	{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
				5320	{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
				5321	{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
				5322	{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
				5323	{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
				5324	{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
				5325	{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
				5326	} },
				5327	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
				5328	{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
				5329	{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
				5330	{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
				5331	{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
				5332	{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
				5333	{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
				5334	{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
				5335	{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
				5336	} },
				5337	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
				5338	{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
				5339	{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
				5340	{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
				5341	{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
				5342	{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
				5343	{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
				5344	{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
				5345	{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
				5346	} },
				5347	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
				5348	{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
				5349	{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
				5350	{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
				5351	{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
				5352	{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
				5353	{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
				5354	{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
				5355	{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
				5356	} },
				5357	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	5358	{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5359	{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
				5360	{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
				5361	{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
				5362	{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
				5363	{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
				5364	{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
				5365	{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
				5366	} },
				5367	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
				5368	{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5369	{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5370	{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
				5371	{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
				5372	{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
				5373	{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
				5374	{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
				5375	{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
				5376	} },
				5377	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
				5378	{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
				5379	{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
				5380	{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
				5381	{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
				5382	{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
				5383	{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
				5384	{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
				5385	{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
				5386	} },
				5387	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5388	{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
				5389	{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
				5390	{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
				5391	{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
				5392	{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
				5393	{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
				5394	{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
				5395	{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
				5396	} },
				5397	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
				5398	{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
				5399	{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
				5400	{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
				5401	{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5402	} },
				5403	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5404	{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
				5405	{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
				5406	{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
				5407	{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
				5408	{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
				5409	{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
				5410	{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
				5411	{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5412	} },
				5413	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
				5414	{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
				5415	{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
				5416	{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
				5417	{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
				5418	{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
				5419	{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
				5420	{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
				5421	{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
				5422	} },
				5423	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
				5424	{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
				5425	{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
				5426	{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
				5427	{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
				5428	{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
				5429	{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
				5430	{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
				5431	{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
				5432	} },
				5433	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
				5434	{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
				5435	{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
				5436	{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
				5437	{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
				5438	{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
				5439	{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
				5440	{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
				5441	{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
				5442	} },
				5443	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
				5444	{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
				5445	{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
				5446	{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
				5447	{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
				5448	{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
				5449	{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
				5450	{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
				5451	{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
				5452	} },
				5453	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	5454	{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5455	{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
				5456	{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
				5457	{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	5458	{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5459	{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
				5460	{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
				5461	{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
				5462	} },
				5463	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
				5464	{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
				5465	{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
				5466	{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
				5467	{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
				5468	{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
				5469	{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
				5470	{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
				5471	{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
				5472	} },
				5473	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
				5474	{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
				5475	{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
				5476	{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
				5477	{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
				5478	{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
				5479	{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5480	{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5481	{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
				5482	} },
				5483	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
				5484	{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
				5485	{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
				5486	{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
				5487	{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	5488	{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
				5489	{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5490	{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
				5491	{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
				5492	} },
				5493	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
				5494	{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
				5495	{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
				5496	{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
				5497	{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
				5498	{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
				5499	{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
				5500	{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
				5501	{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
				5502	} },
				5503	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
				5504	{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
				5505	{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
				5506	{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
				5507	{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
				5508	{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
				5509	{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
				5510	{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
				5511	{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
				5512	} },
				5513	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
				5514	{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
				5515	{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
				5516	{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
				5517	{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
				5518	{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	5519	{ RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
				5520	{ RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5521	} },
				5522	{ },
				5523	};
				5524
Geert Uytterhoeven	e2aad84	2017-09-29 14:15:06 +0200	[diff] [blame]	5525	enum ioctrl_regs {
				5526	POCCTRL,
				5527	};
				5528
				5529	static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
				5530	[POCCTRL] = { 0xe6060380, },
				5531	{ /* sentinel */ },
				5532	};
				5533
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5534	static int r8a7795_pin_to_pocctrl(struct sh_pfc pfc, unsigned int pin, u32 pocctrl)
				5535	{
				5536	int bit = -EINVAL;
				5537
Geert Uytterhoeven	e2aad84	2017-09-29 14:15:06 +0200	[diff] [blame]	5538	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5539
				5540	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
				5541	bit = pin & 0x1f;
				5542
				5543	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
				5544	bit = (pin & 0x1f) + 12;
				5545
				5546	return bit;
				5547	}
				5548
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5549	static const struct pinmux_bias_reg pinmux_bias_regs[] = {
				5550	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
				5551	[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
				5552	[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
				5553	[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
				5554	[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
				5555	[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
				5556	[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
				5557	[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
				5558	[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
				5559	[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
				5560	[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
				5561	[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
				5562	[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
				5563	[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
				5564	[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
				5565	[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
				5566	[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
				5567	[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
				5568	[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
				5569	[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
				5570	[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
				5571	[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
				5572	[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
				5573	[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
				5574	[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
				5575	[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
				5576	[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
				5577	[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
				5578	[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
				5579	[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
				5580	[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
				5581	[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
				5582	[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
				5583	} },
				5584	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
				5585	[ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
				5586	[ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
				5587	[ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
				5588	[ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
				5589	[ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
				5590	[ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
				5591	[ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
				5592	[ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
				5593	[ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
				5594	[ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
				5595	[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
				5596	[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
				5597	[12] = RCAR_GP_PIN(1, 0), /* A0 */
				5598	[13] = RCAR_GP_PIN(1, 1), /* A1 */
				5599	[14] = RCAR_GP_PIN(1, 2), /* A2 */
				5600	[15] = RCAR_GP_PIN(1, 3), /* A3 */
				5601	[16] = RCAR_GP_PIN(1, 4), /* A4 */
				5602	[17] = RCAR_GP_PIN(1, 5), /* A5 */
				5603	[18] = RCAR_GP_PIN(1, 6), /* A6 */
				5604	[19] = RCAR_GP_PIN(1, 7), /* A7 */
				5605	[20] = RCAR_GP_PIN(1, 8), /* A8 */
				5606	[21] = RCAR_GP_PIN(1, 9), /* A9 */
				5607	[22] = RCAR_GP_PIN(1, 10), /* A10 */
				5608	[23] = RCAR_GP_PIN(1, 11), /* A11 */
				5609	[24] = RCAR_GP_PIN(1, 12), /* A12 */
				5610	[25] = RCAR_GP_PIN(1, 13), /* A13 */
				5611	[26] = RCAR_GP_PIN(1, 14), /* A14 */
				5612	[27] = RCAR_GP_PIN(1, 15), /* A15 */
				5613	[28] = RCAR_GP_PIN(1, 16), /* A16 */
				5614	[29] = RCAR_GP_PIN(1, 17), /* A17 */
				5615	[30] = RCAR_GP_PIN(1, 18), /* A18 */
				5616	[31] = RCAR_GP_PIN(1, 19), /* A19 */
				5617	} },
				5618	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
Takeshi Kihara	82d2de5	2017-11-16 12:14:51 +0900	[diff] [blame]	5619	[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5620	[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
				5621	[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
				5622	[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
				5623	[ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
				5624	[ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
				5625	[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
				5626	[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
				5627	[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
				5628	[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
				5629	[10] = RCAR_GP_PIN(0, 0), /* D0 */
				5630	[11] = RCAR_GP_PIN(0, 1), /* D1 */
				5631	[12] = RCAR_GP_PIN(0, 2), /* D2 */
				5632	[13] = RCAR_GP_PIN(0, 3), /* D3 */
				5633	[14] = RCAR_GP_PIN(0, 4), /* D4 */
				5634	[15] = RCAR_GP_PIN(0, 5), /* D5 */
				5635	[16] = RCAR_GP_PIN(0, 6), /* D6 */
				5636	[17] = RCAR_GP_PIN(0, 7), /* D7 */
				5637	[18] = RCAR_GP_PIN(0, 8), /* D8 */
				5638	[19] = RCAR_GP_PIN(0, 9), /* D9 */
				5639	[20] = RCAR_GP_PIN(0, 10), /* D10 */
				5640	[21] = RCAR_GP_PIN(0, 11), /* D11 */
				5641	[22] = RCAR_GP_PIN(0, 12), /* D12 */
				5642	[23] = RCAR_GP_PIN(0, 13), /* D13 */
				5643	[24] = RCAR_GP_PIN(0, 14), /* D14 */
				5644	[25] = RCAR_GP_PIN(0, 15), /* D15 */
				5645	[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
				5646	[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
				5647	[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
				5648	[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
				5649	[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
				5650	[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
				5651	} },
				5652	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
				5653	[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
				5654	[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
				5655	[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
				5656	[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
				5657	[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
				5658	[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
				5659	[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
				5660	[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
				5661	[ 8] = PIN_NONE,
				5662	[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
				5663	[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
				5664	[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
				5665	[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
				5666	[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
				5667	[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
				5668	[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
				5669	[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
				5670	[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
				5671	[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
				5672	[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
				5673	[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
				5674	[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
				5675	[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
				5676	[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
				5677	[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
				5678	[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
				5679	[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
				5680	[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
				5681	[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
				5682	[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
				5683	[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
				5684	[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
				5685	} },
				5686	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
				5687	[ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
				5688	[ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
				5689	[ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
				5690	[ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
				5691	[ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
				5692	[ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
				5693	[ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
				5694	[ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
				5695	[ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
				5696	[ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
				5697	[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
				5698	[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
				5699	[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
				5700	[13] = RCAR_GP_PIN(5, 1), /* RX0 */
				5701	[14] = RCAR_GP_PIN(5, 2), /* TX0 */
				5702	[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	5703	[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5704	[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
				5705	[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
				5706	[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
Takeshi Kihara	8714a9c	2017-11-16 23:58:40 +0900	[diff] [blame]	5707	[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5708	[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
				5709	[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
				5710	[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
				5711	[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
				5712	[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
				5713	[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
				5714	[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
				5715	[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
				5716	[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
				5717	[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
				5718	[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
				5719	} },
				5720	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
				5721	[ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
				5722	[ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
				5723	[ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
				5724	[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
				5725	[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
				5726	[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
				5727	[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
				5728	[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
				5729	[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
				5730	[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
				5731	[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
				5732	[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
				5733	[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
				5734	[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
				5735	[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
				5736	[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
				5737	[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
				5738	[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
				5739	[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
				5740	[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
				5741	[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
				5742	[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
				5743	[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
				5744	[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
				5745	[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
				5746	[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
				5747	[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
				5748	[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
				5749	[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
				5750	[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
				5751	[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
				5752	[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
				5753	} },
				5754	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
				5755	[ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
				5756	[ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
				5757	[ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
				5758	[ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
				5759	[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
				5760	[ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
				5761	[ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
				5762	[ 7] = PIN_NONE,
				5763	[ 8] = PIN_NONE,
				5764	[ 9] = PIN_NONE,
				5765	[10] = PIN_NONE,
				5766	[11] = PIN_NONE,
				5767	[12] = PIN_NONE,
				5768	[13] = PIN_NONE,
				5769	[14] = PIN_NONE,
				5770	[15] = PIN_NONE,
				5771	[16] = PIN_NONE,
				5772	[17] = PIN_NONE,
				5773	[18] = PIN_NONE,
				5774	[19] = PIN_NONE,
				5775	[20] = PIN_NONE,
				5776	[21] = PIN_NONE,
				5777	[22] = PIN_NONE,
				5778	[23] = PIN_NONE,
				5779	[24] = PIN_NONE,
				5780	[25] = PIN_NONE,
				5781	[26] = PIN_NONE,
				5782	[27] = PIN_NONE,
				5783	[28] = PIN_NONE,
				5784	[29] = PIN_NONE,
				5785	[30] = PIN_NONE,
				5786	[31] = PIN_NONE,
				5787	} },
				5788	{ /* sentinel */ },
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5789	};
				5790
				5791	static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
				5792	unsigned int pin)
				5793	{
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5794	const struct pinmux_bias_reg *reg;
				5795	unsigned int bit;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5796
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5797	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
				5798	if (!reg)
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5799	return PIN_CONFIG_BIAS_DISABLE;
				5800
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5801	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5802	return PIN_CONFIG_BIAS_DISABLE;
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5803	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Niklas Söderlund	42831cf	2016-11-12 17:04:26 +0100	[diff] [blame]	5804	return PIN_CONFIG_BIAS_PULL_UP;
				5805	else
				5806	return PIN_CONFIG_BIAS_PULL_DOWN;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5807	}
				5808
				5809	static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
				5810	unsigned int bias)
				5811	{
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5812	const struct pinmux_bias_reg *reg;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5813	u32 enable, updown;
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5814	unsigned int bit;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5815
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5816	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
				5817	if (!reg)
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5818	return;
				5819
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5820	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5821	if (bias != PIN_CONFIG_BIAS_DISABLE)
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5822	enable \|= BIT(bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5823
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5824	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5825	if (bias == PIN_CONFIG_BIAS_PULL_UP)
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5826	updown \|= BIT(bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5827
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5828	sh_pfc_write(pfc, reg->pud, updown);
				5829	sh_pfc_write(pfc, reg->puen, enable);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5830	}
				5831
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5832	static const struct soc_device_attribute r8a7795es1[] = {
				5833	{ .soc_id = "r8a7795", .revision = "ES1.*" },
				5834	{ /* sentinel */ }
				5835	};
				5836
				5837	static int r8a7795_pinmux_init(struct sh_pfc *pfc)
				5838	{
				5839	if (soc_device_match(r8a7795es1))
				5840	pfc->info = &r8a7795es1_pinmux_info;
				5841
				5842	return 0;
				5843	}
				5844
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5845	static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5846	.init = r8a7795_pinmux_init,
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5847	.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5848	.get_bias = r8a7795_pinmux_get_bias,
				5849	.set_bias = r8a7795_pinmux_set_bias,
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5850	};
				5851
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5852	const struct sh_pfc_soc_info r8a7795_pinmux_info = {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5853	.name = "r8a77951_pfc",
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5854	.ops = &r8a7795_pinmux_ops,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5855	.unlock_reg = 0xe6060000, /* PMMR */
				5856
				5857	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
				5858
				5859	.pins = pinmux_pins,
				5860	.nr_pins = ARRAY_SIZE(pinmux_pins),
				5861	.groups = pinmux_groups,
				5862	.nr_groups = ARRAY_SIZE(pinmux_groups),
				5863	.functions = pinmux_functions,
				5864	.nr_functions = ARRAY_SIZE(pinmux_functions),
				5865
				5866	.cfg_regs = pinmux_config_regs,
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5867	.drive_regs = pinmux_drive_regs,
Geert Uytterhoeven	6f4b74f	2017-09-29 14:13:35 +0200	[diff] [blame]	5868	.bias_regs = pinmux_bias_regs,
Geert Uytterhoeven	e2aad84	2017-09-29 14:15:06 +0200	[diff] [blame]	5869	.ioctrl_regs = pinmux_ioctrl_regs,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5870
Geert Uytterhoeven	b8b47d6	2015-09-21 16:27:23 +0200	[diff] [blame]	5871	.pinmux_data = pinmux_data,
				5872	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5873	};