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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 68e6389200120b811cd48bed7621860e1bb4bce8 / . / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
blob: c31881ba4f8de9c7e9a608c957332344be121c39 [file] [log] [blame]
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1/*
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2 * R8A7795 ES2.0+ processor support - PFC hardware block.
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]3 *
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]12#include <linux/sys_soc.h>
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]13
14#include "core.h"
15#include "sh_pfc.h"
16
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]21#define CPU_ALL_PORT(fn, sfx) \
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]146#define GPSR5_22 FM(MSIOF0_RXD)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]148#define GPSR5_20 FM(MSIOF0_TXD)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]151#define GPSR5_17 FM(MSIOF0_SCK)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]169
170/* GPSR6 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]171#define GPSR6_31 F_(USB3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]283#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]307
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]309#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]342#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]344#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
365#define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]366
367#define PINMUX_GPSR \
368\
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402#define PINMUX_IPSR \
403\
404FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412\
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421\
422FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430\
431FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439\
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]440FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]448
449/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]450#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]451#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]455#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
Geert Uytterhoevenfd1aa742015-11-09 09:56:21 +0100[diff] [blame]483#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
504#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
505#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]506#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]508#define PINMUX_MOD_SELS \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]509\
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]510MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
511 MOD_SEL2_30 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]512 MOD_SEL1_29_28_27 MOD_SEL2_29 \
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]513MOD_SEL0_28_27 MOD_SEL2_28_27 \
514MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]516MOD_SEL0_23 MOD_SEL1_23_22_21 \
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]517MOD_SEL0_22 MOD_SEL2_22 \
518MOD_SEL0_21 MOD_SEL2_21 \
519MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
521MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
522 MOD_SEL2_17 \
523MOD_SEL0_16 MOD_SEL1_16 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]524 MOD_SEL1_15_14 \
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]525MOD_SEL0_14_13 \
526 MOD_SEL1_13 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]527MOD_SEL0_12 MOD_SEL1_12 \
528MOD_SEL0_11 MOD_SEL1_11 \
529MOD_SEL0_10 MOD_SEL1_10 \
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]530MOD_SEL0_9_8 MOD_SEL1_9 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]531MOD_SEL0_7_6 \
532 MOD_SEL1_6 \
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]533MOD_SEL0_5 MOD_SEL1_5 \
534MOD_SEL0_4_3 MOD_SEL1_4 \
535 MOD_SEL1_3 \
536 MOD_SEL1_2 \
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]537 MOD_SEL1_1 \
538 MOD_SEL1_0 MOD_SEL2_0
539
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]540/*
541 * These pins are not able to be muxed but have other properties
542 * that can be set, such as drive-strength or pull-up/pull-down enable.
543 */
544#define PINMUX_STATIC \
545 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
546 FM(QSPI0_IO2) FM(QSPI0_IO3) \
547 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
548 FM(QSPI1_IO2) FM(QSPI1_IO3) \
549 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
550 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
551 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
552 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
553 FM(CLKOUT) FM(PRESETOUT) \
554 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]555 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]556
557enum {
558 PINMUX_RESERVED = 0,
559
560 PINMUX_DATA_BEGIN,
561 GP_ALL(DATA),
562 PINMUX_DATA_END,
563
564#define F_(x, y)
565#define FM(x) FN_##x,
566 PINMUX_FUNCTION_BEGIN,
567 GP_ALL(FN),
568 PINMUX_GPSR
569 PINMUX_IPSR
570 PINMUX_MOD_SELS
571 PINMUX_FUNCTION_END,
572#undef F_
573#undef FM
574
575#define F_(x, y)
576#define FM(x) x##_MARK,
577 PINMUX_MARK_BEGIN,
578 PINMUX_GPSR
579 PINMUX_IPSR
580 PINMUX_MOD_SELS
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]581 PINMUX_STATIC
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]582 PINMUX_MARK_END,
583#undef F_
584#undef FM
585};
586
587static const u16 pinmux_data[] = {
588 PINMUX_DATA_GP_ALL(),
589
Geert Uytterhoeven8d4df572015-09-02 20:37:55 +0200[diff] [blame]590 PINMUX_SINGLE(AVS1),
591 PINMUX_SINGLE(AVS2),
592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
Kuninori Morimotod07640f2016-06-21 02:46:55 +0000[diff] [blame]594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
Geert Uytterhoeven8d4df572015-09-02 20:37:55 +0200[diff] [blame]597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
Geert Uytterhoeven8d4df572015-09-02 20:37:55 +0200[diff] [blame]600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]604 /* IPSR0 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
628
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]636
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]644
645 /* IPSR1 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]652
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, A25),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]660
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, A24),
664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]668
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
671 PINMUX_IPSR_GPSR(IP1_15_12, A23),
672 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]673 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]675 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
676 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]677
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]678 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
679 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP1_19_16, A22),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]685 PINMUX_IPSR_GPSR(IP1_23_20, A21),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]686 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]691 PINMUX_IPSR_GPSR(IP1_27_24, A20),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]692 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
693 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
694
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]695 PINMUX_IPSR_GPSR(IP1_31_28, A0),
696 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]697 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]698 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
699 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]700 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
701
702 /* IPSR2 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]703 PINMUX_IPSR_GPSR(IP2_3_0, A1),
704 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]705 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]706 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
707 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]708 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
709
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]710 PINMUX_IPSR_GPSR(IP2_7_4, A2),
711 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]712 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]713 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
714 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]715 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
716
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]717 PINMUX_IPSR_GPSR(IP2_11_8, A3),
718 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]719 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]720 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
721 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]722 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
723
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]724 PINMUX_IPSR_GPSR(IP2_15_12, A4),
725 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]726 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]727 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]730
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]731 PINMUX_IPSR_GPSR(IP2_19_16, A5),
732 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]733 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
734 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]735 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]738
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]739 PINMUX_IPSR_GPSR(IP2_23_20, A6),
740 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]741 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]743 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]746
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]747 PINMUX_IPSR_GPSR(IP2_27_24, A7),
748 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]749 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]751 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]754
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]755 PINMUX_IPSR_GPSR(IP2_31_28, A8),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]756 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
762
763 /* IPSR3 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]764 PINMUX_IPSR_GPSR(IP3_3_0, A9),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]765 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]767 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]768
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]769 PINMUX_IPSR_GPSR(IP3_7_4, A10),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]770 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]772 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]773
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]774 PINMUX_IPSR_GPSR(IP3_11_8, A11),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]775 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]778 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
779 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]780 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
783
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]784 PINMUX_IPSR_GPSR(IP3_15_12, A12),
785 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]786 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]788 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
789 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]790
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]791 PINMUX_IPSR_GPSR(IP3_19_16, A13),
792 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]793 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]795 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
796 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]797
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]798 PINMUX_IPSR_GPSR(IP3_23_20, A14),
799 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]800 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]801 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
802 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
803 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]804
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]805 PINMUX_IPSR_GPSR(IP3_27_24, A15),
806 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]807 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]808 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
809 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
810 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]811
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]812 PINMUX_IPSR_GPSR(IP3_31_28, A16),
813 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
814 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
815 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]816
817 /* IPSR4 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]818 PINMUX_IPSR_GPSR(IP4_3_0, A17),
819 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
820 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]822
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]823 PINMUX_IPSR_GPSR(IP4_7_4, A18),
824 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
825 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
826 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]827
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]828 PINMUX_IPSR_GPSR(IP4_11_8, A19),
829 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
830 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
831 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]832
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]835
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
839
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]840 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
841 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]842 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]843 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
844 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
846 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]847 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
848
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]849 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]850 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
855
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]856 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]857 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
862
863 /* IPSR5 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]864 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]865 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]866 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
867 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]868 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]869 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]870 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
871
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]872 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]873 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]874 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
875 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]876 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]877 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
878 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]879 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
880
881 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]882 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
883 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]885
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]886 PINMUX_IPSR_GPSR(IP5_15_12, D0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]887 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]889 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]891
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]892 PINMUX_IPSR_GPSR(IP5_19_16, D1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]893 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]895 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]897
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]898 PINMUX_IPSR_GPSR(IP5_23_20, D2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]899 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]900 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]902
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]903 PINMUX_IPSR_GPSR(IP5_27_24, D3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]904 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]905 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]907
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]908 PINMUX_IPSR_GPSR(IP5_31_28, D4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]909 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]910 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]912
913 /* IPSR6 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]914 PINMUX_IPSR_GPSR(IP6_3_0, D5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]915 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]916 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]918
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]919 PINMUX_IPSR_GPSR(IP6_7_4, D6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]920 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]921 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]923
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]924 PINMUX_IPSR_GPSR(IP6_11_8, D7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]925 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]926 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]928
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]929 PINMUX_IPSR_GPSR(IP6_15_12, D8),
930 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]931 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]934 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]935
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]936 PINMUX_IPSR_GPSR(IP6_19_16, D9),
937 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]938 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]940 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]941
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]942 PINMUX_IPSR_GPSR(IP6_23_20, D10),
943 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]944 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
947 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]948 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]949
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]950 PINMUX_IPSR_GPSR(IP6_27_24, D11),
951 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]952 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
954 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
955 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]956 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]957
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]958 PINMUX_IPSR_GPSR(IP6_31_28, D12),
959 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]960 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]963 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]964
965 /* IPSR7 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]966 PINMUX_IPSR_GPSR(IP7_3_0, D13),
967 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]968 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
969 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
970 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]971 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]972
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]973 PINMUX_IPSR_GPSR(IP7_7_4, D14),
974 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]975 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]978 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]979 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
980
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]981 PINMUX_IPSR_GPSR(IP7_11_8, D15),
982 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]983 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
984 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
985 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
988
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]989 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]990
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
994
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]995 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]996 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
998
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]999 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1000 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1003
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1004 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1005 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1008
1009 /* IPSR8 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1010 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1011 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1014
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1015 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1016 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1017 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1018 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1019
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1020 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1021 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1023
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1029
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1036
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1043
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1050
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1057
1058 /* IPSR9 */
Geert Uytterhoevene01678e2015-11-30 13:34:47 +0100[diff] [blame]1059 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1060 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1061
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1062 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1063 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1064
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1065 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1066 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1067
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1068 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1069 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1070
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1071 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1072 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1073
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1074 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1075 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1076
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1077 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1078 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1079 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1080
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1081 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1082 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1083
1084 /* IPSR10 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1085 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1086 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1087
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1088 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1089 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1090
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1091 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1092 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1093
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1094 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1095 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1096
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1097 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1098 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1099
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1100 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1103
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1104 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1107
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1111
1112 /* IPSR11 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1114 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1115 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1116
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1117 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1118 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1119
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1120 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1122 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1123
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1124 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1126
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1127 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1128 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1129
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1130 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1131 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1132
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1133 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1141 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1143
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1144 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1145 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1149
1150 /* IPSR12 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1151 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1152 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1155 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1156
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1157 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1162 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1163 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1164 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1165
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1166 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1167 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1170 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1171 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1173 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1174
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1175 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1180
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1181 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1186
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1187 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1194
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1195 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1196 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1197 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1202
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1209 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1210
1211 /* IPSR13 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1212 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1217 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1218
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1219 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1221 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1223 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1224 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1225
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1226 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1229 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1230 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1234
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1235 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1236 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1241
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1242 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1243 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1245 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1248
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1249 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1253 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1256 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1257
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1258 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1259 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1260 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1262 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1263 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1265
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1266 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1267 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1268 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1269 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1270
1271 /* IPSR14 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1280
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1289
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1290 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1291 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1292 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1293
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1294 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1295 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1296 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1298
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1299 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1300 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1301 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1302
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1303 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1304 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1305
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1306 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1307 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1308
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1309 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1310 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1311
1312 /* IPSR15 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1313 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1314
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1316 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1317
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]1318 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1319 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1321
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]1322 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1323 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1325 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1326
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1327 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1328 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1334
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1335 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1336 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1342
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1343 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1344 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1350
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1351 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1352 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1358
1359 /* IPSR16 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1360 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1361 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1362 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1363
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1364 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1365 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1366 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1367
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1368 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1369 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1370 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1371
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1372 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1373 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1379
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1380 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1381 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1387
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1388 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1389 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1396
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1397 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1398 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1404
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1410 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1412 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1413
1414 /* IPSR17 */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1417
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1423
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1429 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1431
1432 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1433 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1434 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1435 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1440 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1447 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1448
1449 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1450 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1452 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1453 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1458
1459 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1470
1471 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1472 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1473 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1474 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1480
1481 /* IPSR18 */
1482 PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN),
1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1491
1492 PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC),
1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1498 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]1501
1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1512};
1513
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]1514/*
1515 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1522static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(),
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]1524
1525 /*
1526 * Pins not associated with a GPIO port.
1527 *
1528 * The pin positions are different between different r8a7795
1529 * packages, all that is needed for the pfc driver is a unique
1530 * number for each pin. To this end use the pin layout from
1531 * R-Car H3SiP to calculate a unique number for each pin.
1532 */
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]1533 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1577};
1578
Geert Uytterhoevene7ad4d32017-03-13 11:28:33 +0100[diff] [blame]1579/* - SCIF0 ------------------------------------------------------------------ */
1580static const unsigned int scif0_data_pins[] = {
1581 /* RX, TX */
1582 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1583};
1584static const unsigned int scif0_data_mux[] = {
1585 RX0_MARK, TX0_MARK,
1586};
1587static const unsigned int scif0_clk_pins[] = {
1588 /* SCK */
1589 RCAR_GP_PIN(5, 0),
1590};
1591static const unsigned int scif0_clk_mux[] = {
1592 SCK0_MARK,
1593};
1594static const unsigned int scif0_ctrl_pins[] = {
1595 /* RTS, CTS */
1596 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1597};
1598static const unsigned int scif0_ctrl_mux[] = {
1599 RTS0_N_TANS_MARK, CTS0_N_MARK,
1600};
1601/* - SCIF1 ------------------------------------------------------------------ */
1602static const unsigned int scif1_data_a_pins[] = {
1603 /* RX, TX */
1604 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1605};
1606static const unsigned int scif1_data_a_mux[] = {
1607 RX1_A_MARK, TX1_A_MARK,
1608};
1609static const unsigned int scif1_clk_pins[] = {
1610 /* SCK */
1611 RCAR_GP_PIN(6, 21),
1612};
1613static const unsigned int scif1_clk_mux[] = {
1614 SCK1_MARK,
1615};
1616static const unsigned int scif1_ctrl_pins[] = {
1617 /* RTS, CTS */
1618 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1619};
1620static const unsigned int scif1_ctrl_mux[] = {
1621 RTS1_N_TANS_MARK, CTS1_N_MARK,
1622};
1623
1624static const unsigned int scif1_data_b_pins[] = {
1625 /* RX, TX */
1626 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1627};
1628static const unsigned int scif1_data_b_mux[] = {
1629 RX1_B_MARK, TX1_B_MARK,
1630};
1631/* - SCIF2 ------------------------------------------------------------------ */
1632static const unsigned int scif2_data_a_pins[] = {
1633 /* RX, TX */
1634 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1635};
1636static const unsigned int scif2_data_a_mux[] = {
1637 RX2_A_MARK, TX2_A_MARK,
1638};
1639static const unsigned int scif2_clk_pins[] = {
1640 /* SCK */
1641 RCAR_GP_PIN(5, 9),
1642};
1643static const unsigned int scif2_clk_mux[] = {
1644 SCK2_MARK,
1645};
1646static const unsigned int scif2_data_b_pins[] = {
1647 /* RX, TX */
1648 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1649};
1650static const unsigned int scif2_data_b_mux[] = {
1651 RX2_B_MARK, TX2_B_MARK,
1652};
1653/* - SCIF3 ------------------------------------------------------------------ */
1654static const unsigned int scif3_data_a_pins[] = {
1655 /* RX, TX */
1656 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1657};
1658static const unsigned int scif3_data_a_mux[] = {
1659 RX3_A_MARK, TX3_A_MARK,
1660};
1661static const unsigned int scif3_clk_pins[] = {
1662 /* SCK */
1663 RCAR_GP_PIN(1, 22),
1664};
1665static const unsigned int scif3_clk_mux[] = {
1666 SCK3_MARK,
1667};
1668static const unsigned int scif3_ctrl_pins[] = {
1669 /* RTS, CTS */
1670 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1671};
1672static const unsigned int scif3_ctrl_mux[] = {
1673 RTS3_N_TANS_MARK, CTS3_N_MARK,
1674};
1675static const unsigned int scif3_data_b_pins[] = {
1676 /* RX, TX */
1677 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1678};
1679static const unsigned int scif3_data_b_mux[] = {
1680 RX3_B_MARK, TX3_B_MARK,
1681};
1682/* - SCIF4 ------------------------------------------------------------------ */
1683static const unsigned int scif4_data_a_pins[] = {
1684 /* RX, TX */
1685 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1686};
1687static const unsigned int scif4_data_a_mux[] = {
1688 RX4_A_MARK, TX4_A_MARK,
1689};
1690static const unsigned int scif4_clk_a_pins[] = {
1691 /* SCK */
1692 RCAR_GP_PIN(2, 10),
1693};
1694static const unsigned int scif4_clk_a_mux[] = {
1695 SCK4_A_MARK,
1696};
1697static const unsigned int scif4_ctrl_a_pins[] = {
1698 /* RTS, CTS */
1699 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1700};
1701static const unsigned int scif4_ctrl_a_mux[] = {
1702 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1703};
1704static const unsigned int scif4_data_b_pins[] = {
1705 /* RX, TX */
1706 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1707};
1708static const unsigned int scif4_data_b_mux[] = {
1709 RX4_B_MARK, TX4_B_MARK,
1710};
1711static const unsigned int scif4_clk_b_pins[] = {
1712 /* SCK */
1713 RCAR_GP_PIN(1, 5),
1714};
1715static const unsigned int scif4_clk_b_mux[] = {
1716 SCK4_B_MARK,
1717};
1718static const unsigned int scif4_ctrl_b_pins[] = {
1719 /* RTS, CTS */
1720 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1721};
1722static const unsigned int scif4_ctrl_b_mux[] = {
1723 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1724};
1725static const unsigned int scif4_data_c_pins[] = {
1726 /* RX, TX */
1727 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1728};
1729static const unsigned int scif4_data_c_mux[] = {
1730 RX4_C_MARK, TX4_C_MARK,
1731};
1732static const unsigned int scif4_clk_c_pins[] = {
1733 /* SCK */
1734 RCAR_GP_PIN(0, 8),
1735};
1736static const unsigned int scif4_clk_c_mux[] = {
1737 SCK4_C_MARK,
1738};
1739static const unsigned int scif4_ctrl_c_pins[] = {
1740 /* RTS, CTS */
1741 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1742};
1743static const unsigned int scif4_ctrl_c_mux[] = {
1744 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1745};
1746/* - SCIF5 ------------------------------------------------------------------ */
1747static const unsigned int scif5_data_a_pins[] = {
1748 /* RX, TX */
1749 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1750};
1751static const unsigned int scif5_data_a_mux[] = {
1752 RX5_A_MARK, TX5_A_MARK,
1753};
1754static const unsigned int scif5_clk_a_pins[] = {
1755 /* SCK */
1756 RCAR_GP_PIN(6, 21),
1757};
1758static const unsigned int scif5_clk_a_mux[] = {
1759 SCK5_A_MARK,
1760};
1761static const unsigned int scif5_data_b_pins[] = {
1762 /* RX, TX */
1763 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
1764};
1765static const unsigned int scif5_data_b_mux[] = {
1766 RX5_B_MARK, TX5_B_MARK,
1767};
1768static const unsigned int scif5_clk_b_pins[] = {
1769 /* SCK */
1770 RCAR_GP_PIN(5, 0),
1771};
1772static const unsigned int scif5_clk_b_mux[] = {
1773 SCK5_B_MARK,
1774};
1775
Geert Uytterhoevend14a39e2017-03-13 11:28:39 +0100[diff] [blame]1776/* - SCIF Clock ------------------------------------------------------------- */
1777static const unsigned int scif_clk_a_pins[] = {
1778 /* SCIF_CLK */
1779 RCAR_GP_PIN(6, 23),
1780};
1781static const unsigned int scif_clk_a_mux[] = {
1782 SCIF_CLK_A_MARK,
1783};
1784static const unsigned int scif_clk_b_pins[] = {
1785 /* SCIF_CLK */
1786 RCAR_GP_PIN(5, 9),
1787};
1788static const unsigned int scif_clk_b_mux[] = {
1789 SCIF_CLK_B_MARK,
1790};
1791
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1792static const struct sh_pfc_pin_group pinmux_groups[] = {
Geert Uytterhoevene7ad4d32017-03-13 11:28:33 +0100[diff] [blame]1793 SH_PFC_PIN_GROUP(scif0_data),
1794 SH_PFC_PIN_GROUP(scif0_clk),
1795 SH_PFC_PIN_GROUP(scif0_ctrl),
1796 SH_PFC_PIN_GROUP(scif1_data_a),
1797 SH_PFC_PIN_GROUP(scif1_clk),
1798 SH_PFC_PIN_GROUP(scif1_ctrl),
1799 SH_PFC_PIN_GROUP(scif1_data_b),
1800 SH_PFC_PIN_GROUP(scif2_data_a),
1801 SH_PFC_PIN_GROUP(scif2_clk),
1802 SH_PFC_PIN_GROUP(scif2_data_b),
1803 SH_PFC_PIN_GROUP(scif3_data_a),
1804 SH_PFC_PIN_GROUP(scif3_clk),
1805 SH_PFC_PIN_GROUP(scif3_ctrl),
1806 SH_PFC_PIN_GROUP(scif3_data_b),
1807 SH_PFC_PIN_GROUP(scif4_data_a),
1808 SH_PFC_PIN_GROUP(scif4_clk_a),
1809 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1810 SH_PFC_PIN_GROUP(scif4_data_b),
1811 SH_PFC_PIN_GROUP(scif4_clk_b),
1812 SH_PFC_PIN_GROUP(scif4_ctrl_b),
1813 SH_PFC_PIN_GROUP(scif4_data_c),
1814 SH_PFC_PIN_GROUP(scif4_clk_c),
1815 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1816 SH_PFC_PIN_GROUP(scif5_data_a),
1817 SH_PFC_PIN_GROUP(scif5_clk_a),
1818 SH_PFC_PIN_GROUP(scif5_data_b),
1819 SH_PFC_PIN_GROUP(scif5_clk_b),
Geert Uytterhoevend14a39e2017-03-13 11:28:39 +0100[diff] [blame]1820 SH_PFC_PIN_GROUP(scif_clk_a),
1821 SH_PFC_PIN_GROUP(scif_clk_b),
Geert Uytterhoevene7ad4d32017-03-13 11:28:33 +0100[diff] [blame]1822};
1823
1824static const char * const scif0_groups[] = {
1825 "scif0_data",
1826 "scif0_clk",
1827 "scif0_ctrl",
1828};
1829
1830static const char * const scif1_groups[] = {
1831 "scif1_data_a",
1832 "scif1_clk",
1833 "scif1_ctrl",
1834 "scif1_data_b",
1835};
1836
1837static const char * const scif2_groups[] = {
1838 "scif2_data_a",
1839 "scif2_clk",
1840 "scif2_data_b",
1841};
1842
1843static const char * const scif3_groups[] = {
1844 "scif3_data_a",
1845 "scif3_clk",
1846 "scif3_ctrl",
1847 "scif3_data_b",
1848};
1849
1850static const char * const scif4_groups[] = {
1851 "scif4_data_a",
1852 "scif4_clk_a",
1853 "scif4_ctrl_a",
1854 "scif4_data_b",
1855 "scif4_clk_b",
1856 "scif4_ctrl_b",
1857 "scif4_data_c",
1858 "scif4_clk_c",
1859 "scif4_ctrl_c",
1860};
1861
1862static const char * const scif5_groups[] = {
1863 "scif5_data_a",
1864 "scif5_clk_a",
1865 "scif5_data_b",
1866 "scif5_clk_b",
Takeshi Kihara76250a62016-02-02 19:18:49 +0900[diff] [blame]1867};
1868
Geert Uytterhoevend14a39e2017-03-13 11:28:39 +0100[diff] [blame]1869static const char * const scif_clk_groups[] = {
1870 "scif_clk_a",
1871 "scif_clk_b",
1872};
1873
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1874static const struct sh_pfc_function pinmux_functions[] = {
Geert Uytterhoevene7ad4d32017-03-13 11:28:33 +0100[diff] [blame]1875 SH_PFC_FUNCTION(scif0),
1876 SH_PFC_FUNCTION(scif1),
1877 SH_PFC_FUNCTION(scif2),
1878 SH_PFC_FUNCTION(scif3),
1879 SH_PFC_FUNCTION(scif4),
1880 SH_PFC_FUNCTION(scif5),
Geert Uytterhoevend14a39e2017-03-13 11:28:39 +0100[diff] [blame]1881 SH_PFC_FUNCTION(scif_clk),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]1882};
1883
1884static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1885#define F_(x, y) FN_##y
1886#define FM(x) FN_##x
1887 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1888 0, 0,
1889 0, 0,
1890 0, 0,
1891 0, 0,
1892 0, 0,
1893 0, 0,
1894 0, 0,
1895 0, 0,
1896 0, 0,
1897 0, 0,
1898 0, 0,
1899 0, 0,
1900 0, 0,
1901 0, 0,
1902 0, 0,
1903 0, 0,
1904 GP_0_15_FN, GPSR0_15,
1905 GP_0_14_FN, GPSR0_14,
1906 GP_0_13_FN, GPSR0_13,
1907 GP_0_12_FN, GPSR0_12,
1908 GP_0_11_FN, GPSR0_11,
1909 GP_0_10_FN, GPSR0_10,
1910 GP_0_9_FN, GPSR0_9,
1911 GP_0_8_FN, GPSR0_8,
1912 GP_0_7_FN, GPSR0_7,
1913 GP_0_6_FN, GPSR0_6,
1914 GP_0_5_FN, GPSR0_5,
1915 GP_0_4_FN, GPSR0_4,
1916 GP_0_3_FN, GPSR0_3,
1917 GP_0_2_FN, GPSR0_2,
1918 GP_0_1_FN, GPSR0_1,
1919 GP_0_0_FN, GPSR0_0, }
1920 },
1921 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1922 0, 0,
1923 0, 0,
1924 0, 0,
1925 0, 0,
1926 GP_1_27_FN, GPSR1_27,
1927 GP_1_26_FN, GPSR1_26,
1928 GP_1_25_FN, GPSR1_25,
1929 GP_1_24_FN, GPSR1_24,
1930 GP_1_23_FN, GPSR1_23,
1931 GP_1_22_FN, GPSR1_22,
1932 GP_1_21_FN, GPSR1_21,
1933 GP_1_20_FN, GPSR1_20,
1934 GP_1_19_FN, GPSR1_19,
1935 GP_1_18_FN, GPSR1_18,
1936 GP_1_17_FN, GPSR1_17,
1937 GP_1_16_FN, GPSR1_16,
1938 GP_1_15_FN, GPSR1_15,
1939 GP_1_14_FN, GPSR1_14,
1940 GP_1_13_FN, GPSR1_13,
1941 GP_1_12_FN, GPSR1_12,
1942 GP_1_11_FN, GPSR1_11,
1943 GP_1_10_FN, GPSR1_10,
1944 GP_1_9_FN, GPSR1_9,
1945 GP_1_8_FN, GPSR1_8,
1946 GP_1_7_FN, GPSR1_7,
1947 GP_1_6_FN, GPSR1_6,
1948 GP_1_5_FN, GPSR1_5,
1949 GP_1_4_FN, GPSR1_4,
1950 GP_1_3_FN, GPSR1_3,
1951 GP_1_2_FN, GPSR1_2,
1952 GP_1_1_FN, GPSR1_1,
1953 GP_1_0_FN, GPSR1_0, }
1954 },
1955 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
1956 0, 0,
1957 0, 0,
1958 0, 0,
1959 0, 0,
1960 0, 0,
1961 0, 0,
1962 0, 0,
1963 0, 0,
1964 0, 0,
1965 0, 0,
1966 0, 0,
1967 0, 0,
1968 0, 0,
1969 0, 0,
1970 0, 0,
1971 0, 0,
1972 0, 0,
1973 GP_2_14_FN, GPSR2_14,
1974 GP_2_13_FN, GPSR2_13,
1975 GP_2_12_FN, GPSR2_12,
1976 GP_2_11_FN, GPSR2_11,
1977 GP_2_10_FN, GPSR2_10,
1978 GP_2_9_FN, GPSR2_9,
1979 GP_2_8_FN, GPSR2_8,
1980 GP_2_7_FN, GPSR2_7,
1981 GP_2_6_FN, GPSR2_6,
1982 GP_2_5_FN, GPSR2_5,
1983 GP_2_4_FN, GPSR2_4,
1984 GP_2_3_FN, GPSR2_3,
1985 GP_2_2_FN, GPSR2_2,
1986 GP_2_1_FN, GPSR2_1,
1987 GP_2_0_FN, GPSR2_0, }
1988 },
1989 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
1990 0, 0,
1991 0, 0,
1992 0, 0,
1993 0, 0,
1994 0, 0,
1995 0, 0,
1996 0, 0,
1997 0, 0,
1998 0, 0,
1999 0, 0,
2000 0, 0,
2001 0, 0,
2002 0, 0,
2003 0, 0,
2004 0, 0,
2005 0, 0,
2006 GP_3_15_FN, GPSR3_15,
2007 GP_3_14_FN, GPSR3_14,
2008 GP_3_13_FN, GPSR3_13,
2009 GP_3_12_FN, GPSR3_12,
2010 GP_3_11_FN, GPSR3_11,
2011 GP_3_10_FN, GPSR3_10,
2012 GP_3_9_FN, GPSR3_9,
2013 GP_3_8_FN, GPSR3_8,
2014 GP_3_7_FN, GPSR3_7,
2015 GP_3_6_FN, GPSR3_6,
2016 GP_3_5_FN, GPSR3_5,
2017 GP_3_4_FN, GPSR3_4,
2018 GP_3_3_FN, GPSR3_3,
2019 GP_3_2_FN, GPSR3_2,
2020 GP_3_1_FN, GPSR3_1,
2021 GP_3_0_FN, GPSR3_0, }
2022 },
2023 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2024 0, 0,
2025 0, 0,
2026 0, 0,
2027 0, 0,
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 0, 0,
2038 GP_4_17_FN, GPSR4_17,
2039 GP_4_16_FN, GPSR4_16,
2040 GP_4_15_FN, GPSR4_15,
2041 GP_4_14_FN, GPSR4_14,
2042 GP_4_13_FN, GPSR4_13,
2043 GP_4_12_FN, GPSR4_12,
2044 GP_4_11_FN, GPSR4_11,
2045 GP_4_10_FN, GPSR4_10,
2046 GP_4_9_FN, GPSR4_9,
2047 GP_4_8_FN, GPSR4_8,
2048 GP_4_7_FN, GPSR4_7,
2049 GP_4_6_FN, GPSR4_6,
2050 GP_4_5_FN, GPSR4_5,
2051 GP_4_4_FN, GPSR4_4,
2052 GP_4_3_FN, GPSR4_3,
2053 GP_4_2_FN, GPSR4_2,
2054 GP_4_1_FN, GPSR4_1,
2055 GP_4_0_FN, GPSR4_0, }
2056 },
2057 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 0, 0,
2064 GP_5_25_FN, GPSR5_25,
2065 GP_5_24_FN, GPSR5_24,
2066 GP_5_23_FN, GPSR5_23,
2067 GP_5_22_FN, GPSR5_22,
2068 GP_5_21_FN, GPSR5_21,
2069 GP_5_20_FN, GPSR5_20,
2070 GP_5_19_FN, GPSR5_19,
2071 GP_5_18_FN, GPSR5_18,
2072 GP_5_17_FN, GPSR5_17,
2073 GP_5_16_FN, GPSR5_16,
2074 GP_5_15_FN, GPSR5_15,
2075 GP_5_14_FN, GPSR5_14,
2076 GP_5_13_FN, GPSR5_13,
2077 GP_5_12_FN, GPSR5_12,
2078 GP_5_11_FN, GPSR5_11,
2079 GP_5_10_FN, GPSR5_10,
2080 GP_5_9_FN, GPSR5_9,
2081 GP_5_8_FN, GPSR5_8,
2082 GP_5_7_FN, GPSR5_7,
2083 GP_5_6_FN, GPSR5_6,
2084 GP_5_5_FN, GPSR5_5,
2085 GP_5_4_FN, GPSR5_4,
2086 GP_5_3_FN, GPSR5_3,
2087 GP_5_2_FN, GPSR5_2,
2088 GP_5_1_FN, GPSR5_1,
2089 GP_5_0_FN, GPSR5_0, }
2090 },
2091 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2092 GP_6_31_FN, GPSR6_31,
2093 GP_6_30_FN, GPSR6_30,
2094 GP_6_29_FN, GPSR6_29,
2095 GP_6_28_FN, GPSR6_28,
2096 GP_6_27_FN, GPSR6_27,
2097 GP_6_26_FN, GPSR6_26,
2098 GP_6_25_FN, GPSR6_25,
2099 GP_6_24_FN, GPSR6_24,
2100 GP_6_23_FN, GPSR6_23,
2101 GP_6_22_FN, GPSR6_22,
2102 GP_6_21_FN, GPSR6_21,
2103 GP_6_20_FN, GPSR6_20,
2104 GP_6_19_FN, GPSR6_19,
2105 GP_6_18_FN, GPSR6_18,
2106 GP_6_17_FN, GPSR6_17,
2107 GP_6_16_FN, GPSR6_16,
2108 GP_6_15_FN, GPSR6_15,
2109 GP_6_14_FN, GPSR6_14,
2110 GP_6_13_FN, GPSR6_13,
2111 GP_6_12_FN, GPSR6_12,
2112 GP_6_11_FN, GPSR6_11,
2113 GP_6_10_FN, GPSR6_10,
2114 GP_6_9_FN, GPSR6_9,
2115 GP_6_8_FN, GPSR6_8,
2116 GP_6_7_FN, GPSR6_7,
2117 GP_6_6_FN, GPSR6_6,
2118 GP_6_5_FN, GPSR6_5,
2119 GP_6_4_FN, GPSR6_4,
2120 GP_6_3_FN, GPSR6_3,
2121 GP_6_2_FN, GPSR6_2,
2122 GP_6_1_FN, GPSR6_1,
2123 GP_6_0_FN, GPSR6_0, }
2124 },
2125 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 0, 0,
2146 0, 0,
2147 0, 0,
2148 0, 0,
2149 0, 0,
2150 0, 0,
2151 0, 0,
2152 0, 0,
2153 0, 0,
2154 GP_7_3_FN, GPSR7_3,
2155 GP_7_2_FN, GPSR7_2,
2156 GP_7_1_FN, GPSR7_1,
2157 GP_7_0_FN, GPSR7_0, }
2158 },
2159#undef F_
2160#undef FM
2161
2162#define F_(x, y) x,
2163#define FM(x) FN_##x,
2164 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2165 IP0_31_28
2166 IP0_27_24
2167 IP0_23_20
2168 IP0_19_16
2169 IP0_15_12
2170 IP0_11_8
2171 IP0_7_4
2172 IP0_3_0 }
2173 },
2174 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2175 IP1_31_28
2176 IP1_27_24
2177 IP1_23_20
2178 IP1_19_16
2179 IP1_15_12
2180 IP1_11_8
2181 IP1_7_4
2182 IP1_3_0 }
2183 },
2184 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2185 IP2_31_28
2186 IP2_27_24
2187 IP2_23_20
2188 IP2_19_16
2189 IP2_15_12
2190 IP2_11_8
2191 IP2_7_4
2192 IP2_3_0 }
2193 },
2194 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2195 IP3_31_28
2196 IP3_27_24
2197 IP3_23_20
2198 IP3_19_16
2199 IP3_15_12
2200 IP3_11_8
2201 IP3_7_4
2202 IP3_3_0 }
2203 },
2204 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2205 IP4_31_28
2206 IP4_27_24
2207 IP4_23_20
2208 IP4_19_16
2209 IP4_15_12
2210 IP4_11_8
2211 IP4_7_4
2212 IP4_3_0 }
2213 },
2214 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2215 IP5_31_28
2216 IP5_27_24
2217 IP5_23_20
2218 IP5_19_16
2219 IP5_15_12
2220 IP5_11_8
2221 IP5_7_4
2222 IP5_3_0 }
2223 },
2224 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2225 IP6_31_28
2226 IP6_27_24
2227 IP6_23_20
2228 IP6_19_16
2229 IP6_15_12
2230 IP6_11_8
2231 IP6_7_4
2232 IP6_3_0 }
2233 },
2234 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2235 IP7_31_28
2236 IP7_27_24
2237 IP7_23_20
2238 IP7_19_16
2239 IP7_15_12
2240 IP7_11_8
2241 IP7_7_4
2242 IP7_3_0 }
2243 },
2244 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2245 IP8_31_28
2246 IP8_27_24
2247 IP8_23_20
2248 IP8_19_16
2249 IP8_15_12
2250 IP8_11_8
2251 IP8_7_4
2252 IP8_3_0 }
2253 },
2254 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2255 IP9_31_28
2256 IP9_27_24
2257 IP9_23_20
2258 IP9_19_16
2259 IP9_15_12
2260 IP9_11_8
2261 IP9_7_4
2262 IP9_3_0 }
2263 },
2264 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2265 IP10_31_28
2266 IP10_27_24
2267 IP10_23_20
2268 IP10_19_16
2269 IP10_15_12
2270 IP10_11_8
2271 IP10_7_4
2272 IP10_3_0 }
2273 },
2274 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2275 IP11_31_28
2276 IP11_27_24
2277 IP11_23_20
2278 IP11_19_16
2279 IP11_15_12
2280 IP11_11_8
2281 IP11_7_4
2282 IP11_3_0 }
2283 },
2284 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2285 IP12_31_28
2286 IP12_27_24
2287 IP12_23_20
2288 IP12_19_16
2289 IP12_15_12
2290 IP12_11_8
2291 IP12_7_4
2292 IP12_3_0 }
2293 },
2294 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2295 IP13_31_28
2296 IP13_27_24
2297 IP13_23_20
2298 IP13_19_16
2299 IP13_15_12
2300 IP13_11_8
2301 IP13_7_4
2302 IP13_3_0 }
2303 },
2304 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2305 IP14_31_28
2306 IP14_27_24
2307 IP14_23_20
2308 IP14_19_16
2309 IP14_15_12
2310 IP14_11_8
2311 IP14_7_4
2312 IP14_3_0 }
2313 },
2314 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2315 IP15_31_28
2316 IP15_27_24
2317 IP15_23_20
2318 IP15_19_16
2319 IP15_15_12
2320 IP15_11_8
2321 IP15_7_4
2322 IP15_3_0 }
2323 },
2324 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2325 IP16_31_28
2326 IP16_27_24
2327 IP16_23_20
2328 IP16_19_16
2329 IP16_15_12
2330 IP16_11_8
2331 IP16_7_4
2332 IP16_3_0 }
2333 },
2334 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2335 IP17_31_28
2336 IP17_27_24
2337 IP17_23_20
2338 IP17_19_16
2339 IP17_15_12
2340 IP17_11_8
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2341 IP17_7_4
2342 IP17_3_0 }
2343 },
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2344 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2345 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2346 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2347 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2348 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2349 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2350 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2351 IP18_7_4
2352 IP18_3_0 }
2353 },
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2354#undef F_
2355#undef FM
2356
2357#define F_(x, y) x,
2358#define FM(x) FN_##x,
2359 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2360 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2361 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2362 MOD_SEL0_31_30_29
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2363 MOD_SEL0_28_27
2364 MOD_SEL0_26_25_24
2365 MOD_SEL0_23
2366 MOD_SEL0_22
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2367 MOD_SEL0_21
2368 MOD_SEL0_20
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2369 MOD_SEL0_19
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2370 MOD_SEL0_18_17
2371 MOD_SEL0_16
2372 0, 0, /* RESERVED 15 */
2373 MOD_SEL0_14_13
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2374 MOD_SEL0_12
2375 MOD_SEL0_11
2376 MOD_SEL0_10
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2377 MOD_SEL0_9_8
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2378 MOD_SEL0_7_6
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2379 MOD_SEL0_5
2380 MOD_SEL0_4_3
2381 /* RESERVED 2, 1, 0 */
2382 0, 0, 0, 0, 0, 0, 0, 0 }
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2383 },
2384 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2385 2, 3, 1, 2, 3, 1, 1, 2, 1,
2386 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2387 MOD_SEL1_31_30
2388 MOD_SEL1_29_28_27
2389 MOD_SEL1_26
2390 MOD_SEL1_25_24
2391 MOD_SEL1_23_22_21
2392 MOD_SEL1_20
2393 MOD_SEL1_19
2394 MOD_SEL1_18_17
2395 MOD_SEL1_16
2396 MOD_SEL1_15_14
2397 MOD_SEL1_13
2398 MOD_SEL1_12
2399 MOD_SEL1_11
2400 MOD_SEL1_10
2401 MOD_SEL1_9
2402 0, 0, 0, 0, /* RESERVED 8, 7 */
2403 MOD_SEL1_6
2404 MOD_SEL1_5
2405 MOD_SEL1_4
2406 MOD_SEL1_3
2407 MOD_SEL1_2
2408 MOD_SEL1_1
2409 MOD_SEL1_0 }
2410 },
2411 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2412 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2413 4, 4, 4, 3, 1) {
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2414 MOD_SEL2_31
2415 MOD_SEL2_30
2416 MOD_SEL2_29
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2417 MOD_SEL2_28_27
2418 MOD_SEL2_26
2419 MOD_SEL2_25_24_23
2420 MOD_SEL2_22
2421 MOD_SEL2_21
2422 MOD_SEL2_20
2423 MOD_SEL2_19
2424 MOD_SEL2_18
2425 MOD_SEL2_17
2426 /* RESERVED 16 */
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2427 0, 0,
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2428 /* RESERVED 15, 14, 13, 12 */
2429 0, 0, 0, 0, 0, 0, 0, 0,
2430 0, 0, 0, 0, 0, 0, 0, 0,
2431 /* RESERVED 11, 10, 9, 8 */
2432 0, 0, 0, 0, 0, 0, 0, 0,
2433 0, 0, 0, 0, 0, 0, 0, 0,
2434 /* RESERVED 7, 6, 5, 4 */
2435 0, 0, 0, 0, 0, 0, 0, 0,
2436 0, 0, 0, 0, 0, 0, 0, 0,
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2437 /* RESERVED 3, 2, 1 */
2438 0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2439 MOD_SEL2_0 }
2440 },
2441 { },
2442};
2443
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2444static const struct pinmux_drive_reg pinmux_drive_regs[] = {
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2445 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
2446 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
2447 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
2448 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
2449 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
2450 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
2451 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
2452 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
2453 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
2454 } },
2455 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
2456 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
2457 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
2458 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
2459 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
2460 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
2461 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
2462 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
2463 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
2464 } },
2465 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
2466 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
2467 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
2468 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
2469 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
2470 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
2471 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
2472 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
2473 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
2474 } },
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2475 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2476 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
2477 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
2478 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
2479 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
2480 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
2481 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
2482 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
2483 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2484 } },
2485 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
2486 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
2487 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
2488 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
2489 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
2490 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
2491 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
2492 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
2493 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
2494 } },
2495 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
2496 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
2497 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
2498 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
2499 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
2500 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
2501 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
2502 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
2503 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
2504 } },
2505 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
2506 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
2507 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
2508 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
2509 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
2510 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
2511 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
2512 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
2513 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
2514 } },
2515 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
2516 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
2517 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
2518 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
2519 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
2520 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
2521 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
2522 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
2523 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
2524 } },
2525 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2526 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2527 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
2528 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
2529 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
2530 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
2531 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
2532 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
2533 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
2534 } },
2535 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
2536 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2537 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2538 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
2539 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
2540 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
2541 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
2542 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
2543 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
2544 } },
2545 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
2546 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
2547 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
2548 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
2549 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
2550 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
2551 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
2552 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
2553 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
2554 } },
2555 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2556 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
2557 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
2558 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
2559 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
2560 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
2561 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
2562 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
2563 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
2564 } },
2565 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
2566 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
2567 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
2568 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
2569 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2570 } },
2571 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2572 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
2573 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
2574 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
2575 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
2576 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
2577 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
2578 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
2579 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2580 } },
2581 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
2582 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
2583 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
2584 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
2585 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
2586 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
2587 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
2588 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
2589 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
2590 } },
2591 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
2592 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
2593 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
2594 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
2595 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
2596 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
2597 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
2598 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
2599 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
2600 } },
2601 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
2602 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
2603 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
2604 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
2605 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
2606 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
2607 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
2608 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
2609 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
2610 } },
2611 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
2612 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
2613 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
2614 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
2615 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
2616 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
2617 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
2618 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
2619 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
2620 } },
2621 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
2622 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
2623 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
2624 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
2625 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
2626 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
2627 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
2628 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
2629 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
2630 } },
2631 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
2632 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
2633 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
2634 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
2635 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
2636 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
2637 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
2638 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
2639 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
2640 } },
2641 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
2642 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
2643 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
2644 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
2645 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
2646 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
2647 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Niklas Söderlundea9c7402016-11-11 21:33:39 +0100[diff] [blame]2648 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2649 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
2650 } },
2651 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
2652 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
2653 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
2654 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
2655 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]2656 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
2657 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2658 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
2659 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
2660 } },
2661 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
2662 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
2663 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
2664 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
2665 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
2666 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
2667 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
2668 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
2669 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
2670 } },
2671 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
2672 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
2673 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
2674 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
2675 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
2676 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
2677 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
2678 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
2679 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
2680 } },
2681 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
2682 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
2683 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
2684 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
2685 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
2686 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2687 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */
2688 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]2689 } },
2690 { },
2691};
2692
Wolfram Sange9eace32016-06-06 18:08:26 +0200[diff] [blame]2693static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2694{
2695 int bit = -EINVAL;
2696
2697 *pocctrl = 0xe6060380;
2698
2699 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
2700 bit = pin & 0x1f;
2701
2702 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
2703 bit = (pin & 0x1f) + 12;
2704
2705 return bit;
2706}
2707
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2708#define PUEN 0xe6060400
2709#define PUD 0xe6060440
2710
2711#define PU0 0x00
2712#define PU1 0x04
2713#define PU2 0x08
2714#define PU3 0x0c
2715#define PU4 0x10
2716#define PU5 0x14
2717#define PU6 0x18
2718
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2719static const struct sh_pfc_bias_info bias_info[] = {
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2720 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
2721 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
2722 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
2723 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
2724 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
2725 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
2726 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
2727 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
2728 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
2729 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
2730 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
2731 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
2732 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
2733 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
2734 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
2735 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
2736 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
2737 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
2738 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
2739 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
2740 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
2741 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
2742 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
2743 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
2744 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
2745 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
2746 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
2747 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
2748 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
2749 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
2750 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
2751 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2752
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2753 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
2754 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
2755 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
2756 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
2757 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
2758 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
2759 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
2760 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
2761 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
2762 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
2763 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
2764 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
2765 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
2766 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
2767 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
2768 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
2769 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
2770 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
2771 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
2772 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
2773 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
2774 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
2775 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
2776 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
2777 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
2778 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
2779 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
2780 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
2781 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
2782 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
2783 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
2784 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2785
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2786 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
2787 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
2788 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
2789 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
2790 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
2791 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
2792 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
2793 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
2794 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
2795 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
2796 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
2797 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
2798 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
2799 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
2800 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
2801 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
2802 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
2803 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
2804 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
2805 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
2806 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
2807 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
2808 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
2809 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
2810 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
2811 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
2812 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
2813 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
2814 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
2815 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
2816 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
2817 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2818
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2819 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
2820 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
2821 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
2822 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
2823 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
2824 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
2825 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
2826 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
2827 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
2828 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
2829 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
2830 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
2831 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
2832 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
2833 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
2834 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
2835 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
2836 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
2837 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
2838 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
2839 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
2840 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
2841 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
2842 /* bit 8 n/a */
2843 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
2844 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
2845 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
2846 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
2847 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
2848 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
2849 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
2850 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2851
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2852 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
2853 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
2854 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
2855 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
2856 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
2857 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
2858 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
2859 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
2860 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
2861 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
2862 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
2863 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
2864 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
2865 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
2866 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
2867 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
2868 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
2869 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
2870 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
2871 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
2872 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
2873 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
2874 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
2875 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
2876 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
2877 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
2878 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
2879 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
2880 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
2881 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
2882 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
2883 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2884
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2885 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
2886 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
2887 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
2888 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
2889 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
2890 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
2891 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
2892 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
2893 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
2894 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
2895 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
2896 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
2897 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
2898 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
2899 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
2900 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
2901 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
2902 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
Kuninori Morimoto68e63892017-05-16 08:01:17 +0000[diff] [blame^]2903 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
2904 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2905 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
2906 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
2907 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
2908 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
2909 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
2910 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
2911 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
2912 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
2913 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
2914 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
2915 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
2916 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2917
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2918 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */
2919 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */
Niklas Söderlund4c2fb442016-11-17 16:26:31 +0100[diff] [blame]2920 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
2921 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
2922 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
2923 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
2924 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2925};
2926
2927static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
2928 unsigned int pin)
2929{
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2930 const struct sh_pfc_bias_info *info;
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2931 u32 reg;
2932 u32 bit;
2933
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2934 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
2935 if (!info)
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2936 return PIN_CONFIG_BIAS_DISABLE;
2937
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2938 reg = info->reg;
2939 bit = BIT(info->bit);
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2940
Niklas Söderlund42831cf2016-11-12 17:04:26 +0100[diff] [blame]2941 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2942 return PIN_CONFIG_BIAS_DISABLE;
Niklas Söderlund42831cf2016-11-12 17:04:26 +0100[diff] [blame]2943 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
2944 return PIN_CONFIG_BIAS_PULL_UP;
2945 else
2946 return PIN_CONFIG_BIAS_PULL_DOWN;
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2947}
2948
2949static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2950 unsigned int bias)
2951{
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2952 const struct sh_pfc_bias_info *info;
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2953 u32 enable, updown;
2954 u32 reg;
2955 u32 bit;
2956
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2957 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
2958 if (!info)
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2959 return;
2960
Niklas Söderlundd3b861b2016-11-12 17:04:27 +0100[diff] [blame]2961 reg = info->reg;
2962 bit = BIT(info->bit);
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2963
2964 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
2965 if (bias != PIN_CONFIG_BIAS_DISABLE)
2966 enable |= bit;
2967
2968 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
2969 if (bias == PIN_CONFIG_BIAS_PULL_UP)
2970 updown |= bit;
2971
2972 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
2973 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
2974}
2975
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2976static const struct soc_device_attribute r8a7795es1[] = {
2977 { .soc_id = "r8a7795", .revision = "ES1.*" },
2978 { /* sentinel */ }
2979};
2980
2981static int r8a7795_pinmux_init(struct sh_pfc *pfc)
2982{
2983 if (soc_device_match(r8a7795es1))
2984 pfc->info = &r8a7795es1_pinmux_info;
2985
2986 return 0;
2987}
2988
Wolfram Sange9eace32016-06-06 18:08:26 +0200[diff] [blame]2989static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2990 .init = r8a7795_pinmux_init,
Wolfram Sange9eace32016-06-06 18:08:26 +0200[diff] [blame]2991 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
Ulrich Hecht56065522016-06-29 18:06:04 +0200[diff] [blame]2992 .get_bias = r8a7795_pinmux_get_bias,
2993 .set_bias = r8a7795_pinmux_set_bias,
Wolfram Sange9eace32016-06-06 18:08:26 +0200[diff] [blame]2994};
2995
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2996const struct sh_pfc_soc_info r8a7795_pinmux_info = {
Geert Uytterhoevenb205914c2016-10-03 14:49:57 +0200[diff] [blame]2997 .name = "r8a77951_pfc",
Wolfram Sange9eace32016-06-06 18:08:26 +0200[diff] [blame]2998 .ops = &r8a7795_pinmux_ops,
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]2999 .unlock_reg = 0xe6060000, /* PMMR */
3000
3001 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3002
3003 .pins = pinmux_pins,
3004 .nr_pins = ARRAY_SIZE(pinmux_pins),
3005 .groups = pinmux_groups,
3006 .nr_groups = ARRAY_SIZE(pinmux_groups),
3007 .functions = pinmux_functions,
3008 .nr_functions = ARRAY_SIZE(pinmux_functions),
3009
3010 .cfg_regs = pinmux_config_regs,
Laurent Pinchart92e6d9a2016-03-23 16:06:01 +0200[diff] [blame]3011 .drive_regs = pinmux_drive_regs,
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]3012
Geert Uytterhoevenb8b47d62015-09-21 16:27:23 +0200[diff] [blame]3013 .pinmux_data = pinmux_data,
3014 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
Takeshi Kihara0b0ffc92015-09-03 02:51:49 +0000[diff] [blame]3015};