Blame - drivers/pinctrl/sh-pfc/pfc-r8a7795.c - SHIFTPHONES/mainline/linux

blob: 22201fc37420fd9db1eba53b77cfe4bf9acf1d3c [file] [log] [blame]

Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1	/*
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	2	* R8A7795 ES2.0+ processor support - PFC hardware block.
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	3	*
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4	* Copyright (C) 2015-2016 Renesas Electronics Corporation
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5	*
				6	* This program is free software; you can redistribute it and/or modify
				7	* it under the terms of the GNU General Public License as published by
				8	* the Free Software Foundation; version 2 of the License.
				9	*/
				10
				11	#include <linux/kernel.h>
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	12	#include <linux/sys_soc.h>
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	13
				14	#include "core.h"
				15	#include "sh_pfc.h"
				16
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	17	#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH \| \
				18	SH_PFC_PIN_CFG_PULL_UP \| \
				19	SH_PFC_PIN_CFG_PULL_DOWN)
				20
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	21	#define CPU_ALL_PORT(fn, sfx) \
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	22	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
				23	PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
				24	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
				25	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE), \
				26	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
				27	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
				28	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
				29	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
				30	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE), \
				31	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
				32	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
				33	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	34	/*
				35	* F_() : just information
				36	* FM() : macro for FN_xxx / xxx_MARK
				37	*/
				38
				39	/* GPSR0 */
				40	#define GPSR0_15 F_(D15, IP7_11_8)
				41	#define GPSR0_14 F_(D14, IP7_7_4)
				42	#define GPSR0_13 F_(D13, IP7_3_0)
				43	#define GPSR0_12 F_(D12, IP6_31_28)
				44	#define GPSR0_11 F_(D11, IP6_27_24)
				45	#define GPSR0_10 F_(D10, IP6_23_20)
				46	#define GPSR0_9 F_(D9, IP6_19_16)
				47	#define GPSR0_8 F_(D8, IP6_15_12)
				48	#define GPSR0_7 F_(D7, IP6_11_8)
				49	#define GPSR0_6 F_(D6, IP6_7_4)
				50	#define GPSR0_5 F_(D5, IP6_3_0)
				51	#define GPSR0_4 F_(D4, IP5_31_28)
				52	#define GPSR0_3 F_(D3, IP5_27_24)
				53	#define GPSR0_2 F_(D2, IP5_23_20)
				54	#define GPSR0_1 F_(D1, IP5_19_16)
				55	#define GPSR0_0 F_(D0, IP5_15_12)
				56
				57	/* GPSR1 */
				58	#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
				59	#define GPSR1_26 F_(WE1_N, IP5_7_4)
				60	#define GPSR1_25 F_(WE0_N, IP5_3_0)
				61	#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
				62	#define GPSR1_23 F_(RD_N, IP4_27_24)
				63	#define GPSR1_22 F_(BS_N, IP4_23_20)
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	64	#define GPSR1_21 F_(CS1_N, IP4_19_16)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	65	#define GPSR1_20 F_(CS0_N, IP4_15_12)
				66	#define GPSR1_19 F_(A19, IP4_11_8)
				67	#define GPSR1_18 F_(A18, IP4_7_4)
				68	#define GPSR1_17 F_(A17, IP4_3_0)
				69	#define GPSR1_16 F_(A16, IP3_31_28)
				70	#define GPSR1_15 F_(A15, IP3_27_24)
				71	#define GPSR1_14 F_(A14, IP3_23_20)
				72	#define GPSR1_13 F_(A13, IP3_19_16)
				73	#define GPSR1_12 F_(A12, IP3_15_12)
				74	#define GPSR1_11 F_(A11, IP3_11_8)
				75	#define GPSR1_10 F_(A10, IP3_7_4)
				76	#define GPSR1_9 F_(A9, IP3_3_0)
				77	#define GPSR1_8 F_(A8, IP2_31_28)
				78	#define GPSR1_7 F_(A7, IP2_27_24)
				79	#define GPSR1_6 F_(A6, IP2_23_20)
				80	#define GPSR1_5 F_(A5, IP2_19_16)
				81	#define GPSR1_4 F_(A4, IP2_15_12)
				82	#define GPSR1_3 F_(A3, IP2_11_8)
				83	#define GPSR1_2 F_(A2, IP2_7_4)
				84	#define GPSR1_1 F_(A1, IP2_3_0)
				85	#define GPSR1_0 F_(A0, IP1_31_28)
				86
				87	/* GPSR2 */
				88	#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
				89	#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
				90	#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
				91	#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
				92	#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
				93	#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
				94	#define GPSR2_8 F_(PWM2_A, IP1_27_24)
				95	#define GPSR2_7 F_(PWM1_A, IP1_23_20)
				96	#define GPSR2_6 F_(PWM0, IP1_19_16)
				97	#define GPSR2_5 F_(IRQ5, IP1_15_12)
				98	#define GPSR2_4 F_(IRQ4, IP1_11_8)
				99	#define GPSR2_3 F_(IRQ3, IP1_7_4)
				100	#define GPSR2_2 F_(IRQ2, IP1_3_0)
				101	#define GPSR2_1 F_(IRQ1, IP0_31_28)
				102	#define GPSR2_0 F_(IRQ0, IP0_27_24)
				103
				104	/* GPSR3 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	105	#define GPSR3_15 F_(SD1_WP, IP11_23_20)
				106	#define GPSR3_14 F_(SD1_CD, IP11_19_16)
				107	#define GPSR3_13 F_(SD0_WP, IP11_15_12)
				108	#define GPSR3_12 F_(SD0_CD, IP11_11_8)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	109	#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
				110	#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
				111	#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
				112	#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
				113	#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
				114	#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
				115	#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
				116	#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
				117	#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
				118	#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
				119	#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
				120	#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
				121
				122	/* GPSR4 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	123	#define GPSR4_17 F_(SD3_DS, IP11_7_4)
				124	#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
				125	#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
				126	#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
				127	#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
				128	#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
				129	#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
				130	#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
				131	#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
				132	#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
				133	#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
				134	#define GPSR4_6 F_(SD2_DS, IP9_27_24)
				135	#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
				136	#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
				137	#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
				138	#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
				139	#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	140	#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
				141
				142	/* GPSR5 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	143	#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
				144	#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
				145	#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	146	#define GPSR5_22 FM(MSIOF0_RXD)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	147	#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	148	#define GPSR5_20 FM(MSIOF0_TXD)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	149	#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
				150	#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	151	#define GPSR5_17 FM(MSIOF0_SCK)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	152	#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
				153	#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
				154	#define GPSR5_14 F_(HTX0, IP13_19_16)
				155	#define GPSR5_13 F_(HRX0, IP13_15_12)
				156	#define GPSR5_12 F_(HSCK0, IP13_11_8)
				157	#define GPSR5_11 F_(RX2_A, IP13_7_4)
				158	#define GPSR5_10 F_(TX2_A, IP13_3_0)
				159	#define GPSR5_9 F_(SCK2, IP12_31_28)
				160	#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
				161	#define GPSR5_7 F_(CTS1_N, IP12_23_20)
				162	#define GPSR5_6 F_(TX1_A, IP12_19_16)
				163	#define GPSR5_5 F_(RX1_A, IP12_15_12)
				164	#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
				165	#define GPSR5_3 F_(CTS0_N, IP12_7_4)
				166	#define GPSR5_2 F_(TX0, IP12_3_0)
				167	#define GPSR5_1 F_(RX0, IP11_31_28)
				168	#define GPSR5_0 F_(SCK0, IP11_27_24)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	169
				170	/* GPSR6 */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	171	#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
				172	#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	173	#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
				174	#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
				175	#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
				176	#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
				177	#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
				178	#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
				179	#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
				180	#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
				181	#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
				182	#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
				183	#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
				184	#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
				185	#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
				186	#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
				187	#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
				188	#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	189	#define GPSR6_13 FM(SSI_SDATA5)
				190	#define GPSR6_12 FM(SSI_WS5)
				191	#define GPSR6_11 FM(SSI_SCK5)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	192	#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
				193	#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
				194	#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
				195	#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	196	#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
				197	#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	198	#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
				199	#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
				200	#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
				201	#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
				202	#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	203
				204	/* GPSR7 */
				205	#define GPSR7_3 FM(HDMI1_CEC)
				206	#define GPSR7_2 FM(HDMI0_CEC)
				207	#define GPSR7_1 FM(AVS2)
				208	#define GPSR7_0 FM(AVS1)
				209
				210
				211	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				212	#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				213	#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				214	#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				215	#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	216	#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	217	#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	e2ab177	2017-05-30 20:15:18 +0900	[diff] [blame]	218	#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				219	#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	220	#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				221	#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				222	#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				223	#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	224	#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				225	#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				226	#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				227	#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				228	#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				229	#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				230	#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				231
				232	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				233	#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				234	#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				235	#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				236	#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				237	#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				238	#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				239	#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				240	#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				241	#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				242	#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				243	#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				244	#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				245	#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				246	#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				247	#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				248	#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				249	#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	250	#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	251	#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				252	#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				253	#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				254	#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				255	#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				256	#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				257	#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				258	#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				259	#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				260	#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				261	#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				262	#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				263	#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				264	#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				265	#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				266	#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				267	#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				268	#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				269	#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				270	#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				271	#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				272	#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	273	#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				274
				275	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				276	#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				277	#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				278	#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				279	#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				280	#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				281	#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	282	#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				283	#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				284	#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				285	#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				286	#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	67c836b	2017-07-28 20:41:17 +0900	[diff] [blame]	287	#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				288	#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				289	#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				290	#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				291	#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				292	#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				293	#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				294	#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				295	#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				296	#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				297	#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				298	#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				299	#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				300	#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				301	#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				302	#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				303	#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				304	#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	305	#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	306
				307	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	308	#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				309	#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				310	#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				311	#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				312	#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				313	#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				314	#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				315	#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				316	#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				317	#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				318	#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				319	#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				320	#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				321	#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				322	#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				323	#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				324	#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				325	#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				326	#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				327	#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				328	#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
				329	#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				330	#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				331	#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				332	#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				333	#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				334	#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				335	#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				336
				337	/* IPSRx / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 / / 8 / / 9 / / A / / B / / C - F */
				338	#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				339	#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				340	#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	341	#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				342	#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	343	#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				344	#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				345	#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				346	#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				347	#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				348	#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				349	#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				350	#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				351	#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				352	#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				353	#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				354	#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				355	#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				356	#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
				357	#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
				358	#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
				359	#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
				360	#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
				361	#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
				362	#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	bad7cc1	2017-07-28 20:41:16 +0900	[diff] [blame]	363	#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
				364	#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	365
				366	#define PINMUX_GPSR \
				367	\
				368	GPSR6_31 \
				369	GPSR6_30 \
				370	GPSR6_29 \
				371	GPSR6_28 \
				372	GPSR1_27 GPSR6_27 \
				373	GPSR1_26 GPSR6_26 \
				374	GPSR1_25 GPSR5_25 GPSR6_25 \
				375	GPSR1_24 GPSR5_24 GPSR6_24 \
				376	GPSR1_23 GPSR5_23 GPSR6_23 \
				377	GPSR1_22 GPSR5_22 GPSR6_22 \
				378	GPSR1_21 GPSR5_21 GPSR6_21 \
				379	GPSR1_20 GPSR5_20 GPSR6_20 \
				380	GPSR1_19 GPSR5_19 GPSR6_19 \
				381	GPSR1_18 GPSR5_18 GPSR6_18 \
				382	GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
				383	GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
				384	GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
				385	GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
				386	GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
				387	GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
				388	GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
				389	GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
				390	GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
				391	GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
				392	GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
				393	GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
				394	GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
				395	GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
				396	GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
				397	GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
				398	GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
				399	GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
				400
				401	#define PINMUX_IPSR \
				402	\
				403	FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
				404	FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
				405	FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
				406	FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
				407	FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
				408	FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
				409	FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
				410	FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
				411	\
				412	FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
				413	FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
				414	FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
Takeshi Kihara	30cd1c4	2017-07-28 20:41:19 +0900	[diff] [blame]	415	FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	416	FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
				417	FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
				418	FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
				419	FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
				420	\
				421	FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
				422	FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
				423	FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
				424	FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
				425	FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
				426	FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
				427	FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
				428	FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
				429	\
				430	FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
				431	FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
				432	FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
				433	FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
				434	FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
				435	FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
				436	FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
				437	FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
				438	\
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	439	FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
				440	FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
				441	FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
				442	FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
				443	FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
				444	FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
				445	FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
				446	FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	447
				448	/* MOD_SEL0 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	449	#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	450	#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
				451	#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
				452	#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
				453	#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	454	#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
				455	#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
				456	#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
				457	#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
				458	#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
				459	#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
				460	#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
				461	#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
				462	#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
				463	#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
				464	#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
				465	#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
				466	#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	467
				468	/* MOD_SEL1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 */
				469	#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
				470	#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	471	#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	472	#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
				473	#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
				474	#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
				475	#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
				476	#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
				477	#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
				478	#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
				479	#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
				480	#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
				481	#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	482	#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	483	#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
				484	#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
				485	#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
				486	#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
				487	#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
				488	#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
				489	#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
				490	#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
				491
				492	/* MOD_SEL2 / / 0 / / 1 / / 2 / / 3 */
				493	#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
				494	#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
				495	#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	496	#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
				497	#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
				498	#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	499	#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
				500	#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
				501	#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
				502	#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
				503	#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	504	#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
				505
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	506	#define PINMUX_MOD_SELS \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	507	\
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	508	MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
				509	MOD_SEL2_30 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	510	MOD_SEL1_29_28_27 MOD_SEL2_29 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	511	MOD_SEL0_28_27 MOD_SEL2_28_27 \
				512	MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
				513	MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	514	MOD_SEL0_23 MOD_SEL1_23_22_21 \
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	515	MOD_SEL0_22 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	516	MOD_SEL0_21 MOD_SEL2_21 \
				517	MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
				518	MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
				519	MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
				520	MOD_SEL2_17 \
				521	MOD_SEL0_16 MOD_SEL1_16 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	522	MOD_SEL1_15_14 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	523	MOD_SEL0_14_13 \
				524	MOD_SEL1_13 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	525	MOD_SEL0_12 MOD_SEL1_12 \
				526	MOD_SEL0_11 MOD_SEL1_11 \
				527	MOD_SEL0_10 MOD_SEL1_10 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	528	MOD_SEL0_9_8 MOD_SEL1_9 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	529	MOD_SEL0_7_6 \
				530	MOD_SEL1_6 \
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	531	MOD_SEL0_5 MOD_SEL1_5 \
				532	MOD_SEL0_4_3 MOD_SEL1_4 \
				533	MOD_SEL1_3 \
				534	MOD_SEL1_2 \
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	535	MOD_SEL1_1 \
				536	MOD_SEL1_0 MOD_SEL2_0
				537
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	538	/*
				539	* These pins are not able to be muxed but have other properties
				540	* that can be set, such as drive-strength or pull-up/pull-down enable.
				541	*/
				542	#define PINMUX_STATIC \
				543	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
				544	FM(QSPI0_IO2) FM(QSPI0_IO3) \
				545	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
				546	FM(QSPI1_IO2) FM(QSPI1_IO3) \
				547	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
				548	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
				549	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
				550	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
				551	FM(CLKOUT) FM(PRESETOUT) \
				552	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	553	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	554
				555	enum {
				556	PINMUX_RESERVED = 0,
				557
				558	PINMUX_DATA_BEGIN,
				559	GP_ALL(DATA),
				560	PINMUX_DATA_END,
				561
				562	#define F_(x, y)
				563	#define FM(x) FN_##x,
				564	PINMUX_FUNCTION_BEGIN,
				565	GP_ALL(FN),
				566	PINMUX_GPSR
				567	PINMUX_IPSR
				568	PINMUX_MOD_SELS
				569	PINMUX_FUNCTION_END,
				570	#undef F_
				571	#undef FM
				572
				573	#define F_(x, y)
				574	#define FM(x) x##_MARK,
				575	PINMUX_MARK_BEGIN,
				576	PINMUX_GPSR
				577	PINMUX_IPSR
				578	PINMUX_MOD_SELS
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	579	PINMUX_STATIC
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	580	PINMUX_MARK_END,
				581	#undef F_
				582	#undef FM
				583	};
				584
				585	static const u16 pinmux_data[] = {
				586	PINMUX_DATA_GP_ALL(),
				587
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	588	PINMUX_SINGLE(AVS1),
				589	PINMUX_SINGLE(AVS2),
				590	PINMUX_SINGLE(HDMI0_CEC),
				591	PINMUX_SINGLE(HDMI1_CEC),
Kuninori Morimoto	d07640f	2016-06-21 02:46:55 +0000	[diff] [blame]	592	PINMUX_SINGLE(I2C_SEL_0_1),
				593	PINMUX_SINGLE(I2C_SEL_3_1),
				594	PINMUX_SINGLE(I2C_SEL_5_1),
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	595	PINMUX_SINGLE(MSIOF0_RXD),
				596	PINMUX_SINGLE(MSIOF0_SCK),
				597	PINMUX_SINGLE(MSIOF0_TXD),
Geert Uytterhoeven	8d4df57	2015-09-02 20:37:55 +0200	[diff] [blame]	598	PINMUX_SINGLE(SSI_SCK5),
				599	PINMUX_SINGLE(SSI_SDATA5),
				600	PINMUX_SINGLE(SSI_WS5),
				601
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	602	/* IPSR0 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	603	PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	604	PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
				605
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	606	PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	607	PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
				608	PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
				609
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	610	PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	611	PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
				612	PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
				613
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	614	PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	615	PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
				616	PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
				617
				618	PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
				619	PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
				620	PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	621	PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	622
				623	PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
				624	PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
				625	PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
				626
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	627	PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
				628	PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
				629	PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	630	PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
				631	PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
				632	PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	633	PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	634
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	635	PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
				636	PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
				637	PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	638	PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
				639	PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
				640	PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	641	PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	642
				643	/* IPSR1 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	644	PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
				645	PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
				646	PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	647	PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
				648	PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	649	PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	650
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	651	PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
				652	PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
				653	PINMUX_IPSR_GPSR(IP1_7_4, A25),
				654	PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	655	PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
				656	PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	657	PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	658
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	659	PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
				660	PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
				661	PINMUX_IPSR_GPSR(IP1_11_8, A24),
				662	PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	663	PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
				664	PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	665	PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	666
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	667	PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
				668	PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
				669	PINMUX_IPSR_GPSR(IP1_15_12, A23),
				670	PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	671	PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
				672	PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	673	PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
				674	PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	675
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	676	PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
				677	PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
				678	PINMUX_IPSR_GPSR(IP1_19_16, A22),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	679	PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
				680	PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
				681
				682	PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	683	PINMUX_IPSR_GPSR(IP1_23_20, A21),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	684	PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
				685	PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
				686	PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
				687
				688	PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	689	PINMUX_IPSR_GPSR(IP1_27_24, A20),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	690	PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
				691	PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
				692
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	693	PINMUX_IPSR_GPSR(IP1_31_28, A0),
				694	PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	695	PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	696	PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
				697	PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	698	PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
				699
				700	/* IPSR2 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	701	PINMUX_IPSR_GPSR(IP2_3_0, A1),
				702	PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	703	PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	704	PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
				705	PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	706	PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
				707
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	708	PINMUX_IPSR_GPSR(IP2_7_4, A2),
				709	PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	710	PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	711	PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
				712	PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	713	PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
				714
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	715	PINMUX_IPSR_GPSR(IP2_11_8, A3),
				716	PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	717	PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	718	PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
				719	PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	720	PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
				721
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	722	PINMUX_IPSR_GPSR(IP2_15_12, A4),
				723	PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	724	PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	725	PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
				726	PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
				727	PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	728
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	729	PINMUX_IPSR_GPSR(IP2_19_16, A5),
				730	PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	731	PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
				732	PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	733	PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
				734	PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
				735	PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	736
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	737	PINMUX_IPSR_GPSR(IP2_23_20, A6),
				738	PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	739	PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
				740	PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	741	PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
				742	PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
				743	PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	744
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	745	PINMUX_IPSR_GPSR(IP2_27_24, A7),
				746	PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	747	PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
				748	PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	749	PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
				750	PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
				751	PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	752
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	753	PINMUX_IPSR_GPSR(IP2_31_28, A8),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	754	PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
				755	PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
				756	PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
				757	PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
				758	PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
				759	PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
				760
				761	/* IPSR3 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	762	PINMUX_IPSR_GPSR(IP3_3_0, A9),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	763	PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
				764	PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	765	PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	766
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	767	PINMUX_IPSR_GPSR(IP3_7_4, A10),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	768	PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
				769	PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	770	PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	771
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	772	PINMUX_IPSR_GPSR(IP3_11_8, A11),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	773	PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
				774	PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
				775	PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	776	PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
				777	PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	778	PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
				779	PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
				780	PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
				781
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	782	PINMUX_IPSR_GPSR(IP3_15_12, A12),
				783	PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	784	PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
				785	PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	786	PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
				787	PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	788
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	789	PINMUX_IPSR_GPSR(IP3_19_16, A13),
				790	PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	791	PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
				792	PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	793	PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
				794	PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	795
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	796	PINMUX_IPSR_GPSR(IP3_23_20, A14),
				797	PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	798	PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	799	PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
				800	PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
				801	PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	802
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	803	PINMUX_IPSR_GPSR(IP3_27_24, A15),
				804	PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	805	PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	806	PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
				807	PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
				808	PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	809
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	810	PINMUX_IPSR_GPSR(IP3_31_28, A16),
				811	PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
				812	PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
				813	PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	814
				815	/* IPSR4 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	816	PINMUX_IPSR_GPSR(IP4_3_0, A17),
				817	PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
				818	PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
				819	PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	820
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	821	PINMUX_IPSR_GPSR(IP4_7_4, A18),
				822	PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
				823	PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
				824	PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	825
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	826	PINMUX_IPSR_GPSR(IP4_11_8, A19),
				827	PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
				828	PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
				829	PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	830
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	831	PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
				832	PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	833
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	834	PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	835	PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	836	PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
				837
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	838	PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
				839	PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	840	PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	841	PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
				842	PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
				843	PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
				844	PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	845	PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
				846
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	847	PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	848	PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
				849	PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
				850	PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
				851	PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
				852	PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
				853
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	854	PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	855	PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
				856	PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
				857	PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
				858	PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
				859	PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
				860
				861	/* IPSR5 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	862	PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	863	PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	864	PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
				865	PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	866	PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	867	PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	868	PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
				869
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	870	PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	871	PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	872	PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
				873	PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	874	PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	875	PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
				876	PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	877	PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
				878
				879	PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	880	PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
				881	PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
				882	PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	883
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	884	PINMUX_IPSR_GPSR(IP5_15_12, D0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	885	PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
				886	PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	887	PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
				888	PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	889
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	890	PINMUX_IPSR_GPSR(IP5_19_16, D1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	891	PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
				892	PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	893	PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
				894	PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	895
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	896	PINMUX_IPSR_GPSR(IP5_23_20, D2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	897	PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	898	PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
				899	PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	900
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	901	PINMUX_IPSR_GPSR(IP5_27_24, D3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	902	PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	903	PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
				904	PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	905
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	906	PINMUX_IPSR_GPSR(IP5_31_28, D4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	907	PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	908	PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
				909	PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	910
				911	/* IPSR6 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	912	PINMUX_IPSR_GPSR(IP6_3_0, D5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	913	PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	914	PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
				915	PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	916
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	917	PINMUX_IPSR_GPSR(IP6_7_4, D6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	918	PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	919	PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
				920	PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	921
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	922	PINMUX_IPSR_GPSR(IP6_11_8, D7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	923	PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	924	PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
				925	PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	926
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	927	PINMUX_IPSR_GPSR(IP6_15_12, D8),
				928	PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	929	PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
				930	PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
				931	PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	932	PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	933
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	934	PINMUX_IPSR_GPSR(IP6_19_16, D9),
				935	PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	936	PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
				937	PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	938	PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	939
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	940	PINMUX_IPSR_GPSR(IP6_23_20, D10),
				941	PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	942	PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
				943	PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
				944	PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
				945	PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	946	PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	947
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	948	PINMUX_IPSR_GPSR(IP6_27_24, D11),
				949	PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	950	PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
				951	PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
				952	PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
				953	PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	954	PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	955
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	956	PINMUX_IPSR_GPSR(IP6_31_28, D12),
				957	PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	958	PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
				959	PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
				960	PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	961	PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	962
				963	/* IPSR7 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	964	PINMUX_IPSR_GPSR(IP7_3_0, D13),
				965	PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	966	PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
				967	PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
				968	PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	969	PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	970
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	971	PINMUX_IPSR_GPSR(IP7_7_4, D14),
				972	PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	973	PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
				974	PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
				975	PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	976	PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	977	PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
				978
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	979	PINMUX_IPSR_GPSR(IP7_11_8, D15),
				980	PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	981	PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
				982	PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
				983	PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	984	PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	985	PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
				986
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	987	PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	988	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
				989	PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
				990
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	991	PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	992	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
				993	PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
				994
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	995	PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	996	PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
				997	PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
				998	PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
				999
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1000	PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1001	PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
				1002	PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
				1003	PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
				1004
				1005	/* IPSR8 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1006	PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1007	PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
				1008	PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
				1009	PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
				1010
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1011	PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1012	PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
				1013	PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
				1014	PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
				1015
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1016	PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1017	PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
				1018	PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
				1019
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1020	PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1021	PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1022	PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1023	PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
				1024	PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
				1025
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1026	PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
				1027	PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1028	PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1029	PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1030	PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
				1031	PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
				1032
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1033	PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
				1034	PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1035	PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1036	PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1037	PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
				1038	PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
				1039
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1040	PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
				1041	PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1042	PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1043	PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1044	PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
				1045	PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
				1046
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1047	PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
				1048	PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1049	PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1050	PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1051	PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
				1052	PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
				1053
				1054	/* IPSR9 */
Geert Uytterhoeven	e01678e	2015-11-30 13:34:47 +0100	[diff] [blame]	1055	PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1056	PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1057
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1058	PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
				1059	PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1060
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1061	PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
				1062	PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1063
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1064	PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
				1065	PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1066
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1067	PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
				1068	PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1069
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1070	PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
				1071	PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1072
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1073	PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
				1074	PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
				1075	PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1076
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1077	PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
				1078	PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1079
				1080	/* IPSR10 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1081	PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
				1082	PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1083
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1084	PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
				1085	PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1086
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1087	PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
				1088	PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1089
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1090	PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
				1091	PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1092
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1093	PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
				1094	PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1095
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1096	PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
				1097	PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
				1098	PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1099
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1100	PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
				1101	PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
				1102	PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1103
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1104	PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
				1105	PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
				1106	PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1107
				1108	/* IPSR11 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1109	PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
				1110	PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
				1111	PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1112
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1113	PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
				1114	PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1115
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1116	PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
				1117	PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
				1118	PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1119
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1120	PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
				1121	PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1122
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1123	PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
				1124	PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1125
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1126	PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
				1127	PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1128
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1129	PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
				1130	PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
				1131	PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
				1132	PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
				1133	PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
				1134	PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
				1135	PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
				1136	PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
				1137	PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
				1138	PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1139
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1140	PINMUX_IPSR_GPSR(IP11_31_28, RX0),
				1141	PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
				1142	PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
				1143	PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
				1144	PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1145
				1146	/* IPSR12 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1147	PINMUX_IPSR_GPSR(IP12_3_0, TX0),
				1148	PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
				1149	PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
				1150	PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
				1151	PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1152
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1153	PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
				1154	PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
				1155	PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
				1156	PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
				1157	PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
				1158	PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
				1159	PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
				1160	PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1161
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1162	PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
				1163	PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
				1164	PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
				1165	PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
				1166	PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
				1167	PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
				1168	PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
				1169	PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1170
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1171	PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
				1172	PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
				1173	PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
				1174	PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
				1175	PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1176
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1177	PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
				1178	PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
				1179	PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
				1180	PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
				1181	PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1182
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1183	PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
				1184	PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
				1185	PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
				1186	PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
				1187	PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
				1188	PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
				1189	PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1190
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1191	PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
				1192	PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
				1193	PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
				1194	PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
				1195	PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
				1196	PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
				1197	PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1198
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1199	PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	1200	PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1201	PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
				1202	PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
				1203	PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
				1204	PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
				1205	PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1206
				1207	/* IPSR13 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1208	PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
				1209	PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
				1210	PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
				1211	PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
				1212	PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
				1213	PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1214
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1215	PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
				1216	PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
				1217	PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
				1218	PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
				1219	PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
				1220	PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1221
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1222	PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
				1223	PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
				1224	PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
				1225	PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
				1226	PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
				1227	PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
				1228	PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
				1229	PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1230
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1231	PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
				1232	PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
				1233	PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
				1234	PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
				1235	PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
				1236	PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1237
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1238	PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
				1239	PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
				1240	PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
				1241	PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
				1242	PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
				1243	PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1244
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1245	PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
				1246	PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
				1247	PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
				1248	PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
				1249	PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
				1250	PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
				1251	PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
				1252	PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1253
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1254	PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
				1255	PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
				1256	PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
				1257	PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
				1258	PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
				1259	PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
				1260	PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1261
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1262	PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
				1263	PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
				1264	PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
				1265	PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1266
				1267	/* IPSR14 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1268	PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
				1269	PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	1270	PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1271	PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
				1272	PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
				1273	PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
				1274	PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1275	PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1276
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1277	PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
				1278	PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
				1279	PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
				1280	PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
				1281	PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
				1282	PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
				1283	PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
				1284	PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1285
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1286	PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
				1287	PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
				1288	PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1289
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1290	PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
				1291	PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
				1292	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
				1293	PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1294
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1295	PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
				1296	PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
				1297	PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1298
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1299	PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
				1300	PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1301
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1302	PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
				1303	PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1304
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1305	PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
				1306	PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1307
				1308	/* IPSR15 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1309	PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1310
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1311	PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
				1312	PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1313
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	1314	PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1315	PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
				1316	PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1317
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	1318	PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1319	PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
				1320	PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
				1321	PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1322
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1323	PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
				1324	PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
				1325	PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
				1326	PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
				1327	PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
				1328	PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
				1329	PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1330
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1331	PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
				1332	PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
				1333	PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
				1334	PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
				1335	PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
				1336	PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
				1337	PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1338
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1339	PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
				1340	PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
				1341	PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
				1342	PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
				1343	PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
				1344	PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
				1345	PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1346
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1347	PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
				1348	PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
				1349	PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
				1350	PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
				1351	PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
				1352	PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
				1353	PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1354
				1355	/* IPSR16 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1356	PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
				1357	PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
				1358	PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1359
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1360	PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
				1361	PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
				1362	PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1363
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1364	PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
				1365	PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
				1366	PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1367
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1368	PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
				1369	PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
				1370	PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
				1371	PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
				1372	PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
				1373	PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
				1374	PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1375
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1376	PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
				1377	PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
				1378	PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
				1379	PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
				1380	PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
				1381	PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
				1382	PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1383
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1384	PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
				1385	PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
				1386	PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
				1387	PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
				1388	PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
				1389	PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
				1390	PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1391	PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1392
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1393	PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
				1394	PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
				1395	PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
				1396	PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
				1397	PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
				1398	PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
				1399	PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1400
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1401	PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
				1402	PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
				1403	PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
				1404	PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
				1405	PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
				1406	PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
				1407	PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
Takeshi Kihara	712f36f	2017-07-28 20:41:14 +0900	[diff] [blame]	1408	PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1409
				1410	/* IPSR17 */
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1411	PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
				1412	PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1413
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1414	PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
Takeshi Kihara	eada11a	2017-07-28 20:41:15 +0900	[diff] [blame]	1415	PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1416	PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
				1417	PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1418	PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1419
				1420	PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
				1421	PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
				1422	PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
				1423	PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
				1424	PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
				1425	PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
				1426	PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
				1427
				1428	PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
				1429	PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
				1430	PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
				1431	PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
				1432	PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
				1433	PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
				1434
				1435	PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
				1436	PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
				1437	PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
				1438	PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
				1439	PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
				1440	PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
				1441	PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
				1442	PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
				1443	PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
				1444
				1445	PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
				1446	PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
				1447	PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
				1448	PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
				1449	PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
				1450	PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
				1451	PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
				1452	PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
				1453	PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
				1454
				1455	PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
				1456	PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
				1457	PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
				1458	PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
Takeshi Kihara	50d8315	2017-07-28 20:41:13 +0900	[diff] [blame]	1459	PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1460	PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
				1461	PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
Takeshi Kihara	ae03c4e	2017-07-28 20:41:18 +0900	[diff] [blame]	1462	PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1463	PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
				1464	PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
				1465	PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
				1466
				1467	PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
				1468	PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
				1469	PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
				1470	PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
				1471	PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
				1472	PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
				1473	PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
				1474	PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
				1475	PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
				1476
				1477	/* IPSR18 */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	1478	PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1479	PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
				1480	PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
				1481	PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
				1482	PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
				1483	PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
				1484	PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
				1485	PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
				1486	PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
				1487
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	1488	PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	1489	PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
				1490	PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
				1491	PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
				1492	PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
				1493	PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
				1494	PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
				1495	PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
				1496	PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1497
				1498	/*
				1499	* Static pins can not be muxed between different functions but
				1500	* still needs a mark entry in the pinmux list. Add each static
				1501	* pin to the list without an associated function. The sh-pfc
				1502	* core will do the right thing and skip trying to mux then pin
				1503	* while still applying configuration to it
				1504	*/
				1505	#define FM(x) PINMUX_DATA(x##_MARK, 0),
				1506	PINMUX_STATIC
				1507	#undef FM
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1508	};
				1509
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1510	/*
				1511	* R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
				1512	* Physical layout rows: A - AW, cols: 1 - 39.
				1513	*/
				1514	#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
				1515	#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
				1516	#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
				1517
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1518	static const struct sh_pfc_pin pinmux_pins[] = {
				1519	PINMUX_GPIO_GP_ALL(),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1520
				1521	/*
				1522	* Pins not associated with a GPIO port.
				1523	*
				1524	* The pin positions are different between different r8a7795
				1525	* packages, all that is needed for the pfc driver is a unique
				1526	* number for each pin. To this end use the pin layout from
				1527	* R-Car H3SiP to calculate a unique number for each pin.
				1528	*/
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	1529	SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
				1530	SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
				1531	SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
				1532	SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
				1533	SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
				1534	SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
				1535	SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
				1536	SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
				1537	SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
				1538	SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
				1539	SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
				1540	SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
				1541	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
				1542	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
				1543	SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
				1544	SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
				1545	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
				1546	SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
				1547	SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
				1548	SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
				1549	SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
				1550	SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
				1551	SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
				1552	SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
				1553	SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
				1554	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
				1555	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
				1556	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
				1557	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
				1558	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
				1559	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
				1560	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1561	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
				1562	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
				1563	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
				1564	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
				1565	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
				1566	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
				1567	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1568	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
				1569	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
				1570	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP \| SH_PFC_PIN_CFG_PULL_DOWN),
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	1571	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	1572	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	1573	};
				1574
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	1575	/* - AUDIO CLOCK ------------------------------------------------------------ */
				1576	static const unsigned int audio_clk_a_a_pins[] = {
				1577	/* CLK A */
				1578	RCAR_GP_PIN(6, 22),
				1579	};
				1580	static const unsigned int audio_clk_a_a_mux[] = {
				1581	AUDIO_CLKA_A_MARK,
				1582	};
				1583	static const unsigned int audio_clk_a_b_pins[] = {
				1584	/* CLK A */
				1585	RCAR_GP_PIN(5, 4),
				1586	};
				1587	static const unsigned int audio_clk_a_b_mux[] = {
				1588	AUDIO_CLKA_B_MARK,
				1589	};
				1590	static const unsigned int audio_clk_a_c_pins[] = {
				1591	/* CLK A */
				1592	RCAR_GP_PIN(5, 19),
				1593	};
				1594	static const unsigned int audio_clk_a_c_mux[] = {
				1595	AUDIO_CLKA_C_MARK,
				1596	};
				1597	static const unsigned int audio_clk_b_a_pins[] = {
				1598	/* CLK B */
				1599	RCAR_GP_PIN(5, 12),
				1600	};
				1601	static const unsigned int audio_clk_b_a_mux[] = {
				1602	AUDIO_CLKB_A_MARK,
				1603	};
				1604	static const unsigned int audio_clk_b_b_pins[] = {
				1605	/* CLK B */
				1606	RCAR_GP_PIN(6, 23),
				1607	};
				1608	static const unsigned int audio_clk_b_b_mux[] = {
				1609	AUDIO_CLKB_B_MARK,
				1610	};
				1611	static const unsigned int audio_clk_c_a_pins[] = {
				1612	/* CLK C */
				1613	RCAR_GP_PIN(5, 21),
				1614	};
				1615	static const unsigned int audio_clk_c_a_mux[] = {
				1616	AUDIO_CLKC_A_MARK,
				1617	};
				1618	static const unsigned int audio_clk_c_b_pins[] = {
				1619	/* CLK C */
				1620	RCAR_GP_PIN(5, 0),
				1621	};
				1622	static const unsigned int audio_clk_c_b_mux[] = {
				1623	AUDIO_CLKC_B_MARK,
				1624	};
				1625	static const unsigned int audio_clkout_a_pins[] = {
				1626	/* CLKOUT */
				1627	RCAR_GP_PIN(5, 18),
				1628	};
				1629	static const unsigned int audio_clkout_a_mux[] = {
				1630	AUDIO_CLKOUT_A_MARK,
				1631	};
				1632	static const unsigned int audio_clkout_b_pins[] = {
				1633	/* CLKOUT */
				1634	RCAR_GP_PIN(6, 28),
				1635	};
				1636	static const unsigned int audio_clkout_b_mux[] = {
				1637	AUDIO_CLKOUT_B_MARK,
				1638	};
				1639	static const unsigned int audio_clkout_c_pins[] = {
				1640	/* CLKOUT */
				1641	RCAR_GP_PIN(5, 3),
				1642	};
				1643	static const unsigned int audio_clkout_c_mux[] = {
				1644	AUDIO_CLKOUT_C_MARK,
				1645	};
				1646	static const unsigned int audio_clkout_d_pins[] = {
				1647	/* CLKOUT */
				1648	RCAR_GP_PIN(5, 21),
				1649	};
				1650	static const unsigned int audio_clkout_d_mux[] = {
				1651	AUDIO_CLKOUT_D_MARK,
				1652	};
				1653	static const unsigned int audio_clkout1_a_pins[] = {
				1654	/* CLKOUT1 */
				1655	RCAR_GP_PIN(5, 15),
				1656	};
				1657	static const unsigned int audio_clkout1_a_mux[] = {
				1658	AUDIO_CLKOUT1_A_MARK,
				1659	};
				1660	static const unsigned int audio_clkout1_b_pins[] = {
				1661	/* CLKOUT1 */
				1662	RCAR_GP_PIN(6, 29),
				1663	};
				1664	static const unsigned int audio_clkout1_b_mux[] = {
				1665	AUDIO_CLKOUT1_B_MARK,
				1666	};
				1667	static const unsigned int audio_clkout2_a_pins[] = {
				1668	/* CLKOUT2 */
				1669	RCAR_GP_PIN(5, 16),
				1670	};
				1671	static const unsigned int audio_clkout2_a_mux[] = {
				1672	AUDIO_CLKOUT2_A_MARK,
				1673	};
				1674	static const unsigned int audio_clkout2_b_pins[] = {
				1675	/* CLKOUT2 */
				1676	RCAR_GP_PIN(6, 30),
				1677	};
				1678	static const unsigned int audio_clkout2_b_mux[] = {
				1679	AUDIO_CLKOUT2_B_MARK,
				1680	};
				1681	static const unsigned int audio_clkout3_a_pins[] = {
				1682	/* CLKOUT3 */
				1683	RCAR_GP_PIN(5, 19),
				1684	};
				1685	static const unsigned int audio_clkout3_a_mux[] = {
				1686	AUDIO_CLKOUT3_A_MARK,
				1687	};
				1688	static const unsigned int audio_clkout3_b_pins[] = {
				1689	/* CLKOUT3 */
				1690	RCAR_GP_PIN(6, 31),
				1691	};
				1692	static const unsigned int audio_clkout3_b_mux[] = {
				1693	AUDIO_CLKOUT3_B_MARK,
				1694	};
				1695
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	1696	/* - EtherAVB --------------------------------------------------------------- */
				1697	static const unsigned int avb_link_pins[] = {
				1698	/* AVB_LINK */
				1699	RCAR_GP_PIN(2, 12),
				1700	};
				1701	static const unsigned int avb_link_mux[] = {
				1702	AVB_LINK_MARK,
				1703	};
				1704	static const unsigned int avb_magic_pins[] = {
				1705	/* AVB_MAGIC_ */
				1706	RCAR_GP_PIN(2, 10),
				1707	};
				1708	static const unsigned int avb_magic_mux[] = {
				1709	AVB_MAGIC_MARK,
				1710	};
				1711	static const unsigned int avb_phy_int_pins[] = {
				1712	/* AVB_PHY_INT */
				1713	RCAR_GP_PIN(2, 11),
				1714	};
				1715	static const unsigned int avb_phy_int_mux[] = {
				1716	AVB_PHY_INT_MARK,
				1717	};
				1718	static const unsigned int avb_mdc_pins[] = {
				1719	/* AVB_MDC, AVB_MDIO */
				1720	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
				1721	};
				1722	static const unsigned int avb_mdc_mux[] = {
				1723	AVB_MDC_MARK, AVB_MDIO_MARK,
				1724	};
				1725	static const unsigned int avb_mii_pins[] = {
				1726	/*
				1727	* AVB_TX_CTL, AVB_TXC, AVB_TD0,
				1728	* AVB_TD1, AVB_TD2, AVB_TD3,
				1729	* AVB_RX_CTL, AVB_RXC, AVB_RD0,
				1730	* AVB_RD1, AVB_RD2, AVB_RD3,
				1731	* AVB_TXCREFCLK
				1732	*/
				1733	PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
				1734	PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
				1735	PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
				1736	PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
				1737	PIN_NUMBER('A', 12),
				1738
				1739	};
				1740	static const unsigned int avb_mii_mux[] = {
				1741	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
				1742	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
				1743	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
				1744	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
				1745	AVB_TXCREFCLK_MARK,
				1746	};
				1747	static const unsigned int avb_avtp_pps_pins[] = {
				1748	/* AVB_AVTP_PPS */
				1749	RCAR_GP_PIN(2, 6),
				1750	};
				1751	static const unsigned int avb_avtp_pps_mux[] = {
				1752	AVB_AVTP_PPS_MARK,
				1753	};
				1754	static const unsigned int avb_avtp_match_a_pins[] = {
				1755	/* AVB_AVTP_MATCH_A */
				1756	RCAR_GP_PIN(2, 13),
				1757	};
				1758	static const unsigned int avb_avtp_match_a_mux[] = {
				1759	AVB_AVTP_MATCH_A_MARK,
				1760	};
				1761	static const unsigned int avb_avtp_capture_a_pins[] = {
				1762	/* AVB_AVTP_CAPTURE_A */
				1763	RCAR_GP_PIN(2, 14),
				1764	};
				1765	static const unsigned int avb_avtp_capture_a_mux[] = {
				1766	AVB_AVTP_CAPTURE_A_MARK,
				1767	};
				1768	static const unsigned int avb_avtp_match_b_pins[] = {
				1769	/* AVB_AVTP_MATCH_B */
				1770	RCAR_GP_PIN(1, 8),
				1771	};
				1772	static const unsigned int avb_avtp_match_b_mux[] = {
				1773	AVB_AVTP_MATCH_B_MARK,
				1774	};
				1775	static const unsigned int avb_avtp_capture_b_pins[] = {
				1776	/* AVB_AVTP_CAPTURE_B */
				1777	RCAR_GP_PIN(1, 11),
				1778	};
				1779	static const unsigned int avb_avtp_capture_b_mux[] = {
				1780	AVB_AVTP_CAPTURE_B_MARK,
				1781	};
				1782
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	1783	/* - DRIF0 --------------------------------------------------------------- */
				1784	static const unsigned int drif0_ctrl_a_pins[] = {
				1785	/* CLK, SYNC */
				1786	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				1787	};
				1788	static const unsigned int drif0_ctrl_a_mux[] = {
				1789	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
				1790	};
				1791	static const unsigned int drif0_data0_a_pins[] = {
				1792	/* D0 */
				1793	RCAR_GP_PIN(6, 10),
				1794	};
				1795	static const unsigned int drif0_data0_a_mux[] = {
				1796	RIF0_D0_A_MARK,
				1797	};
				1798	static const unsigned int drif0_data1_a_pins[] = {
				1799	/* D1 */
				1800	RCAR_GP_PIN(6, 7),
				1801	};
				1802	static const unsigned int drif0_data1_a_mux[] = {
				1803	RIF0_D1_A_MARK,
				1804	};
				1805	static const unsigned int drif0_ctrl_b_pins[] = {
				1806	/* CLK, SYNC */
				1807	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
				1808	};
				1809	static const unsigned int drif0_ctrl_b_mux[] = {
				1810	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
				1811	};
				1812	static const unsigned int drif0_data0_b_pins[] = {
				1813	/* D0 */
				1814	RCAR_GP_PIN(5, 1),
				1815	};
				1816	static const unsigned int drif0_data0_b_mux[] = {
				1817	RIF0_D0_B_MARK,
				1818	};
				1819	static const unsigned int drif0_data1_b_pins[] = {
				1820	/* D1 */
				1821	RCAR_GP_PIN(5, 2),
				1822	};
				1823	static const unsigned int drif0_data1_b_mux[] = {
				1824	RIF0_D1_B_MARK,
				1825	};
				1826	static const unsigned int drif0_ctrl_c_pins[] = {
				1827	/* CLK, SYNC */
				1828	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
				1829	};
				1830	static const unsigned int drif0_ctrl_c_mux[] = {
				1831	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
				1832	};
				1833	static const unsigned int drif0_data0_c_pins[] = {
				1834	/* D0 */
				1835	RCAR_GP_PIN(5, 13),
				1836	};
				1837	static const unsigned int drif0_data0_c_mux[] = {
				1838	RIF0_D0_C_MARK,
				1839	};
				1840	static const unsigned int drif0_data1_c_pins[] = {
				1841	/* D1 */
				1842	RCAR_GP_PIN(5, 14),
				1843	};
				1844	static const unsigned int drif0_data1_c_mux[] = {
				1845	RIF0_D1_C_MARK,
				1846	};
				1847	/* - DRIF1 --------------------------------------------------------------- */
				1848	static const unsigned int drif1_ctrl_a_pins[] = {
				1849	/* CLK, SYNC */
				1850	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				1851	};
				1852	static const unsigned int drif1_ctrl_a_mux[] = {
				1853	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
				1854	};
				1855	static const unsigned int drif1_data0_a_pins[] = {
				1856	/* D0 */
				1857	RCAR_GP_PIN(6, 19),
				1858	};
				1859	static const unsigned int drif1_data0_a_mux[] = {
				1860	RIF1_D0_A_MARK,
				1861	};
				1862	static const unsigned int drif1_data1_a_pins[] = {
				1863	/* D1 */
				1864	RCAR_GP_PIN(6, 20),
				1865	};
				1866	static const unsigned int drif1_data1_a_mux[] = {
				1867	RIF1_D1_A_MARK,
				1868	};
				1869	static const unsigned int drif1_ctrl_b_pins[] = {
				1870	/* CLK, SYNC */
				1871	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
				1872	};
				1873	static const unsigned int drif1_ctrl_b_mux[] = {
				1874	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
				1875	};
				1876	static const unsigned int drif1_data0_b_pins[] = {
				1877	/* D0 */
				1878	RCAR_GP_PIN(5, 7),
				1879	};
				1880	static const unsigned int drif1_data0_b_mux[] = {
				1881	RIF1_D0_B_MARK,
				1882	};
				1883	static const unsigned int drif1_data1_b_pins[] = {
				1884	/* D1 */
				1885	RCAR_GP_PIN(5, 8),
				1886	};
				1887	static const unsigned int drif1_data1_b_mux[] = {
				1888	RIF1_D1_B_MARK,
				1889	};
				1890	static const unsigned int drif1_ctrl_c_pins[] = {
				1891	/* CLK, SYNC */
				1892	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
				1893	};
				1894	static const unsigned int drif1_ctrl_c_mux[] = {
				1895	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
				1896	};
				1897	static const unsigned int drif1_data0_c_pins[] = {
				1898	/* D0 */
				1899	RCAR_GP_PIN(5, 6),
				1900	};
				1901	static const unsigned int drif1_data0_c_mux[] = {
				1902	RIF1_D0_C_MARK,
				1903	};
				1904	static const unsigned int drif1_data1_c_pins[] = {
				1905	/* D1 */
				1906	RCAR_GP_PIN(5, 10),
				1907	};
				1908	static const unsigned int drif1_data1_c_mux[] = {
				1909	RIF1_D1_C_MARK,
				1910	};
				1911	/* - DRIF2 --------------------------------------------------------------- */
				1912	static const unsigned int drif2_ctrl_a_pins[] = {
				1913	/* CLK, SYNC */
				1914	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				1915	};
				1916	static const unsigned int drif2_ctrl_a_mux[] = {
				1917	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
				1918	};
				1919	static const unsigned int drif2_data0_a_pins[] = {
				1920	/* D0 */
				1921	RCAR_GP_PIN(6, 7),
				1922	};
				1923	static const unsigned int drif2_data0_a_mux[] = {
				1924	RIF2_D0_A_MARK,
				1925	};
				1926	static const unsigned int drif2_data1_a_pins[] = {
				1927	/* D1 */
				1928	RCAR_GP_PIN(6, 10),
				1929	};
				1930	static const unsigned int drif2_data1_a_mux[] = {
				1931	RIF2_D1_A_MARK,
				1932	};
				1933	static const unsigned int drif2_ctrl_b_pins[] = {
				1934	/* CLK, SYNC */
				1935	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				1936	};
				1937	static const unsigned int drif2_ctrl_b_mux[] = {
				1938	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
				1939	};
				1940	static const unsigned int drif2_data0_b_pins[] = {
				1941	/* D0 */
				1942	RCAR_GP_PIN(6, 30),
				1943	};
				1944	static const unsigned int drif2_data0_b_mux[] = {
				1945	RIF2_D0_B_MARK,
				1946	};
				1947	static const unsigned int drif2_data1_b_pins[] = {
				1948	/* D1 */
				1949	RCAR_GP_PIN(6, 31),
				1950	};
				1951	static const unsigned int drif2_data1_b_mux[] = {
				1952	RIF2_D1_B_MARK,
				1953	};
				1954	/* - DRIF3 --------------------------------------------------------------- */
				1955	static const unsigned int drif3_ctrl_a_pins[] = {
				1956	/* CLK, SYNC */
				1957	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				1958	};
				1959	static const unsigned int drif3_ctrl_a_mux[] = {
				1960	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
				1961	};
				1962	static const unsigned int drif3_data0_a_pins[] = {
				1963	/* D0 */
				1964	RCAR_GP_PIN(6, 19),
				1965	};
				1966	static const unsigned int drif3_data0_a_mux[] = {
				1967	RIF3_D0_A_MARK,
				1968	};
				1969	static const unsigned int drif3_data1_a_pins[] = {
				1970	/* D1 */
				1971	RCAR_GP_PIN(6, 20),
				1972	};
				1973	static const unsigned int drif3_data1_a_mux[] = {
				1974	RIF3_D1_A_MARK,
				1975	};
				1976	static const unsigned int drif3_ctrl_b_pins[] = {
				1977	/* CLK, SYNC */
				1978	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
				1979	};
				1980	static const unsigned int drif3_ctrl_b_mux[] = {
				1981	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
				1982	};
				1983	static const unsigned int drif3_data0_b_pins[] = {
				1984	/* D0 */
				1985	RCAR_GP_PIN(6, 28),
				1986	};
				1987	static const unsigned int drif3_data0_b_mux[] = {
				1988	RIF3_D0_B_MARK,
				1989	};
				1990	static const unsigned int drif3_data1_b_pins[] = {
				1991	/* D1 */
				1992	RCAR_GP_PIN(6, 29),
				1993	};
				1994	static const unsigned int drif3_data1_b_mux[] = {
				1995	RIF3_D1_B_MARK,
				1996	};
				1997
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	1998	/* - DU --------------------------------------------------------------------- */
				1999	static const unsigned int du_rgb666_pins[] = {
				2000	/* R[7:2], G[7:2], B[7:2] */
				2001	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
				2002	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				2003	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
				2004	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
				2005	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
				2006	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
				2007	};
				2008	static const unsigned int du_rgb666_mux[] = {
				2009	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
				2010	DU_DR3_MARK, DU_DR2_MARK,
				2011	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
				2012	DU_DG3_MARK, DU_DG2_MARK,
				2013	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
				2014	DU_DB3_MARK, DU_DB2_MARK,
				2015	};
				2016	static const unsigned int du_rgb888_pins[] = {
				2017	/* R[7:0], G[7:0], B[7:0] */
				2018	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
				2019	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				2020	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
				2021	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
				2022	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
				2023	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
				2024	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
				2025	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
				2026	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
				2027	};
				2028	static const unsigned int du_rgb888_mux[] = {
				2029	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
				2030	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
				2031	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
				2032	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
				2033	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
				2034	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
				2035	};
				2036	static const unsigned int du_clk_out_0_pins[] = {
				2037	/* CLKOUT */
				2038	RCAR_GP_PIN(1, 27),
				2039	};
				2040	static const unsigned int du_clk_out_0_mux[] = {
				2041	DU_DOTCLKOUT0_MARK
				2042	};
				2043	static const unsigned int du_clk_out_1_pins[] = {
				2044	/* CLKOUT */
				2045	RCAR_GP_PIN(2, 3),
				2046	};
				2047	static const unsigned int du_clk_out_1_mux[] = {
				2048	DU_DOTCLKOUT1_MARK
				2049	};
				2050	static const unsigned int du_sync_pins[] = {
				2051	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
				2052	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
				2053	};
				2054	static const unsigned int du_sync_mux[] = {
				2055	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
				2056	};
				2057	static const unsigned int du_oddf_pins[] = {
				2058	/* EXDISP/EXODDF/EXCDE */
				2059	RCAR_GP_PIN(2, 2),
				2060	};
				2061	static const unsigned int du_oddf_mux[] = {
				2062	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
				2063	};
				2064	static const unsigned int du_cde_pins[] = {
				2065	/* CDE */
				2066	RCAR_GP_PIN(2, 0),
				2067	};
				2068	static const unsigned int du_cde_mux[] = {
				2069	DU_CDE_MARK,
				2070	};
				2071	static const unsigned int du_disp_pins[] = {
				2072	/* DISP */
				2073	RCAR_GP_PIN(2, 1),
				2074	};
				2075	static const unsigned int du_disp_mux[] = {
				2076	DU_DISP_MARK,
				2077	};
				2078
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	2079	/* - I2C -------------------------------------------------------------------- */
				2080	static const unsigned int i2c1_a_pins[] = {
				2081	/* SDA, SCL */
				2082	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
				2083	};
				2084	static const unsigned int i2c1_a_mux[] = {
				2085	SDA1_A_MARK, SCL1_A_MARK,
				2086	};
				2087	static const unsigned int i2c1_b_pins[] = {
				2088	/* SDA, SCL */
				2089	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
				2090	};
				2091	static const unsigned int i2c1_b_mux[] = {
				2092	SDA1_B_MARK, SCL1_B_MARK,
				2093	};
				2094	static const unsigned int i2c2_a_pins[] = {
				2095	/* SDA, SCL */
				2096	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
				2097	};
				2098	static const unsigned int i2c2_a_mux[] = {
				2099	SDA2_A_MARK, SCL2_A_MARK,
				2100	};
				2101	static const unsigned int i2c2_b_pins[] = {
				2102	/* SDA, SCL */
				2103	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
				2104	};
				2105	static const unsigned int i2c2_b_mux[] = {
				2106	SDA2_B_MARK, SCL2_B_MARK,
				2107	};
				2108	static const unsigned int i2c6_a_pins[] = {
				2109	/* SDA, SCL */
				2110	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
				2111	};
				2112	static const unsigned int i2c6_a_mux[] = {
				2113	SDA6_A_MARK, SCL6_A_MARK,
				2114	};
				2115	static const unsigned int i2c6_b_pins[] = {
				2116	/* SDA, SCL */
				2117	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
				2118	};
				2119	static const unsigned int i2c6_b_mux[] = {
				2120	SDA6_B_MARK, SCL6_B_MARK,
				2121	};
				2122	static const unsigned int i2c6_c_pins[] = {
				2123	/* SDA, SCL */
				2124	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
				2125	};
				2126	static const unsigned int i2c6_c_mux[] = {
				2127	SDA6_C_MARK, SCL6_C_MARK,
				2128	};
				2129
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame^]	2130	/* - INTC-EX ---------------------------------------------------------------- */
				2131	static const unsigned int intc_ex_irq0_pins[] = {
				2132	/* IRQ0 */
				2133	RCAR_GP_PIN(2, 0),
				2134	};
				2135	static const unsigned int intc_ex_irq0_mux[] = {
				2136	IRQ0_MARK,
				2137	};
				2138	static const unsigned int intc_ex_irq1_pins[] = {
				2139	/* IRQ1 */
				2140	RCAR_GP_PIN(2, 1),
				2141	};
				2142	static const unsigned int intc_ex_irq1_mux[] = {
				2143	IRQ1_MARK,
				2144	};
				2145	static const unsigned int intc_ex_irq2_pins[] = {
				2146	/* IRQ2 */
				2147	RCAR_GP_PIN(2, 2),
				2148	};
				2149	static const unsigned int intc_ex_irq2_mux[] = {
				2150	IRQ2_MARK,
				2151	};
				2152	static const unsigned int intc_ex_irq3_pins[] = {
				2153	/* IRQ3 */
				2154	RCAR_GP_PIN(2, 3),
				2155	};
				2156	static const unsigned int intc_ex_irq3_mux[] = {
				2157	IRQ3_MARK,
				2158	};
				2159	static const unsigned int intc_ex_irq4_pins[] = {
				2160	/* IRQ4 */
				2161	RCAR_GP_PIN(2, 4),
				2162	};
				2163	static const unsigned int intc_ex_irq4_mux[] = {
				2164	IRQ4_MARK,
				2165	};
				2166	static const unsigned int intc_ex_irq5_pins[] = {
				2167	/* IRQ5 */
				2168	RCAR_GP_PIN(2, 5),
				2169	};
				2170	static const unsigned int intc_ex_irq5_mux[] = {
				2171	IRQ5_MARK,
				2172	};
				2173
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	2174	/* - MSIOF0 ----------------------------------------------------------------- */
				2175	static const unsigned int msiof0_clk_pins[] = {
				2176	/* SCK */
				2177	RCAR_GP_PIN(5, 17),
				2178	};
				2179	static const unsigned int msiof0_clk_mux[] = {
				2180	MSIOF0_SCK_MARK,
				2181	};
				2182	static const unsigned int msiof0_sync_pins[] = {
				2183	/* SYNC */
				2184	RCAR_GP_PIN(5, 18),
				2185	};
				2186	static const unsigned int msiof0_sync_mux[] = {
				2187	MSIOF0_SYNC_MARK,
				2188	};
				2189	static const unsigned int msiof0_ss1_pins[] = {
				2190	/* SS1 */
				2191	RCAR_GP_PIN(5, 19),
				2192	};
				2193	static const unsigned int msiof0_ss1_mux[] = {
				2194	MSIOF0_SS1_MARK,
				2195	};
				2196	static const unsigned int msiof0_ss2_pins[] = {
				2197	/* SS2 */
				2198	RCAR_GP_PIN(5, 21),
				2199	};
				2200	static const unsigned int msiof0_ss2_mux[] = {
				2201	MSIOF0_SS2_MARK,
				2202	};
				2203	static const unsigned int msiof0_txd_pins[] = {
				2204	/* TXD */
				2205	RCAR_GP_PIN(5, 20),
				2206	};
				2207	static const unsigned int msiof0_txd_mux[] = {
				2208	MSIOF0_TXD_MARK,
				2209	};
				2210	static const unsigned int msiof0_rxd_pins[] = {
				2211	/* RXD */
				2212	RCAR_GP_PIN(5, 22),
				2213	};
				2214	static const unsigned int msiof0_rxd_mux[] = {
				2215	MSIOF0_RXD_MARK,
				2216	};
				2217	/* - MSIOF1 ----------------------------------------------------------------- */
				2218	static const unsigned int msiof1_clk_a_pins[] = {
				2219	/* SCK */
				2220	RCAR_GP_PIN(6, 8),
				2221	};
				2222	static const unsigned int msiof1_clk_a_mux[] = {
				2223	MSIOF1_SCK_A_MARK,
				2224	};
				2225	static const unsigned int msiof1_sync_a_pins[] = {
				2226	/* SYNC */
				2227	RCAR_GP_PIN(6, 9),
				2228	};
				2229	static const unsigned int msiof1_sync_a_mux[] = {
				2230	MSIOF1_SYNC_A_MARK,
				2231	};
				2232	static const unsigned int msiof1_ss1_a_pins[] = {
				2233	/* SS1 */
				2234	RCAR_GP_PIN(6, 5),
				2235	};
				2236	static const unsigned int msiof1_ss1_a_mux[] = {
				2237	MSIOF1_SS1_A_MARK,
				2238	};
				2239	static const unsigned int msiof1_ss2_a_pins[] = {
				2240	/* SS2 */
				2241	RCAR_GP_PIN(6, 6),
				2242	};
				2243	static const unsigned int msiof1_ss2_a_mux[] = {
				2244	MSIOF1_SS2_A_MARK,
				2245	};
				2246	static const unsigned int msiof1_txd_a_pins[] = {
				2247	/* TXD */
				2248	RCAR_GP_PIN(6, 7),
				2249	};
				2250	static const unsigned int msiof1_txd_a_mux[] = {
				2251	MSIOF1_TXD_A_MARK,
				2252	};
				2253	static const unsigned int msiof1_rxd_a_pins[] = {
				2254	/* RXD */
				2255	RCAR_GP_PIN(6, 10),
				2256	};
				2257	static const unsigned int msiof1_rxd_a_mux[] = {
				2258	MSIOF1_RXD_A_MARK,
				2259	};
				2260	static const unsigned int msiof1_clk_b_pins[] = {
				2261	/* SCK */
				2262	RCAR_GP_PIN(5, 9),
				2263	};
				2264	static const unsigned int msiof1_clk_b_mux[] = {
				2265	MSIOF1_SCK_B_MARK,
				2266	};
				2267	static const unsigned int msiof1_sync_b_pins[] = {
				2268	/* SYNC */
				2269	RCAR_GP_PIN(5, 3),
				2270	};
				2271	static const unsigned int msiof1_sync_b_mux[] = {
				2272	MSIOF1_SYNC_B_MARK,
				2273	};
				2274	static const unsigned int msiof1_ss1_b_pins[] = {
				2275	/* SS1 */
				2276	RCAR_GP_PIN(5, 4),
				2277	};
				2278	static const unsigned int msiof1_ss1_b_mux[] = {
				2279	MSIOF1_SS1_B_MARK,
				2280	};
				2281	static const unsigned int msiof1_ss2_b_pins[] = {
				2282	/* SS2 */
				2283	RCAR_GP_PIN(5, 0),
				2284	};
				2285	static const unsigned int msiof1_ss2_b_mux[] = {
				2286	MSIOF1_SS2_B_MARK,
				2287	};
				2288	static const unsigned int msiof1_txd_b_pins[] = {
				2289	/* TXD */
				2290	RCAR_GP_PIN(5, 8),
				2291	};
				2292	static const unsigned int msiof1_txd_b_mux[] = {
				2293	MSIOF1_TXD_B_MARK,
				2294	};
				2295	static const unsigned int msiof1_rxd_b_pins[] = {
				2296	/* RXD */
				2297	RCAR_GP_PIN(5, 7),
				2298	};
				2299	static const unsigned int msiof1_rxd_b_mux[] = {
				2300	MSIOF1_RXD_B_MARK,
				2301	};
				2302	static const unsigned int msiof1_clk_c_pins[] = {
				2303	/* SCK */
				2304	RCAR_GP_PIN(6, 17),
				2305	};
				2306	static const unsigned int msiof1_clk_c_mux[] = {
				2307	MSIOF1_SCK_C_MARK,
				2308	};
				2309	static const unsigned int msiof1_sync_c_pins[] = {
				2310	/* SYNC */
				2311	RCAR_GP_PIN(6, 18),
				2312	};
				2313	static const unsigned int msiof1_sync_c_mux[] = {
				2314	MSIOF1_SYNC_C_MARK,
				2315	};
				2316	static const unsigned int msiof1_ss1_c_pins[] = {
				2317	/* SS1 */
				2318	RCAR_GP_PIN(6, 21),
				2319	};
				2320	static const unsigned int msiof1_ss1_c_mux[] = {
				2321	MSIOF1_SS1_C_MARK,
				2322	};
				2323	static const unsigned int msiof1_ss2_c_pins[] = {
				2324	/* SS2 */
				2325	RCAR_GP_PIN(6, 27),
				2326	};
				2327	static const unsigned int msiof1_ss2_c_mux[] = {
				2328	MSIOF1_SS2_C_MARK,
				2329	};
				2330	static const unsigned int msiof1_txd_c_pins[] = {
				2331	/* TXD */
				2332	RCAR_GP_PIN(6, 20),
				2333	};
				2334	static const unsigned int msiof1_txd_c_mux[] = {
				2335	MSIOF1_TXD_C_MARK,
				2336	};
				2337	static const unsigned int msiof1_rxd_c_pins[] = {
				2338	/* RXD */
				2339	RCAR_GP_PIN(6, 19),
				2340	};
				2341	static const unsigned int msiof1_rxd_c_mux[] = {
				2342	MSIOF1_RXD_C_MARK,
				2343	};
				2344	static const unsigned int msiof1_clk_d_pins[] = {
				2345	/* SCK */
				2346	RCAR_GP_PIN(5, 12),
				2347	};
				2348	static const unsigned int msiof1_clk_d_mux[] = {
				2349	MSIOF1_SCK_D_MARK,
				2350	};
				2351	static const unsigned int msiof1_sync_d_pins[] = {
				2352	/* SYNC */
				2353	RCAR_GP_PIN(5, 15),
				2354	};
				2355	static const unsigned int msiof1_sync_d_mux[] = {
				2356	MSIOF1_SYNC_D_MARK,
				2357	};
				2358	static const unsigned int msiof1_ss1_d_pins[] = {
				2359	/* SS1 */
				2360	RCAR_GP_PIN(5, 16),
				2361	};
				2362	static const unsigned int msiof1_ss1_d_mux[] = {
				2363	MSIOF1_SS1_D_MARK,
				2364	};
				2365	static const unsigned int msiof1_ss2_d_pins[] = {
				2366	/* SS2 */
				2367	RCAR_GP_PIN(5, 21),
				2368	};
				2369	static const unsigned int msiof1_ss2_d_mux[] = {
				2370	MSIOF1_SS2_D_MARK,
				2371	};
				2372	static const unsigned int msiof1_txd_d_pins[] = {
				2373	/* TXD */
				2374	RCAR_GP_PIN(5, 14),
				2375	};
				2376	static const unsigned int msiof1_txd_d_mux[] = {
				2377	MSIOF1_TXD_D_MARK,
				2378	};
				2379	static const unsigned int msiof1_rxd_d_pins[] = {
				2380	/* RXD */
				2381	RCAR_GP_PIN(5, 13),
				2382	};
				2383	static const unsigned int msiof1_rxd_d_mux[] = {
				2384	MSIOF1_RXD_D_MARK,
				2385	};
				2386	static const unsigned int msiof1_clk_e_pins[] = {
				2387	/* SCK */
				2388	RCAR_GP_PIN(3, 0),
				2389	};
				2390	static const unsigned int msiof1_clk_e_mux[] = {
				2391	MSIOF1_SCK_E_MARK,
				2392	};
				2393	static const unsigned int msiof1_sync_e_pins[] = {
				2394	/* SYNC */
				2395	RCAR_GP_PIN(3, 1),
				2396	};
				2397	static const unsigned int msiof1_sync_e_mux[] = {
				2398	MSIOF1_SYNC_E_MARK,
				2399	};
				2400	static const unsigned int msiof1_ss1_e_pins[] = {
				2401	/* SS1 */
				2402	RCAR_GP_PIN(3, 4),
				2403	};
				2404	static const unsigned int msiof1_ss1_e_mux[] = {
				2405	MSIOF1_SS1_E_MARK,
				2406	};
				2407	static const unsigned int msiof1_ss2_e_pins[] = {
				2408	/* SS2 */
				2409	RCAR_GP_PIN(3, 5),
				2410	};
				2411	static const unsigned int msiof1_ss2_e_mux[] = {
				2412	MSIOF1_SS2_E_MARK,
				2413	};
				2414	static const unsigned int msiof1_txd_e_pins[] = {
				2415	/* TXD */
				2416	RCAR_GP_PIN(3, 3),
				2417	};
				2418	static const unsigned int msiof1_txd_e_mux[] = {
				2419	MSIOF1_TXD_E_MARK,
				2420	};
				2421	static const unsigned int msiof1_rxd_e_pins[] = {
				2422	/* RXD */
				2423	RCAR_GP_PIN(3, 2),
				2424	};
				2425	static const unsigned int msiof1_rxd_e_mux[] = {
				2426	MSIOF1_RXD_E_MARK,
				2427	};
				2428	static const unsigned int msiof1_clk_f_pins[] = {
				2429	/* SCK */
				2430	RCAR_GP_PIN(5, 23),
				2431	};
				2432	static const unsigned int msiof1_clk_f_mux[] = {
				2433	MSIOF1_SCK_F_MARK,
				2434	};
				2435	static const unsigned int msiof1_sync_f_pins[] = {
				2436	/* SYNC */
				2437	RCAR_GP_PIN(5, 24),
				2438	};
				2439	static const unsigned int msiof1_sync_f_mux[] = {
				2440	MSIOF1_SYNC_F_MARK,
				2441	};
				2442	static const unsigned int msiof1_ss1_f_pins[] = {
				2443	/* SS1 */
				2444	RCAR_GP_PIN(6, 1),
				2445	};
				2446	static const unsigned int msiof1_ss1_f_mux[] = {
				2447	MSIOF1_SS1_F_MARK,
				2448	};
				2449	static const unsigned int msiof1_ss2_f_pins[] = {
				2450	/* SS2 */
				2451	RCAR_GP_PIN(6, 2),
				2452	};
				2453	static const unsigned int msiof1_ss2_f_mux[] = {
				2454	MSIOF1_SS2_F_MARK,
				2455	};
				2456	static const unsigned int msiof1_txd_f_pins[] = {
				2457	/* TXD */
				2458	RCAR_GP_PIN(6, 0),
				2459	};
				2460	static const unsigned int msiof1_txd_f_mux[] = {
				2461	MSIOF1_TXD_F_MARK,
				2462	};
				2463	static const unsigned int msiof1_rxd_f_pins[] = {
				2464	/* RXD */
				2465	RCAR_GP_PIN(5, 25),
				2466	};
				2467	static const unsigned int msiof1_rxd_f_mux[] = {
				2468	MSIOF1_RXD_F_MARK,
				2469	};
				2470	static const unsigned int msiof1_clk_g_pins[] = {
				2471	/* SCK */
				2472	RCAR_GP_PIN(3, 6),
				2473	};
				2474	static const unsigned int msiof1_clk_g_mux[] = {
				2475	MSIOF1_SCK_G_MARK,
				2476	};
				2477	static const unsigned int msiof1_sync_g_pins[] = {
				2478	/* SYNC */
				2479	RCAR_GP_PIN(3, 7),
				2480	};
				2481	static const unsigned int msiof1_sync_g_mux[] = {
				2482	MSIOF1_SYNC_G_MARK,
				2483	};
				2484	static const unsigned int msiof1_ss1_g_pins[] = {
				2485	/* SS1 */
				2486	RCAR_GP_PIN(3, 10),
				2487	};
				2488	static const unsigned int msiof1_ss1_g_mux[] = {
				2489	MSIOF1_SS1_G_MARK,
				2490	};
				2491	static const unsigned int msiof1_ss2_g_pins[] = {
				2492	/* SS2 */
				2493	RCAR_GP_PIN(3, 11),
				2494	};
				2495	static const unsigned int msiof1_ss2_g_mux[] = {
				2496	MSIOF1_SS2_G_MARK,
				2497	};
				2498	static const unsigned int msiof1_txd_g_pins[] = {
				2499	/* TXD */
				2500	RCAR_GP_PIN(3, 9),
				2501	};
				2502	static const unsigned int msiof1_txd_g_mux[] = {
				2503	MSIOF1_TXD_G_MARK,
				2504	};
				2505	static const unsigned int msiof1_rxd_g_pins[] = {
				2506	/* RXD */
				2507	RCAR_GP_PIN(3, 8),
				2508	};
				2509	static const unsigned int msiof1_rxd_g_mux[] = {
				2510	MSIOF1_RXD_G_MARK,
				2511	};
				2512	/* - MSIOF2 ----------------------------------------------------------------- */
				2513	static const unsigned int msiof2_clk_a_pins[] = {
				2514	/* SCK */
				2515	RCAR_GP_PIN(1, 9),
				2516	};
				2517	static const unsigned int msiof2_clk_a_mux[] = {
				2518	MSIOF2_SCK_A_MARK,
				2519	};
				2520	static const unsigned int msiof2_sync_a_pins[] = {
				2521	/* SYNC */
				2522	RCAR_GP_PIN(1, 8),
				2523	};
				2524	static const unsigned int msiof2_sync_a_mux[] = {
				2525	MSIOF2_SYNC_A_MARK,
				2526	};
				2527	static const unsigned int msiof2_ss1_a_pins[] = {
				2528	/* SS1 */
				2529	RCAR_GP_PIN(1, 6),
				2530	};
				2531	static const unsigned int msiof2_ss1_a_mux[] = {
				2532	MSIOF2_SS1_A_MARK,
				2533	};
				2534	static const unsigned int msiof2_ss2_a_pins[] = {
				2535	/* SS2 */
				2536	RCAR_GP_PIN(1, 7),
				2537	};
				2538	static const unsigned int msiof2_ss2_a_mux[] = {
				2539	MSIOF2_SS2_A_MARK,
				2540	};
				2541	static const unsigned int msiof2_txd_a_pins[] = {
				2542	/* TXD */
				2543	RCAR_GP_PIN(1, 11),
				2544	};
				2545	static const unsigned int msiof2_txd_a_mux[] = {
				2546	MSIOF2_TXD_A_MARK,
				2547	};
				2548	static const unsigned int msiof2_rxd_a_pins[] = {
				2549	/* RXD */
				2550	RCAR_GP_PIN(1, 10),
				2551	};
				2552	static const unsigned int msiof2_rxd_a_mux[] = {
				2553	MSIOF2_RXD_A_MARK,
				2554	};
				2555	static const unsigned int msiof2_clk_b_pins[] = {
				2556	/* SCK */
				2557	RCAR_GP_PIN(0, 4),
				2558	};
				2559	static const unsigned int msiof2_clk_b_mux[] = {
				2560	MSIOF2_SCK_B_MARK,
				2561	};
				2562	static const unsigned int msiof2_sync_b_pins[] = {
				2563	/* SYNC */
				2564	RCAR_GP_PIN(0, 5),
				2565	};
				2566	static const unsigned int msiof2_sync_b_mux[] = {
				2567	MSIOF2_SYNC_B_MARK,
				2568	};
				2569	static const unsigned int msiof2_ss1_b_pins[] = {
				2570	/* SS1 */
				2571	RCAR_GP_PIN(0, 0),
				2572	};
				2573	static const unsigned int msiof2_ss1_b_mux[] = {
				2574	MSIOF2_SS1_B_MARK,
				2575	};
				2576	static const unsigned int msiof2_ss2_b_pins[] = {
				2577	/* SS2 */
				2578	RCAR_GP_PIN(0, 1),
				2579	};
				2580	static const unsigned int msiof2_ss2_b_mux[] = {
				2581	MSIOF2_SS2_B_MARK,
				2582	};
				2583	static const unsigned int msiof2_txd_b_pins[] = {
				2584	/* TXD */
				2585	RCAR_GP_PIN(0, 7),
				2586	};
				2587	static const unsigned int msiof2_txd_b_mux[] = {
				2588	MSIOF2_TXD_B_MARK,
				2589	};
				2590	static const unsigned int msiof2_rxd_b_pins[] = {
				2591	/* RXD */
				2592	RCAR_GP_PIN(0, 6),
				2593	};
				2594	static const unsigned int msiof2_rxd_b_mux[] = {
				2595	MSIOF2_RXD_B_MARK,
				2596	};
				2597	static const unsigned int msiof2_clk_c_pins[] = {
				2598	/* SCK */
				2599	RCAR_GP_PIN(2, 12),
				2600	};
				2601	static const unsigned int msiof2_clk_c_mux[] = {
				2602	MSIOF2_SCK_C_MARK,
				2603	};
				2604	static const unsigned int msiof2_sync_c_pins[] = {
				2605	/* SYNC */
				2606	RCAR_GP_PIN(2, 11),
				2607	};
				2608	static const unsigned int msiof2_sync_c_mux[] = {
				2609	MSIOF2_SYNC_C_MARK,
				2610	};
				2611	static const unsigned int msiof2_ss1_c_pins[] = {
				2612	/* SS1 */
				2613	RCAR_GP_PIN(2, 10),
				2614	};
				2615	static const unsigned int msiof2_ss1_c_mux[] = {
				2616	MSIOF2_SS1_C_MARK,
				2617	};
				2618	static const unsigned int msiof2_ss2_c_pins[] = {
				2619	/* SS2 */
				2620	RCAR_GP_PIN(2, 9),
				2621	};
				2622	static const unsigned int msiof2_ss2_c_mux[] = {
				2623	MSIOF2_SS2_C_MARK,
				2624	};
				2625	static const unsigned int msiof2_txd_c_pins[] = {
				2626	/* TXD */
				2627	RCAR_GP_PIN(2, 14),
				2628	};
				2629	static const unsigned int msiof2_txd_c_mux[] = {
				2630	MSIOF2_TXD_C_MARK,
				2631	};
				2632	static const unsigned int msiof2_rxd_c_pins[] = {
				2633	/* RXD */
				2634	RCAR_GP_PIN(2, 13),
				2635	};
				2636	static const unsigned int msiof2_rxd_c_mux[] = {
				2637	MSIOF2_RXD_C_MARK,
				2638	};
				2639	static const unsigned int msiof2_clk_d_pins[] = {
				2640	/* SCK */
				2641	RCAR_GP_PIN(0, 8),
				2642	};
				2643	static const unsigned int msiof2_clk_d_mux[] = {
				2644	MSIOF2_SCK_D_MARK,
				2645	};
				2646	static const unsigned int msiof2_sync_d_pins[] = {
				2647	/* SYNC */
				2648	RCAR_GP_PIN(0, 9),
				2649	};
				2650	static const unsigned int msiof2_sync_d_mux[] = {
				2651	MSIOF2_SYNC_D_MARK,
				2652	};
				2653	static const unsigned int msiof2_ss1_d_pins[] = {
				2654	/* SS1 */
				2655	RCAR_GP_PIN(0, 12),
				2656	};
				2657	static const unsigned int msiof2_ss1_d_mux[] = {
				2658	MSIOF2_SS1_D_MARK,
				2659	};
				2660	static const unsigned int msiof2_ss2_d_pins[] = {
				2661	/* SS2 */
				2662	RCAR_GP_PIN(0, 13),
				2663	};
				2664	static const unsigned int msiof2_ss2_d_mux[] = {
				2665	MSIOF2_SS2_D_MARK,
				2666	};
				2667	static const unsigned int msiof2_txd_d_pins[] = {
				2668	/* TXD */
				2669	RCAR_GP_PIN(0, 11),
				2670	};
				2671	static const unsigned int msiof2_txd_d_mux[] = {
				2672	MSIOF2_TXD_D_MARK,
				2673	};
				2674	static const unsigned int msiof2_rxd_d_pins[] = {
				2675	/* RXD */
				2676	RCAR_GP_PIN(0, 10),
				2677	};
				2678	static const unsigned int msiof2_rxd_d_mux[] = {
				2679	MSIOF2_RXD_D_MARK,
				2680	};
				2681	/* - MSIOF3 ----------------------------------------------------------------- */
				2682	static const unsigned int msiof3_clk_a_pins[] = {
				2683	/* SCK */
				2684	RCAR_GP_PIN(0, 0),
				2685	};
				2686	static const unsigned int msiof3_clk_a_mux[] = {
				2687	MSIOF3_SCK_A_MARK,
				2688	};
				2689	static const unsigned int msiof3_sync_a_pins[] = {
				2690	/* SYNC */
				2691	RCAR_GP_PIN(0, 1),
				2692	};
				2693	static const unsigned int msiof3_sync_a_mux[] = {
				2694	MSIOF3_SYNC_A_MARK,
				2695	};
				2696	static const unsigned int msiof3_ss1_a_pins[] = {
				2697	/* SS1 */
				2698	RCAR_GP_PIN(0, 14),
				2699	};
				2700	static const unsigned int msiof3_ss1_a_mux[] = {
				2701	MSIOF3_SS1_A_MARK,
				2702	};
				2703	static const unsigned int msiof3_ss2_a_pins[] = {
				2704	/* SS2 */
				2705	RCAR_GP_PIN(0, 15),
				2706	};
				2707	static const unsigned int msiof3_ss2_a_mux[] = {
				2708	MSIOF3_SS2_A_MARK,
				2709	};
				2710	static const unsigned int msiof3_txd_a_pins[] = {
				2711	/* TXD */
				2712	RCAR_GP_PIN(0, 3),
				2713	};
				2714	static const unsigned int msiof3_txd_a_mux[] = {
				2715	MSIOF3_TXD_A_MARK,
				2716	};
				2717	static const unsigned int msiof3_rxd_a_pins[] = {
				2718	/* RXD */
				2719	RCAR_GP_PIN(0, 2),
				2720	};
				2721	static const unsigned int msiof3_rxd_a_mux[] = {
				2722	MSIOF3_RXD_A_MARK,
				2723	};
				2724	static const unsigned int msiof3_clk_b_pins[] = {
				2725	/* SCK */
				2726	RCAR_GP_PIN(1, 2),
				2727	};
				2728	static const unsigned int msiof3_clk_b_mux[] = {
				2729	MSIOF3_SCK_B_MARK,
				2730	};
				2731	static const unsigned int msiof3_sync_b_pins[] = {
				2732	/* SYNC */
				2733	RCAR_GP_PIN(1, 0),
				2734	};
				2735	static const unsigned int msiof3_sync_b_mux[] = {
				2736	MSIOF3_SYNC_B_MARK,
				2737	};
				2738	static const unsigned int msiof3_ss1_b_pins[] = {
				2739	/* SS1 */
				2740	RCAR_GP_PIN(1, 4),
				2741	};
				2742	static const unsigned int msiof3_ss1_b_mux[] = {
				2743	MSIOF3_SS1_B_MARK,
				2744	};
				2745	static const unsigned int msiof3_ss2_b_pins[] = {
				2746	/* SS2 */
				2747	RCAR_GP_PIN(1, 5),
				2748	};
				2749	static const unsigned int msiof3_ss2_b_mux[] = {
				2750	MSIOF3_SS2_B_MARK,
				2751	};
				2752	static const unsigned int msiof3_txd_b_pins[] = {
				2753	/* TXD */
				2754	RCAR_GP_PIN(1, 1),
				2755	};
				2756	static const unsigned int msiof3_txd_b_mux[] = {
				2757	MSIOF3_TXD_B_MARK,
				2758	};
				2759	static const unsigned int msiof3_rxd_b_pins[] = {
				2760	/* RXD */
				2761	RCAR_GP_PIN(1, 3),
				2762	};
				2763	static const unsigned int msiof3_rxd_b_mux[] = {
				2764	MSIOF3_RXD_B_MARK,
				2765	};
				2766	static const unsigned int msiof3_clk_c_pins[] = {
				2767	/* SCK */
				2768	RCAR_GP_PIN(1, 12),
				2769	};
				2770	static const unsigned int msiof3_clk_c_mux[] = {
				2771	MSIOF3_SCK_C_MARK,
				2772	};
				2773	static const unsigned int msiof3_sync_c_pins[] = {
				2774	/* SYNC */
				2775	RCAR_GP_PIN(1, 13),
				2776	};
				2777	static const unsigned int msiof3_sync_c_mux[] = {
				2778	MSIOF3_SYNC_C_MARK,
				2779	};
				2780	static const unsigned int msiof3_txd_c_pins[] = {
				2781	/* TXD */
				2782	RCAR_GP_PIN(1, 15),
				2783	};
				2784	static const unsigned int msiof3_txd_c_mux[] = {
				2785	MSIOF3_TXD_C_MARK,
				2786	};
				2787	static const unsigned int msiof3_rxd_c_pins[] = {
				2788	/* RXD */
				2789	RCAR_GP_PIN(1, 14),
				2790	};
				2791	static const unsigned int msiof3_rxd_c_mux[] = {
				2792	MSIOF3_RXD_C_MARK,
				2793	};
				2794	static const unsigned int msiof3_clk_d_pins[] = {
				2795	/* SCK */
				2796	RCAR_GP_PIN(1, 22),
				2797	};
				2798	static const unsigned int msiof3_clk_d_mux[] = {
				2799	MSIOF3_SCK_D_MARK,
				2800	};
				2801	static const unsigned int msiof3_sync_d_pins[] = {
				2802	/* SYNC */
				2803	RCAR_GP_PIN(1, 23),
				2804	};
				2805	static const unsigned int msiof3_sync_d_mux[] = {
				2806	MSIOF3_SYNC_D_MARK,
				2807	};
				2808	static const unsigned int msiof3_ss1_d_pins[] = {
				2809	/* SS1 */
				2810	RCAR_GP_PIN(1, 26),
				2811	};
				2812	static const unsigned int msiof3_ss1_d_mux[] = {
				2813	MSIOF3_SS1_D_MARK,
				2814	};
				2815	static const unsigned int msiof3_txd_d_pins[] = {
				2816	/* TXD */
				2817	RCAR_GP_PIN(1, 25),
				2818	};
				2819	static const unsigned int msiof3_txd_d_mux[] = {
				2820	MSIOF3_TXD_D_MARK,
				2821	};
				2822	static const unsigned int msiof3_rxd_d_pins[] = {
				2823	/* RXD */
				2824	RCAR_GP_PIN(1, 24),
				2825	};
				2826	static const unsigned int msiof3_rxd_d_mux[] = {
				2827	MSIOF3_RXD_D_MARK,
				2828	};
				2829	static const unsigned int msiof3_clk_e_pins[] = {
				2830	/* SCK */
				2831	RCAR_GP_PIN(2, 3),
				2832	};
				2833	static const unsigned int msiof3_clk_e_mux[] = {
				2834	MSIOF3_SCK_E_MARK,
				2835	};
				2836	static const unsigned int msiof3_sync_e_pins[] = {
				2837	/* SYNC */
				2838	RCAR_GP_PIN(2, 2),
				2839	};
				2840	static const unsigned int msiof3_sync_e_mux[] = {
				2841	MSIOF3_SYNC_E_MARK,
				2842	};
				2843	static const unsigned int msiof3_ss1_e_pins[] = {
				2844	/* SS1 */
				2845	RCAR_GP_PIN(2, 1),
				2846	};
				2847	static const unsigned int msiof3_ss1_e_mux[] = {
				2848	MSIOF3_SS1_E_MARK,
				2849	};
				2850	static const unsigned int msiof3_ss2_e_pins[] = {
				2851	/* SS1 */
				2852	RCAR_GP_PIN(2, 0),
				2853	};
				2854	static const unsigned int msiof3_ss2_e_mux[] = {
				2855	MSIOF3_SS2_E_MARK,
				2856	};
				2857	static const unsigned int msiof3_txd_e_pins[] = {
				2858	/* TXD */
				2859	RCAR_GP_PIN(2, 5),
				2860	};
				2861	static const unsigned int msiof3_txd_e_mux[] = {
				2862	MSIOF3_TXD_E_MARK,
				2863	};
				2864	static const unsigned int msiof3_rxd_e_pins[] = {
				2865	/* RXD */
				2866	RCAR_GP_PIN(2, 4),
				2867	};
				2868	static const unsigned int msiof3_rxd_e_mux[] = {
				2869	MSIOF3_RXD_E_MARK,
				2870	};
				2871
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	2872	/* - PWM0 --------------------------------------------------------------------*/
				2873	static const unsigned int pwm0_pins[] = {
				2874	/* PWM */
				2875	RCAR_GP_PIN(2, 6),
				2876	};
				2877	static const unsigned int pwm0_mux[] = {
				2878	PWM0_MARK,
				2879	};
				2880	/* - PWM1 --------------------------------------------------------------------*/
				2881	static const unsigned int pwm1_a_pins[] = {
				2882	/* PWM */
				2883	RCAR_GP_PIN(2, 7),
				2884	};
				2885	static const unsigned int pwm1_a_mux[] = {
				2886	PWM1_A_MARK,
				2887	};
				2888	static const unsigned int pwm1_b_pins[] = {
				2889	/* PWM */
				2890	RCAR_GP_PIN(1, 8),
				2891	};
				2892	static const unsigned int pwm1_b_mux[] = {
				2893	PWM1_B_MARK,
				2894	};
				2895	/* - PWM2 --------------------------------------------------------------------*/
				2896	static const unsigned int pwm2_a_pins[] = {
				2897	/* PWM */
				2898	RCAR_GP_PIN(2, 8),
				2899	};
				2900	static const unsigned int pwm2_a_mux[] = {
				2901	PWM2_A_MARK,
				2902	};
				2903	static const unsigned int pwm2_b_pins[] = {
				2904	/* PWM */
				2905	RCAR_GP_PIN(1, 11),
				2906	};
				2907	static const unsigned int pwm2_b_mux[] = {
				2908	PWM2_B_MARK,
				2909	};
				2910	/* - PWM3 --------------------------------------------------------------------*/
				2911	static const unsigned int pwm3_a_pins[] = {
				2912	/* PWM */
				2913	RCAR_GP_PIN(1, 0),
				2914	};
				2915	static const unsigned int pwm3_a_mux[] = {
				2916	PWM3_A_MARK,
				2917	};
				2918	static const unsigned int pwm3_b_pins[] = {
				2919	/* PWM */
				2920	RCAR_GP_PIN(2, 2),
				2921	};
				2922	static const unsigned int pwm3_b_mux[] = {
				2923	PWM3_B_MARK,
				2924	};
				2925	/* - PWM4 --------------------------------------------------------------------*/
				2926	static const unsigned int pwm4_a_pins[] = {
				2927	/* PWM */
				2928	RCAR_GP_PIN(1, 1),
				2929	};
				2930	static const unsigned int pwm4_a_mux[] = {
				2931	PWM4_A_MARK,
				2932	};
				2933	static const unsigned int pwm4_b_pins[] = {
				2934	/* PWM */
				2935	RCAR_GP_PIN(2, 3),
				2936	};
				2937	static const unsigned int pwm4_b_mux[] = {
				2938	PWM4_B_MARK,
				2939	};
				2940	/* - PWM5 --------------------------------------------------------------------*/
				2941	static const unsigned int pwm5_a_pins[] = {
				2942	/* PWM */
				2943	RCAR_GP_PIN(1, 2),
				2944	};
				2945	static const unsigned int pwm5_a_mux[] = {
				2946	PWM5_A_MARK,
				2947	};
				2948	static const unsigned int pwm5_b_pins[] = {
				2949	/* PWM */
				2950	RCAR_GP_PIN(2, 4),
				2951	};
				2952	static const unsigned int pwm5_b_mux[] = {
				2953	PWM5_B_MARK,
				2954	};
				2955	/* - PWM6 --------------------------------------------------------------------*/
				2956	static const unsigned int pwm6_a_pins[] = {
				2957	/* PWM */
				2958	RCAR_GP_PIN(1, 3),
				2959	};
				2960	static const unsigned int pwm6_a_mux[] = {
				2961	PWM6_A_MARK,
				2962	};
				2963	static const unsigned int pwm6_b_pins[] = {
				2964	/* PWM */
				2965	RCAR_GP_PIN(2, 5),
				2966	};
				2967	static const unsigned int pwm6_b_mux[] = {
				2968	PWM6_B_MARK,
				2969	};
				2970
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	2971	/* - SCIF0 ------------------------------------------------------------------ */
				2972	static const unsigned int scif0_data_pins[] = {
				2973	/* RX, TX */
				2974	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
				2975	};
				2976	static const unsigned int scif0_data_mux[] = {
				2977	RX0_MARK, TX0_MARK,
				2978	};
				2979	static const unsigned int scif0_clk_pins[] = {
				2980	/* SCK */
				2981	RCAR_GP_PIN(5, 0),
				2982	};
				2983	static const unsigned int scif0_clk_mux[] = {
				2984	SCK0_MARK,
				2985	};
				2986	static const unsigned int scif0_ctrl_pins[] = {
				2987	/* RTS, CTS */
				2988	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
				2989	};
				2990	static const unsigned int scif0_ctrl_mux[] = {
				2991	RTS0_N_TANS_MARK, CTS0_N_MARK,
				2992	};
				2993	/* - SCIF1 ------------------------------------------------------------------ */
				2994	static const unsigned int scif1_data_a_pins[] = {
				2995	/* RX, TX */
				2996	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
				2997	};
				2998	static const unsigned int scif1_data_a_mux[] = {
				2999	RX1_A_MARK, TX1_A_MARK,
				3000	};
				3001	static const unsigned int scif1_clk_pins[] = {
				3002	/* SCK */
				3003	RCAR_GP_PIN(6, 21),
				3004	};
				3005	static const unsigned int scif1_clk_mux[] = {
				3006	SCK1_MARK,
				3007	};
				3008	static const unsigned int scif1_ctrl_pins[] = {
				3009	/* RTS, CTS */
				3010	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
				3011	};
				3012	static const unsigned int scif1_ctrl_mux[] = {
				3013	RTS1_N_TANS_MARK, CTS1_N_MARK,
				3014	};
				3015
				3016	static const unsigned int scif1_data_b_pins[] = {
				3017	/* RX, TX */
				3018	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
				3019	};
				3020	static const unsigned int scif1_data_b_mux[] = {
				3021	RX1_B_MARK, TX1_B_MARK,
				3022	};
				3023	/* - SCIF2 ------------------------------------------------------------------ */
				3024	static const unsigned int scif2_data_a_pins[] = {
				3025	/* RX, TX */
				3026	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
				3027	};
				3028	static const unsigned int scif2_data_a_mux[] = {
				3029	RX2_A_MARK, TX2_A_MARK,
				3030	};
				3031	static const unsigned int scif2_clk_pins[] = {
				3032	/* SCK */
				3033	RCAR_GP_PIN(5, 9),
				3034	};
				3035	static const unsigned int scif2_clk_mux[] = {
				3036	SCK2_MARK,
				3037	};
				3038	static const unsigned int scif2_data_b_pins[] = {
				3039	/* RX, TX */
				3040	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
				3041	};
				3042	static const unsigned int scif2_data_b_mux[] = {
				3043	RX2_B_MARK, TX2_B_MARK,
				3044	};
				3045	/* - SCIF3 ------------------------------------------------------------------ */
				3046	static const unsigned int scif3_data_a_pins[] = {
				3047	/* RX, TX */
				3048	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
				3049	};
				3050	static const unsigned int scif3_data_a_mux[] = {
				3051	RX3_A_MARK, TX3_A_MARK,
				3052	};
				3053	static const unsigned int scif3_clk_pins[] = {
				3054	/* SCK */
				3055	RCAR_GP_PIN(1, 22),
				3056	};
				3057	static const unsigned int scif3_clk_mux[] = {
				3058	SCK3_MARK,
				3059	};
				3060	static const unsigned int scif3_ctrl_pins[] = {
				3061	/* RTS, CTS */
				3062	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
				3063	};
				3064	static const unsigned int scif3_ctrl_mux[] = {
				3065	RTS3_N_TANS_MARK, CTS3_N_MARK,
				3066	};
				3067	static const unsigned int scif3_data_b_pins[] = {
				3068	/* RX, TX */
				3069	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
				3070	};
				3071	static const unsigned int scif3_data_b_mux[] = {
				3072	RX3_B_MARK, TX3_B_MARK,
				3073	};
				3074	/* - SCIF4 ------------------------------------------------------------------ */
				3075	static const unsigned int scif4_data_a_pins[] = {
				3076	/* RX, TX */
				3077	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
				3078	};
				3079	static const unsigned int scif4_data_a_mux[] = {
				3080	RX4_A_MARK, TX4_A_MARK,
				3081	};
				3082	static const unsigned int scif4_clk_a_pins[] = {
				3083	/* SCK */
				3084	RCAR_GP_PIN(2, 10),
				3085	};
				3086	static const unsigned int scif4_clk_a_mux[] = {
				3087	SCK4_A_MARK,
				3088	};
				3089	static const unsigned int scif4_ctrl_a_pins[] = {
				3090	/* RTS, CTS */
				3091	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
				3092	};
				3093	static const unsigned int scif4_ctrl_a_mux[] = {
				3094	RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
				3095	};
				3096	static const unsigned int scif4_data_b_pins[] = {
				3097	/* RX, TX */
				3098	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
				3099	};
				3100	static const unsigned int scif4_data_b_mux[] = {
				3101	RX4_B_MARK, TX4_B_MARK,
				3102	};
				3103	static const unsigned int scif4_clk_b_pins[] = {
				3104	/* SCK */
				3105	RCAR_GP_PIN(1, 5),
				3106	};
				3107	static const unsigned int scif4_clk_b_mux[] = {
				3108	SCK4_B_MARK,
				3109	};
				3110	static const unsigned int scif4_ctrl_b_pins[] = {
				3111	/* RTS, CTS */
				3112	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
				3113	};
				3114	static const unsigned int scif4_ctrl_b_mux[] = {
				3115	RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
				3116	};
				3117	static const unsigned int scif4_data_c_pins[] = {
				3118	/* RX, TX */
				3119	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
				3120	};
				3121	static const unsigned int scif4_data_c_mux[] = {
				3122	RX4_C_MARK, TX4_C_MARK,
				3123	};
				3124	static const unsigned int scif4_clk_c_pins[] = {
				3125	/* SCK */
				3126	RCAR_GP_PIN(0, 8),
				3127	};
				3128	static const unsigned int scif4_clk_c_mux[] = {
				3129	SCK4_C_MARK,
				3130	};
				3131	static const unsigned int scif4_ctrl_c_pins[] = {
				3132	/* RTS, CTS */
				3133	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
				3134	};
				3135	static const unsigned int scif4_ctrl_c_mux[] = {
				3136	RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
				3137	};
				3138	/* - SCIF5 ------------------------------------------------------------------ */
				3139	static const unsigned int scif5_data_a_pins[] = {
				3140	/* RX, TX */
				3141	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
				3142	};
				3143	static const unsigned int scif5_data_a_mux[] = {
				3144	RX5_A_MARK, TX5_A_MARK,
				3145	};
				3146	static const unsigned int scif5_clk_a_pins[] = {
				3147	/* SCK */
				3148	RCAR_GP_PIN(6, 21),
				3149	};
				3150	static const unsigned int scif5_clk_a_mux[] = {
				3151	SCK5_A_MARK,
				3152	};
				3153	static const unsigned int scif5_data_b_pins[] = {
				3154	/* RX, TX */
				3155	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
				3156	};
				3157	static const unsigned int scif5_data_b_mux[] = {
				3158	RX5_B_MARK, TX5_B_MARK,
				3159	};
				3160	static const unsigned int scif5_clk_b_pins[] = {
				3161	/* SCK */
				3162	RCAR_GP_PIN(5, 0),
				3163	};
				3164	static const unsigned int scif5_clk_b_mux[] = {
				3165	SCK5_B_MARK,
				3166	};
				3167
Geert Uytterhoeven	b4062b4	2017-10-05 12:14:00 +0200	[diff] [blame]	3168	/* - SCIF Clock ------------------------------------------------------------- */
				3169	static const unsigned int scif_clk_a_pins[] = {
				3170	/* SCIF_CLK */
				3171	RCAR_GP_PIN(6, 23),
				3172	};
				3173	static const unsigned int scif_clk_a_mux[] = {
				3174	SCIF_CLK_A_MARK,
				3175	};
				3176	static const unsigned int scif_clk_b_pins[] = {
				3177	/* SCIF_CLK */
				3178	RCAR_GP_PIN(5, 9),
				3179	};
				3180	static const unsigned int scif_clk_b_mux[] = {
				3181	SCIF_CLK_B_MARK,
				3182	};
				3183
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	3184	/* - SDHI0 ------------------------------------------------------------------ */
				3185	static const unsigned int sdhi0_data1_pins[] = {
				3186	/* D0 */
				3187	RCAR_GP_PIN(3, 2),
				3188	};
				3189	static const unsigned int sdhi0_data1_mux[] = {
				3190	SD0_DAT0_MARK,
				3191	};
				3192	static const unsigned int sdhi0_data4_pins[] = {
				3193	/* D[0:3] */
				3194	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
				3195	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
				3196	};
				3197	static const unsigned int sdhi0_data4_mux[] = {
				3198	SD0_DAT0_MARK, SD0_DAT1_MARK,
				3199	SD0_DAT2_MARK, SD0_DAT3_MARK,
				3200	};
				3201	static const unsigned int sdhi0_ctrl_pins[] = {
				3202	/* CLK, CMD */
				3203	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
				3204	};
				3205	static const unsigned int sdhi0_ctrl_mux[] = {
				3206	SD0_CLK_MARK, SD0_CMD_MARK,
				3207	};
				3208	static const unsigned int sdhi0_cd_pins[] = {
				3209	/* CD */
				3210	RCAR_GP_PIN(3, 12),
				3211	};
				3212	static const unsigned int sdhi0_cd_mux[] = {
				3213	SD0_CD_MARK,
				3214	};
				3215	static const unsigned int sdhi0_wp_pins[] = {
				3216	/* WP */
				3217	RCAR_GP_PIN(3, 13),
				3218	};
				3219	static const unsigned int sdhi0_wp_mux[] = {
				3220	SD0_WP_MARK,
				3221	};
				3222	/* - SDHI1 ------------------------------------------------------------------ */
				3223	static const unsigned int sdhi1_data1_pins[] = {
				3224	/* D0 */
				3225	RCAR_GP_PIN(3, 8),
				3226	};
				3227	static const unsigned int sdhi1_data1_mux[] = {
				3228	SD1_DAT0_MARK,
				3229	};
				3230	static const unsigned int sdhi1_data4_pins[] = {
				3231	/* D[0:3] */
				3232	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
				3233	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
				3234	};
				3235	static const unsigned int sdhi1_data4_mux[] = {
				3236	SD1_DAT0_MARK, SD1_DAT1_MARK,
				3237	SD1_DAT2_MARK, SD1_DAT3_MARK,
				3238	};
				3239	static const unsigned int sdhi1_ctrl_pins[] = {
				3240	/* CLK, CMD */
				3241	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
				3242	};
				3243	static const unsigned int sdhi1_ctrl_mux[] = {
				3244	SD1_CLK_MARK, SD1_CMD_MARK,
				3245	};
				3246	static const unsigned int sdhi1_cd_pins[] = {
				3247	/* CD */
				3248	RCAR_GP_PIN(3, 14),
				3249	};
				3250	static const unsigned int sdhi1_cd_mux[] = {
				3251	SD1_CD_MARK,
				3252	};
				3253	static const unsigned int sdhi1_wp_pins[] = {
				3254	/* WP */
				3255	RCAR_GP_PIN(3, 15),
				3256	};
				3257	static const unsigned int sdhi1_wp_mux[] = {
				3258	SD1_WP_MARK,
				3259	};
				3260	/* - SDHI2 ------------------------------------------------------------------ */
				3261	static const unsigned int sdhi2_data1_pins[] = {
				3262	/* D0 */
				3263	RCAR_GP_PIN(4, 2),
				3264	};
				3265	static const unsigned int sdhi2_data1_mux[] = {
				3266	SD2_DAT0_MARK,
				3267	};
				3268	static const unsigned int sdhi2_data4_pins[] = {
				3269	/* D[0:3] */
				3270	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
				3271	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
				3272	};
				3273	static const unsigned int sdhi2_data4_mux[] = {
				3274	SD2_DAT0_MARK, SD2_DAT1_MARK,
				3275	SD2_DAT2_MARK, SD2_DAT3_MARK,
				3276	};
				3277	static const unsigned int sdhi2_data8_pins[] = {
				3278	/* D[0:7] */
				3279	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
				3280	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
				3281	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
				3282	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
				3283	};
				3284	static const unsigned int sdhi2_data8_mux[] = {
				3285	SD2_DAT0_MARK, SD2_DAT1_MARK,
				3286	SD2_DAT2_MARK, SD2_DAT3_MARK,
				3287	SD2_DAT4_MARK, SD2_DAT5_MARK,
				3288	SD2_DAT6_MARK, SD2_DAT7_MARK,
				3289	};
				3290	static const unsigned int sdhi2_ctrl_pins[] = {
				3291	/* CLK, CMD */
				3292	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
				3293	};
				3294	static const unsigned int sdhi2_ctrl_mux[] = {
				3295	SD2_CLK_MARK, SD2_CMD_MARK,
				3296	};
				3297	static const unsigned int sdhi2_cd_a_pins[] = {
				3298	/* CD */
				3299	RCAR_GP_PIN(4, 13),
				3300	};
				3301	static const unsigned int sdhi2_cd_a_mux[] = {
				3302	SD2_CD_A_MARK,
				3303	};
				3304	static const unsigned int sdhi2_cd_b_pins[] = {
				3305	/* CD */
				3306	RCAR_GP_PIN(5, 10),
				3307	};
				3308	static const unsigned int sdhi2_cd_b_mux[] = {
				3309	SD2_CD_B_MARK,
				3310	};
				3311	static const unsigned int sdhi2_wp_a_pins[] = {
				3312	/* WP */
				3313	RCAR_GP_PIN(4, 14),
				3314	};
				3315	static const unsigned int sdhi2_wp_a_mux[] = {
				3316	SD2_WP_A_MARK,
				3317	};
				3318	static const unsigned int sdhi2_wp_b_pins[] = {
				3319	/* WP */
				3320	RCAR_GP_PIN(5, 11),
				3321	};
				3322	static const unsigned int sdhi2_wp_b_mux[] = {
				3323	SD2_WP_B_MARK,
				3324	};
				3325	static const unsigned int sdhi2_ds_pins[] = {
				3326	/* DS */
				3327	RCAR_GP_PIN(4, 6),
				3328	};
				3329	static const unsigned int sdhi2_ds_mux[] = {
				3330	SD2_DS_MARK,
				3331	};
				3332	/* - SDHI3 ------------------------------------------------------------------ */
				3333	static const unsigned int sdhi3_data1_pins[] = {
				3334	/* D0 */
				3335	RCAR_GP_PIN(4, 9),
				3336	};
				3337	static const unsigned int sdhi3_data1_mux[] = {
				3338	SD3_DAT0_MARK,
				3339	};
				3340	static const unsigned int sdhi3_data4_pins[] = {
				3341	/* D[0:3] */
				3342	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
				3343	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
				3344	};
				3345	static const unsigned int sdhi3_data4_mux[] = {
				3346	SD3_DAT0_MARK, SD3_DAT1_MARK,
				3347	SD3_DAT2_MARK, SD3_DAT3_MARK,
				3348	};
				3349	static const unsigned int sdhi3_data8_pins[] = {
				3350	/* D[0:7] */
				3351	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
				3352	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
				3353	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
				3354	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
				3355	};
				3356	static const unsigned int sdhi3_data8_mux[] = {
				3357	SD3_DAT0_MARK, SD3_DAT1_MARK,
				3358	SD3_DAT2_MARK, SD3_DAT3_MARK,
				3359	SD3_DAT4_MARK, SD3_DAT5_MARK,
				3360	SD3_DAT6_MARK, SD3_DAT7_MARK,
				3361	};
				3362	static const unsigned int sdhi3_ctrl_pins[] = {
				3363	/* CLK, CMD */
				3364	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
				3365	};
				3366	static const unsigned int sdhi3_ctrl_mux[] = {
				3367	SD3_CLK_MARK, SD3_CMD_MARK,
				3368	};
				3369	static const unsigned int sdhi3_cd_pins[] = {
				3370	/* CD */
				3371	RCAR_GP_PIN(4, 15),
				3372	};
				3373	static const unsigned int sdhi3_cd_mux[] = {
				3374	SD3_CD_MARK,
				3375	};
				3376	static const unsigned int sdhi3_wp_pins[] = {
				3377	/* WP */
				3378	RCAR_GP_PIN(4, 16),
				3379	};
				3380	static const unsigned int sdhi3_wp_mux[] = {
				3381	SD3_WP_MARK,
				3382	};
				3383	static const unsigned int sdhi3_ds_pins[] = {
				3384	/* DS */
				3385	RCAR_GP_PIN(4, 17),
				3386	};
				3387	static const unsigned int sdhi3_ds_mux[] = {
				3388	SD3_DS_MARK,
				3389	};
				3390
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	3391	/* - SSI -------------------------------------------------------------------- */
				3392	static const unsigned int ssi0_data_pins[] = {
				3393	/* SDATA */
				3394	RCAR_GP_PIN(6, 2),
				3395	};
				3396	static const unsigned int ssi0_data_mux[] = {
				3397	SSI_SDATA0_MARK,
				3398	};
				3399	static const unsigned int ssi01239_ctrl_pins[] = {
				3400	/* SCK, WS */
				3401	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
				3402	};
				3403	static const unsigned int ssi01239_ctrl_mux[] = {
				3404	SSI_SCK01239_MARK, SSI_WS01239_MARK,
				3405	};
				3406	static const unsigned int ssi1_data_a_pins[] = {
				3407	/* SDATA */
				3408	RCAR_GP_PIN(6, 3),
				3409	};
				3410	static const unsigned int ssi1_data_a_mux[] = {
				3411	SSI_SDATA1_A_MARK,
				3412	};
				3413	static const unsigned int ssi1_data_b_pins[] = {
				3414	/* SDATA */
				3415	RCAR_GP_PIN(5, 12),
				3416	};
				3417	static const unsigned int ssi1_data_b_mux[] = {
				3418	SSI_SDATA1_B_MARK,
				3419	};
				3420	static const unsigned int ssi1_ctrl_a_pins[] = {
				3421	/* SCK, WS */
				3422	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				3423	};
				3424	static const unsigned int ssi1_ctrl_a_mux[] = {
				3425	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
				3426	};
				3427	static const unsigned int ssi1_ctrl_b_pins[] = {
				3428	/* SCK, WS */
				3429	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
				3430	};
				3431	static const unsigned int ssi1_ctrl_b_mux[] = {
				3432	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
				3433	};
				3434	static const unsigned int ssi2_data_a_pins[] = {
				3435	/* SDATA */
				3436	RCAR_GP_PIN(6, 4),
				3437	};
				3438	static const unsigned int ssi2_data_a_mux[] = {
				3439	SSI_SDATA2_A_MARK,
				3440	};
				3441	static const unsigned int ssi2_data_b_pins[] = {
				3442	/* SDATA */
				3443	RCAR_GP_PIN(5, 13),
				3444	};
				3445	static const unsigned int ssi2_data_b_mux[] = {
				3446	SSI_SDATA2_B_MARK,
				3447	};
				3448	static const unsigned int ssi2_ctrl_a_pins[] = {
				3449	/* SCK, WS */
				3450	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
				3451	};
				3452	static const unsigned int ssi2_ctrl_a_mux[] = {
				3453	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
				3454	};
				3455	static const unsigned int ssi2_ctrl_b_pins[] = {
				3456	/* SCK, WS */
				3457	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
				3458	};
				3459	static const unsigned int ssi2_ctrl_b_mux[] = {
				3460	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
				3461	};
				3462	static const unsigned int ssi3_data_pins[] = {
				3463	/* SDATA */
				3464	RCAR_GP_PIN(6, 7),
				3465	};
				3466	static const unsigned int ssi3_data_mux[] = {
				3467	SSI_SDATA3_MARK,
				3468	};
				3469	static const unsigned int ssi349_ctrl_pins[] = {
				3470	/* SCK, WS */
				3471	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
				3472	};
				3473	static const unsigned int ssi349_ctrl_mux[] = {
				3474	SSI_SCK349_MARK, SSI_WS349_MARK,
				3475	};
				3476	static const unsigned int ssi4_data_pins[] = {
				3477	/* SDATA */
				3478	RCAR_GP_PIN(6, 10),
				3479	};
				3480	static const unsigned int ssi4_data_mux[] = {
				3481	SSI_SDATA4_MARK,
				3482	};
				3483	static const unsigned int ssi4_ctrl_pins[] = {
				3484	/* SCK, WS */
				3485	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
				3486	};
				3487	static const unsigned int ssi4_ctrl_mux[] = {
				3488	SSI_SCK4_MARK, SSI_WS4_MARK,
				3489	};
				3490	static const unsigned int ssi5_data_pins[] = {
				3491	/* SDATA */
				3492	RCAR_GP_PIN(6, 13),
				3493	};
				3494	static const unsigned int ssi5_data_mux[] = {
				3495	SSI_SDATA5_MARK,
				3496	};
				3497	static const unsigned int ssi5_ctrl_pins[] = {
				3498	/* SCK, WS */
				3499	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
				3500	};
				3501	static const unsigned int ssi5_ctrl_mux[] = {
				3502	SSI_SCK5_MARK, SSI_WS5_MARK,
				3503	};
				3504	static const unsigned int ssi6_data_pins[] = {
				3505	/* SDATA */
				3506	RCAR_GP_PIN(6, 16),
				3507	};
				3508	static const unsigned int ssi6_data_mux[] = {
				3509	SSI_SDATA6_MARK,
				3510	};
				3511	static const unsigned int ssi6_ctrl_pins[] = {
				3512	/* SCK, WS */
				3513	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
				3514	};
				3515	static const unsigned int ssi6_ctrl_mux[] = {
				3516	SSI_SCK6_MARK, SSI_WS6_MARK,
				3517	};
				3518	static const unsigned int ssi7_data_pins[] = {
				3519	/* SDATA */
				3520	RCAR_GP_PIN(6, 19),
				3521	};
				3522	static const unsigned int ssi7_data_mux[] = {
				3523	SSI_SDATA7_MARK,
				3524	};
				3525	static const unsigned int ssi78_ctrl_pins[] = {
				3526	/* SCK, WS */
				3527	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
				3528	};
				3529	static const unsigned int ssi78_ctrl_mux[] = {
				3530	SSI_SCK78_MARK, SSI_WS78_MARK,
				3531	};
				3532	static const unsigned int ssi8_data_pins[] = {
				3533	/* SDATA */
				3534	RCAR_GP_PIN(6, 20),
				3535	};
				3536	static const unsigned int ssi8_data_mux[] = {
				3537	SSI_SDATA8_MARK,
				3538	};
				3539	static const unsigned int ssi9_data_a_pins[] = {
				3540	/* SDATA */
				3541	RCAR_GP_PIN(6, 21),
				3542	};
				3543	static const unsigned int ssi9_data_a_mux[] = {
				3544	SSI_SDATA9_A_MARK,
				3545	};
				3546	static const unsigned int ssi9_data_b_pins[] = {
				3547	/* SDATA */
				3548	RCAR_GP_PIN(5, 14),
				3549	};
				3550	static const unsigned int ssi9_data_b_mux[] = {
				3551	SSI_SDATA9_B_MARK,
				3552	};
				3553	static const unsigned int ssi9_ctrl_a_pins[] = {
				3554	/* SCK, WS */
				3555	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
				3556	};
				3557	static const unsigned int ssi9_ctrl_a_mux[] = {
				3558	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
				3559	};
				3560	static const unsigned int ssi9_ctrl_b_pins[] = {
				3561	/* SCK, WS */
				3562	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
				3563	};
				3564	static const unsigned int ssi9_ctrl_b_mux[] = {
				3565	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
				3566	};
				3567
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	3568	/* - USB0 ------------------------------------------------------------------- */
				3569	static const unsigned int usb0_pins[] = {
				3570	/* PWEN, OVC */
				3571	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
				3572	};
				3573	static const unsigned int usb0_mux[] = {
				3574	USB0_PWEN_MARK, USB0_OVC_MARK,
				3575	};
				3576	/* - USB1 ------------------------------------------------------------------- */
				3577	static const unsigned int usb1_pins[] = {
				3578	/* PWEN, OVC */
				3579	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
				3580	};
				3581	static const unsigned int usb1_mux[] = {
				3582	USB1_PWEN_MARK, USB1_OVC_MARK,
				3583	};
				3584	/* - USB2 ------------------------------------------------------------------- */
				3585	static const unsigned int usb2_pins[] = {
				3586	/* PWEN, OVC */
				3587	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
				3588	};
				3589	static const unsigned int usb2_mux[] = {
				3590	USB2_PWEN_MARK, USB2_OVC_MARK,
				3591	};
				3592	/* - USB2_CH3 --------------------------------------------------------------- */
				3593	static const unsigned int usb2_ch3_pins[] = {
				3594	/* PWEN, OVC */
				3595	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
				3596	};
				3597	static const unsigned int usb2_ch3_mux[] = {
				3598	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
				3599	};
				3600
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	3601	/* - USB30 ------------------------------------------------------------------ */
				3602	static const unsigned int usb30_pins[] = {
				3603	/* PWEN, OVC */
				3604	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
				3605	};
				3606	static const unsigned int usb30_mux[] = {
				3607	USB30_PWEN_MARK, USB30_OVC_MARK,
				3608	};
				3609
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	3610	static const struct sh_pfc_pin_group pinmux_groups[] = {
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	3611	SH_PFC_PIN_GROUP(audio_clk_a_a),
				3612	SH_PFC_PIN_GROUP(audio_clk_a_b),
				3613	SH_PFC_PIN_GROUP(audio_clk_a_c),
				3614	SH_PFC_PIN_GROUP(audio_clk_b_a),
				3615	SH_PFC_PIN_GROUP(audio_clk_b_b),
				3616	SH_PFC_PIN_GROUP(audio_clk_c_a),
				3617	SH_PFC_PIN_GROUP(audio_clk_c_b),
				3618	SH_PFC_PIN_GROUP(audio_clkout_a),
				3619	SH_PFC_PIN_GROUP(audio_clkout_b),
				3620	SH_PFC_PIN_GROUP(audio_clkout_c),
				3621	SH_PFC_PIN_GROUP(audio_clkout_d),
				3622	SH_PFC_PIN_GROUP(audio_clkout1_a),
				3623	SH_PFC_PIN_GROUP(audio_clkout1_b),
				3624	SH_PFC_PIN_GROUP(audio_clkout2_a),
				3625	SH_PFC_PIN_GROUP(audio_clkout2_b),
				3626	SH_PFC_PIN_GROUP(audio_clkout3_a),
				3627	SH_PFC_PIN_GROUP(audio_clkout3_b),
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	3628	SH_PFC_PIN_GROUP(avb_link),
				3629	SH_PFC_PIN_GROUP(avb_magic),
				3630	SH_PFC_PIN_GROUP(avb_phy_int),
				3631	SH_PFC_PIN_GROUP(avb_mdc),
				3632	SH_PFC_PIN_GROUP(avb_mii),
				3633	SH_PFC_PIN_GROUP(avb_avtp_pps),
				3634	SH_PFC_PIN_GROUP(avb_avtp_match_a),
				3635	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
				3636	SH_PFC_PIN_GROUP(avb_avtp_match_b),
				3637	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	3638	SH_PFC_PIN_GROUP(drif0_ctrl_a),
				3639	SH_PFC_PIN_GROUP(drif0_data0_a),
				3640	SH_PFC_PIN_GROUP(drif0_data1_a),
				3641	SH_PFC_PIN_GROUP(drif0_ctrl_b),
				3642	SH_PFC_PIN_GROUP(drif0_data0_b),
				3643	SH_PFC_PIN_GROUP(drif0_data1_b),
				3644	SH_PFC_PIN_GROUP(drif0_ctrl_c),
				3645	SH_PFC_PIN_GROUP(drif0_data0_c),
				3646	SH_PFC_PIN_GROUP(drif0_data1_c),
				3647	SH_PFC_PIN_GROUP(drif1_ctrl_a),
				3648	SH_PFC_PIN_GROUP(drif1_data0_a),
				3649	SH_PFC_PIN_GROUP(drif1_data1_a),
				3650	SH_PFC_PIN_GROUP(drif1_ctrl_b),
				3651	SH_PFC_PIN_GROUP(drif1_data0_b),
				3652	SH_PFC_PIN_GROUP(drif1_data1_b),
				3653	SH_PFC_PIN_GROUP(drif1_ctrl_c),
				3654	SH_PFC_PIN_GROUP(drif1_data0_c),
				3655	SH_PFC_PIN_GROUP(drif1_data1_c),
				3656	SH_PFC_PIN_GROUP(drif2_ctrl_a),
				3657	SH_PFC_PIN_GROUP(drif2_data0_a),
				3658	SH_PFC_PIN_GROUP(drif2_data1_a),
				3659	SH_PFC_PIN_GROUP(drif2_ctrl_b),
				3660	SH_PFC_PIN_GROUP(drif2_data0_b),
				3661	SH_PFC_PIN_GROUP(drif2_data1_b),
				3662	SH_PFC_PIN_GROUP(drif3_ctrl_a),
				3663	SH_PFC_PIN_GROUP(drif3_data0_a),
				3664	SH_PFC_PIN_GROUP(drif3_data1_a),
				3665	SH_PFC_PIN_GROUP(drif3_ctrl_b),
				3666	SH_PFC_PIN_GROUP(drif3_data0_b),
				3667	SH_PFC_PIN_GROUP(drif3_data1_b),
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	3668	SH_PFC_PIN_GROUP(du_rgb666),
				3669	SH_PFC_PIN_GROUP(du_rgb888),
				3670	SH_PFC_PIN_GROUP(du_clk_out_0),
				3671	SH_PFC_PIN_GROUP(du_clk_out_1),
				3672	SH_PFC_PIN_GROUP(du_sync),
				3673	SH_PFC_PIN_GROUP(du_oddf),
				3674	SH_PFC_PIN_GROUP(du_cde),
				3675	SH_PFC_PIN_GROUP(du_disp),
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	3676	SH_PFC_PIN_GROUP(i2c1_a),
				3677	SH_PFC_PIN_GROUP(i2c1_b),
				3678	SH_PFC_PIN_GROUP(i2c2_a),
				3679	SH_PFC_PIN_GROUP(i2c2_b),
				3680	SH_PFC_PIN_GROUP(i2c6_a),
				3681	SH_PFC_PIN_GROUP(i2c6_b),
				3682	SH_PFC_PIN_GROUP(i2c6_c),
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame^]	3683	SH_PFC_PIN_GROUP(intc_ex_irq0),
				3684	SH_PFC_PIN_GROUP(intc_ex_irq1),
				3685	SH_PFC_PIN_GROUP(intc_ex_irq2),
				3686	SH_PFC_PIN_GROUP(intc_ex_irq3),
				3687	SH_PFC_PIN_GROUP(intc_ex_irq4),
				3688	SH_PFC_PIN_GROUP(intc_ex_irq5),
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	3689	SH_PFC_PIN_GROUP(msiof0_clk),
				3690	SH_PFC_PIN_GROUP(msiof0_sync),
				3691	SH_PFC_PIN_GROUP(msiof0_ss1),
				3692	SH_PFC_PIN_GROUP(msiof0_ss2),
				3693	SH_PFC_PIN_GROUP(msiof0_txd),
				3694	SH_PFC_PIN_GROUP(msiof0_rxd),
				3695	SH_PFC_PIN_GROUP(msiof1_clk_a),
				3696	SH_PFC_PIN_GROUP(msiof1_sync_a),
				3697	SH_PFC_PIN_GROUP(msiof1_ss1_a),
				3698	SH_PFC_PIN_GROUP(msiof1_ss2_a),
				3699	SH_PFC_PIN_GROUP(msiof1_txd_a),
				3700	SH_PFC_PIN_GROUP(msiof1_rxd_a),
				3701	SH_PFC_PIN_GROUP(msiof1_clk_b),
				3702	SH_PFC_PIN_GROUP(msiof1_sync_b),
				3703	SH_PFC_PIN_GROUP(msiof1_ss1_b),
				3704	SH_PFC_PIN_GROUP(msiof1_ss2_b),
				3705	SH_PFC_PIN_GROUP(msiof1_txd_b),
				3706	SH_PFC_PIN_GROUP(msiof1_rxd_b),
				3707	SH_PFC_PIN_GROUP(msiof1_clk_c),
				3708	SH_PFC_PIN_GROUP(msiof1_sync_c),
				3709	SH_PFC_PIN_GROUP(msiof1_ss1_c),
				3710	SH_PFC_PIN_GROUP(msiof1_ss2_c),
				3711	SH_PFC_PIN_GROUP(msiof1_txd_c),
				3712	SH_PFC_PIN_GROUP(msiof1_rxd_c),
				3713	SH_PFC_PIN_GROUP(msiof1_clk_d),
				3714	SH_PFC_PIN_GROUP(msiof1_sync_d),
				3715	SH_PFC_PIN_GROUP(msiof1_ss1_d),
				3716	SH_PFC_PIN_GROUP(msiof1_ss2_d),
				3717	SH_PFC_PIN_GROUP(msiof1_txd_d),
				3718	SH_PFC_PIN_GROUP(msiof1_rxd_d),
				3719	SH_PFC_PIN_GROUP(msiof1_clk_e),
				3720	SH_PFC_PIN_GROUP(msiof1_sync_e),
				3721	SH_PFC_PIN_GROUP(msiof1_ss1_e),
				3722	SH_PFC_PIN_GROUP(msiof1_ss2_e),
				3723	SH_PFC_PIN_GROUP(msiof1_txd_e),
				3724	SH_PFC_PIN_GROUP(msiof1_rxd_e),
				3725	SH_PFC_PIN_GROUP(msiof1_clk_f),
				3726	SH_PFC_PIN_GROUP(msiof1_sync_f),
				3727	SH_PFC_PIN_GROUP(msiof1_ss1_f),
				3728	SH_PFC_PIN_GROUP(msiof1_ss2_f),
				3729	SH_PFC_PIN_GROUP(msiof1_txd_f),
				3730	SH_PFC_PIN_GROUP(msiof1_rxd_f),
				3731	SH_PFC_PIN_GROUP(msiof1_clk_g),
				3732	SH_PFC_PIN_GROUP(msiof1_sync_g),
				3733	SH_PFC_PIN_GROUP(msiof1_ss1_g),
				3734	SH_PFC_PIN_GROUP(msiof1_ss2_g),
				3735	SH_PFC_PIN_GROUP(msiof1_txd_g),
				3736	SH_PFC_PIN_GROUP(msiof1_rxd_g),
				3737	SH_PFC_PIN_GROUP(msiof2_clk_a),
				3738	SH_PFC_PIN_GROUP(msiof2_sync_a),
				3739	SH_PFC_PIN_GROUP(msiof2_ss1_a),
				3740	SH_PFC_PIN_GROUP(msiof2_ss2_a),
				3741	SH_PFC_PIN_GROUP(msiof2_txd_a),
				3742	SH_PFC_PIN_GROUP(msiof2_rxd_a),
				3743	SH_PFC_PIN_GROUP(msiof2_clk_b),
				3744	SH_PFC_PIN_GROUP(msiof2_sync_b),
				3745	SH_PFC_PIN_GROUP(msiof2_ss1_b),
				3746	SH_PFC_PIN_GROUP(msiof2_ss2_b),
				3747	SH_PFC_PIN_GROUP(msiof2_txd_b),
				3748	SH_PFC_PIN_GROUP(msiof2_rxd_b),
				3749	SH_PFC_PIN_GROUP(msiof2_clk_c),
				3750	SH_PFC_PIN_GROUP(msiof2_sync_c),
				3751	SH_PFC_PIN_GROUP(msiof2_ss1_c),
				3752	SH_PFC_PIN_GROUP(msiof2_ss2_c),
				3753	SH_PFC_PIN_GROUP(msiof2_txd_c),
				3754	SH_PFC_PIN_GROUP(msiof2_rxd_c),
				3755	SH_PFC_PIN_GROUP(msiof2_clk_d),
				3756	SH_PFC_PIN_GROUP(msiof2_sync_d),
				3757	SH_PFC_PIN_GROUP(msiof2_ss1_d),
				3758	SH_PFC_PIN_GROUP(msiof2_ss2_d),
				3759	SH_PFC_PIN_GROUP(msiof2_txd_d),
				3760	SH_PFC_PIN_GROUP(msiof2_rxd_d),
				3761	SH_PFC_PIN_GROUP(msiof3_clk_a),
				3762	SH_PFC_PIN_GROUP(msiof3_sync_a),
				3763	SH_PFC_PIN_GROUP(msiof3_ss1_a),
				3764	SH_PFC_PIN_GROUP(msiof3_ss2_a),
				3765	SH_PFC_PIN_GROUP(msiof3_txd_a),
				3766	SH_PFC_PIN_GROUP(msiof3_rxd_a),
				3767	SH_PFC_PIN_GROUP(msiof3_clk_b),
				3768	SH_PFC_PIN_GROUP(msiof3_sync_b),
				3769	SH_PFC_PIN_GROUP(msiof3_ss1_b),
				3770	SH_PFC_PIN_GROUP(msiof3_ss2_b),
				3771	SH_PFC_PIN_GROUP(msiof3_txd_b),
				3772	SH_PFC_PIN_GROUP(msiof3_rxd_b),
				3773	SH_PFC_PIN_GROUP(msiof3_clk_c),
				3774	SH_PFC_PIN_GROUP(msiof3_sync_c),
				3775	SH_PFC_PIN_GROUP(msiof3_txd_c),
				3776	SH_PFC_PIN_GROUP(msiof3_rxd_c),
				3777	SH_PFC_PIN_GROUP(msiof3_clk_d),
				3778	SH_PFC_PIN_GROUP(msiof3_sync_d),
				3779	SH_PFC_PIN_GROUP(msiof3_ss1_d),
				3780	SH_PFC_PIN_GROUP(msiof3_txd_d),
				3781	SH_PFC_PIN_GROUP(msiof3_rxd_d),
				3782	SH_PFC_PIN_GROUP(msiof3_clk_e),
				3783	SH_PFC_PIN_GROUP(msiof3_sync_e),
				3784	SH_PFC_PIN_GROUP(msiof3_ss1_e),
				3785	SH_PFC_PIN_GROUP(msiof3_ss2_e),
				3786	SH_PFC_PIN_GROUP(msiof3_txd_e),
				3787	SH_PFC_PIN_GROUP(msiof3_rxd_e),
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	3788	SH_PFC_PIN_GROUP(pwm0),
				3789	SH_PFC_PIN_GROUP(pwm1_a),
				3790	SH_PFC_PIN_GROUP(pwm1_b),
				3791	SH_PFC_PIN_GROUP(pwm2_a),
				3792	SH_PFC_PIN_GROUP(pwm2_b),
				3793	SH_PFC_PIN_GROUP(pwm3_a),
				3794	SH_PFC_PIN_GROUP(pwm3_b),
				3795	SH_PFC_PIN_GROUP(pwm4_a),
				3796	SH_PFC_PIN_GROUP(pwm4_b),
				3797	SH_PFC_PIN_GROUP(pwm5_a),
				3798	SH_PFC_PIN_GROUP(pwm5_b),
				3799	SH_PFC_PIN_GROUP(pwm6_a),
				3800	SH_PFC_PIN_GROUP(pwm6_b),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3801	SH_PFC_PIN_GROUP(scif0_data),
				3802	SH_PFC_PIN_GROUP(scif0_clk),
				3803	SH_PFC_PIN_GROUP(scif0_ctrl),
				3804	SH_PFC_PIN_GROUP(scif1_data_a),
				3805	SH_PFC_PIN_GROUP(scif1_clk),
				3806	SH_PFC_PIN_GROUP(scif1_ctrl),
				3807	SH_PFC_PIN_GROUP(scif1_data_b),
				3808	SH_PFC_PIN_GROUP(scif2_data_a),
				3809	SH_PFC_PIN_GROUP(scif2_clk),
				3810	SH_PFC_PIN_GROUP(scif2_data_b),
				3811	SH_PFC_PIN_GROUP(scif3_data_a),
				3812	SH_PFC_PIN_GROUP(scif3_clk),
				3813	SH_PFC_PIN_GROUP(scif3_ctrl),
				3814	SH_PFC_PIN_GROUP(scif3_data_b),
				3815	SH_PFC_PIN_GROUP(scif4_data_a),
				3816	SH_PFC_PIN_GROUP(scif4_clk_a),
				3817	SH_PFC_PIN_GROUP(scif4_ctrl_a),
				3818	SH_PFC_PIN_GROUP(scif4_data_b),
				3819	SH_PFC_PIN_GROUP(scif4_clk_b),
				3820	SH_PFC_PIN_GROUP(scif4_ctrl_b),
				3821	SH_PFC_PIN_GROUP(scif4_data_c),
				3822	SH_PFC_PIN_GROUP(scif4_clk_c),
				3823	SH_PFC_PIN_GROUP(scif4_ctrl_c),
				3824	SH_PFC_PIN_GROUP(scif5_data_a),
				3825	SH_PFC_PIN_GROUP(scif5_clk_a),
				3826	SH_PFC_PIN_GROUP(scif5_data_b),
				3827	SH_PFC_PIN_GROUP(scif5_clk_b),
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	3828	SH_PFC_PIN_GROUP(scif_clk_a),
				3829	SH_PFC_PIN_GROUP(scif_clk_b),
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	3830	SH_PFC_PIN_GROUP(sdhi0_data1),
				3831	SH_PFC_PIN_GROUP(sdhi0_data4),
				3832	SH_PFC_PIN_GROUP(sdhi0_ctrl),
				3833	SH_PFC_PIN_GROUP(sdhi0_cd),
				3834	SH_PFC_PIN_GROUP(sdhi0_wp),
				3835	SH_PFC_PIN_GROUP(sdhi1_data1),
				3836	SH_PFC_PIN_GROUP(sdhi1_data4),
				3837	SH_PFC_PIN_GROUP(sdhi1_ctrl),
				3838	SH_PFC_PIN_GROUP(sdhi1_cd),
				3839	SH_PFC_PIN_GROUP(sdhi1_wp),
				3840	SH_PFC_PIN_GROUP(sdhi2_data1),
				3841	SH_PFC_PIN_GROUP(sdhi2_data4),
				3842	SH_PFC_PIN_GROUP(sdhi2_data8),
				3843	SH_PFC_PIN_GROUP(sdhi2_ctrl),
				3844	SH_PFC_PIN_GROUP(sdhi2_cd_a),
				3845	SH_PFC_PIN_GROUP(sdhi2_wp_a),
				3846	SH_PFC_PIN_GROUP(sdhi2_cd_b),
				3847	SH_PFC_PIN_GROUP(sdhi2_wp_b),
				3848	SH_PFC_PIN_GROUP(sdhi2_ds),
				3849	SH_PFC_PIN_GROUP(sdhi3_data1),
				3850	SH_PFC_PIN_GROUP(sdhi3_data4),
				3851	SH_PFC_PIN_GROUP(sdhi3_data8),
				3852	SH_PFC_PIN_GROUP(sdhi3_ctrl),
				3853	SH_PFC_PIN_GROUP(sdhi3_cd),
				3854	SH_PFC_PIN_GROUP(sdhi3_wp),
				3855	SH_PFC_PIN_GROUP(sdhi3_ds),
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	3856	SH_PFC_PIN_GROUP(ssi0_data),
				3857	SH_PFC_PIN_GROUP(ssi01239_ctrl),
				3858	SH_PFC_PIN_GROUP(ssi1_data_a),
				3859	SH_PFC_PIN_GROUP(ssi1_data_b),
				3860	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
				3861	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
				3862	SH_PFC_PIN_GROUP(ssi2_data_a),
				3863	SH_PFC_PIN_GROUP(ssi2_data_b),
				3864	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
				3865	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
				3866	SH_PFC_PIN_GROUP(ssi3_data),
				3867	SH_PFC_PIN_GROUP(ssi349_ctrl),
				3868	SH_PFC_PIN_GROUP(ssi4_data),
				3869	SH_PFC_PIN_GROUP(ssi4_ctrl),
				3870	SH_PFC_PIN_GROUP(ssi5_data),
				3871	SH_PFC_PIN_GROUP(ssi5_ctrl),
				3872	SH_PFC_PIN_GROUP(ssi6_data),
				3873	SH_PFC_PIN_GROUP(ssi6_ctrl),
				3874	SH_PFC_PIN_GROUP(ssi7_data),
				3875	SH_PFC_PIN_GROUP(ssi78_ctrl),
				3876	SH_PFC_PIN_GROUP(ssi8_data),
				3877	SH_PFC_PIN_GROUP(ssi9_data_a),
				3878	SH_PFC_PIN_GROUP(ssi9_data_b),
				3879	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
				3880	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	3881	SH_PFC_PIN_GROUP(usb0),
				3882	SH_PFC_PIN_GROUP(usb1),
				3883	SH_PFC_PIN_GROUP(usb2),
				3884	SH_PFC_PIN_GROUP(usb2_ch3),
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	3885	SH_PFC_PIN_GROUP(usb30),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	3886	};
				3887
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	3888	static const char * const audio_clk_groups[] = {
				3889	"audio_clk_a_a",
				3890	"audio_clk_a_b",
				3891	"audio_clk_a_c",
				3892	"audio_clk_b_a",
				3893	"audio_clk_b_b",
				3894	"audio_clk_c_a",
				3895	"audio_clk_c_b",
				3896	"audio_clkout_a",
				3897	"audio_clkout_b",
				3898	"audio_clkout_c",
				3899	"audio_clkout_d",
				3900	"audio_clkout1_a",
				3901	"audio_clkout1_b",
				3902	"audio_clkout2_a",
				3903	"audio_clkout2_b",
				3904	"audio_clkout3_a",
				3905	"audio_clkout3_b",
				3906	};
				3907
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	3908	static const char * const avb_groups[] = {
				3909	"avb_link",
				3910	"avb_magic",
				3911	"avb_phy_int",
				3912	"avb_mdc",
				3913	"avb_mii",
				3914	"avb_avtp_pps",
				3915	"avb_avtp_match_a",
				3916	"avb_avtp_capture_a",
				3917	"avb_avtp_match_b",
				3918	"avb_avtp_capture_b",
				3919	};
				3920
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	3921	static const char * const drif0_groups[] = {
				3922	"drif0_ctrl_a",
				3923	"drif0_data0_a",
				3924	"drif0_data1_a",
				3925	"drif0_ctrl_b",
				3926	"drif0_data0_b",
				3927	"drif0_data1_b",
				3928	"drif0_ctrl_c",
				3929	"drif0_data0_c",
				3930	"drif0_data1_c",
				3931	};
				3932
				3933	static const char * const drif1_groups[] = {
				3934	"drif1_ctrl_a",
				3935	"drif1_data0_a",
				3936	"drif1_data1_a",
				3937	"drif1_ctrl_b",
				3938	"drif1_data0_b",
				3939	"drif1_data1_b",
				3940	"drif1_ctrl_c",
				3941	"drif1_data0_c",
				3942	"drif1_data1_c",
				3943	};
				3944
				3945	static const char * const drif2_groups[] = {
				3946	"drif2_ctrl_a",
				3947	"drif2_data0_a",
				3948	"drif2_data1_a",
				3949	"drif2_ctrl_b",
				3950	"drif2_data0_b",
				3951	"drif2_data1_b",
				3952	};
				3953
				3954	static const char * const drif3_groups[] = {
				3955	"drif3_ctrl_a",
				3956	"drif3_data0_a",
				3957	"drif3_data1_a",
				3958	"drif3_ctrl_b",
				3959	"drif3_data0_b",
				3960	"drif3_data1_b",
				3961	};
				3962
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	3963	static const char * const du_groups[] = {
				3964	"du_rgb666",
				3965	"du_rgb888",
				3966	"du_clk_out_0",
				3967	"du_clk_out_1",
				3968	"du_sync",
				3969	"du_oddf",
				3970	"du_cde",
				3971	"du_disp",
				3972	};
				3973
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	3974	static const char * const i2c1_groups[] = {
				3975	"i2c1_a",
				3976	"i2c1_b",
				3977	};
				3978
				3979	static const char * const i2c2_groups[] = {
				3980	"i2c2_a",
				3981	"i2c2_b",
				3982	};
				3983
				3984	static const char * const i2c6_groups[] = {
				3985	"i2c6_a",
				3986	"i2c6_b",
				3987	"i2c6_c",
				3988	};
				3989
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame^]	3990	static const char * const intc_ex_groups[] = {
				3991	"intc_ex_irq0",
				3992	"intc_ex_irq1",
				3993	"intc_ex_irq2",
				3994	"intc_ex_irq3",
				3995	"intc_ex_irq4",
				3996	"intc_ex_irq5",
				3997	};
				3998
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	3999	static const char * const msiof0_groups[] = {
				4000	"msiof0_clk",
				4001	"msiof0_sync",
				4002	"msiof0_ss1",
				4003	"msiof0_ss2",
				4004	"msiof0_txd",
				4005	"msiof0_rxd",
				4006	};
				4007
				4008	static const char * const msiof1_groups[] = {
				4009	"msiof1_clk_a",
				4010	"msiof1_sync_a",
				4011	"msiof1_ss1_a",
				4012	"msiof1_ss2_a",
				4013	"msiof1_txd_a",
				4014	"msiof1_rxd_a",
				4015	"msiof1_clk_b",
				4016	"msiof1_sync_b",
				4017	"msiof1_ss1_b",
				4018	"msiof1_ss2_b",
				4019	"msiof1_txd_b",
				4020	"msiof1_rxd_b",
				4021	"msiof1_clk_c",
				4022	"msiof1_sync_c",
				4023	"msiof1_ss1_c",
				4024	"msiof1_ss2_c",
				4025	"msiof1_txd_c",
				4026	"msiof1_rxd_c",
				4027	"msiof1_clk_d",
				4028	"msiof1_sync_d",
				4029	"msiof1_ss1_d",
				4030	"msiof1_ss2_d",
				4031	"msiof1_txd_d",
				4032	"msiof1_rxd_d",
				4033	"msiof1_clk_e",
				4034	"msiof1_sync_e",
				4035	"msiof1_ss1_e",
				4036	"msiof1_ss2_e",
				4037	"msiof1_txd_e",
				4038	"msiof1_rxd_e",
				4039	"msiof1_clk_f",
				4040	"msiof1_sync_f",
				4041	"msiof1_ss1_f",
				4042	"msiof1_ss2_f",
				4043	"msiof1_txd_f",
				4044	"msiof1_rxd_f",
				4045	"msiof1_clk_g",
				4046	"msiof1_sync_g",
				4047	"msiof1_ss1_g",
				4048	"msiof1_ss2_g",
				4049	"msiof1_txd_g",
				4050	"msiof1_rxd_g",
				4051	};
				4052
				4053	static const char * const msiof2_groups[] = {
				4054	"msiof2_clk_a",
				4055	"msiof2_sync_a",
				4056	"msiof2_ss1_a",
				4057	"msiof2_ss2_a",
				4058	"msiof2_txd_a",
				4059	"msiof2_rxd_a",
				4060	"msiof2_clk_b",
				4061	"msiof2_sync_b",
				4062	"msiof2_ss1_b",
				4063	"msiof2_ss2_b",
				4064	"msiof2_txd_b",
				4065	"msiof2_rxd_b",
				4066	"msiof2_clk_c",
				4067	"msiof2_sync_c",
				4068	"msiof2_ss1_c",
				4069	"msiof2_ss2_c",
				4070	"msiof2_txd_c",
				4071	"msiof2_rxd_c",
				4072	"msiof2_clk_d",
				4073	"msiof2_sync_d",
				4074	"msiof2_ss1_d",
				4075	"msiof2_ss2_d",
				4076	"msiof2_txd_d",
				4077	"msiof2_rxd_d",
				4078	};
				4079
				4080	static const char * const msiof3_groups[] = {
				4081	"msiof3_clk_a",
				4082	"msiof3_sync_a",
				4083	"msiof3_ss1_a",
				4084	"msiof3_ss2_a",
				4085	"msiof3_txd_a",
				4086	"msiof3_rxd_a",
				4087	"msiof3_clk_b",
				4088	"msiof3_sync_b",
				4089	"msiof3_ss1_b",
				4090	"msiof3_ss2_b",
				4091	"msiof3_txd_b",
				4092	"msiof3_rxd_b",
				4093	"msiof3_clk_c",
				4094	"msiof3_sync_c",
				4095	"msiof3_txd_c",
				4096	"msiof3_rxd_c",
				4097	"msiof3_clk_d",
				4098	"msiof3_sync_d",
				4099	"msiof3_ss1_d",
				4100	"msiof3_txd_d",
				4101	"msiof3_rxd_d",
				4102	"msiof3_clk_e",
				4103	"msiof3_sync_e",
				4104	"msiof3_ss1_e",
				4105	"msiof3_ss2_e",
				4106	"msiof3_txd_e",
				4107	"msiof3_rxd_e",
				4108	};
				4109
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	4110	static const char * const pwm0_groups[] = {
				4111	"pwm0",
				4112	};
				4113
				4114	static const char * const pwm1_groups[] = {
				4115	"pwm1_a",
				4116	"pwm1_b",
				4117	};
				4118
				4119	static const char * const pwm2_groups[] = {
				4120	"pwm2_a",
				4121	"pwm2_b",
				4122	};
				4123
				4124	static const char * const pwm3_groups[] = {
				4125	"pwm3_a",
				4126	"pwm3_b",
				4127	};
				4128
				4129	static const char * const pwm4_groups[] = {
				4130	"pwm4_a",
				4131	"pwm4_b",
				4132	};
				4133
				4134	static const char * const pwm5_groups[] = {
				4135	"pwm5_a",
				4136	"pwm5_b",
				4137	};
				4138
				4139	static const char * const pwm6_groups[] = {
				4140	"pwm6_a",
				4141	"pwm6_b",
				4142	};
				4143
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4144	static const char * const scif0_groups[] = {
				4145	"scif0_data",
				4146	"scif0_clk",
				4147	"scif0_ctrl",
				4148	};
				4149
				4150	static const char * const scif1_groups[] = {
				4151	"scif1_data_a",
				4152	"scif1_clk",
				4153	"scif1_ctrl",
				4154	"scif1_data_b",
				4155	};
				4156
				4157	static const char * const scif2_groups[] = {
				4158	"scif2_data_a",
				4159	"scif2_clk",
				4160	"scif2_data_b",
				4161	};
				4162
				4163	static const char * const scif3_groups[] = {
				4164	"scif3_data_a",
				4165	"scif3_clk",
				4166	"scif3_ctrl",
				4167	"scif3_data_b",
				4168	};
				4169
				4170	static const char * const scif4_groups[] = {
				4171	"scif4_data_a",
				4172	"scif4_clk_a",
				4173	"scif4_ctrl_a",
				4174	"scif4_data_b",
				4175	"scif4_clk_b",
				4176	"scif4_ctrl_b",
				4177	"scif4_data_c",
				4178	"scif4_clk_c",
				4179	"scif4_ctrl_c",
				4180	};
				4181
				4182	static const char * const scif5_groups[] = {
				4183	"scif5_data_a",
				4184	"scif5_clk_a",
				4185	"scif5_data_b",
				4186	"scif5_clk_b",
Takeshi Kihara	76250a6	2016-02-02 19:18:49 +0900	[diff] [blame]	4187	};
				4188
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	4189	static const char * const scif_clk_groups[] = {
				4190	"scif_clk_a",
				4191	"scif_clk_b",
				4192	};
				4193
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	4194	static const char * const sdhi0_groups[] = {
				4195	"sdhi0_data1",
				4196	"sdhi0_data4",
				4197	"sdhi0_ctrl",
				4198	"sdhi0_cd",
				4199	"sdhi0_wp",
				4200	};
				4201
				4202	static const char * const sdhi1_groups[] = {
				4203	"sdhi1_data1",
				4204	"sdhi1_data4",
				4205	"sdhi1_ctrl",
				4206	"sdhi1_cd",
				4207	"sdhi1_wp",
				4208	};
				4209
				4210	static const char * const sdhi2_groups[] = {
				4211	"sdhi2_data1",
				4212	"sdhi2_data4",
				4213	"sdhi2_data8",
				4214	"sdhi2_ctrl",
				4215	"sdhi2_cd_a",
				4216	"sdhi2_wp_a",
				4217	"sdhi2_cd_b",
				4218	"sdhi2_wp_b",
				4219	"sdhi2_ds",
				4220	};
				4221
				4222	static const char * const sdhi3_groups[] = {
				4223	"sdhi3_data1",
				4224	"sdhi3_data4",
				4225	"sdhi3_data8",
				4226	"sdhi3_ctrl",
				4227	"sdhi3_cd",
				4228	"sdhi3_wp",
				4229	"sdhi3_ds",
				4230	};
				4231
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	4232	static const char * const ssi_groups[] = {
				4233	"ssi0_data",
				4234	"ssi01239_ctrl",
				4235	"ssi1_data_a",
				4236	"ssi1_data_b",
				4237	"ssi1_ctrl_a",
				4238	"ssi1_ctrl_b",
				4239	"ssi2_data_a",
				4240	"ssi2_data_b",
				4241	"ssi2_ctrl_a",
				4242	"ssi2_ctrl_b",
				4243	"ssi3_data",
				4244	"ssi349_ctrl",
				4245	"ssi4_data",
				4246	"ssi4_ctrl",
				4247	"ssi5_data",
				4248	"ssi5_ctrl",
				4249	"ssi6_data",
				4250	"ssi6_ctrl",
				4251	"ssi7_data",
				4252	"ssi78_ctrl",
				4253	"ssi8_data",
				4254	"ssi9_data_a",
				4255	"ssi9_data_b",
				4256	"ssi9_ctrl_a",
				4257	"ssi9_ctrl_b",
				4258	};
				4259
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	4260	static const char * const usb0_groups[] = {
				4261	"usb0",
				4262	};
				4263
				4264	static const char * const usb1_groups[] = {
				4265	"usb1",
				4266	};
				4267
				4268	static const char * const usb2_groups[] = {
				4269	"usb2",
				4270	};
				4271
				4272	static const char * const usb2_ch3_groups[] = {
				4273	"usb2_ch3",
				4274	};
				4275
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	4276	static const char * const usb30_groups[] = {
				4277	"usb30",
				4278	};
				4279
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4280	static const struct sh_pfc_function pinmux_functions[] = {
Kuninori Morimoto	55bfea9	2017-10-03 02:22:51 +0000	[diff] [blame]	4281	SH_PFC_FUNCTION(audio_clk),
Geert Uytterhoeven	30c078d	2017-03-13 11:59:19 +0100	[diff] [blame]	4282	SH_PFC_FUNCTION(avb),
Dirk Behme	641b0ab	2017-08-30 10:05:48 +0200	[diff] [blame]	4283	SH_PFC_FUNCTION(drif0),
				4284	SH_PFC_FUNCTION(drif1),
				4285	SH_PFC_FUNCTION(drif2),
				4286	SH_PFC_FUNCTION(drif3),
Laurent Pinchart	a20a658	2017-06-15 10:30:31 +0300	[diff] [blame]	4287	SH_PFC_FUNCTION(du),
Wolfram Sang	f62d4c9	2017-10-04 17:52:52 +0200	[diff] [blame]	4288	SH_PFC_FUNCTION(i2c1),
				4289	SH_PFC_FUNCTION(i2c2),
				4290	SH_PFC_FUNCTION(i2c6),
Geert Uytterhoeven	8480e6c	2017-03-13 11:59:42 +0100	[diff] [blame^]	4291	SH_PFC_FUNCTION(intc_ex),
Geert Uytterhoeven	3e6c772	2017-03-13 11:59:41 +0100	[diff] [blame]	4292	SH_PFC_FUNCTION(msiof0),
				4293	SH_PFC_FUNCTION(msiof1),
				4294	SH_PFC_FUNCTION(msiof2),
				4295	SH_PFC_FUNCTION(msiof3),
Laurent Pinchart	c03a133	2017-06-24 13:18:54 +0300	[diff] [blame]	4296	SH_PFC_FUNCTION(pwm0),
				4297	SH_PFC_FUNCTION(pwm1),
				4298	SH_PFC_FUNCTION(pwm2),
				4299	SH_PFC_FUNCTION(pwm3),
				4300	SH_PFC_FUNCTION(pwm4),
				4301	SH_PFC_FUNCTION(pwm5),
				4302	SH_PFC_FUNCTION(pwm6),
Geert Uytterhoeven	e7ad4d3	2017-03-13 11:28:33 +0100	[diff] [blame]	4303	SH_PFC_FUNCTION(scif0),
				4304	SH_PFC_FUNCTION(scif1),
				4305	SH_PFC_FUNCTION(scif2),
				4306	SH_PFC_FUNCTION(scif3),
				4307	SH_PFC_FUNCTION(scif4),
				4308	SH_PFC_FUNCTION(scif5),
Geert Uytterhoeven	d14a39e	2017-03-13 11:28:39 +0100	[diff] [blame]	4309	SH_PFC_FUNCTION(scif_clk),
Takeshi Kihara	9ed1395	2017-08-29 17:51:57 +0200	[diff] [blame]	4310	SH_PFC_FUNCTION(sdhi0),
				4311	SH_PFC_FUNCTION(sdhi1),
				4312	SH_PFC_FUNCTION(sdhi2),
				4313	SH_PFC_FUNCTION(sdhi3),
Kuninori Morimoto	0526234	2017-10-03 02:23:11 +0000	[diff] [blame]	4314	SH_PFC_FUNCTION(ssi),
Yoshihiro Shimoda	933ddbe	2017-07-26 20:28:11 +0900	[diff] [blame]	4315	SH_PFC_FUNCTION(usb0),
				4316	SH_PFC_FUNCTION(usb1),
				4317	SH_PFC_FUNCTION(usb2),
				4318	SH_PFC_FUNCTION(usb2_ch3),
Takeshi Kihara	5ec8a41	2017-10-02 18:45:25 +0900	[diff] [blame]	4319	SH_PFC_FUNCTION(usb30),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4320	};
				4321
				4322	static const struct pinmux_cfg_reg pinmux_config_regs[] = {
				4323	#define F_(x, y) FN_##y
				4324	#define FM(x) FN_##x
				4325	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
				4326	0, 0,
				4327	0, 0,
				4328	0, 0,
				4329	0, 0,
				4330	0, 0,
				4331	0, 0,
				4332	0, 0,
				4333	0, 0,
				4334	0, 0,
				4335	0, 0,
				4336	0, 0,
				4337	0, 0,
				4338	0, 0,
				4339	0, 0,
				4340	0, 0,
				4341	0, 0,
				4342	GP_0_15_FN, GPSR0_15,
				4343	GP_0_14_FN, GPSR0_14,
				4344	GP_0_13_FN, GPSR0_13,
				4345	GP_0_12_FN, GPSR0_12,
				4346	GP_0_11_FN, GPSR0_11,
				4347	GP_0_10_FN, GPSR0_10,
				4348	GP_0_9_FN, GPSR0_9,
				4349	GP_0_8_FN, GPSR0_8,
				4350	GP_0_7_FN, GPSR0_7,
				4351	GP_0_6_FN, GPSR0_6,
				4352	GP_0_5_FN, GPSR0_5,
				4353	GP_0_4_FN, GPSR0_4,
				4354	GP_0_3_FN, GPSR0_3,
				4355	GP_0_2_FN, GPSR0_2,
				4356	GP_0_1_FN, GPSR0_1,
				4357	GP_0_0_FN, GPSR0_0, }
				4358	},
				4359	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
				4360	0, 0,
				4361	0, 0,
				4362	0, 0,
				4363	0, 0,
				4364	GP_1_27_FN, GPSR1_27,
				4365	GP_1_26_FN, GPSR1_26,
				4366	GP_1_25_FN, GPSR1_25,
				4367	GP_1_24_FN, GPSR1_24,
				4368	GP_1_23_FN, GPSR1_23,
				4369	GP_1_22_FN, GPSR1_22,
				4370	GP_1_21_FN, GPSR1_21,
				4371	GP_1_20_FN, GPSR1_20,
				4372	GP_1_19_FN, GPSR1_19,
				4373	GP_1_18_FN, GPSR1_18,
				4374	GP_1_17_FN, GPSR1_17,
				4375	GP_1_16_FN, GPSR1_16,
				4376	GP_1_15_FN, GPSR1_15,
				4377	GP_1_14_FN, GPSR1_14,
				4378	GP_1_13_FN, GPSR1_13,
				4379	GP_1_12_FN, GPSR1_12,
				4380	GP_1_11_FN, GPSR1_11,
				4381	GP_1_10_FN, GPSR1_10,
				4382	GP_1_9_FN, GPSR1_9,
				4383	GP_1_8_FN, GPSR1_8,
				4384	GP_1_7_FN, GPSR1_7,
				4385	GP_1_6_FN, GPSR1_6,
				4386	GP_1_5_FN, GPSR1_5,
				4387	GP_1_4_FN, GPSR1_4,
				4388	GP_1_3_FN, GPSR1_3,
				4389	GP_1_2_FN, GPSR1_2,
				4390	GP_1_1_FN, GPSR1_1,
				4391	GP_1_0_FN, GPSR1_0, }
				4392	},
				4393	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
				4394	0, 0,
				4395	0, 0,
				4396	0, 0,
				4397	0, 0,
				4398	0, 0,
				4399	0, 0,
				4400	0, 0,
				4401	0, 0,
				4402	0, 0,
				4403	0, 0,
				4404	0, 0,
				4405	0, 0,
				4406	0, 0,
				4407	0, 0,
				4408	0, 0,
				4409	0, 0,
				4410	0, 0,
				4411	GP_2_14_FN, GPSR2_14,
				4412	GP_2_13_FN, GPSR2_13,
				4413	GP_2_12_FN, GPSR2_12,
				4414	GP_2_11_FN, GPSR2_11,
				4415	GP_2_10_FN, GPSR2_10,
				4416	GP_2_9_FN, GPSR2_9,
				4417	GP_2_8_FN, GPSR2_8,
				4418	GP_2_7_FN, GPSR2_7,
				4419	GP_2_6_FN, GPSR2_6,
				4420	GP_2_5_FN, GPSR2_5,
				4421	GP_2_4_FN, GPSR2_4,
				4422	GP_2_3_FN, GPSR2_3,
				4423	GP_2_2_FN, GPSR2_2,
				4424	GP_2_1_FN, GPSR2_1,
				4425	GP_2_0_FN, GPSR2_0, }
				4426	},
				4427	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
				4428	0, 0,
				4429	0, 0,
				4430	0, 0,
				4431	0, 0,
				4432	0, 0,
				4433	0, 0,
				4434	0, 0,
				4435	0, 0,
				4436	0, 0,
				4437	0, 0,
				4438	0, 0,
				4439	0, 0,
				4440	0, 0,
				4441	0, 0,
				4442	0, 0,
				4443	0, 0,
				4444	GP_3_15_FN, GPSR3_15,
				4445	GP_3_14_FN, GPSR3_14,
				4446	GP_3_13_FN, GPSR3_13,
				4447	GP_3_12_FN, GPSR3_12,
				4448	GP_3_11_FN, GPSR3_11,
				4449	GP_3_10_FN, GPSR3_10,
				4450	GP_3_9_FN, GPSR3_9,
				4451	GP_3_8_FN, GPSR3_8,
				4452	GP_3_7_FN, GPSR3_7,
				4453	GP_3_6_FN, GPSR3_6,
				4454	GP_3_5_FN, GPSR3_5,
				4455	GP_3_4_FN, GPSR3_4,
				4456	GP_3_3_FN, GPSR3_3,
				4457	GP_3_2_FN, GPSR3_2,
				4458	GP_3_1_FN, GPSR3_1,
				4459	GP_3_0_FN, GPSR3_0, }
				4460	},
				4461	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
				4462	0, 0,
				4463	0, 0,
				4464	0, 0,
				4465	0, 0,
				4466	0, 0,
				4467	0, 0,
				4468	0, 0,
				4469	0, 0,
				4470	0, 0,
				4471	0, 0,
				4472	0, 0,
				4473	0, 0,
				4474	0, 0,
				4475	0, 0,
				4476	GP_4_17_FN, GPSR4_17,
				4477	GP_4_16_FN, GPSR4_16,
				4478	GP_4_15_FN, GPSR4_15,
				4479	GP_4_14_FN, GPSR4_14,
				4480	GP_4_13_FN, GPSR4_13,
				4481	GP_4_12_FN, GPSR4_12,
				4482	GP_4_11_FN, GPSR4_11,
				4483	GP_4_10_FN, GPSR4_10,
				4484	GP_4_9_FN, GPSR4_9,
				4485	GP_4_8_FN, GPSR4_8,
				4486	GP_4_7_FN, GPSR4_7,
				4487	GP_4_6_FN, GPSR4_6,
				4488	GP_4_5_FN, GPSR4_5,
				4489	GP_4_4_FN, GPSR4_4,
				4490	GP_4_3_FN, GPSR4_3,
				4491	GP_4_2_FN, GPSR4_2,
				4492	GP_4_1_FN, GPSR4_1,
				4493	GP_4_0_FN, GPSR4_0, }
				4494	},
				4495	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
				4496	0, 0,
				4497	0, 0,
				4498	0, 0,
				4499	0, 0,
				4500	0, 0,
				4501	0, 0,
				4502	GP_5_25_FN, GPSR5_25,
				4503	GP_5_24_FN, GPSR5_24,
				4504	GP_5_23_FN, GPSR5_23,
				4505	GP_5_22_FN, GPSR5_22,
				4506	GP_5_21_FN, GPSR5_21,
				4507	GP_5_20_FN, GPSR5_20,
				4508	GP_5_19_FN, GPSR5_19,
				4509	GP_5_18_FN, GPSR5_18,
				4510	GP_5_17_FN, GPSR5_17,
				4511	GP_5_16_FN, GPSR5_16,
				4512	GP_5_15_FN, GPSR5_15,
				4513	GP_5_14_FN, GPSR5_14,
				4514	GP_5_13_FN, GPSR5_13,
				4515	GP_5_12_FN, GPSR5_12,
				4516	GP_5_11_FN, GPSR5_11,
				4517	GP_5_10_FN, GPSR5_10,
				4518	GP_5_9_FN, GPSR5_9,
				4519	GP_5_8_FN, GPSR5_8,
				4520	GP_5_7_FN, GPSR5_7,
				4521	GP_5_6_FN, GPSR5_6,
				4522	GP_5_5_FN, GPSR5_5,
				4523	GP_5_4_FN, GPSR5_4,
				4524	GP_5_3_FN, GPSR5_3,
				4525	GP_5_2_FN, GPSR5_2,
				4526	GP_5_1_FN, GPSR5_1,
				4527	GP_5_0_FN, GPSR5_0, }
				4528	},
				4529	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
				4530	GP_6_31_FN, GPSR6_31,
				4531	GP_6_30_FN, GPSR6_30,
				4532	GP_6_29_FN, GPSR6_29,
				4533	GP_6_28_FN, GPSR6_28,
				4534	GP_6_27_FN, GPSR6_27,
				4535	GP_6_26_FN, GPSR6_26,
				4536	GP_6_25_FN, GPSR6_25,
				4537	GP_6_24_FN, GPSR6_24,
				4538	GP_6_23_FN, GPSR6_23,
				4539	GP_6_22_FN, GPSR6_22,
				4540	GP_6_21_FN, GPSR6_21,
				4541	GP_6_20_FN, GPSR6_20,
				4542	GP_6_19_FN, GPSR6_19,
				4543	GP_6_18_FN, GPSR6_18,
				4544	GP_6_17_FN, GPSR6_17,
				4545	GP_6_16_FN, GPSR6_16,
				4546	GP_6_15_FN, GPSR6_15,
				4547	GP_6_14_FN, GPSR6_14,
				4548	GP_6_13_FN, GPSR6_13,
				4549	GP_6_12_FN, GPSR6_12,
				4550	GP_6_11_FN, GPSR6_11,
				4551	GP_6_10_FN, GPSR6_10,
				4552	GP_6_9_FN, GPSR6_9,
				4553	GP_6_8_FN, GPSR6_8,
				4554	GP_6_7_FN, GPSR6_7,
				4555	GP_6_6_FN, GPSR6_6,
				4556	GP_6_5_FN, GPSR6_5,
				4557	GP_6_4_FN, GPSR6_4,
				4558	GP_6_3_FN, GPSR6_3,
				4559	GP_6_2_FN, GPSR6_2,
				4560	GP_6_1_FN, GPSR6_1,
				4561	GP_6_0_FN, GPSR6_0, }
				4562	},
				4563	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
				4564	0, 0,
				4565	0, 0,
				4566	0, 0,
				4567	0, 0,
				4568	0, 0,
				4569	0, 0,
				4570	0, 0,
				4571	0, 0,
				4572	0, 0,
				4573	0, 0,
				4574	0, 0,
				4575	0, 0,
				4576	0, 0,
				4577	0, 0,
				4578	0, 0,
				4579	0, 0,
				4580	0, 0,
				4581	0, 0,
				4582	0, 0,
				4583	0, 0,
				4584	0, 0,
				4585	0, 0,
				4586	0, 0,
				4587	0, 0,
				4588	0, 0,
				4589	0, 0,
				4590	0, 0,
				4591	0, 0,
				4592	GP_7_3_FN, GPSR7_3,
				4593	GP_7_2_FN, GPSR7_2,
				4594	GP_7_1_FN, GPSR7_1,
				4595	GP_7_0_FN, GPSR7_0, }
				4596	},
				4597	#undef F_
				4598	#undef FM
				4599
				4600	#define F_(x, y) x,
				4601	#define FM(x) FN_##x,
				4602	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
				4603	IP0_31_28
				4604	IP0_27_24
				4605	IP0_23_20
				4606	IP0_19_16
				4607	IP0_15_12
				4608	IP0_11_8
				4609	IP0_7_4
				4610	IP0_3_0 }
				4611	},
				4612	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
				4613	IP1_31_28
				4614	IP1_27_24
				4615	IP1_23_20
				4616	IP1_19_16
				4617	IP1_15_12
				4618	IP1_11_8
				4619	IP1_7_4
				4620	IP1_3_0 }
				4621	},
				4622	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
				4623	IP2_31_28
				4624	IP2_27_24
				4625	IP2_23_20
				4626	IP2_19_16
				4627	IP2_15_12
				4628	IP2_11_8
				4629	IP2_7_4
				4630	IP2_3_0 }
				4631	},
				4632	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
				4633	IP3_31_28
				4634	IP3_27_24
				4635	IP3_23_20
				4636	IP3_19_16
				4637	IP3_15_12
				4638	IP3_11_8
				4639	IP3_7_4
				4640	IP3_3_0 }
				4641	},
				4642	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
				4643	IP4_31_28
				4644	IP4_27_24
				4645	IP4_23_20
				4646	IP4_19_16
				4647	IP4_15_12
				4648	IP4_11_8
				4649	IP4_7_4
				4650	IP4_3_0 }
				4651	},
				4652	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
				4653	IP5_31_28
				4654	IP5_27_24
				4655	IP5_23_20
				4656	IP5_19_16
				4657	IP5_15_12
				4658	IP5_11_8
				4659	IP5_7_4
				4660	IP5_3_0 }
				4661	},
				4662	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
				4663	IP6_31_28
				4664	IP6_27_24
				4665	IP6_23_20
				4666	IP6_19_16
				4667	IP6_15_12
				4668	IP6_11_8
				4669	IP6_7_4
				4670	IP6_3_0 }
				4671	},
				4672	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
				4673	IP7_31_28
				4674	IP7_27_24
				4675	IP7_23_20
				4676	IP7_19_16
Takeshi Kihara	30cd1c4	2017-07-28 20:41:19 +0900	[diff] [blame]	4677	/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4678	IP7_11_8
				4679	IP7_7_4
				4680	IP7_3_0 }
				4681	},
				4682	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
				4683	IP8_31_28
				4684	IP8_27_24
				4685	IP8_23_20
				4686	IP8_19_16
				4687	IP8_15_12
				4688	IP8_11_8
				4689	IP8_7_4
				4690	IP8_3_0 }
				4691	},
				4692	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
				4693	IP9_31_28
				4694	IP9_27_24
				4695	IP9_23_20
				4696	IP9_19_16
				4697	IP9_15_12
				4698	IP9_11_8
				4699	IP9_7_4
				4700	IP9_3_0 }
				4701	},
				4702	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
				4703	IP10_31_28
				4704	IP10_27_24
				4705	IP10_23_20
				4706	IP10_19_16
				4707	IP10_15_12
				4708	IP10_11_8
				4709	IP10_7_4
				4710	IP10_3_0 }
				4711	},
				4712	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
				4713	IP11_31_28
				4714	IP11_27_24
				4715	IP11_23_20
				4716	IP11_19_16
				4717	IP11_15_12
				4718	IP11_11_8
				4719	IP11_7_4
				4720	IP11_3_0 }
				4721	},
				4722	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
				4723	IP12_31_28
				4724	IP12_27_24
				4725	IP12_23_20
				4726	IP12_19_16
				4727	IP12_15_12
				4728	IP12_11_8
				4729	IP12_7_4
				4730	IP12_3_0 }
				4731	},
				4732	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
				4733	IP13_31_28
				4734	IP13_27_24
				4735	IP13_23_20
				4736	IP13_19_16
				4737	IP13_15_12
				4738	IP13_11_8
				4739	IP13_7_4
				4740	IP13_3_0 }
				4741	},
				4742	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
				4743	IP14_31_28
				4744	IP14_27_24
				4745	IP14_23_20
				4746	IP14_19_16
				4747	IP14_15_12
				4748	IP14_11_8
				4749	IP14_7_4
				4750	IP14_3_0 }
				4751	},
				4752	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
				4753	IP15_31_28
				4754	IP15_27_24
				4755	IP15_23_20
				4756	IP15_19_16
				4757	IP15_15_12
				4758	IP15_11_8
				4759	IP15_7_4
				4760	IP15_3_0 }
				4761	},
				4762	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
				4763	IP16_31_28
				4764	IP16_27_24
				4765	IP16_23_20
				4766	IP16_19_16
				4767	IP16_15_12
				4768	IP16_11_8
				4769	IP16_7_4
				4770	IP16_3_0 }
				4771	},
				4772	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4773	IP17_31_28
				4774	IP17_27_24
				4775	IP17_23_20
				4776	IP17_19_16
				4777	IP17_15_12
				4778	IP17_11_8
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4779	IP17_7_4
				4780	IP17_3_0 }
				4781	},
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4782	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
				4783	/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4784	/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4785	/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4786	/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4787	/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4788	/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
				4789	IP18_7_4
				4790	IP18_3_0 }
				4791	},
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4792	#undef F_
				4793	#undef FM
				4794
				4795	#define F_(x, y) x,
				4796	#define FM(x) FN_##x,
				4797	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4798	3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
				4799	1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
				4800	MOD_SEL0_31_30_29
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4801	MOD_SEL0_28_27
				4802	MOD_SEL0_26_25_24
				4803	MOD_SEL0_23
				4804	MOD_SEL0_22
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4805	MOD_SEL0_21
				4806	MOD_SEL0_20
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4807	MOD_SEL0_19
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4808	MOD_SEL0_18_17
				4809	MOD_SEL0_16
				4810	0, 0, /* RESERVED 15 */
				4811	MOD_SEL0_14_13
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4812	MOD_SEL0_12
				4813	MOD_SEL0_11
				4814	MOD_SEL0_10
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4815	MOD_SEL0_9_8
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4816	MOD_SEL0_7_6
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4817	MOD_SEL0_5
				4818	MOD_SEL0_4_3
				4819	/* RESERVED 2, 1, 0 */
				4820	0, 0, 0, 0, 0, 0, 0, 0 }
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4821	},
				4822	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
				4823	2, 3, 1, 2, 3, 1, 1, 2, 1,
				4824	2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
				4825	MOD_SEL1_31_30
				4826	MOD_SEL1_29_28_27
				4827	MOD_SEL1_26
				4828	MOD_SEL1_25_24
				4829	MOD_SEL1_23_22_21
				4830	MOD_SEL1_20
				4831	MOD_SEL1_19
				4832	MOD_SEL1_18_17
				4833	MOD_SEL1_16
				4834	MOD_SEL1_15_14
				4835	MOD_SEL1_13
				4836	MOD_SEL1_12
				4837	MOD_SEL1_11
				4838	MOD_SEL1_10
				4839	MOD_SEL1_9
				4840	0, 0, 0, 0, /* RESERVED 8, 7 */
				4841	MOD_SEL1_6
				4842	MOD_SEL1_5
				4843	MOD_SEL1_4
				4844	MOD_SEL1_3
				4845	MOD_SEL1_2
				4846	MOD_SEL1_1
				4847	MOD_SEL1_0 }
				4848	},
				4849	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4850	1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
				4851	4, 4, 4, 3, 1) {
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4852	MOD_SEL2_31
				4853	MOD_SEL2_30
				4854	MOD_SEL2_29
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4855	MOD_SEL2_28_27
				4856	MOD_SEL2_26
				4857	MOD_SEL2_25_24_23
Takeshi Kihara	3c612d2	2017-07-28 20:41:21 +0900	[diff] [blame]	4858	/* RESERVED 22 */
				4859	0, 0,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4860	MOD_SEL2_21
				4861	MOD_SEL2_20
				4862	MOD_SEL2_19
				4863	MOD_SEL2_18
				4864	MOD_SEL2_17
				4865	/* RESERVED 16 */
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4866	0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4867	/* RESERVED 15, 14, 13, 12 */
				4868	0, 0, 0, 0, 0, 0, 0, 0,
				4869	0, 0, 0, 0, 0, 0, 0, 0,
				4870	/* RESERVED 11, 10, 9, 8 */
				4871	0, 0, 0, 0, 0, 0, 0, 0,
				4872	0, 0, 0, 0, 0, 0, 0, 0,
				4873	/* RESERVED 7, 6, 5, 4 */
				4874	0, 0, 0, 0, 0, 0, 0, 0,
				4875	0, 0, 0, 0, 0, 0, 0, 0,
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	4876	/* RESERVED 3, 2, 1 */
				4877	0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	4878	MOD_SEL2_0 }
				4879	},
				4880	{ },
				4881	};
				4882
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	4883	static const struct pinmux_drive_reg pinmux_drive_regs[] = {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	4884	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
				4885	{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
				4886	{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
				4887	{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
				4888	{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
				4889	{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
				4890	{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
				4891	{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
				4892	{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
				4893	} },
				4894	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
				4895	{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
				4896	{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
				4897	{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
				4898	{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
				4899	{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
				4900	{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
				4901	{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
				4902	{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
				4903	} },
				4904	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
				4905	{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
				4906	{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
				4907	{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
				4908	{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
				4909	{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
				4910	{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
				4911	{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
				4912	{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
				4913	} },
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	4914	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	4915	{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
				4916	{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
				4917	{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
				4918	{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
				4919	{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
				4920	{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
				4921	{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
				4922	{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	4923	} },
				4924	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
				4925	{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
				4926	{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
				4927	{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
				4928	{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
				4929	{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
				4930	{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
				4931	{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
				4932	{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
				4933	} },
				4934	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
				4935	{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
				4936	{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
				4937	{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
				4938	{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
				4939	{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
				4940	{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
				4941	{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
				4942	{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
				4943	} },
				4944	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
				4945	{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
				4946	{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
				4947	{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
				4948	{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
				4949	{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
				4950	{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
				4951	{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
				4952	{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
				4953	} },
				4954	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
				4955	{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
				4956	{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
				4957	{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
				4958	{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
				4959	{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
				4960	{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
				4961	{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
				4962	{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
				4963	} },
				4964	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	4965	{ PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	4966	{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
				4967	{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
				4968	{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
				4969	{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
				4970	{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
				4971	{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
				4972	{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
				4973	} },
				4974	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
				4975	{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	4976	{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	4977	{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
				4978	{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
				4979	{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
				4980	{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
				4981	{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
				4982	{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
				4983	} },
				4984	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
				4985	{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
				4986	{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
				4987	{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
				4988	{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
				4989	{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
				4990	{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
				4991	{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
				4992	{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
				4993	} },
				4994	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	4995	{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
				4996	{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
				4997	{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
				4998	{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
				4999	{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
				5000	{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
				5001	{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
				5002	{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
				5003	} },
				5004	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
				5005	{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
				5006	{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
				5007	{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
				5008	{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5009	} },
				5010	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5011	{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
				5012	{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
				5013	{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
				5014	{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
				5015	{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
				5016	{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
				5017	{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
				5018	{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5019	} },
				5020	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
				5021	{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
				5022	{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
				5023	{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
				5024	{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
				5025	{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
				5026	{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
				5027	{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
				5028	{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
				5029	} },
				5030	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
				5031	{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
				5032	{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
				5033	{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
				5034	{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
				5035	{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
				5036	{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
				5037	{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
				5038	{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
				5039	} },
				5040	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
				5041	{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
				5042	{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
				5043	{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
				5044	{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
				5045	{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
				5046	{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
				5047	{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
				5048	{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
				5049	} },
				5050	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
				5051	{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
				5052	{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
				5053	{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
				5054	{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
				5055	{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
				5056	{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
				5057	{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
				5058	{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
				5059	} },
				5060	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
				5061	{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
				5062	{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
				5063	{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
				5064	{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
				5065	{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
				5066	{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
				5067	{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
				5068	{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
				5069	} },
				5070	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
				5071	{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
				5072	{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
				5073	{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
				5074	{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
				5075	{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
				5076	{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
				5077	{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
				5078	{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
				5079	} },
				5080	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
				5081	{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
				5082	{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
				5083	{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
				5084	{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
				5085	{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
				5086	{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Niklas Söderlund	ea9c740	2016-11-11 21:33:39 +0100	[diff] [blame]	5087	{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5088	{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
				5089	} },
				5090	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
				5091	{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
				5092	{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
				5093	{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
				5094	{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	5095	{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
				5096	{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5097	{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
				5098	{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
				5099	} },
				5100	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
				5101	{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
				5102	{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
				5103	{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
				5104	{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
				5105	{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
				5106	{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
				5107	{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
				5108	{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
				5109	} },
				5110	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
				5111	{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
				5112	{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
				5113	{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
				5114	{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
				5115	{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
				5116	{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
				5117	{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
				5118	{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
				5119	} },
				5120	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
				5121	{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
				5122	{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
				5123	{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
				5124	{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
				5125	{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	5126	{ RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
				5127	{ RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5128	} },
				5129	{ },
				5130	};
				5131
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5132	static int r8a7795_pin_to_pocctrl(struct sh_pfc pfc, unsigned int pin, u32 pocctrl)
				5133	{
				5134	int bit = -EINVAL;
				5135
				5136	*pocctrl = 0xe6060380;
				5137
				5138	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
				5139	bit = pin & 0x1f;
				5140
				5141	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
				5142	bit = (pin & 0x1f) + 12;
				5143
				5144	return bit;
				5145	}
				5146
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5147	#define PUEN 0xe6060400
				5148	#define PUD 0xe6060440
				5149
				5150	#define PU0 0x00
				5151	#define PU1 0x04
				5152	#define PU2 0x08
				5153	#define PU3 0x0c
				5154	#define PU4 0x10
				5155	#define PU5 0x14
				5156	#define PU6 0x18
				5157
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5158	static const struct sh_pfc_bias_info bias_info[] = {
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5159	{ RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
				5160	{ RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
				5161	{ RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
				5162	{ PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
				5163	{ PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
				5164	{ PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
				5165	{ PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
				5166	{ PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
				5167	{ PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
				5168	{ PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
				5169	{ PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
				5170	{ PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
				5171	{ PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
				5172	{ PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
				5173	{ PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
				5174	{ PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
				5175	{ PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
				5176	{ PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
				5177	{ PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
				5178	{ PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
				5179	{ PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
				5180	{ PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
				5181	{ PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
				5182	{ PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
				5183	{ PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
				5184	{ PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
				5185	{ PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
				5186	{ PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
				5187	{ PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
				5188	{ PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
				5189	{ PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
				5190	{ PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5191
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5192	{ RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
				5193	{ RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
				5194	{ RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
				5195	{ RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
				5196	{ RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
				5197	{ RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
				5198	{ RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
				5199	{ RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
				5200	{ RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
				5201	{ RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
				5202	{ RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
				5203	{ RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
				5204	{ RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
				5205	{ RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
				5206	{ RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
				5207	{ RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
				5208	{ RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
				5209	{ RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
				5210	{ RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
				5211	{ RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
				5212	{ RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
				5213	{ RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
				5214	{ RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
				5215	{ RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
				5216	{ RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
				5217	{ RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
				5218	{ RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
				5219	{ RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
				5220	{ RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
				5221	{ RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
				5222	{ RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
				5223	{ RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5224
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5225	{ PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
				5226	{ PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
				5227	{ RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
				5228	{ RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
				5229	{ RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
				5230	{ RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
				5231	{ RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
				5232	{ RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
				5233	{ RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
				5234	{ RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
				5235	{ RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
				5236	{ RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
				5237	{ RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
				5238	{ RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
				5239	{ RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
				5240	{ RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
				5241	{ RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
				5242	{ RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
				5243	{ RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
				5244	{ RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
				5245	{ RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
				5246	{ RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
				5247	{ PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
				5248	{ RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
				5249	{ RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
				5250	{ RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
				5251	{ RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
				5252	{ RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
				5253	{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
Takeshi Kihara	fc8fd9b	2017-07-28 20:41:20 +0900	[diff] [blame]	5254	{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5255	{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
				5256	{ PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5257
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5258	{ RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
				5259	{ RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
				5260	{ RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
				5261	{ RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
				5262	{ RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
				5263	{ RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
				5264	{ RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
				5265	{ RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
				5266	{ RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
				5267	{ RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
				5268	{ RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
				5269	{ RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
				5270	{ RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
				5271	{ RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
				5272	{ RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
				5273	{ RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
				5274	{ RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
				5275	{ RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
				5276	{ RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
				5277	{ RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
				5278	{ RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
				5279	{ RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
				5280	{ PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
				5281	/* bit 8 n/a */
				5282	{ PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
				5283	{ PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
				5284	{ PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
				5285	{ PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
				5286	{ PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
				5287	{ PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
				5288	{ PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
				5289	{ PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5290
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5291	{ RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
				5292	{ RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
				5293	{ RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
				5294	{ RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
				5295	{ RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
				5296	{ RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
				5297	{ RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
				5298	{ RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
				5299	{ RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
				5300	{ RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
				5301	{ RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
				5302	{ RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
				5303	{ RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
				5304	{ RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
				5305	{ RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
				5306	{ RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
				5307	{ RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
				5308	{ RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
				5309	{ RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
				5310	{ RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
				5311	{ RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
				5312	{ RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
				5313	{ RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
				5314	{ RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
				5315	{ RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
				5316	{ RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
				5317	{ RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
				5318	{ RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
				5319	{ RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
				5320	{ RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
				5321	{ RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
				5322	{ RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5323
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5324	{ RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
				5325	{ RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
				5326	{ RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
				5327	{ RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
				5328	{ RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
				5329	{ RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
				5330	{ RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
				5331	{ RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
				5332	{ RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
				5333	{ RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
				5334	{ RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
				5335	{ RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
				5336	{ RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
				5337	{ RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
				5338	{ RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
				5339	{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
				5340	{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
				5341	{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
Kuninori Morimoto	68e6389	2017-05-16 08:01:17 +0000	[diff] [blame]	5342	{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
				5343	{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5344	{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
				5345	{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
				5346	{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
				5347	{ RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
				5348	{ RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
				5349	{ PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
				5350	{ RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
				5351	{ RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
				5352	{ RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
				5353	{ RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
				5354	{ RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
				5355	{ RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5356
Yoshihiro Shimoda	f9d1308	2017-07-26 20:28:10 +0900	[diff] [blame]	5357	{ RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
				5358	{ RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
Niklas Söderlund	4c2fb44	2016-11-17 16:26:31 +0100	[diff] [blame]	5359	{ RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
				5360	{ RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
				5361	{ RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
				5362	{ RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
				5363	{ RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5364	};
				5365
				5366	static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
				5367	unsigned int pin)
				5368	{
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5369	const struct sh_pfc_bias_info *info;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5370	u32 reg;
				5371	u32 bit;
				5372
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5373	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
				5374	if (!info)
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5375	return PIN_CONFIG_BIAS_DISABLE;
				5376
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5377	reg = info->reg;
				5378	bit = BIT(info->bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5379
Niklas Söderlund	42831cf	2016-11-12 17:04:26 +0100	[diff] [blame]	5380	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5381	return PIN_CONFIG_BIAS_DISABLE;
Niklas Söderlund	42831cf	2016-11-12 17:04:26 +0100	[diff] [blame]	5382	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
				5383	return PIN_CONFIG_BIAS_PULL_UP;
				5384	else
				5385	return PIN_CONFIG_BIAS_PULL_DOWN;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5386	}
				5387
				5388	static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
				5389	unsigned int bias)
				5390	{
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5391	const struct sh_pfc_bias_info *info;
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5392	u32 enable, updown;
				5393	u32 reg;
				5394	u32 bit;
				5395
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5396	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
				5397	if (!info)
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5398	return;
				5399
Niklas Söderlund	d3b861b	2016-11-12 17:04:27 +0100	[diff] [blame]	5400	reg = info->reg;
				5401	bit = BIT(info->bit);
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5402
				5403	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
				5404	if (bias != PIN_CONFIG_BIAS_DISABLE)
				5405	enable \|= bit;
				5406
				5407	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
				5408	if (bias == PIN_CONFIG_BIAS_PULL_UP)
				5409	updown \|= bit;
				5410
				5411	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
				5412	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
				5413	}
				5414
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5415	static const struct soc_device_attribute r8a7795es1[] = {
				5416	{ .soc_id = "r8a7795", .revision = "ES1.*" },
				5417	{ /* sentinel */ }
				5418	};
				5419
				5420	static int r8a7795_pinmux_init(struct sh_pfc *pfc)
				5421	{
				5422	if (soc_device_match(r8a7795es1))
				5423	pfc->info = &r8a7795es1_pinmux_info;
				5424
				5425	return 0;
				5426	}
				5427
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5428	static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5429	.init = r8a7795_pinmux_init,
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5430	.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
Ulrich Hecht	5606552	2016-06-29 18:06:04 +0200	[diff] [blame]	5431	.get_bias = r8a7795_pinmux_get_bias,
				5432	.set_bias = r8a7795_pinmux_set_bias,
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5433	};
				5434
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5435	const struct sh_pfc_soc_info r8a7795_pinmux_info = {
Geert Uytterhoeven	b205914c	2016-10-03 14:49:57 +0200	[diff] [blame]	5436	.name = "r8a77951_pfc",
Wolfram Sang	e9eace3	2016-06-06 18:08:26 +0200	[diff] [blame]	5437	.ops = &r8a7795_pinmux_ops,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5438	.unlock_reg = 0xe6060000, /* PMMR */
				5439
				5440	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
				5441
				5442	.pins = pinmux_pins,
				5443	.nr_pins = ARRAY_SIZE(pinmux_pins),
				5444	.groups = pinmux_groups,
				5445	.nr_groups = ARRAY_SIZE(pinmux_groups),
				5446	.functions = pinmux_functions,
				5447	.nr_functions = ARRAY_SIZE(pinmux_functions),
				5448
				5449	.cfg_regs = pinmux_config_regs,
Laurent Pinchart	92e6d9a	2016-03-23 16:06:01 +0200	[diff] [blame]	5450	.drive_regs = pinmux_drive_regs,
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5451
Geert Uytterhoeven	b8b47d6	2015-09-21 16:27:23 +0200	[diff] [blame]	5452	.pinmux_data = pinmux_data,
				5453	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
Takeshi Kihara	0b0ffc9	2015-09-03 02:51:49 +0000	[diff] [blame]	5454	};