blob: 660ec46eecf2588d7a277c8ff4a2b63a67242145 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Mark Brownf2644a22009-04-07 19:20:14 +01002/*
3 * wm8960.c -- WM8960 ALSA SoC Audio driver
4 *
Mark Brown656baae2012-05-23 12:39:07 +01005 * Copyright 2007-11 Wolfson Microelectronics, plc
6 *
Mark Brownf2644a22009-04-07 19:20:14 +01007 * Author: Liam Girdwood
Mark Brownf2644a22009-04-07 19:20:14 +01008 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/pm.h>
Zidan Wang75aa8862015-01-07 15:31:44 +080015#include <linux/clk.h>
Mark Brownf2644a22009-04-07 19:20:14 +010016#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090017#include <linux/slab.h>
Mark Brownf2644a22009-04-07 19:20:14 +010018#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
Mark Brownf2644a22009-04-07 19:20:14 +010022#include <sound/initval.h>
23#include <sound/tlv.h>
Mark Brownb6877a42010-03-03 11:43:38 +000024#include <sound/wm8960.h>
Mark Brownf2644a22009-04-07 19:20:14 +010025
26#include "wm8960.h"
27
Mark Brownf2644a22009-04-07 19:20:14 +010028/* R25 - Power 1 */
Mark Brown913d7b42010-03-03 13:47:03 +000029#define WM8960_VMID_MASK 0x180
Mark Brownf2644a22009-04-07 19:20:14 +010030#define WM8960_VREF 0x40
31
Mark Brown913d7b42010-03-03 13:47:03 +000032/* R26 - Power 2 */
33#define WM8960_PWR2_LOUT1 0x40
34#define WM8960_PWR2_ROUT1 0x20
35#define WM8960_PWR2_OUT3 0x02
36
Mark Brownf2644a22009-04-07 19:20:14 +010037/* R28 - Anti-pop 1 */
38#define WM8960_POBCTRL 0x80
39#define WM8960_BUFDCOPEN 0x10
40#define WM8960_BUFIOEN 0x08
41#define WM8960_SOFT_ST 0x04
42#define WM8960_HPSTBY 0x01
43
44/* R29 - Anti-pop 2 */
45#define WM8960_DISOP 0x40
Mark Brown913d7b42010-03-03 13:47:03 +000046#define WM8960_DRES_MASK 0x30
Mark Brownf2644a22009-04-07 19:20:14 +010047
Zidan Wang3176bf22015-08-11 19:25:15 +080048static bool is_pll_freq_available(unsigned int source, unsigned int target);
Kuninori Morimotoe075fc12018-01-29 03:05:45 +000049static int wm8960_set_pll(struct snd_soc_component *component,
Zidan Wang3176bf22015-08-11 19:25:15 +080050 unsigned int freq_in, unsigned int freq_out);
Mark Brownf2644a22009-04-07 19:20:14 +010051/*
52 * wm8960 register cache
53 * We can't read the WM8960 register space when we are
54 * using 2 wire for device control, so we cache them instead.
55 */
Mark Brown0ebe36c2012-09-10 19:23:57 +080056static const struct reg_default wm8960_reg_defaults[] = {
Mark Brownb3df0262013-02-26 23:35:46 +000057 { 0x0, 0x00a7 },
58 { 0x1, 0x00a7 },
Mark Brown0ebe36c2012-09-10 19:23:57 +080059 { 0x2, 0x0000 },
60 { 0x3, 0x0000 },
61 { 0x4, 0x0000 },
62 { 0x5, 0x0008 },
63 { 0x6, 0x0000 },
64 { 0x7, 0x000a },
65 { 0x8, 0x01c0 },
66 { 0x9, 0x0000 },
67 { 0xa, 0x00ff },
68 { 0xb, 0x00ff },
69
70 { 0x10, 0x0000 },
71 { 0x11, 0x007b },
72 { 0x12, 0x0100 },
73 { 0x13, 0x0032 },
74 { 0x14, 0x0000 },
75 { 0x15, 0x00c3 },
76 { 0x16, 0x00c3 },
77 { 0x17, 0x01c0 },
78 { 0x18, 0x0000 },
79 { 0x19, 0x0000 },
80 { 0x1a, 0x0000 },
81 { 0x1b, 0x0000 },
82 { 0x1c, 0x0000 },
83 { 0x1d, 0x0000 },
84
85 { 0x20, 0x0100 },
86 { 0x21, 0x0100 },
87 { 0x22, 0x0050 },
88
89 { 0x25, 0x0050 },
90 { 0x26, 0x0000 },
91 { 0x27, 0x0000 },
92 { 0x28, 0x0000 },
93 { 0x29, 0x0000 },
94 { 0x2a, 0x0040 },
95 { 0x2b, 0x0000 },
96 { 0x2c, 0x0000 },
97 { 0x2d, 0x0050 },
98 { 0x2e, 0x0050 },
99 { 0x2f, 0x0000 },
100 { 0x30, 0x0002 },
101 { 0x31, 0x0037 },
102
103 { 0x33, 0x0080 },
104 { 0x34, 0x0008 },
105 { 0x35, 0x0031 },
106 { 0x36, 0x0026 },
107 { 0x37, 0x00e9 },
Mark Brownf2644a22009-04-07 19:20:14 +0100108};
109
Mark Brown0ebe36c2012-09-10 19:23:57 +0800110static bool wm8960_volatile(struct device *dev, unsigned int reg)
111{
112 switch (reg) {
113 case WM8960_RESET:
114 return true;
115 default:
116 return false;
117 }
118}
119
Mark Brownf2644a22009-04-07 19:20:14 +0100120struct wm8960_priv {
Zidan Wang75aa8862015-01-07 15:31:44 +0800121 struct clk *mclk;
Mark Brown0ebe36c2012-09-10 19:23:57 +0800122 struct regmap *regmap;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000123 int (*set_bias_level)(struct snd_soc_component *,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000124 enum snd_soc_bias_level level);
Mark Brown913d7b42010-03-03 13:47:03 +0000125 struct snd_soc_dapm_widget *lout1;
126 struct snd_soc_dapm_widget *rout1;
127 struct snd_soc_dapm_widget *out3;
Mark Brownafd6d362010-07-05 13:58:16 +0900128 bool deemph;
Zidan Wang3176bf22015-08-11 19:25:15 +0800129 int lrclk;
Zidan Wang0e50b512015-05-12 14:58:08 +0800130 int bclk;
131 int sysclk;
Zidan Wang3176bf22015-08-11 19:25:15 +0800132 int clk_id;
133 int freq_in;
134 bool is_stream_in_use[2];
Zidan Wange2280c902014-11-20 19:07:48 +0800135 struct wm8960_data pdata;
Mark Brownf2644a22009-04-07 19:20:14 +0100136};
137
Zidan Wang3ad5e862014-11-27 16:53:08 +0800138#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
Mark Brownf2644a22009-04-07 19:20:14 +0100139
140/* enumerated controls */
Mark Brownf2644a22009-04-07 19:20:14 +0100141static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
142 "Right Inverted", "Stereo Inversion"};
143static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
144static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
145static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
146static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
Zidan Wang4a5893c2015-12-24 14:58:03 +0800147static const char *wm8960_adc_data_output_sel[] = {
148 "Left Data = Left ADC; Right Data = Right ADC",
149 "Left Data = Left ADC; Right Data = Left ADC",
150 "Left Data = Right ADC; Right Data = Right ADC",
151 "Left Data = Right ADC; Right Data = Left ADC",
152};
Zidan Wangdefbf702016-01-08 16:57:01 +0800153static const char *wm8960_dmonomix[] = {"Stereo", "Mono"};
Mark Brownf2644a22009-04-07 19:20:14 +0100154
155static const struct soc_enum wm8960_enum[] = {
Mark Brownf2644a22009-04-07 19:20:14 +0100156 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
157 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
158 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
159 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
160 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
161 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
Zidan Wang4a5893c2015-12-24 14:58:03 +0800162 SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel),
Zidan Wangdefbf702016-01-08 16:57:01 +0800163 SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix),
Mark Brownf2644a22009-04-07 19:20:14 +0100164};
165
Mark Brownafd6d362010-07-05 13:58:16 +0900166static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
167
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000168static int wm8960_set_deemph(struct snd_soc_component *component)
Mark Brownafd6d362010-07-05 13:58:16 +0900169{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000170 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Mark Brownafd6d362010-07-05 13:58:16 +0900171 int val, i, best;
172
173 /* If we're using deemphasis select the nearest available sample
174 * rate.
175 */
176 if (wm8960->deemph) {
177 best = 1;
178 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
Zidan Wang3176bf22015-08-11 19:25:15 +0800179 if (abs(deemph_settings[i] - wm8960->lrclk) <
180 abs(deemph_settings[best] - wm8960->lrclk))
Mark Brownafd6d362010-07-05 13:58:16 +0900181 best = i;
182 }
183
184 val = best << 1;
185 } else {
186 val = 0;
187 }
188
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000189 dev_dbg(component->dev, "Set deemphasis %d\n", val);
Mark Brownafd6d362010-07-05 13:58:16 +0900190
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000191 return snd_soc_component_update_bits(component, WM8960_DACCTL1,
Mark Brownafd6d362010-07-05 13:58:16 +0900192 0x6, val);
193}
194
195static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
196 struct snd_ctl_elem_value *ucontrol)
197{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000198 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
199 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Mark Brownafd6d362010-07-05 13:58:16 +0900200
Takashi Iwaib4a18c82015-03-10 12:39:14 +0100201 ucontrol->value.integer.value[0] = wm8960->deemph;
Dmitry Artamonow3f343f82010-12-08 23:36:17 +0300202 return 0;
Mark Brownafd6d362010-07-05 13:58:16 +0900203}
204
205static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
206 struct snd_ctl_elem_value *ucontrol)
207{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000208 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
209 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Dan Carpenterc1fe81f2015-10-13 10:09:19 +0300210 unsigned int deemph = ucontrol->value.integer.value[0];
Mark Brownafd6d362010-07-05 13:58:16 +0900211
212 if (deemph > 1)
213 return -EINVAL;
214
215 wm8960->deemph = deemph;
216
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000217 return wm8960_set_deemph(component);
Mark Brownafd6d362010-07-05 13:58:16 +0900218}
219
Zidan Wang3758ff52015-09-09 19:29:10 +0800220static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800221static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
Zidan Wang3758ff52015-09-09 19:29:10 +0800222static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
Mark Brownf2644a22009-04-07 19:20:14 +0100223static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
224static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800225static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
Takashi Sakamotob269ceb2016-09-28 09:29:21 +0900226static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(micboost_tlv,
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800227 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
228 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
Takashi Sakamotob269ceb2016-09-28 09:29:21 +0900229);
Mark Brownf2644a22009-04-07 19:20:14 +0100230
231static const struct snd_kcontrol_new wm8960_snd_controls[] = {
232SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800233 0, 63, 0, inpga_tlv),
Mark Brownf2644a22009-04-07 19:20:14 +0100234SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
235 6, 1, 0),
236SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
JongHo Kim41a59ca2015-11-03 11:06:32 +0900237 7, 1, 1),
Mark Brownf2644a22009-04-07 19:20:14 +0100238
Mark Brown21eb2692013-02-26 23:36:37 +0000239SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
Stuart Henderson95826a32016-01-19 13:09:08 +0000240 WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
Mark Brown21eb2692013-02-26 23:36:37 +0000241SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
Stuart Henderson95826a32016-01-19 13:09:08 +0000242 WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
243SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
244 WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
245SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800246 WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
247SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
Zidan Wang8524bb02015-09-18 17:19:43 +0800248 WM8960_RINPATH, 4, 3, 0, micboost_tlv),
Zidan Wang7e90f9b2015-09-09 19:29:11 +0800249SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
Zidan Wang8524bb02015-09-18 17:19:43 +0800250 WM8960_LINPATH, 4, 3, 0, micboost_tlv),
Mark Brown21eb2692013-02-26 23:36:37 +0000251
Mark Brownf2644a22009-04-07 19:20:14 +0100252SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
253 0, 255, 0, dac_tlv),
254
255SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
256 0, 127, 0, out_tlv),
257SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
258 7, 1, 0),
259
260SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
261 0, 127, 0, out_tlv),
262SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
263 7, 1, 0),
264SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
265SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
266
267SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
Mark Brown4faaa8d2010-07-05 13:54:32 +0900268SOC_ENUM("ADC Polarity", wm8960_enum[0]),
Mark Brownf2644a22009-04-07 19:20:14 +0100269SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
270
Zidan Wanga077e812015-06-11 19:14:36 +0800271SOC_ENUM("DAC Polarity", wm8960_enum[1]),
Mark Brownafd6d362010-07-05 13:58:16 +0900272SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
273 wm8960_get_deemph, wm8960_put_deemph),
Mark Brownf2644a22009-04-07 19:20:14 +0100274
Mark Brown4faaa8d2010-07-05 13:54:32 +0900275SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
276SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
Mark Brownf2644a22009-04-07 19:20:14 +0100277SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
278SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
279
Mark Brown4faaa8d2010-07-05 13:54:32 +0900280SOC_ENUM("ALC Function", wm8960_enum[4]),
Mark Brownf2644a22009-04-07 19:20:14 +0100281SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
282SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
283SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
284SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
Mark Brown4faaa8d2010-07-05 13:54:32 +0900285SOC_ENUM("ALC Mode", wm8960_enum[5]),
Mark Brownf2644a22009-04-07 19:20:14 +0100286SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
287SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
288
289SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
290SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
291
Ma Haijunc324aac2013-08-14 09:15:38 +0800292SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
293 0, 255, 0, adc_tlv),
Mark Brownf2644a22009-04-07 19:20:14 +0100294
295SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
296 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
297SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
298 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
299SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
300 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
301SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
302 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
Zidan Wang4a5893c2015-12-24 14:58:03 +0800303
304SOC_ENUM("ADC Data Output Select", wm8960_enum[6]),
Zidan Wangdefbf702016-01-08 16:57:01 +0800305SOC_ENUM("DAC Mono Mix", wm8960_enum[7]),
Mark Brownf2644a22009-04-07 19:20:14 +0100306};
307
308static const struct snd_kcontrol_new wm8960_lin_boost[] = {
309SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
310SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
311SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
312};
313
314static const struct snd_kcontrol_new wm8960_lin[] = {
315SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
316};
317
318static const struct snd_kcontrol_new wm8960_rin_boost[] = {
319SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
320SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
321SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
322};
323
324static const struct snd_kcontrol_new wm8960_rin[] = {
325SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
326};
327
328static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
329SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
330SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
331SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
332};
333
334static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
335SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
336SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
337SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
338};
339
340static const struct snd_kcontrol_new wm8960_mono_out[] = {
341SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
342SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
343};
344
345static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
346SND_SOC_DAPM_INPUT("LINPUT1"),
347SND_SOC_DAPM_INPUT("RINPUT1"),
348SND_SOC_DAPM_INPUT("LINPUT2"),
349SND_SOC_DAPM_INPUT("RINPUT2"),
350SND_SOC_DAPM_INPUT("LINPUT3"),
351SND_SOC_DAPM_INPUT("RINPUT3"),
352
Mark Brown187774c2011-10-27 09:46:17 +0200353SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
Mark Brownf2644a22009-04-07 19:20:14 +0100354
355SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
356 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
357SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
358 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
359
360SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
361 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
362SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
363 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
364
Mark Brown44426de2013-02-26 23:36:48 +0000365SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
366SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
Mark Brownf2644a22009-04-07 19:20:14 +0100367
368SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
369SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
370
371SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
372 &wm8960_loutput_mixer[0],
373 ARRAY_SIZE(wm8960_loutput_mixer)),
374SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
375 &wm8960_routput_mixer[0],
376 ARRAY_SIZE(wm8960_routput_mixer)),
377
Mark Brownf2644a22009-04-07 19:20:14 +0100378SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
379SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
380
381SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
382SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
383
384SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
385SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
386
387SND_SOC_DAPM_OUTPUT("SPK_LP"),
388SND_SOC_DAPM_OUTPUT("SPK_LN"),
389SND_SOC_DAPM_OUTPUT("HP_L"),
390SND_SOC_DAPM_OUTPUT("HP_R"),
391SND_SOC_DAPM_OUTPUT("SPK_RP"),
392SND_SOC_DAPM_OUTPUT("SPK_RN"),
393SND_SOC_DAPM_OUTPUT("OUT3"),
394};
395
Mark Brown913d7b42010-03-03 13:47:03 +0000396static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
397SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
398 &wm8960_mono_out[0],
399 ARRAY_SIZE(wm8960_mono_out)),
400};
401
402/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
403static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
404SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
405};
406
Mark Brownf2644a22009-04-07 19:20:14 +0100407static const struct snd_soc_dapm_route audio_paths[] = {
408 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
409 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
410 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
411
Zidan Wang2d4a3262016-01-08 16:57:02 +0800412 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer" },
413 { "Left Input Mixer", "Boost Switch", "LINPUT1" }, /* Really Boost Switch */
Mark Brownf2644a22009-04-07 19:20:14 +0100414 { "Left Input Mixer", NULL, "LINPUT2" },
415 { "Left Input Mixer", NULL, "LINPUT3" },
416
417 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
418 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
419 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
420
Zidan Wang2d4a3262016-01-08 16:57:02 +0800421 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer" },
422 { "Right Input Mixer", "Boost Switch", "RINPUT1" }, /* Really Boost Switch */
Mark Brownf2644a22009-04-07 19:20:14 +0100423 { "Right Input Mixer", NULL, "RINPUT2" },
Zidan Wang85e36a1f2015-05-12 14:58:36 +0800424 { "Right Input Mixer", NULL, "RINPUT3" },
Mark Brownf2644a22009-04-07 19:20:14 +0100425
426 { "Left ADC", NULL, "Left Input Mixer" },
427 { "Right ADC", NULL, "Right Input Mixer" },
428
429 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
Zidan Wang2d4a3262016-01-08 16:57:02 +0800430 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" },
Mark Brownf2644a22009-04-07 19:20:14 +0100431 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
432
433 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
Zidan Wang2d4a3262016-01-08 16:57:02 +0800434 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" },
Mark Brownf2644a22009-04-07 19:20:14 +0100435 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
436
Mark Brownf2644a22009-04-07 19:20:14 +0100437 { "LOUT1 PGA", NULL, "Left Output Mixer" },
438 { "ROUT1 PGA", NULL, "Right Output Mixer" },
439
440 { "HP_L", NULL, "LOUT1 PGA" },
441 { "HP_R", NULL, "ROUT1 PGA" },
442
443 { "Left Speaker PGA", NULL, "Left Output Mixer" },
444 { "Right Speaker PGA", NULL, "Right Output Mixer" },
445
446 { "Left Speaker Output", NULL, "Left Speaker PGA" },
447 { "Right Speaker Output", NULL, "Right Speaker PGA" },
448
449 { "SPK_LN", NULL, "Left Speaker Output" },
450 { "SPK_LP", NULL, "Left Speaker Output" },
451 { "SPK_RN", NULL, "Right Speaker Output" },
452 { "SPK_RP", NULL, "Right Speaker Output" },
Mark Brown913d7b42010-03-03 13:47:03 +0000453};
454
455static const struct snd_soc_dapm_route audio_paths_out3[] = {
456 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
457 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
Mark Brownf2644a22009-04-07 19:20:14 +0100458
459 { "OUT3", NULL, "Mono Output Mixer", }
460};
461
Mark Brown913d7b42010-03-03 13:47:03 +0000462static const struct snd_soc_dapm_route audio_paths_capless[] = {
463 { "HP_L", NULL, "OUT3 VMID" },
464 { "HP_R", NULL, "OUT3 VMID" },
465
466 { "OUT3 VMID", NULL, "Left Output Mixer" },
467 { "OUT3 VMID", NULL, "Right Output Mixer" },
468};
469
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000470static int wm8960_add_widgets(struct snd_soc_component *component)
Mark Brownf2644a22009-04-07 19:20:14 +0100471{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000472 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Zidan Wange2280c902014-11-20 19:07:48 +0800473 struct wm8960_data *pdata = &wm8960->pdata;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000474 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
Mark Brown913d7b42010-03-03 13:47:03 +0000475 struct snd_soc_dapm_widget *w;
476
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200477 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
Mark Brownf2644a22009-04-07 19:20:14 +0100478 ARRAY_SIZE(wm8960_dapm_widgets));
479
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200480 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
Mark Brownf2644a22009-04-07 19:20:14 +0100481
Mark Brown913d7b42010-03-03 13:47:03 +0000482 /* In capless mode OUT3 is used to provide VMID for the
483 * headphone outputs, otherwise it is used as a mono mixer.
484 */
485 if (pdata && pdata->capless) {
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200486 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
Mark Brown913d7b42010-03-03 13:47:03 +0000487 ARRAY_SIZE(wm8960_dapm_widgets_capless));
488
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200489 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
Mark Brown913d7b42010-03-03 13:47:03 +0000490 ARRAY_SIZE(audio_paths_capless));
491 } else {
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200492 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
Mark Brown913d7b42010-03-03 13:47:03 +0000493 ARRAY_SIZE(wm8960_dapm_widgets_out3));
494
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200495 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
Mark Brown913d7b42010-03-03 13:47:03 +0000496 ARRAY_SIZE(audio_paths_out3));
497 }
498
499 /* We need to power up the headphone output stage out of
500 * sequence for capless mode. To save scanning the widget
501 * list each time to find the desired power state do so now
502 * and save the result.
503 */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000504 list_for_each_entry(w, &component->card->widgets, list) {
Lars-Peter Clausen93f32f52015-06-01 10:10:48 +0200505 if (w->dapm != dapm)
Jarkko Nikula97c866d2010-12-14 12:18:31 +0200506 continue;
Mark Brown913d7b42010-03-03 13:47:03 +0000507 if (strcmp(w->name, "LOUT1 PGA") == 0)
508 wm8960->lout1 = w;
509 if (strcmp(w->name, "ROUT1 PGA") == 0)
510 wm8960->rout1 = w;
511 if (strcmp(w->name, "OUT3 VMID") == 0)
512 wm8960->out3 = w;
513 }
514
Mark Brownf2644a22009-04-07 19:20:14 +0100515 return 0;
516}
517
518static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
519 unsigned int fmt)
520{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000521 struct snd_soc_component *component = codec_dai->component;
Mark Brownf2644a22009-04-07 19:20:14 +0100522 u16 iface = 0;
523
524 /* set master/slave audio interface */
525 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
526 case SND_SOC_DAIFMT_CBM_CFM:
527 iface |= 0x0040;
528 break;
529 case SND_SOC_DAIFMT_CBS_CFS:
530 break;
531 default:
532 return -EINVAL;
533 }
534
535 /* interface format */
536 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
537 case SND_SOC_DAIFMT_I2S:
538 iface |= 0x0002;
539 break;
540 case SND_SOC_DAIFMT_RIGHT_J:
541 break;
542 case SND_SOC_DAIFMT_LEFT_J:
543 iface |= 0x0001;
544 break;
545 case SND_SOC_DAIFMT_DSP_A:
546 iface |= 0x0003;
547 break;
548 case SND_SOC_DAIFMT_DSP_B:
549 iface |= 0x0013;
550 break;
551 default:
552 return -EINVAL;
553 }
554
555 /* clock inversion */
556 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
557 case SND_SOC_DAIFMT_NB_NF:
558 break;
559 case SND_SOC_DAIFMT_IB_IF:
560 iface |= 0x0090;
561 break;
562 case SND_SOC_DAIFMT_IB_NF:
563 iface |= 0x0080;
564 break;
565 case SND_SOC_DAIFMT_NB_IF:
566 iface |= 0x0010;
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 /* set iface */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000573 snd_soc_component_write(component, WM8960_IFACE1, iface);
Mark Brownf2644a22009-04-07 19:20:14 +0100574 return 0;
575}
576
Mark Browndb059c02010-07-05 23:54:51 +0900577static struct {
578 int rate;
579 unsigned int val;
580} alc_rates[] = {
581 { 48000, 0 },
582 { 44100, 0 },
583 { 32000, 1 },
584 { 22050, 2 },
585 { 24000, 2 },
586 { 16000, 3 },
Zidan Wang22ee76d2014-12-31 11:39:14 +0800587 { 11025, 4 },
Mark Browndb059c02010-07-05 23:54:51 +0900588 { 12000, 4 },
589 { 8000, 5 },
590};
591
Zidan Wang3176bf22015-08-11 19:25:15 +0800592/* -1 for reserved value */
593static const int sysclk_divs[] = { 1, -1, 2, -1 };
594
Zidan Wang0e50b512015-05-12 14:58:08 +0800595/* Multiply 256 for internal 256 div */
596static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
597
598/* Multiply 10 to eliminate decimials */
599static const int bclk_divs[] = {
600 10, 15, 20, 30, 40, 55, 60, 80, 110,
601 120, 160, 220, 240, 320, 320, 320
602};
603
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200604/**
605 * wm8960_configure_sysclk - checks if there is a sysclk frequency available
606 * The sysclk must be chosen such that:
607 * - sysclk = MCLK / sysclk_divs
608 * - lrclk = sysclk / dac_divs
609 * - 10 * bclk = sysclk / bclk_divs
610 *
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200611 * If we cannot find an exact match for (sysclk, lrclk, bclk)
612 * triplet, we relax the bclk such that bclk is chosen as the
613 * closest available frequency greater than expected bclk.
614 *
Pierre-Louis Bossart419eac32020-07-01 13:13:17 -0500615 * @wm8960: codec private data
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200616 * @mclk: MCLK used to derive sysclk
617 * @sysclk_idx: sysclk_divs index for found sysclk
618 * @dac_idx: dac_divs index for found lrclk
619 * @bclk_idx: bclk_divs index for found bclk
620 *
621 * Returns:
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200622 * -1, in case no sysclk frequency available found
623 * >=0, in case we could derive bclk and lrclk from sysclk using
624 * (@sysclk_idx, @dac_idx, @bclk_idx) dividers
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200625 */
626static
627int wm8960_configure_sysclk(struct wm8960_priv *wm8960, int mclk,
628 int *sysclk_idx, int *dac_idx, int *bclk_idx)
629{
630 int sysclk, bclk, lrclk;
631 int i, j, k;
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200632 int diff, closest = mclk;
633
634 /* marker for no match */
635 *bclk_idx = -1;
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200636
637 bclk = wm8960->bclk;
638 lrclk = wm8960->lrclk;
639
640 /* check if the sysclk frequency is available. */
641 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
642 if (sysclk_divs[i] == -1)
643 continue;
644 sysclk = mclk / sysclk_divs[i];
645 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
646 if (sysclk != dac_divs[j] * lrclk)
647 continue;
648 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
649 diff = sysclk - bclk * bclk_divs[k] / 10;
650 if (diff == 0) {
651 *sysclk_idx = i;
652 *dac_idx = j;
653 *bclk_idx = k;
654 break;
655 }
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200656 if (diff > 0 && closest > diff) {
657 *sysclk_idx = i;
658 *dac_idx = j;
659 *bclk_idx = k;
660 closest = diff;
661 }
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200662 }
663 if (k != ARRAY_SIZE(bclk_divs))
664 break;
665 }
666 if (j != ARRAY_SIZE(dac_divs))
667 break;
668 }
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200669 return *bclk_idx;
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200670}
671
Daniel Baluta84fdc002017-04-04 19:45:13 +0300672/**
673 * wm8960_configure_pll - checks if there is a PLL out frequency available
674 * The PLL out frequency must be chosen such that:
675 * - sysclk = lrclk * dac_divs
676 * - freq_out = sysclk * sysclk_divs
677 * - 10 * sysclk = bclk * bclk_divs
678 *
Daniel Baluta82bab882017-04-26 16:09:52 +0300679 * If we cannot find an exact match for (sysclk, lrclk, bclk)
680 * triplet, we relax the bclk such that bclk is chosen as the
681 * closest available frequency greater than expected bclk.
682 *
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000683 * @component: component structure
Daniel Baluta84fdc002017-04-04 19:45:13 +0300684 * @freq_in: input frequency used to derive freq out via PLL
685 * @sysclk_idx: sysclk_divs index for found sysclk
686 * @dac_idx: dac_divs index for found lrclk
687 * @bclk_idx: bclk_divs index for found bclk
688 *
689 * Returns:
Daniel Baluta66772ed2017-04-26 16:09:51 +0300690 * < 0, in case no PLL frequency out available was found
Daniel Baluta84fdc002017-04-04 19:45:13 +0300691 * >=0, in case we could derive bclk, lrclk, sysclk from PLL out using
692 * (@sysclk_idx, @dac_idx, @bclk_idx) dividers
693 */
694static
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000695int wm8960_configure_pll(struct snd_soc_component *component, int freq_in,
Daniel Baluta84fdc002017-04-04 19:45:13 +0300696 int *sysclk_idx, int *dac_idx, int *bclk_idx)
697{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000698 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Daniel Baluta84fdc002017-04-04 19:45:13 +0300699 int sysclk, bclk, lrclk, freq_out;
Daniel Baluta82bab882017-04-26 16:09:52 +0300700 int diff, closest, best_freq_out;
Daniel Baluta84fdc002017-04-04 19:45:13 +0300701 int i, j, k;
702
703 bclk = wm8960->bclk;
704 lrclk = wm8960->lrclk;
Daniel Baluta82bab882017-04-26 16:09:52 +0300705 closest = freq_in;
Daniel Baluta84fdc002017-04-04 19:45:13 +0300706
Daniel Baluta82bab882017-04-26 16:09:52 +0300707 best_freq_out = -EINVAL;
Daniel Baluta66772ed2017-04-26 16:09:51 +0300708 *sysclk_idx = *dac_idx = *bclk_idx = -1;
Daniel Baluta84fdc002017-04-04 19:45:13 +0300709
710 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
711 if (sysclk_divs[i] == -1)
712 continue;
713 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
714 sysclk = lrclk * dac_divs[j];
715 freq_out = sysclk * sysclk_divs[i];
716
717 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
718 if (!is_pll_freq_available(freq_in, freq_out))
719 continue;
720
721 diff = sysclk - bclk * bclk_divs[k] / 10;
722 if (diff == 0) {
723 *sysclk_idx = i;
724 *dac_idx = j;
725 *bclk_idx = k;
Daniel Baluta66772ed2017-04-26 16:09:51 +0300726 return freq_out;
Daniel Baluta84fdc002017-04-04 19:45:13 +0300727 }
Daniel Baluta82bab882017-04-26 16:09:52 +0300728 if (diff > 0 && closest > diff) {
729 *sysclk_idx = i;
730 *dac_idx = j;
731 *bclk_idx = k;
732 closest = diff;
733 best_freq_out = freq_out;
734 }
Daniel Baluta84fdc002017-04-04 19:45:13 +0300735 }
736 }
737 }
Daniel Baluta82bab882017-04-26 16:09:52 +0300738
739 return best_freq_out;
Daniel Baluta84fdc002017-04-04 19:45:13 +0300740}
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000741static int wm8960_configure_clocking(struct snd_soc_component *component)
Zidan Wang0e50b512015-05-12 14:58:08 +0800742{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000743 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Daniel Baluta84fdc002017-04-04 19:45:13 +0300744 int freq_out, freq_in;
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +0900745 u16 iface1 = snd_soc_component_read(component, WM8960_IFACE1);
Zidan Wang3176bf22015-08-11 19:25:15 +0800746 int i, j, k;
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200747 int ret;
Zidan Wang0e50b512015-05-12 14:58:08 +0800748
749 if (!(iface1 & (1<<6))) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000750 dev_dbg(component->dev,
Zidan Wang0e50b512015-05-12 14:58:08 +0800751 "Codec is slave mode, no need to configure clock\n");
Zidan Wang3176bf22015-08-11 19:25:15 +0800752 return 0;
Zidan Wang0e50b512015-05-12 14:58:08 +0800753 }
754
Zidan Wang3176bf22015-08-11 19:25:15 +0800755 if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000756 dev_err(component->dev, "No MCLK configured\n");
Zidan Wang3176bf22015-08-11 19:25:15 +0800757 return -EINVAL;
Zidan Wang0e50b512015-05-12 14:58:08 +0800758 }
759
Zidan Wang3176bf22015-08-11 19:25:15 +0800760 freq_in = wm8960->freq_in;
Zidan Wang3176bf22015-08-11 19:25:15 +0800761 /*
762 * If it's sysclk auto mode, check if the MCLK can provide sysclk or
763 * not. If MCLK can provide sysclk, using MCLK to provide sysclk
764 * directly. Otherwise, auto select a available pll out frequency
765 * and set PLL.
766 */
767 if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
768 /* disable the PLL and using MCLK to provide sysclk */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000769 wm8960_set_pll(component, 0, 0);
Zidan Wang3176bf22015-08-11 19:25:15 +0800770 freq_out = freq_in;
771 } else if (wm8960->sysclk) {
772 freq_out = wm8960->sysclk;
773 } else {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000774 dev_err(component->dev, "No SYSCLK configured\n");
Zidan Wang3176bf22015-08-11 19:25:15 +0800775 return -EINVAL;
Zidan Wang0e50b512015-05-12 14:58:08 +0800776 }
777
Stuart Henderson6bb74512016-01-19 13:09:09 +0000778 if (wm8960->clk_id != WM8960_SYSCLK_PLL) {
Daniel Baluta3ddc9722017-03-21 17:03:24 +0200779 ret = wm8960_configure_sysclk(wm8960, freq_out, &i, &j, &k);
Daniel Baluta3c01b9e2017-03-21 17:03:25 +0200780 if (ret >= 0) {
Stuart Henderson6bb74512016-01-19 13:09:09 +0000781 goto configure_clock;
782 } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000783 dev_err(component->dev, "failed to configure clock\n");
Stuart Henderson6bb74512016-01-19 13:09:09 +0000784 return -EINVAL;
785 }
Zidan Wang3176bf22015-08-11 19:25:15 +0800786 }
Zidan Wang3176bf22015-08-11 19:25:15 +0800787
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000788 freq_out = wm8960_configure_pll(component, freq_in, &i, &j, &k);
Daniel Baluta66772ed2017-04-26 16:09:51 +0300789 if (freq_out < 0) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000790 dev_err(component->dev, "failed to configure clock via PLL\n");
Daniel Baluta66772ed2017-04-26 16:09:51 +0300791 return freq_out;
Zidan Wang0e50b512015-05-12 14:58:08 +0800792 }
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000793 wm8960_set_pll(component, freq_in, freq_out);
Zidan Wang0e50b512015-05-12 14:58:08 +0800794
Zidan Wang3176bf22015-08-11 19:25:15 +0800795configure_clock:
796 /* configure sysclk clock */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000797 snd_soc_component_update_bits(component, WM8960_CLOCK1, 3 << 1, i << 1);
Zidan Wang3176bf22015-08-11 19:25:15 +0800798
799 /* configure frame clock */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000800 snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 3, j << 3);
801 snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 6, j << 6);
Zidan Wang0e50b512015-05-12 14:58:08 +0800802
803 /* configure bit clock */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000804 snd_soc_component_update_bits(component, WM8960_CLOCK2, 0xf, k);
Zidan Wang3176bf22015-08-11 19:25:15 +0800805
806 return 0;
Zidan Wang0e50b512015-05-12 14:58:08 +0800807}
808
Mark Brownf2644a22009-04-07 19:20:14 +0100809static int wm8960_hw_params(struct snd_pcm_substream *substream,
810 struct snd_pcm_hw_params *params,
811 struct snd_soc_dai *dai)
812{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000813 struct snd_soc_component *component = dai->component;
814 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +0900815 u16 iface = snd_soc_component_read(component, WM8960_IFACE1) & 0xfff3;
Zidan Wang0e50b512015-05-12 14:58:08 +0800816 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Mark Browndb059c02010-07-05 23:54:51 +0900817 int i;
Mark Brownf2644a22009-04-07 19:20:14 +0100818
Zidan Wang0e50b512015-05-12 14:58:08 +0800819 wm8960->bclk = snd_soc_params_to_bclk(params);
820 if (params_channels(params) == 1)
821 wm8960->bclk *= 2;
822
Mark Brownf2644a22009-04-07 19:20:14 +0100823 /* bit size */
Mark Brown39e9cc42014-07-31 12:53:23 +0100824 switch (params_width(params)) {
825 case 16:
Mark Brownf2644a22009-04-07 19:20:14 +0100826 break;
Mark Brown39e9cc42014-07-31 12:53:23 +0100827 case 20:
Mark Brownf2644a22009-04-07 19:20:14 +0100828 iface |= 0x0004;
829 break;
Mark Brown39e9cc42014-07-31 12:53:23 +0100830 case 24:
Mark Brownf2644a22009-04-07 19:20:14 +0100831 iface |= 0x0008;
832 break;
Zidan Wang7a8c7862015-05-12 14:58:21 +0800833 case 32:
834 /* right justify mode does not support 32 word length */
835 if ((iface & 0x3) != 0) {
836 iface |= 0x000c;
837 break;
838 }
Gustavo A. R. Silva3e146b52020-07-08 20:03:59 -0500839 fallthrough;
Timur Tabi4c2474c2012-09-14 16:14:37 -0500840 default:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000841 dev_err(component->dev, "unsupported width %d\n",
Mark Brown39e9cc42014-07-31 12:53:23 +0100842 params_width(params));
Timur Tabi4c2474c2012-09-14 16:14:37 -0500843 return -EINVAL;
Mark Brownf2644a22009-04-07 19:20:14 +0100844 }
845
Zidan Wang3176bf22015-08-11 19:25:15 +0800846 wm8960->lrclk = params_rate(params);
Mark Brownafd6d362010-07-05 13:58:16 +0900847 /* Update filters for the new rate */
Zidan Wang3176bf22015-08-11 19:25:15 +0800848 if (tx) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000849 wm8960_set_deemph(component);
Mark Browndb059c02010-07-05 23:54:51 +0900850 } else {
851 for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
852 if (alc_rates[i].rate == params_rate(params))
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000853 snd_soc_component_update_bits(component,
Mark Browndb059c02010-07-05 23:54:51 +0900854 WM8960_ADDCTL3, 0x7,
855 alc_rates[i].val);
Mark Brownafd6d362010-07-05 13:58:16 +0900856 }
857
Mark Brownf2644a22009-04-07 19:20:14 +0100858 /* set iface */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000859 snd_soc_component_write(component, WM8960_IFACE1, iface);
Zidan Wang0e50b512015-05-12 14:58:08 +0800860
Zidan Wang3176bf22015-08-11 19:25:15 +0800861 wm8960->is_stream_in_use[tx] = true;
862
Shengjiu Wang1e060a42020-04-21 19:28:45 +0800863 if (!wm8960->is_stream_in_use[!tx])
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000864 return wm8960_configure_clocking(component);
Zidan Wang3176bf22015-08-11 19:25:15 +0800865
866 return 0;
867}
868
869static int wm8960_hw_free(struct snd_pcm_substream *substream,
870 struct snd_soc_dai *dai)
871{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000872 struct snd_soc_component *component = dai->component;
873 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Zidan Wang3176bf22015-08-11 19:25:15 +0800874 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
875
876 wm8960->is_stream_in_use[tx] = false;
Zidan Wang0e50b512015-05-12 14:58:08 +0800877
Mark Brownf2644a22009-04-07 19:20:14 +0100878 return 0;
879}
880
Kuninori Morimoto26d3c162020-07-09 10:56:53 +0900881static int wm8960_mute(struct snd_soc_dai *dai, int mute, int direction)
Mark Brownf2644a22009-04-07 19:20:14 +0100882{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000883 struct snd_soc_component *component = dai->component;
Mark Brownf2644a22009-04-07 19:20:14 +0100884
885 if (mute)
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000886 snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0x8);
Mark Brownf2644a22009-04-07 19:20:14 +0100887 else
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000888 snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0);
Mark Brownf2644a22009-04-07 19:20:14 +0100889 return 0;
890}
891
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000892static int wm8960_set_bias_level_out3(struct snd_soc_component *component,
Mark Brown913d7b42010-03-03 13:47:03 +0000893 enum snd_soc_bias_level level)
Mark Brownf2644a22009-04-07 19:20:14 +0100894{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000895 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +0900896 u16 pm2 = snd_soc_component_read(component, WM8960_POWER2);
Zidan Wang75aa8862015-01-07 15:31:44 +0800897 int ret;
Mark Brown0ebe36c2012-09-10 19:23:57 +0800898
Mark Brownf2644a22009-04-07 19:20:14 +0100899 switch (level) {
900 case SND_SOC_BIAS_ON:
901 break;
902
903 case SND_SOC_BIAS_PREPARE:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000904 switch (snd_soc_component_get_bias_level(component)) {
Zidan Wang75aa8862015-01-07 15:31:44 +0800905 case SND_SOC_BIAS_STANDBY:
906 if (!IS_ERR(wm8960->mclk)) {
907 ret = clk_prepare_enable(wm8960->mclk);
908 if (ret) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000909 dev_err(component->dev,
Zidan Wang75aa8862015-01-07 15:31:44 +0800910 "Failed to enable MCLK: %d\n",
911 ret);
912 return ret;
913 }
914 }
915
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000916 ret = wm8960_configure_clocking(component);
Zidan Wang3176bf22015-08-11 19:25:15 +0800917 if (ret)
918 return ret;
919
Zidan Wang75aa8862015-01-07 15:31:44 +0800920 /* Set VMID to 2x50k */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000921 snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x80);
Zidan Wang75aa8862015-01-07 15:31:44 +0800922 break;
923
924 case SND_SOC_BIAS_ON:
Zidan Wang3176bf22015-08-11 19:25:15 +0800925 /*
926 * If it's sysclk auto mode, and the pll is enabled,
927 * disable the pll
928 */
929 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000930 wm8960_set_pll(component, 0, 0);
Zidan Wang3176bf22015-08-11 19:25:15 +0800931
Zidan Wang75aa8862015-01-07 15:31:44 +0800932 if (!IS_ERR(wm8960->mclk))
933 clk_disable_unprepare(wm8960->mclk);
934 break;
935
936 default:
937 break;
938 }
939
Mark Brownf2644a22009-04-07 19:20:14 +0100940 break;
941
942 case SND_SOC_BIAS_STANDBY:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000943 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
Mark Brown0ebe36c2012-09-10 19:23:57 +0800944 regcache_sync(wm8960->regmap);
Axel Linbc45df22011-10-07 21:50:23 +0800945
Mark Brownf2644a22009-04-07 19:20:14 +0100946 /* Enable anti-pop features */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000947 snd_soc_component_write(component, WM8960_APOP1,
Mark Brown913d7b42010-03-03 13:47:03 +0000948 WM8960_POBCTRL | WM8960_SOFT_ST |
949 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
Mark Brownf2644a22009-04-07 19:20:14 +0100950
951 /* Enable & ramp VMID at 2x50k */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000952 snd_soc_component_update_bits(component, WM8960_POWER1, 0x80, 0x80);
Mark Brownf2644a22009-04-07 19:20:14 +0100953 msleep(100);
954
955 /* Enable VREF */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000956 snd_soc_component_update_bits(component, WM8960_POWER1, WM8960_VREF,
Axel Lin16b24882011-12-08 11:09:15 +0800957 WM8960_VREF);
Mark Brownf2644a22009-04-07 19:20:14 +0100958
959 /* Disable anti-pop features */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000960 snd_soc_component_write(component, WM8960_APOP1, WM8960_BUFIOEN);
Mark Brownf2644a22009-04-07 19:20:14 +0100961 }
962
963 /* Set VMID to 2x250k */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000964 snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x100);
Mark Brownf2644a22009-04-07 19:20:14 +0100965 break;
966
967 case SND_SOC_BIAS_OFF:
968 /* Enable anti-pop features */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000969 snd_soc_component_write(component, WM8960_APOP1,
Mark Brownf2644a22009-04-07 19:20:14 +0100970 WM8960_POBCTRL | WM8960_SOFT_ST |
971 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
972
973 /* Disable VMID and VREF, let them discharge */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000974 snd_soc_component_write(component, WM8960_POWER1, 0);
Mark Brownf2644a22009-04-07 19:20:14 +0100975 msleep(600);
Mark Brown913d7b42010-03-03 13:47:03 +0000976 break;
977 }
Mark Brownf2644a22009-04-07 19:20:14 +0100978
Mark Brown913d7b42010-03-03 13:47:03 +0000979 return 0;
980}
981
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000982static int wm8960_set_bias_level_capless(struct snd_soc_component *component,
Mark Brown913d7b42010-03-03 13:47:03 +0000983 enum snd_soc_bias_level level)
984{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000985 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +0900986 u16 pm2 = snd_soc_component_read(component, WM8960_POWER2);
Zidan Wang75aa8862015-01-07 15:31:44 +0800987 int reg, ret;
Mark Brown913d7b42010-03-03 13:47:03 +0000988
989 switch (level) {
990 case SND_SOC_BIAS_ON:
991 break;
992
993 case SND_SOC_BIAS_PREPARE:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000994 switch (snd_soc_component_get_bias_level(component)) {
Mark Brown913d7b42010-03-03 13:47:03 +0000995 case SND_SOC_BIAS_STANDBY:
996 /* Enable anti pop mode */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +0000997 snd_soc_component_update_bits(component, WM8960_APOP1,
Mark Brown913d7b42010-03-03 13:47:03 +0000998 WM8960_POBCTRL | WM8960_SOFT_ST |
999 WM8960_BUFDCOPEN,
1000 WM8960_POBCTRL | WM8960_SOFT_ST |
1001 WM8960_BUFDCOPEN);
1002
1003 /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
1004 reg = 0;
1005 if (wm8960->lout1 && wm8960->lout1->power)
1006 reg |= WM8960_PWR2_LOUT1;
1007 if (wm8960->rout1 && wm8960->rout1->power)
1008 reg |= WM8960_PWR2_ROUT1;
1009 if (wm8960->out3 && wm8960->out3->power)
1010 reg |= WM8960_PWR2_OUT3;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001011 snd_soc_component_update_bits(component, WM8960_POWER2,
Mark Brown913d7b42010-03-03 13:47:03 +00001012 WM8960_PWR2_LOUT1 |
1013 WM8960_PWR2_ROUT1 |
1014 WM8960_PWR2_OUT3, reg);
1015
1016 /* Enable VMID at 2*50k */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001017 snd_soc_component_update_bits(component, WM8960_POWER1,
Mark Brown913d7b42010-03-03 13:47:03 +00001018 WM8960_VMID_MASK, 0x80);
1019
1020 /* Ramp */
1021 msleep(100);
1022
1023 /* Enable VREF */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001024 snd_soc_component_update_bits(component, WM8960_POWER1,
Mark Brown913d7b42010-03-03 13:47:03 +00001025 WM8960_VREF, WM8960_VREF);
1026
1027 msleep(100);
Zidan Wang75aa8862015-01-07 15:31:44 +08001028
1029 if (!IS_ERR(wm8960->mclk)) {
1030 ret = clk_prepare_enable(wm8960->mclk);
1031 if (ret) {
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001032 dev_err(component->dev,
Zidan Wang75aa8862015-01-07 15:31:44 +08001033 "Failed to enable MCLK: %d\n",
1034 ret);
1035 return ret;
1036 }
1037 }
Zidan Wang3176bf22015-08-11 19:25:15 +08001038
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001039 ret = wm8960_configure_clocking(component);
Zidan Wang3176bf22015-08-11 19:25:15 +08001040 if (ret)
1041 return ret;
1042
Mark Brown913d7b42010-03-03 13:47:03 +00001043 break;
1044
1045 case SND_SOC_BIAS_ON:
Zidan Wang3176bf22015-08-11 19:25:15 +08001046 /*
1047 * If it's sysclk auto mode, and the pll is enabled,
1048 * disable the pll
1049 */
1050 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001051 wm8960_set_pll(component, 0, 0);
Zidan Wang3176bf22015-08-11 19:25:15 +08001052
Zidan Wang75aa8862015-01-07 15:31:44 +08001053 if (!IS_ERR(wm8960->mclk))
1054 clk_disable_unprepare(wm8960->mclk);
1055
Mark Brown913d7b42010-03-03 13:47:03 +00001056 /* Enable anti-pop mode */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001057 snd_soc_component_update_bits(component, WM8960_APOP1,
Mark Brown913d7b42010-03-03 13:47:03 +00001058 WM8960_POBCTRL | WM8960_SOFT_ST |
1059 WM8960_BUFDCOPEN,
1060 WM8960_POBCTRL | WM8960_SOFT_ST |
1061 WM8960_BUFDCOPEN);
1062
1063 /* Disable VMID and VREF */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001064 snd_soc_component_update_bits(component, WM8960_POWER1,
Mark Brown913d7b42010-03-03 13:47:03 +00001065 WM8960_VREF | WM8960_VMID_MASK, 0);
1066 break;
1067
Axel Linbc45df22011-10-07 21:50:23 +08001068 case SND_SOC_BIAS_OFF:
Mark Brown0ebe36c2012-09-10 19:23:57 +08001069 regcache_sync(wm8960->regmap);
Axel Linbc45df22011-10-07 21:50:23 +08001070 break;
Mark Brown913d7b42010-03-03 13:47:03 +00001071 default:
1072 break;
1073 }
1074 break;
1075
1076 case SND_SOC_BIAS_STANDBY:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001077 switch (snd_soc_component_get_bias_level(component)) {
Mark Brown913d7b42010-03-03 13:47:03 +00001078 case SND_SOC_BIAS_PREPARE:
1079 /* Disable HP discharge */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001080 snd_soc_component_update_bits(component, WM8960_APOP2,
Mark Brown913d7b42010-03-03 13:47:03 +00001081 WM8960_DISOP | WM8960_DRES_MASK,
1082 0);
1083
1084 /* Disable anti-pop features */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001085 snd_soc_component_update_bits(component, WM8960_APOP1,
Mark Brown913d7b42010-03-03 13:47:03 +00001086 WM8960_POBCTRL | WM8960_SOFT_ST |
1087 WM8960_BUFDCOPEN,
1088 WM8960_POBCTRL | WM8960_SOFT_ST |
1089 WM8960_BUFDCOPEN);
1090 break;
1091
1092 default:
1093 break;
1094 }
1095 break;
1096
1097 case SND_SOC_BIAS_OFF:
Mark Brownf2644a22009-04-07 19:20:14 +01001098 break;
1099 }
1100
Mark Brownf2644a22009-04-07 19:20:14 +01001101 return 0;
1102}
1103
1104/* PLL divisors */
1105struct _pll_div {
1106 u32 pre_div:1;
1107 u32 n:4;
1108 u32 k:24;
1109};
1110
Zidan Wang3176bf22015-08-11 19:25:15 +08001111static bool is_pll_freq_available(unsigned int source, unsigned int target)
1112{
1113 unsigned int Ndiv;
1114
1115 if (source == 0 || target == 0)
1116 return false;
1117
1118 /* Scale up target to PLL operating frequency */
1119 target *= 4;
1120 Ndiv = target / source;
1121
1122 if (Ndiv < 6) {
1123 source >>= 1;
1124 Ndiv = target / source;
1125 }
1126
1127 if ((Ndiv < 6) || (Ndiv > 12))
1128 return false;
1129
1130 return true;
1131}
1132
Mark Brownf2644a22009-04-07 19:20:14 +01001133/* The size in bits of the pll divide multiplied by 10
1134 * to allow rounding later */
1135#define FIXED_PLL_SIZE ((1 << 24) * 10)
1136
1137static int pll_factors(unsigned int source, unsigned int target,
1138 struct _pll_div *pll_div)
1139{
1140 unsigned long long Kpart;
1141 unsigned int K, Ndiv, Nmod;
1142
1143 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
1144
1145 /* Scale up target to PLL operating frequency */
1146 target *= 4;
1147
1148 Ndiv = target / source;
1149 if (Ndiv < 6) {
1150 source >>= 1;
1151 pll_div->pre_div = 1;
1152 Ndiv = target / source;
1153 } else
1154 pll_div->pre_div = 0;
1155
1156 if ((Ndiv < 6) || (Ndiv > 12)) {
1157 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
1158 return -EINVAL;
1159 }
1160
1161 pll_div->n = Ndiv;
1162 Nmod = target % source;
1163 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1164
1165 do_div(Kpart, source);
1166
1167 K = Kpart & 0xFFFFFFFF;
1168
1169 /* Check if we need to round */
1170 if ((K % 10) >= 5)
1171 K += 5;
1172
1173 /* Move down to proper range now rounding is done */
1174 K /= 10;
1175
1176 pll_div->k = K;
1177
1178 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
1179 pll_div->n, pll_div->k, pll_div->pre_div);
1180
1181 return 0;
1182}
1183
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001184static int wm8960_set_pll(struct snd_soc_component *component,
Zidan Wang3176bf22015-08-11 19:25:15 +08001185 unsigned int freq_in, unsigned int freq_out)
Mark Brownf2644a22009-04-07 19:20:14 +01001186{
Mark Brownf2644a22009-04-07 19:20:14 +01001187 u16 reg;
1188 static struct _pll_div pll_div;
1189 int ret;
1190
1191 if (freq_in && freq_out) {
1192 ret = pll_factors(freq_in, freq_out, &pll_div);
1193 if (ret != 0)
1194 return ret;
1195 }
1196
1197 /* Disable the PLL: even if we are changing the frequency the
1198 * PLL needs to be disabled while we do so. */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001199 snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0);
1200 snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0);
Mark Brownf2644a22009-04-07 19:20:14 +01001201
1202 if (!freq_in || !freq_out)
1203 return 0;
1204
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001205 reg = snd_soc_component_read(component, WM8960_PLL1) & ~0x3f;
Mark Brownf2644a22009-04-07 19:20:14 +01001206 reg |= pll_div.pre_div << 4;
1207 reg |= pll_div.n;
1208
1209 if (pll_div.k) {
1210 reg |= 0x20;
1211
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001212 snd_soc_component_write(component, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
1213 snd_soc_component_write(component, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
1214 snd_soc_component_write(component, WM8960_PLL4, pll_div.k & 0xff);
Mark Brownf2644a22009-04-07 19:20:14 +01001215 }
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001216 snd_soc_component_write(component, WM8960_PLL1, reg);
Mark Brownf2644a22009-04-07 19:20:14 +01001217
1218 /* Turn it on */
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001219 snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0x1);
Mark Brownf2644a22009-04-07 19:20:14 +01001220 msleep(250);
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001221 snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0x1);
Mark Brownf2644a22009-04-07 19:20:14 +01001222
1223 return 0;
1224}
1225
Zidan Wang3176bf22015-08-11 19:25:15 +08001226static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1227 int source, unsigned int freq_in, unsigned int freq_out)
1228{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001229 struct snd_soc_component *component = codec_dai->component;
1230 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Zidan Wang3176bf22015-08-11 19:25:15 +08001231
1232 wm8960->freq_in = freq_in;
1233
1234 if (pll_id == WM8960_SYSCLK_AUTO)
1235 return 0;
1236
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001237 return wm8960_set_pll(component, freq_in, freq_out);
Zidan Wang3176bf22015-08-11 19:25:15 +08001238}
1239
Mark Brownf2644a22009-04-07 19:20:14 +01001240static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1241 int div_id, int div)
1242{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001243 struct snd_soc_component *component = codec_dai->component;
Mark Brownf2644a22009-04-07 19:20:14 +01001244 u16 reg;
1245
1246 switch (div_id) {
Mark Brownf2644a22009-04-07 19:20:14 +01001247 case WM8960_SYSCLKDIV:
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001248 reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1f9;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001249 snd_soc_component_write(component, WM8960_CLOCK1, reg | div);
Mark Brownf2644a22009-04-07 19:20:14 +01001250 break;
1251 case WM8960_DACDIV:
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001252 reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1c7;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001253 snd_soc_component_write(component, WM8960_CLOCK1, reg | div);
Mark Brownf2644a22009-04-07 19:20:14 +01001254 break;
1255 case WM8960_OPCLKDIV:
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001256 reg = snd_soc_component_read(component, WM8960_PLL1) & 0x03f;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001257 snd_soc_component_write(component, WM8960_PLL1, reg | div);
Mark Brownf2644a22009-04-07 19:20:14 +01001258 break;
1259 case WM8960_DCLKDIV:
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001260 reg = snd_soc_component_read(component, WM8960_CLOCK2) & 0x03f;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001261 snd_soc_component_write(component, WM8960_CLOCK2, reg | div);
Mark Brownf2644a22009-04-07 19:20:14 +01001262 break;
1263 case WM8960_TOCLKSEL:
Kuninori Morimoto6d75dfc2020-06-16 14:21:29 +09001264 reg = snd_soc_component_read(component, WM8960_ADDCTL1) & 0x1fd;
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001265 snd_soc_component_write(component, WM8960_ADDCTL1, reg | div);
Mark Brownf2644a22009-04-07 19:20:14 +01001266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 return 0;
1272}
1273
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001274static int wm8960_set_bias_level(struct snd_soc_component *component,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001275 enum snd_soc_bias_level level)
1276{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001277 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001278
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001279 return wm8960->set_bias_level(component, level);
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001280}
1281
Zidan Wang0e50b512015-05-12 14:58:08 +08001282static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1283 unsigned int freq, int dir)
1284{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001285 struct snd_soc_component *component = dai->component;
1286 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Zidan Wang0e50b512015-05-12 14:58:08 +08001287
1288 switch (clk_id) {
1289 case WM8960_SYSCLK_MCLK:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001290 snd_soc_component_update_bits(component, WM8960_CLOCK1,
Zidan Wang0e50b512015-05-12 14:58:08 +08001291 0x1, WM8960_SYSCLK_MCLK);
1292 break;
1293 case WM8960_SYSCLK_PLL:
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001294 snd_soc_component_update_bits(component, WM8960_CLOCK1,
Zidan Wang0e50b512015-05-12 14:58:08 +08001295 0x1, WM8960_SYSCLK_PLL);
1296 break;
Zidan Wang3176bf22015-08-11 19:25:15 +08001297 case WM8960_SYSCLK_AUTO:
1298 break;
Zidan Wang0e50b512015-05-12 14:58:08 +08001299 default:
1300 return -EINVAL;
1301 }
1302
1303 wm8960->sysclk = freq;
Zidan Wang3176bf22015-08-11 19:25:15 +08001304 wm8960->clk_id = clk_id;
Zidan Wang0e50b512015-05-12 14:58:08 +08001305
1306 return 0;
1307}
1308
Mark Brownf2644a22009-04-07 19:20:14 +01001309#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
1310
1311#define WM8960_FORMATS \
1312 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
Zidan Wang7a8c7862015-05-12 14:58:21 +08001313 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
Mark Brownf2644a22009-04-07 19:20:14 +01001314
Lars-Peter Clausen85e76522011-11-23 11:40:40 +01001315static const struct snd_soc_dai_ops wm8960_dai_ops = {
Mark Brownf2644a22009-04-07 19:20:14 +01001316 .hw_params = wm8960_hw_params,
Zidan Wang3176bf22015-08-11 19:25:15 +08001317 .hw_free = wm8960_hw_free,
Kuninori Morimoto26d3c162020-07-09 10:56:53 +09001318 .mute_stream = wm8960_mute,
Mark Brownf2644a22009-04-07 19:20:14 +01001319 .set_fmt = wm8960_set_dai_fmt,
1320 .set_clkdiv = wm8960_set_dai_clkdiv,
1321 .set_pll = wm8960_set_dai_pll,
Zidan Wang0e50b512015-05-12 14:58:08 +08001322 .set_sysclk = wm8960_set_dai_sysclk,
Kuninori Morimoto26d3c162020-07-09 10:56:53 +09001323 .no_capture_mute = 1,
Mark Brownf2644a22009-04-07 19:20:14 +01001324};
1325
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001326static struct snd_soc_dai_driver wm8960_dai = {
1327 .name = "wm8960-hifi",
Mark Brownf2644a22009-04-07 19:20:14 +01001328 .playback = {
1329 .stream_name = "Playback",
1330 .channels_min = 1,
1331 .channels_max = 2,
1332 .rates = WM8960_RATES,
1333 .formats = WM8960_FORMATS,},
1334 .capture = {
1335 .stream_name = "Capture",
1336 .channels_min = 1,
1337 .channels_max = 2,
1338 .rates = WM8960_RATES,
1339 .formats = WM8960_FORMATS,},
1340 .ops = &wm8960_dai_ops,
1341 .symmetric_rates = 1,
1342};
Mark Brownf2644a22009-04-07 19:20:14 +01001343
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001344static int wm8960_probe(struct snd_soc_component *component)
Mark Brownf2644a22009-04-07 19:20:14 +01001345{
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001346 struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
Zidan Wange2280c902014-11-20 19:07:48 +08001347 struct wm8960_data *pdata = &wm8960->pdata;
Mark Brownf2644a22009-04-07 19:20:14 +01001348
Zidan Wange2280c902014-11-20 19:07:48 +08001349 if (pdata->capless)
1350 wm8960->set_bias_level = wm8960_set_bias_level_capless;
1351 else
1352 wm8960->set_bias_level = wm8960_set_bias_level_out3;
Mark Brownf2644a22009-04-07 19:20:14 +01001353
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001354 snd_soc_add_component_controls(component, wm8960_snd_controls,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001355 ARRAY_SIZE(wm8960_snd_controls));
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001356 wm8960_add_widgets(component);
Mark Brownf2644a22009-04-07 19:20:14 +01001357
1358 return 0;
1359}
1360
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001361static const struct snd_soc_component_driver soc_component_dev_wm8960 = {
1362 .probe = wm8960_probe,
1363 .set_bias_level = wm8960_set_bias_level,
1364 .suspend_bias_off = 1,
1365 .idle_bias_on = 1,
1366 .use_pmdown_time = 1,
1367 .endianness = 1,
1368 .non_legacy_dai_naming = 1,
Mark Brown0ebe36c2012-09-10 19:23:57 +08001369};
1370
1371static const struct regmap_config wm8960_regmap = {
1372 .reg_bits = 7,
1373 .val_bits = 9,
1374 .max_register = WM8960_PLL4,
1375
1376 .reg_defaults = wm8960_reg_defaults,
1377 .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
1378 .cache_type = REGCACHE_RBTREE,
1379
1380 .volatile_reg = wm8960_volatile,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001381};
1382
Zidan Wange2280c902014-11-20 19:07:48 +08001383static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
1384 struct wm8960_data *pdata)
1385{
1386 const struct device_node *np = i2c->dev.of_node;
1387
1388 if (of_property_read_bool(np, "wlf,capless"))
1389 pdata->capless = true;
1390
1391 if (of_property_read_bool(np, "wlf,shared-lrclk"))
1392 pdata->shared_lrclk = true;
Shengjiu Wangc9015a12020-06-03 18:26:53 +08001393
1394 of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_cfg,
1395 ARRAY_SIZE(pdata->gpio_cfg));
1396
1397 of_property_read_u32_array(np, "wlf,hp-cfg", pdata->hp_cfg,
1398 ARRAY_SIZE(pdata->hp_cfg));
Zidan Wange2280c902014-11-20 19:07:48 +08001399}
1400
Bill Pemberton7a79e942012-12-07 09:26:37 -05001401static int wm8960_i2c_probe(struct i2c_client *i2c,
1402 const struct i2c_device_id *id)
Mark Brownf2644a22009-04-07 19:20:14 +01001403{
Mark Brown37061632012-09-13 11:46:58 +08001404 struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
Mark Brownf2644a22009-04-07 19:20:14 +01001405 struct wm8960_priv *wm8960;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001406 int ret;
Mark Brownf2644a22009-04-07 19:20:14 +01001407
Mark Brownb9791c02011-12-16 07:42:58 +01001408 wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
1409 GFP_KERNEL);
Mark Brownf2644a22009-04-07 19:20:14 +01001410 if (wm8960 == NULL)
1411 return -ENOMEM;
1412
Zidan Wang75aa8862015-01-07 15:31:44 +08001413 wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
1414 if (IS_ERR(wm8960->mclk)) {
1415 if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
1416 return -EPROBE_DEFER;
1417 }
1418
Sachin Kamatc5e6f5f2012-11-26 17:19:43 +05301419 wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
Mark Brown0ebe36c2012-09-10 19:23:57 +08001420 if (IS_ERR(wm8960->regmap))
1421 return PTR_ERR(wm8960->regmap);
1422
Zidan Wange2280c902014-11-20 19:07:48 +08001423 if (pdata)
1424 memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
1425 else if (i2c->dev.of_node)
1426 wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
1427
Zidan Wang3ad5e862014-11-27 16:53:08 +08001428 ret = wm8960_reset(wm8960->regmap);
1429 if (ret != 0) {
1430 dev_err(&i2c->dev, "Failed to issue reset\n");
1431 return ret;
1432 }
1433
1434 if (wm8960->pdata.shared_lrclk) {
Mark Brown37061632012-09-13 11:46:58 +08001435 ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
1436 0x4, 0x4);
1437 if (ret != 0) {
1438 dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
1439 ret);
1440 return ret;
1441 }
1442 }
1443
Zidan Wang3ad5e862014-11-27 16:53:08 +08001444 /* Latch the update bits */
1445 regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
1446 regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
1447 regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
1448 regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
1449 regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
1450 regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
1451 regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
1452 regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
1453 regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
1454 regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
1455
Shengjiu Wangc9015a12020-06-03 18:26:53 +08001456 /* ADCLRC pin configured as GPIO. */
1457 regmap_update_bits(wm8960->regmap, WM8960_IFACE2, 1 << 6,
1458 wm8960->pdata.gpio_cfg[0] << 6);
1459 regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 0xF << 4,
1460 wm8960->pdata.gpio_cfg[1] << 4);
1461
1462 /* Enable headphone jack detect */
1463 regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 3 << 2,
1464 wm8960->pdata.hp_cfg[0] << 2);
1465 regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, 3 << 5,
1466 wm8960->pdata.hp_cfg[1] << 5);
1467 regmap_update_bits(wm8960->regmap, WM8960_ADDCTL1, 3,
1468 wm8960->pdata.hp_cfg[2]);
1469
Mark Brownf2644a22009-04-07 19:20:14 +01001470 i2c_set_clientdata(i2c, wm8960);
Mark Brownf2644a22009-04-07 19:20:14 +01001471
Kuninori Morimotoe075fc12018-01-29 03:05:45 +00001472 ret = devm_snd_soc_register_component(&i2c->dev,
1473 &soc_component_dev_wm8960, &wm8960_dai, 1);
Mark Brownb9791c02011-12-16 07:42:58 +01001474
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001475 return ret;
Mark Brownf2644a22009-04-07 19:20:14 +01001476}
1477
Bill Pemberton7a79e942012-12-07 09:26:37 -05001478static int wm8960_i2c_remove(struct i2c_client *client)
Mark Brownf2644a22009-04-07 19:20:14 +01001479{
Mark Brownf2644a22009-04-07 19:20:14 +01001480 return 0;
1481}
1482
1483static const struct i2c_device_id wm8960_i2c_id[] = {
1484 { "wm8960", 0 },
1485 { }
1486};
1487MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
1488
Zidan Wange2280c902014-11-20 19:07:48 +08001489static const struct of_device_id wm8960_of_match[] = {
1490 { .compatible = "wlf,wm8960", },
1491 { }
1492};
1493MODULE_DEVICE_TABLE(of, wm8960_of_match);
1494
Mark Brownf2644a22009-04-07 19:20:14 +01001495static struct i2c_driver wm8960_i2c_driver = {
1496 .driver = {
Mark Brown091edcc2011-12-02 22:08:49 +00001497 .name = "wm8960",
Zidan Wange2280c902014-11-20 19:07:48 +08001498 .of_match_table = wm8960_of_match,
Mark Brownf2644a22009-04-07 19:20:14 +01001499 },
1500 .probe = wm8960_i2c_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -05001501 .remove = wm8960_i2c_remove,
Mark Brownf2644a22009-04-07 19:20:14 +01001502 .id_table = wm8960_i2c_id,
1503};
1504
Sachin Kamat3c010e62012-08-06 17:25:36 +05301505module_i2c_driver(wm8960_i2c_driver);
Mark Brownf2644a22009-04-07 19:20:14 +01001506
Mark Brownf2644a22009-04-07 19:20:14 +01001507MODULE_DESCRIPTION("ASoC WM8960 driver");
1508MODULE_AUTHOR("Liam Girdwood");
1509MODULE_LICENSE("GPL");