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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 5d324410d4de8dec7e9d8d9f66832ed7e0a947bc / . / arch / arm / boot / dts / tegra20.dtsi
blob: c9121337ed2c6c80f7d18bf4fa930e021b2b6116 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]38 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]65 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]66 };
67
68 dc@54200000 {
69 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]72 clocks = <&tegra_car 27>, <&tegra_car 121>;
73 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 dc@54240000 {
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]84 clocks = <&tegra_car 26>, <&tegra_car 121>;
85 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]86
87 rgb {
88 status = "disabled";
89 };
90 };
91
92 hdmi {
93 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]96 clocks = <&tegra_car 51>, <&tegra_car 117>;
97 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]98 status = "disabled";
99 };
100
101 tvo {
102 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]105 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]106 status = "disabled";
107 };
108
109 dsi {
110 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]112 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]113 status = "disabled";
114 };
115 };
116
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]117 timer@50004600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>;
Prashant Gaikwaded3ced32013-03-01 11:32:24 -0700[diff] [blame]121 clocks = <&tegra_car 132>;
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]122 };
123
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]124 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]125 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]126 reg = <0x50041000 0x1000
127 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]128 interrupt-controller;
129 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]130 };
131
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]132 cache-controller {
133 compatible = "arm,pl310-cache";
134 reg = <0x50043000 0x1000>;
135 arm,data-latency = <5 5 2>;
136 arm,tag-latency = <4 4 2>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]141 timer@60005000 {
142 compatible = "nvidia,tegra20-timer";
143 reg = <0x60005000 0x60>;
144 interrupts = <0 0 0x04
145 0 1 0x04
146 0 41 0x04
147 0 42 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]148 clocks = <&tegra_car 5>;
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]149 };
150
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]151 tegra_car: clock {
152 compatible = "nvidia,tegra20-car";
153 reg = <0x60006000 0x1000>;
154 #clock-cells = <1>;
155 };
156
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]157 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]158 compatible = "nvidia,tegra20-apbdma";
159 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]160 interrupts = <0 104 0x04
161 0 105 0x04
162 0 106 0x04
163 0 107 0x04
164 0 108 0x04
165 0 109 0x04
166 0 110 0x04
167 0 111 0x04
168 0 112 0x04
169 0 113 0x04
170 0 114 0x04
171 0 115 0x04
172 0 116 0x04
173 0 117 0x04
174 0 118 0x04
175 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]176 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]177 };
178
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]179 ahb {
180 compatible = "nvidia,tegra20-ahb";
181 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]182 };
183
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]184 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]185 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]186 reg = <0x6000d000 0x1000>;
187 interrupts = <0 32 0x04
188 0 33 0x04
189 0 34 0x04
190 0 35 0x04
191 0 55 0x04
192 0 87 0x04
193 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]194 #gpio-cells = <2>;
195 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]196 #interrupt-cells = <2>;
197 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]198 };
199
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]200 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]201 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]202 reg = <0x70000014 0x10 /* Tri-state registers */
203 0x70000080 0x20 /* Mux registers */
204 0x700000a0 0x14 /* Pull-up/down registers */
205 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]206 };
207
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]208 das {
209 compatible = "nvidia,tegra20-das";
210 reg = <0x70000c00 0x80>;
211 };
Stephen Warrenfc5c3062013-03-06 11:28:32 -0700[diff] [blame]212
Lucas Stach0698ed12013-01-05 02:18:44 +0100[diff] [blame]213 tegra_ac97: ac97 {
214 compatible = "nvidia,tegra20-ac97";
215 reg = <0x70002000 0x200>;
216 interrupts = <0 81 0x04>;
217 nvidia,dma-request-selector = <&apbdma 12>;
218 clocks = <&tegra_car 3>;
219 status = "disabled";
220 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]221
222 tegra_i2s1: i2s@70002800 {
223 compatible = "nvidia,tegra20-i2s";
224 reg = <0x70002800 0x200>;
225 interrupts = <0 13 0x04>;
226 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]227 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]228 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]229 };
230
231 tegra_i2s2: i2s@70002a00 {
232 compatible = "nvidia,tegra20-i2s";
233 reg = <0x70002a00 0x200>;
234 interrupts = <0 3 0x04>;
235 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]236 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]237 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]238 };
239
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]240 /*
241 * There are two serial driver i.e. 8250 based simple serial
242 * driver and APB DMA based serial driver for higher baudrate
243 * and performace. To enable the 8250 based driver, the compatible
244 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
245 * driver, the comptible is "nvidia,tegra20-hsuart".
246 */
247 uarta: serial@70006000 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]248 compatible = "nvidia,tegra20-uart";
249 reg = <0x70006000 0x40>;
250 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]251 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]252 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]253 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]254 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]255 };
256
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]257 uartb: serial@70006040 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]258 compatible = "nvidia,tegra20-uart";
259 reg = <0x70006040 0x40>;
260 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]261 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]262 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]263 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]264 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]265 };
266
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]267 uartc: serial@70006200 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]268 compatible = "nvidia,tegra20-uart";
269 reg = <0x70006200 0x100>;
270 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]271 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]272 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]273 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]274 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]275 };
276
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]277 uartd: serial@70006300 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]278 compatible = "nvidia,tegra20-uart";
279 reg = <0x70006300 0x100>;
280 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]281 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]282 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]283 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]284 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]285 };
286
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]287 uarte: serial@70006400 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]288 compatible = "nvidia,tegra20-uart";
289 reg = <0x70006400 0x100>;
290 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]291 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]292 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]293 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]294 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]295 };
296
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]297 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]298 compatible = "nvidia,tegra20-pwm";
299 reg = <0x7000a000 0x100>;
300 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]301 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]302 };
303
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]304 rtc {
305 compatible = "nvidia,tegra20-rtc";
306 reg = <0x7000e000 0x100>;
307 interrupts = <0 2 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]308 clocks = <&tegra_car 4>;
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]309 };
310
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]311 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]312 compatible = "nvidia,tegra20-i2c";
313 reg = <0x7000c000 0x100>;
314 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]315 #address-cells = <1>;
316 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]317 clocks = <&tegra_car 12>, <&tegra_car 124>;
318 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]319 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]320 };
321
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]322 spi@7000c380 {
323 compatible = "nvidia,tegra20-sflash";
324 reg = <0x7000c380 0x80>;
325 interrupts = <0 39 0x04>;
326 nvidia,dma-request-selector = <&apbdma 11>;
327 #address-cells = <1>;
328 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]329 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]330 status = "disabled";
331 };
332
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]333 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]334 compatible = "nvidia,tegra20-i2c";
335 reg = <0x7000c400 0x100>;
336 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]337 #address-cells = <1>;
338 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]339 clocks = <&tegra_car 54>, <&tegra_car 124>;
340 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]341 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]342 };
343
344 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]345 compatible = "nvidia,tegra20-i2c";
346 reg = <0x7000c500 0x100>;
347 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]348 #address-cells = <1>;
349 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]350 clocks = <&tegra_car 67>, <&tegra_car 124>;
351 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]352 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]353 };
354
355 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]356 compatible = "nvidia,tegra20-i2c-dvc";
357 reg = <0x7000d000 0x200>;
358 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]359 #address-cells = <1>;
360 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]361 clocks = <&tegra_car 47>, <&tegra_car 124>;
362 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]363 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]364 };
365
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]366 spi@7000d400 {
367 compatible = "nvidia,tegra20-slink";
368 reg = <0x7000d400 0x200>;
369 interrupts = <0 59 0x04>;
370 nvidia,dma-request-selector = <&apbdma 15>;
371 #address-cells = <1>;
372 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]373 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]374 status = "disabled";
375 };
376
377 spi@7000d600 {
378 compatible = "nvidia,tegra20-slink";
379 reg = <0x7000d600 0x200>;
380 interrupts = <0 82 0x04>;
381 nvidia,dma-request-selector = <&apbdma 16>;
382 #address-cells = <1>;
383 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]384 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]385 status = "disabled";
386 };
387
388 spi@7000d800 {
389 compatible = "nvidia,tegra20-slink";
390 reg = <0x7000d480 0x200>;
391 interrupts = <0 83 0x04>;
392 nvidia,dma-request-selector = <&apbdma 17>;
393 #address-cells = <1>;
394 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]395 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]396 status = "disabled";
397 };
398
399 spi@7000da00 {
400 compatible = "nvidia,tegra20-slink";
401 reg = <0x7000da00 0x200>;
402 interrupts = <0 93 0x04>;
403 nvidia,dma-request-selector = <&apbdma 18>;
404 #address-cells = <1>;
405 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]406 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]407 status = "disabled";
408 };
409
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]410 kbc {
411 compatible = "nvidia,tegra20-kbc";
412 reg = <0x7000e200 0x100>;
413 interrupts = <0 85 0x04>;
414 clocks = <&tegra_car 36>;
415 status = "disabled";
416 };
417
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]418 pmc {
419 compatible = "nvidia,tegra20-pmc";
420 reg = <0x7000e400 0x400>;
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]421 clocks = <&tegra_car 110>, <&clk32k_in>;
422 clock-names = "pclk", "clk32k_in";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]423 };
424
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]425 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]426 compatible = "nvidia,tegra20-mc";
427 reg = <0x7000f000 0x024
428 0x7000f03c 0x3c4>;
429 interrupts = <0 77 0x04>;
430 };
431
Hiroshi Doyu109269e2013-01-29 10:30:30 +0200[diff] [blame]432 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]433 compatible = "nvidia,tegra20-gart";
434 reg = <0x7000f024 0x00000018 /* controller registers */
435 0x58000000 0x02000000>; /* GART aperture */
436 };
437
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]438 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]439 compatible = "nvidia,tegra20-emc";
440 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]441 #address-cells = <1>;
442 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]443 };
444
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]445 usb@c5000000 {
446 compatible = "nvidia,tegra20-ehci", "usb-ehci";
447 reg = <0xc5000000 0x4000>;
448 interrupts = <0 20 0x04>;
449 phy_type = "utmi";
450 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]451 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame]452 nvidia,needs-double-reset;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]453 nvidia,phy = <&phy1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]454 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]455 };
456
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame^]457 phy1: usb-phy@c5000400 {
458 compatible = "nvidia,tegra20-usb-phy";
459 reg = <0xc5000400 0x3c00>;
460 phy_type = "utmi";
461 nvidia,has-legacy-mode;
462 clocks = <&tegra_car 22>, <&tegra_car 127>;
463 clock-names = "phy", "pll_u";
464 };
465
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]466 usb@c5004000 {
467 compatible = "nvidia,tegra20-ehci", "usb-ehci";
468 reg = <0xc5004000 0x4000>;
469 interrupts = <0 21 0x04>;
470 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]471 clocks = <&tegra_car 58>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]472 nvidia,phy = <&phy2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]473 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]474 };
475
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame^]476 phy2: usb-phy@c5004400 {
477 compatible = "nvidia,tegra20-usb-phy";
478 reg = <0xc5004400 0x3c00>;
479 phy_type = "ulpi";
480 clocks = <&tegra_car 94>, <&tegra_car 127>;
481 clock-names = "phy", "pll_u";
482 };
483
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]484 usb@c5008000 {
485 compatible = "nvidia,tegra20-ehci", "usb-ehci";
486 reg = <0xc5008000 0x4000>;
487 interrupts = <0 97 0x04>;
488 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]489 clocks = <&tegra_car 59>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]490 nvidia,phy = <&phy3>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]491 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]492 };
493
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame^]494 phy3: usb-phy@c5008400 {
495 compatible = "nvidia,tegra20-usb-phy";
496 reg = <0xc5008400 0x3c00>;
497 phy_type = "utmi";
498 clocks = <&tegra_car 22>, <&tegra_car 127>;
499 clock-names = "phy", "pll_u";
500 };
501
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]502 sdhci@c8000000 {
503 compatible = "nvidia,tegra20-sdhci";
504 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]505 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]506 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]507 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]508 };
509
510 sdhci@c8000200 {
511 compatible = "nvidia,tegra20-sdhci";
512 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]513 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]514 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]515 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]516 };
517
518 sdhci@c8000400 {
519 compatible = "nvidia,tegra20-sdhci";
520 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]521 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]522 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]523 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]524 };
525
526 sdhci@c8000600 {
527 compatible = "nvidia,tegra20-sdhci";
528 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]529 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]530 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]531 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]532 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]533
Hiroshi Doyu4dd2bd32013-01-11 15:26:55 +0200[diff] [blame]534 cpus {
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 cpu@0 {
539 device_type = "cpu";
540 compatible = "arm,cortex-a9";
541 reg = <0>;
542 };
543
544 cpu@1 {
545 device_type = "cpu";
546 compatible = "arm,cortex-a9";
547 reg = <1>;
548 };
549 };
550
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]551 pmu {
552 compatible = "arm,cortex-a9-pmu";
553 interrupts = <0 56 0x04
554 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]555 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]556};