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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 699ed4b94c6278ab0f629fde261af78cd1458f73 / . / arch / arm / boot / dts / tegra20.dtsi
blob: 47534d9970bdd620a6fc15d49310c6aeb68631c7 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]38 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]65 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]66 };
67
68 dc@54200000 {
69 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]72 clocks = <&tegra_car 27>, <&tegra_car 121>;
73 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 dc@54240000 {
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]84 clocks = <&tegra_car 26>, <&tegra_car 121>;
85 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]86
87 rgb {
88 status = "disabled";
89 };
90 };
91
92 hdmi {
93 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]96 clocks = <&tegra_car 51>, <&tegra_car 117>;
97 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]98 status = "disabled";
99 };
100
101 tvo {
102 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]105 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]106 status = "disabled";
107 };
108
109 dsi {
110 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]112 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]113 status = "disabled";
114 };
115 };
116
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]117 timer@50004600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>;
121 };
122
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]123 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]124 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]125 reg = <0x50041000 0x1000
126 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]127 interrupt-controller;
128 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]129 };
130
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]131 cache-controller {
132 compatible = "arm,pl310-cache";
133 reg = <0x50043000 0x1000>;
134 arm,data-latency = <5 5 2>;
135 arm,tag-latency = <4 4 2>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]140 timer@60005000 {
141 compatible = "nvidia,tegra20-timer";
142 reg = <0x60005000 0x60>;
143 interrupts = <0 0 0x04
144 0 1 0x04
145 0 41 0x04
146 0 42 0x04>;
147 };
148
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]149 tegra_car: clock {
150 compatible = "nvidia,tegra20-car";
151 reg = <0x60006000 0x1000>;
152 #clock-cells = <1>;
153 };
154
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]155 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]156 compatible = "nvidia,tegra20-apbdma";
157 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]158 interrupts = <0 104 0x04
159 0 105 0x04
160 0 106 0x04
161 0 107 0x04
162 0 108 0x04
163 0 109 0x04
164 0 110 0x04
165 0 111 0x04
166 0 112 0x04
167 0 113 0x04
168 0 114 0x04
169 0 115 0x04
170 0 116 0x04
171 0 117 0x04
172 0 118 0x04
173 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]174 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]175 };
176
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]177 ahb {
178 compatible = "nvidia,tegra20-ahb";
179 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]180 };
181
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]182 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]183 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]184 reg = <0x6000d000 0x1000>;
185 interrupts = <0 32 0x04
186 0 33 0x04
187 0 34 0x04
188 0 35 0x04
189 0 55 0x04
190 0 87 0x04
191 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]192 #gpio-cells = <2>;
193 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]194 #interrupt-cells = <2>;
195 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]196 };
197
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]198 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]199 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]200 reg = <0x70000014 0x10 /* Tri-state registers */
201 0x70000080 0x20 /* Mux registers */
202 0x700000a0 0x14 /* Pull-up/down registers */
203 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]204 };
205
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]206 das {
207 compatible = "nvidia,tegra20-das";
208 reg = <0x70000c00 0x80>;
209 };
Lucas Stach0698ed12013-01-05 02:18:44 +0100[diff] [blame]210
211 tegra_ac97: ac97 {
212 compatible = "nvidia,tegra20-ac97";
213 reg = <0x70002000 0x200>;
214 interrupts = <0 81 0x04>;
215 nvidia,dma-request-selector = <&apbdma 12>;
216 clocks = <&tegra_car 3>;
217 status = "disabled";
218 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]219
220 tegra_i2s1: i2s@70002800 {
221 compatible = "nvidia,tegra20-i2s";
222 reg = <0x70002800 0x200>;
223 interrupts = <0 13 0x04>;
224 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]225 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]226 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]227 };
228
229 tegra_i2s2: i2s@70002a00 {
230 compatible = "nvidia,tegra20-i2s";
231 reg = <0x70002a00 0x200>;
232 interrupts = <0 3 0x04>;
233 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]234 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]235 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]236 };
237
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]238 /*
239 * There are two serial driver i.e. 8250 based simple serial
240 * driver and APB DMA based serial driver for higher baudrate
241 * and performace. To enable the 8250 based driver, the compatible
242 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
243 * driver, the comptible is "nvidia,tegra20-hsuart".
244 */
245 uarta: serial@70006000 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]246 compatible = "nvidia,tegra20-uart";
247 reg = <0x70006000 0x40>;
248 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]249 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]250 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]251 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]252 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]253 };
254
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]255 uartb: serial@70006040 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]256 compatible = "nvidia,tegra20-uart";
257 reg = <0x70006040 0x40>;
258 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]259 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]260 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]261 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]262 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]263 };
264
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]265 uartc: serial@70006200 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]266 compatible = "nvidia,tegra20-uart";
267 reg = <0x70006200 0x100>;
268 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]269 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]270 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]271 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]272 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]273 };
274
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]275 uartd: serial@70006300 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]276 compatible = "nvidia,tegra20-uart";
277 reg = <0x70006300 0x100>;
278 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]279 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]280 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]281 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]282 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]283 };
284
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]285 uarte: serial@70006400 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]286 compatible = "nvidia,tegra20-uart";
287 reg = <0x70006400 0x100>;
288 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]289 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]290 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]291 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]292 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]293 };
294
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]295 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]296 compatible = "nvidia,tegra20-pwm";
297 reg = <0x7000a000 0x100>;
298 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]299 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]300 };
301
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]302 rtc {
303 compatible = "nvidia,tegra20-rtc";
304 reg = <0x7000e000 0x100>;
305 interrupts = <0 2 0x04>;
306 };
307
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]308 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]309 compatible = "nvidia,tegra20-i2c";
310 reg = <0x7000c000 0x100>;
311 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]312 #address-cells = <1>;
313 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]314 clocks = <&tegra_car 12>, <&tegra_car 124>;
315 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]316 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]317 };
318
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]319 spi@7000c380 {
320 compatible = "nvidia,tegra20-sflash";
321 reg = <0x7000c380 0x80>;
322 interrupts = <0 39 0x04>;
323 nvidia,dma-request-selector = <&apbdma 11>;
324 #address-cells = <1>;
325 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]326 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]327 status = "disabled";
328 };
329
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]330 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]331 compatible = "nvidia,tegra20-i2c";
332 reg = <0x7000c400 0x100>;
333 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]334 #address-cells = <1>;
335 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]336 clocks = <&tegra_car 54>, <&tegra_car 124>;
337 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]338 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]339 };
340
341 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]342 compatible = "nvidia,tegra20-i2c";
343 reg = <0x7000c500 0x100>;
344 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]345 #address-cells = <1>;
346 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]347 clocks = <&tegra_car 67>, <&tegra_car 124>;
348 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]349 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]350 };
351
352 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]353 compatible = "nvidia,tegra20-i2c-dvc";
354 reg = <0x7000d000 0x200>;
355 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]356 #address-cells = <1>;
357 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]358 clocks = <&tegra_car 47>, <&tegra_car 124>;
359 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]360 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]361 };
362
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]363 spi@7000d400 {
364 compatible = "nvidia,tegra20-slink";
365 reg = <0x7000d400 0x200>;
366 interrupts = <0 59 0x04>;
367 nvidia,dma-request-selector = <&apbdma 15>;
368 #address-cells = <1>;
369 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]370 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]371 status = "disabled";
372 };
373
374 spi@7000d600 {
375 compatible = "nvidia,tegra20-slink";
376 reg = <0x7000d600 0x200>;
377 interrupts = <0 82 0x04>;
378 nvidia,dma-request-selector = <&apbdma 16>;
379 #address-cells = <1>;
380 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]381 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]382 status = "disabled";
383 };
384
385 spi@7000d800 {
386 compatible = "nvidia,tegra20-slink";
387 reg = <0x7000d480 0x200>;
388 interrupts = <0 83 0x04>;
389 nvidia,dma-request-selector = <&apbdma 17>;
390 #address-cells = <1>;
391 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]392 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]393 status = "disabled";
394 };
395
396 spi@7000da00 {
397 compatible = "nvidia,tegra20-slink";
398 reg = <0x7000da00 0x200>;
399 interrupts = <0 93 0x04>;
400 nvidia,dma-request-selector = <&apbdma 18>;
401 #address-cells = <1>;
402 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]403 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]404 status = "disabled";
405 };
406
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame^]407 kbc {
408 compatible = "nvidia,tegra20-kbc";
409 reg = <0x7000e200 0x100>;
410 interrupts = <0 85 0x04>;
411 clocks = <&tegra_car 36>;
412 status = "disabled";
413 };
414
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]415 pmc {
416 compatible = "nvidia,tegra20-pmc";
417 reg = <0x7000e400 0x400>;
418 };
419
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]420 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]421 compatible = "nvidia,tegra20-mc";
422 reg = <0x7000f000 0x024
423 0x7000f03c 0x3c4>;
424 interrupts = <0 77 0x04>;
425 };
426
427 gart {
428 compatible = "nvidia,tegra20-gart";
429 reg = <0x7000f024 0x00000018 /* controller registers */
430 0x58000000 0x02000000>; /* GART aperture */
431 };
432
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]433 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]434 compatible = "nvidia,tegra20-emc";
435 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]436 #address-cells = <1>;
437 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]438 };
439
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]440 phy1: usb-phy@c5000400 {
441 compatible = "nvidia,tegra20-usb-phy";
442 reg = <0xc5000400 0x3c00>;
443 phy_type = "utmi";
444 nvidia,has-legacy-mode;
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]445 clocks = <&tegra_car 22>, <&tegra_car 127>;
446 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]447 };
448
449 phy2: usb-phy@c5004400 {
450 compatible = "nvidia,tegra20-usb-phy";
451 reg = <0xc5004400 0x3c00>;
452 phy_type = "ulpi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]453 clocks = <&tegra_car 94>, <&tegra_car 127>;
454 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]455 };
456
457 phy3: usb-phy@c5008400 {
458 compatible = "nvidia,tegra20-usb-phy";
459 reg = <0xc5008400 0x3C00>;
460 phy_type = "utmi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]461 clocks = <&tegra_car 22>, <&tegra_car 127>;
462 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]463 };
464
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]465 usb@c5000000 {
466 compatible = "nvidia,tegra20-ehci", "usb-ehci";
467 reg = <0xc5000000 0x4000>;
468 interrupts = <0 20 0x04>;
469 phy_type = "utmi";
470 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]471 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame]472 nvidia,needs-double-reset;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]473 nvidia,phy = <&phy1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]474 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]475 };
476
477 usb@c5004000 {
478 compatible = "nvidia,tegra20-ehci", "usb-ehci";
479 reg = <0xc5004000 0x4000>;
480 interrupts = <0 21 0x04>;
481 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]482 clocks = <&tegra_car 58>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]483 nvidia,phy = <&phy2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]484 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]485 };
486
487 usb@c5008000 {
488 compatible = "nvidia,tegra20-ehci", "usb-ehci";
489 reg = <0xc5008000 0x4000>;
490 interrupts = <0 97 0x04>;
491 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]492 clocks = <&tegra_car 59>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]493 nvidia,phy = <&phy3>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]494 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]495 };
496
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]497 sdhci@c8000000 {
498 compatible = "nvidia,tegra20-sdhci";
499 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]500 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]501 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]502 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]503 };
504
505 sdhci@c8000200 {
506 compatible = "nvidia,tegra20-sdhci";
507 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]508 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]509 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]510 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]511 };
512
513 sdhci@c8000400 {
514 compatible = "nvidia,tegra20-sdhci";
515 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]516 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]517 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]518 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]519 };
520
521 sdhci@c8000600 {
522 compatible = "nvidia,tegra20-sdhci";
523 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]524 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]525 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]526 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]527 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]528
Hiroshi Doyu4dd2bd32013-01-11 15:26:55 +0200[diff] [blame]529 cpus {
530 #address-cells = <1>;
531 #size-cells = <0>;
532
533 cpu@0 {
534 device_type = "cpu";
535 compatible = "arm,cortex-a9";
536 reg = <0>;
537 };
538
539 cpu@1 {
540 device_type = "cpu";
541 compatible = "arm,cortex-a9";
542 reg = <1>;
543 };
544 };
545
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]546 pmu {
547 compatible = "arm,cortex-a9-pmu";
548 interrupts = <0 56 0x04
549 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]550 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]551};