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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / b4e074788a4a461431e25906358c6e62cb8daf9d / . / arch / arm / boot / dts / tegra20.dtsi
blob: 88cf8332e3f743c83a040f0b89d7956db3811858 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]12 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]13
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 ranges = <0x54000000 0x54000000 0x04000000>;
18
19 mpe {
20 compatible = "nvidia,tegra20-mpe";
21 reg = <0x54040000 0x00040000>;
22 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]23 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]24 };
25
26 vi {
27 compatible = "nvidia,tegra20-vi";
28 reg = <0x54080000 0x00040000>;
29 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]30 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]31 };
32
33 epp {
34 compatible = "nvidia,tegra20-epp";
35 reg = <0x540c0000 0x00040000>;
36 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]37 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]38 };
39
40 isp {
41 compatible = "nvidia,tegra20-isp";
42 reg = <0x54100000 0x00040000>;
43 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]44 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]45 };
46
47 gr2d {
48 compatible = "nvidia,tegra20-gr2d";
49 reg = <0x54140000 0x00040000>;
50 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]51 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]52 };
53
54 gr3d {
55 compatible = "nvidia,tegra20-gr3d";
56 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]57 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]58 };
59
60 dc@54200000 {
61 compatible = "nvidia,tegra20-dc";
62 reg = <0x54200000 0x00040000>;
63 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]64 clocks = <&tegra_car 27>, <&tegra_car 121>;
65 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]66
67 rgb {
68 status = "disabled";
69 };
70 };
71
72 dc@54240000 {
73 compatible = "nvidia,tegra20-dc";
74 reg = <0x54240000 0x00040000>;
75 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]76 clocks = <&tegra_car 26>, <&tegra_car 121>;
77 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]78
79 rgb {
80 status = "disabled";
81 };
82 };
83
84 hdmi {
85 compatible = "nvidia,tegra20-hdmi";
86 reg = <0x54280000 0x00040000>;
87 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]88 clocks = <&tegra_car 51>, <&tegra_car 117>;
89 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]90 status = "disabled";
91 };
92
93 tvo {
94 compatible = "nvidia,tegra20-tvo";
95 reg = <0x542c0000 0x00040000>;
96 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]97 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]98 status = "disabled";
99 };
100
101 dsi {
102 compatible = "nvidia,tegra20-dsi";
103 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]104 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]105 status = "disabled";
106 };
107 };
108
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]109 timer@50004600 {
110 compatible = "arm,cortex-a9-twd-timer";
111 reg = <0x50040600 0x20>;
112 interrupts = <1 13 0x304>;
113 };
114
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]115 cache-controller@50043000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x50043000 0x1000>;
118 arm,data-latency = <5 5 2>;
119 arm,tag-latency = <4 4 2>;
120 cache-unified;
121 cache-level = <2>;
122 };
123
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]124 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]125 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]126 reg = <0x50041000 0x1000
127 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]128 interrupt-controller;
129 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]130 };
131
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]132 timer@60005000 {
133 compatible = "nvidia,tegra20-timer";
134 reg = <0x60005000 0x60>;
135 interrupts = <0 0 0x04
136 0 1 0x04
137 0 41 0x04
138 0 42 0x04>;
139 };
140
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]141 tegra_car: clock {
142 compatible = "nvidia,tegra20-car";
143 reg = <0x60006000 0x1000>;
144 #clock-cells = <1>;
145 };
146
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]147 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]148 compatible = "nvidia,tegra20-apbdma";
149 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]150 interrupts = <0 104 0x04
151 0 105 0x04
152 0 106 0x04
153 0 107 0x04
154 0 108 0x04
155 0 109 0x04
156 0 110 0x04
157 0 111 0x04
158 0 112 0x04
159 0 113 0x04
160 0 114 0x04
161 0 115 0x04
162 0 116 0x04
163 0 117 0x04
164 0 118 0x04
165 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]166 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]167 };
168
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]169 ahb {
170 compatible = "nvidia,tegra20-ahb";
171 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]172 };
173
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]174 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]175 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]176 reg = <0x6000d000 0x1000>;
177 interrupts = <0 32 0x04
178 0 33 0x04
179 0 34 0x04
180 0 35 0x04
181 0 55 0x04
182 0 87 0x04
183 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]184 #gpio-cells = <2>;
185 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]186 #interrupt-cells = <2>;
187 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]188 };
189
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]190 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]191 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]192 reg = <0x70000014 0x10 /* Tri-state registers */
193 0x70000080 0x20 /* Mux registers */
194 0x700000a0 0x14 /* Pull-up/down registers */
195 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]196 };
197
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]198 das {
199 compatible = "nvidia,tegra20-das";
200 reg = <0x70000c00 0x80>;
201 };
202
203 tegra_i2s1: i2s@70002800 {
204 compatible = "nvidia,tegra20-i2s";
205 reg = <0x70002800 0x200>;
206 interrupts = <0 13 0x04>;
207 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]208 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]209 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]210 };
211
212 tegra_i2s2: i2s@70002a00 {
213 compatible = "nvidia,tegra20-i2s";
214 reg = <0x70002a00 0x200>;
215 interrupts = <0 3 0x04>;
216 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]217 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]218 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]219 };
220
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]221 serial@70006000 {
222 compatible = "nvidia,tegra20-uart";
223 reg = <0x70006000 0x40>;
224 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]225 interrupts = <0 36 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]226 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]227 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]228 };
229
230 serial@70006040 {
231 compatible = "nvidia,tegra20-uart";
232 reg = <0x70006040 0x40>;
233 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]234 interrupts = <0 37 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]235 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]236 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]237 };
238
239 serial@70006200 {
240 compatible = "nvidia,tegra20-uart";
241 reg = <0x70006200 0x100>;
242 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]243 interrupts = <0 46 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]244 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]245 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]246 };
247
248 serial@70006300 {
249 compatible = "nvidia,tegra20-uart";
250 reg = <0x70006300 0x100>;
251 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]252 interrupts = <0 90 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]253 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]254 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]255 };
256
257 serial@70006400 {
258 compatible = "nvidia,tegra20-uart";
259 reg = <0x70006400 0x100>;
260 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]261 interrupts = <0 91 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]262 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]263 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]264 };
265
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]266 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]267 compatible = "nvidia,tegra20-pwm";
268 reg = <0x7000a000 0x100>;
269 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]270 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]271 };
272
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]273 rtc {
274 compatible = "nvidia,tegra20-rtc";
275 reg = <0x7000e000 0x100>;
276 interrupts = <0 2 0x04>;
277 };
278
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]279 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]280 compatible = "nvidia,tegra20-i2c";
281 reg = <0x7000c000 0x100>;
282 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]283 #address-cells = <1>;
284 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]285 clocks = <&tegra_car 12>, <&tegra_car 124>;
286 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]287 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]288 };
289
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]290 spi@7000c380 {
291 compatible = "nvidia,tegra20-sflash";
292 reg = <0x7000c380 0x80>;
293 interrupts = <0 39 0x04>;
294 nvidia,dma-request-selector = <&apbdma 11>;
295 #address-cells = <1>;
296 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]297 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]298 status = "disabled";
299 };
300
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]301 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]302 compatible = "nvidia,tegra20-i2c";
303 reg = <0x7000c400 0x100>;
304 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]305 #address-cells = <1>;
306 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]307 clocks = <&tegra_car 54>, <&tegra_car 124>;
308 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]309 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]310 };
311
312 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]313 compatible = "nvidia,tegra20-i2c";
314 reg = <0x7000c500 0x100>;
315 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]316 #address-cells = <1>;
317 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]318 clocks = <&tegra_car 67>, <&tegra_car 124>;
319 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]320 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]321 };
322
323 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]324 compatible = "nvidia,tegra20-i2c-dvc";
325 reg = <0x7000d000 0x200>;
326 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]327 #address-cells = <1>;
328 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]329 clocks = <&tegra_car 47>, <&tegra_car 124>;
330 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]331 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]332 };
333
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]334 spi@7000d400 {
335 compatible = "nvidia,tegra20-slink";
336 reg = <0x7000d400 0x200>;
337 interrupts = <0 59 0x04>;
338 nvidia,dma-request-selector = <&apbdma 15>;
339 #address-cells = <1>;
340 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]341 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]342 status = "disabled";
343 };
344
345 spi@7000d600 {
346 compatible = "nvidia,tegra20-slink";
347 reg = <0x7000d600 0x200>;
348 interrupts = <0 82 0x04>;
349 nvidia,dma-request-selector = <&apbdma 16>;
350 #address-cells = <1>;
351 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]352 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]353 status = "disabled";
354 };
355
356 spi@7000d800 {
357 compatible = "nvidia,tegra20-slink";
358 reg = <0x7000d480 0x200>;
359 interrupts = <0 83 0x04>;
360 nvidia,dma-request-selector = <&apbdma 17>;
361 #address-cells = <1>;
362 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]363 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]364 status = "disabled";
365 };
366
367 spi@7000da00 {
368 compatible = "nvidia,tegra20-slink";
369 reg = <0x7000da00 0x200>;
370 interrupts = <0 93 0x04>;
371 nvidia,dma-request-selector = <&apbdma 18>;
372 #address-cells = <1>;
373 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]374 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]375 status = "disabled";
376 };
377
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]378 pmc {
379 compatible = "nvidia,tegra20-pmc";
380 reg = <0x7000e400 0x400>;
381 };
382
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]383 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]384 compatible = "nvidia,tegra20-mc";
385 reg = <0x7000f000 0x024
386 0x7000f03c 0x3c4>;
387 interrupts = <0 77 0x04>;
388 };
389
390 gart {
391 compatible = "nvidia,tegra20-gart";
392 reg = <0x7000f024 0x00000018 /* controller registers */
393 0x58000000 0x02000000>; /* GART aperture */
394 };
395
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]396 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]397 compatible = "nvidia,tegra20-emc";
398 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]399 #address-cells = <1>;
400 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]401 };
402
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]403 usb@c5000000 {
404 compatible = "nvidia,tegra20-ehci", "usb-ehci";
405 reg = <0xc5000000 0x4000>;
406 interrupts = <0 20 0x04>;
407 phy_type = "utmi";
408 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]409 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame^]410 nvidia,needs-double-reset;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]411 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]412 };
413
414 usb@c5004000 {
415 compatible = "nvidia,tegra20-ehci", "usb-ehci";
416 reg = <0xc5004000 0x4000>;
417 interrupts = <0 21 0x04>;
418 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]419 clocks = <&tegra_car 58>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]420 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]421 };
422
423 usb@c5008000 {
424 compatible = "nvidia,tegra20-ehci", "usb-ehci";
425 reg = <0xc5008000 0x4000>;
426 interrupts = <0 97 0x04>;
427 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]428 clocks = <&tegra_car 59>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]429 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]430 };
431
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]432 sdhci@c8000000 {
433 compatible = "nvidia,tegra20-sdhci";
434 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]435 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]436 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]437 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]438 };
439
440 sdhci@c8000200 {
441 compatible = "nvidia,tegra20-sdhci";
442 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]443 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]444 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]445 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]446 };
447
448 sdhci@c8000400 {
449 compatible = "nvidia,tegra20-sdhci";
450 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]451 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]452 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]453 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]454 };
455
456 sdhci@c8000600 {
457 compatible = "nvidia,tegra20-sdhci";
458 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]459 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]460 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]461 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]462 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]463
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]464 pmu {
465 compatible = "arm,cortex-a9-pmu";
466 interrupts = <0 56 0x04
467 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]468 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]469};