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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 5af9f1433824304f5945ee48b78b9e6c447badc0 / . / arch / arm / boot / dts / imx53.dtsi
blob: fa974e4068a82acac8eb4adb2f3831833d48de28 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]78 };
79
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]80 aips@50000000 { /* AIPS1 */
81 compatible = "fsl,aips-bus", "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 reg = <0x50000000 0x10000000>;
85 ranges;
86
87 spba@50000000 {
88 compatible = "fsl,spba-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x50000000 0x40000>;
92 ranges;
93
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]94 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]95 compatible = "fsl,imx53-esdhc";
96 reg = <0x50004000 0x4000>;
97 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]98 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
99 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]100 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]101 status = "disabled";
102 };
103
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]104 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]105 compatible = "fsl,imx53-esdhc";
106 reg = <0x50008000 0x4000>;
107 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]108 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
109 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]110 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]111 status = "disabled";
112 };
113
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]114 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]115 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
116 reg = <0x5000c000 0x4000>;
117 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]118 clocks = <&clks 32>, <&clks 33>;
119 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]120 status = "disabled";
121 };
122
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]123 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
127 reg = <0x50010000 0x4000>;
128 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]129 clocks = <&clks 51>, <&clks 52>;
130 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]131 status = "disabled";
132 };
133
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]134 ssi2: ssi@50014000 {
135 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
136 reg = <0x50014000 0x4000>;
137 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]138 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]139 fsl,fifo-depth = <15>;
140 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
141 status = "disabled";
142 };
143
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]144 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]145 compatible = "fsl,imx53-esdhc";
146 reg = <0x50020000 0x4000>;
147 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]148 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
149 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]150 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]151 status = "disabled";
152 };
153
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]154 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]155 compatible = "fsl,imx53-esdhc";
156 reg = <0x50024000 0x4000>;
157 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]158 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
159 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]160 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]161 status = "disabled";
162 };
163 };
164
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]165 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]166 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
167 reg = <0x53f80000 0x0200>;
168 interrupts = <18>;
169 status = "disabled";
170 };
171
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]172 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]173 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
174 reg = <0x53f80200 0x0200>;
175 interrupts = <14>;
176 status = "disabled";
177 };
178
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]179 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]180 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
181 reg = <0x53f80400 0x0200>;
182 interrupts = <16>;
183 status = "disabled";
184 };
185
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]186 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]187 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
188 reg = <0x53f80600 0x0200>;
189 interrupts = <17>;
190 status = "disabled";
191 };
192
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]193 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]194 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]195 reg = <0x53f84000 0x4000>;
196 interrupts = <50 51>;
197 gpio-controller;
198 #gpio-cells = <2>;
199 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]200 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]201 };
202
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]203 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]204 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]205 reg = <0x53f88000 0x4000>;
206 interrupts = <52 53>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]210 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]211 };
212
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]213 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]214 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]215 reg = <0x53f8c000 0x4000>;
216 interrupts = <54 55>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]220 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]221 };
222
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]223 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]224 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]225 reg = <0x53f90000 0x4000>;
226 interrupts = <56 57>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]230 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]231 };
232
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]233 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
235 reg = <0x53f98000 0x4000>;
236 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]237 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]238 };
239
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]240 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]241 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
242 reg = <0x53f9c000 0x4000>;
243 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]244 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]245 status = "disabled";
246 };
247
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]248 gpt: timer@53fa0000 {
249 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
250 reg = <0x53fa0000 0x4000>;
251 interrupts = <39>;
252 clocks = <&clks 36>, <&clks 41>;
253 clock-names = "ipg", "per";
254 };
255
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]256 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]257 compatible = "fsl,imx53-iomuxc";
258 reg = <0x53fa8000 0x4000>;
259
260 audmux {
261 pinctrl_audmux_1: audmuxgrp-1 {
262 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]263 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
264 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
265 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
266 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]267 >;
268 };
269 };
270
271 fec {
272 pinctrl_fec_1: fecgrp-1 {
273 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]274 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
275 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
276 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
277 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
278 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
279 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
280 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
281 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
282 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
283 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]284 >;
285 };
286 };
287
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]288 csi {
289 pinctrl_csi_1: csigrp-1 {
290 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]291 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
292 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
293 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
294 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
295 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
296 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
297 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
298 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
299 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
300 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
301 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
302 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
303 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
304 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
305 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
306 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
307 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
308 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
309 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
310 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
311 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]312 >;
313 };
314 };
315
316 cspi {
317 pinctrl_cspi_1: cspigrp-1 {
318 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]319 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
320 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
321 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]322 >;
323 };
324 };
325
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]326 ecspi1 {
327 pinctrl_ecspi1_1: ecspi1grp-1 {
328 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]329 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
330 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
331 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]332 >;
333 };
334 };
335
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]336 esdhc1 {
337 pinctrl_esdhc1_1: esdhc1grp-1 {
338 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]339 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
340 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
341 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
342 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
343 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
344 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]345 >;
346 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]347
348 pinctrl_esdhc1_2: esdhc1grp-2 {
349 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]350 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
351 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
352 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
353 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
354 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
355 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
356 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
357 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
358 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
359 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]360 >;
361 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]362 };
363
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]364 esdhc2 {
365 pinctrl_esdhc2_1: esdhc2grp-1 {
366 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]367 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
368 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
369 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
370 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
371 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
372 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]373 >;
374 };
375 };
376
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]377 esdhc3 {
378 pinctrl_esdhc3_1: esdhc3grp-1 {
379 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]380 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
381 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
382 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
383 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
384 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
385 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
386 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
387 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
388 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
389 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]390 >;
391 };
392 };
393
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]394 can1 {
395 pinctrl_can1_1: can1grp-1 {
396 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]397 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
398 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]399 >;
400 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]401
402 pinctrl_can1_2: can1grp-2 {
403 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]404 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
405 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]406 >;
407 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]408 };
409
410 can2 {
411 pinctrl_can2_1: can2grp-1 {
412 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]413 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
414 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]415 >;
416 };
417 };
418
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]419 i2c1 {
420 pinctrl_i2c1_1: i2c1grp-1 {
421 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]422 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
423 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]424 >;
425 };
426 };
427
428 i2c2 {
429 pinctrl_i2c2_1: i2c2grp-1 {
430 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]431 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
432 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]433 >;
434 };
435 };
436
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]437 i2c3 {
438 pinctrl_i2c3_1: i2c3grp-1 {
439 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]440 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
441 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]442 >;
443 };
444 };
445
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]446 owire {
447 pinctrl_owire_1: owiregrp-1 {
448 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]449 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]450 >;
451 };
452 };
453
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]454 uart1 {
455 pinctrl_uart1_1: uart1grp-1 {
456 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]457 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
458 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]459 >;
460 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]461
462 pinctrl_uart1_2: uart1grp-2 {
463 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]464 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
465 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]466 >;
467 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]468 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]469
470 uart2 {
471 pinctrl_uart2_1: uart2grp-1 {
472 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]473 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
474 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]475 >;
476 };
477 };
478
479 uart3 {
480 pinctrl_uart3_1: uart3grp-1 {
481 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]482 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
483 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
484 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
485 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]486 >;
487 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]488
489 pinctrl_uart3_2: uart3grp-2 {
490 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]491 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
492 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]493 >;
494 };
495
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]496 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]497
498 uart4 {
499 pinctrl_uart4_1: uart4grp-1 {
500 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]501 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
502 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]503 >;
504 };
505 };
506
507 uart5 {
508 pinctrl_uart5_1: uart5grp-1 {
509 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]510 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
511 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]512 >;
513 };
514 };
515
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]516 };
517
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame^]518 gpr: iomuxc-gpr@53fa8000 {
519 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
520 reg = <0x53fa8000 0xc>;
521 };
522
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]523 pwm1: pwm@53fb4000 {
524 #pwm-cells = <2>;
525 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
526 reg = <0x53fb4000 0x4000>;
527 clocks = <&clks 37>, <&clks 38>;
528 clock-names = "ipg", "per";
529 interrupts = <61>;
530 };
531
532 pwm2: pwm@53fb8000 {
533 #pwm-cells = <2>;
534 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
535 reg = <0x53fb8000 0x4000>;
536 clocks = <&clks 39>, <&clks 40>;
537 clock-names = "ipg", "per";
538 interrupts = <94>;
539 };
540
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]541 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]542 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
543 reg = <0x53fbc000 0x4000>;
544 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]545 clocks = <&clks 28>, <&clks 29>;
546 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]547 status = "disabled";
548 };
549
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]550 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]551 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
552 reg = <0x53fc0000 0x4000>;
553 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]554 clocks = <&clks 30>, <&clks 31>;
555 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]556 status = "disabled";
557 };
558
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]559 can1: can@53fc8000 {
560 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
561 reg = <0x53fc8000 0x4000>;
562 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]563 clocks = <&clks 158>, <&clks 157>;
564 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]565 status = "disabled";
566 };
567
568 can2: can@53fcc000 {
569 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
570 reg = <0x53fcc000 0x4000>;
571 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]572 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]573 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]574 status = "disabled";
575 };
576
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]577 clks: ccm@53fd4000{
578 compatible = "fsl,imx53-ccm";
579 reg = <0x53fd4000 0x4000>;
580 interrupts = <0 71 0x04 0 72 0x04>;
581 #clock-cells = <1>;
582 };
583
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]584 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]585 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]586 reg = <0x53fdc000 0x4000>;
587 interrupts = <103 104>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]591 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]592 };
593
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]594 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]595 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]596 reg = <0x53fe0000 0x4000>;
597 interrupts = <105 106>;
598 gpio-controller;
599 #gpio-cells = <2>;
600 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]601 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]602 };
603
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]604 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]605 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]606 reg = <0x53fe4000 0x4000>;
607 interrupts = <107 108>;
608 gpio-controller;
609 #gpio-cells = <2>;
610 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]611 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]612 };
613
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]614 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]615 #address-cells = <1>;
616 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]617 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]618 reg = <0x53fec000 0x4000>;
619 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]620 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]621 status = "disabled";
622 };
623
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]624 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]625 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
626 reg = <0x53ff0000 0x4000>;
627 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]628 clocks = <&clks 65>, <&clks 66>;
629 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]630 status = "disabled";
631 };
632 };
633
634 aips@60000000 { /* AIPS2 */
635 compatible = "fsl,aips-bus", "simple-bus";
636 #address-cells = <1>;
637 #size-cells = <1>;
638 reg = <0x60000000 0x10000000>;
639 ranges;
640
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]641 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]642 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
643 reg = <0x63f90000 0x4000>;
644 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]645 clocks = <&clks 67>, <&clks 68>;
646 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]647 status = "disabled";
648 };
649
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]650 owire: owire@63fa4000 {
651 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
652 reg = <0x63fa4000 0x4000>;
653 clocks = <&clks 159>;
654 status = "disabled";
655 };
656
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]657 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
661 reg = <0x63fac000 0x4000>;
662 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]663 clocks = <&clks 53>, <&clks 54>;
664 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]665 status = "disabled";
666 };
667
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]668 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]669 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
670 reg = <0x63fb0000 0x4000>;
671 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]672 clocks = <&clks 56>, <&clks 56>;
673 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]674 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]675 };
676
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]677 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]678 #address-cells = <1>;
679 #size-cells = <0>;
680 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
681 reg = <0x63fc0000 0x4000>;
682 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]683 clocks = <&clks 55>, <&clks 0>;
684 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]685 status = "disabled";
686 };
687
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]688 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]689 #address-cells = <1>;
690 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]691 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]692 reg = <0x63fc4000 0x4000>;
693 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]694 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]695 status = "disabled";
696 };
697
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]698 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]699 #address-cells = <1>;
700 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]701 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]702 reg = <0x63fc8000 0x4000>;
703 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]704 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]705 status = "disabled";
706 };
707
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]708 ssi1: ssi@63fcc000 {
709 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
710 reg = <0x63fcc000 0x4000>;
711 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]712 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]713 fsl,fifo-depth = <15>;
714 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
715 status = "disabled";
716 };
717
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]718 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]719 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
720 reg = <0x63fd0000 0x4000>;
721 status = "disabled";
722 };
723
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]724 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]725 compatible = "fsl,imx53-nand";
726 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
727 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]728 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]729 status = "disabled";
730 };
731
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]732 ssi3: ssi@63fe8000 {
733 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
734 reg = <0x63fe8000 0x4000>;
735 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]736 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]737 fsl,fifo-depth = <15>;
738 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
739 status = "disabled";
740 };
741
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]742 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]743 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
744 reg = <0x63fec000 0x4000>;
745 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]746 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
747 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]748 status = "disabled";
749 };
750 };
751 };
752};