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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 9ae90afaeba3469eccce140fb0a1d5fa5c816ddc / . / arch / arm / boot / dts / imx53.dtsi
blob: da9a047ce4cf29049a8ada0d262b8b685e731b3e [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]29 };
30
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ckil {
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 ckih1 {
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
50 };
51
52 ckih2 {
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
68 ranges;
69
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]70 ipu: ipu@18000000 {
71 #crtc-cells = <1>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>;
75 };
76
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x50000000 0x10000000>;
82 ranges;
83
84 spba@50000000 {
85 compatible = "fsl,spba-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x40000>;
89 ranges;
90
91 esdhc@50004000 { /* ESDHC1 */
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
94 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]97 status = "disabled";
98 };
99
100 esdhc@50008000 { /* ESDHC2 */
101 compatible = "fsl,imx53-esdhc";
102 reg = <0x50008000 0x4000>;
103 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]104 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
105 clock-names = "ipg", "ahb", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]106 status = "disabled";
107 };
108
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]109 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]110 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
111 reg = <0x5000c000 0x4000>;
112 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]113 clocks = <&clks 32>, <&clks 33>;
114 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]115 status = "disabled";
116 };
117
118 ecspi@50010000 { /* ECSPI1 */
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
122 reg = <0x50010000 0x4000>;
123 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]124 clocks = <&clks 51>, <&clks 52>;
125 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]126 status = "disabled";
127 };
128
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]129 ssi2: ssi@50014000 {
130 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
131 reg = <0x50014000 0x4000>;
132 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]133 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]134 fsl,fifo-depth = <15>;
135 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
136 status = "disabled";
137 };
138
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]139 esdhc@50020000 { /* ESDHC3 */
140 compatible = "fsl,imx53-esdhc";
141 reg = <0x50020000 0x4000>;
142 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]143 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
144 clock-names = "ipg", "ahb", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]145 status = "disabled";
146 };
147
148 esdhc@50024000 { /* ESDHC4 */
149 compatible = "fsl,imx53-esdhc";
150 reg = <0x50024000 0x4000>;
151 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]152 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
153 clock-names = "ipg", "ahb", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]154 status = "disabled";
155 };
156 };
157
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]158 usb@53f80000 {
159 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
160 reg = <0x53f80000 0x0200>;
161 interrupts = <18>;
162 status = "disabled";
163 };
164
165 usb@53f80200 {
166 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
167 reg = <0x53f80200 0x0200>;
168 interrupts = <14>;
169 status = "disabled";
170 };
171
172 usb@53f80400 {
173 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
174 reg = <0x53f80400 0x0200>;
175 interrupts = <16>;
176 status = "disabled";
177 };
178
179 usb@53f80600 {
180 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
181 reg = <0x53f80600 0x0200>;
182 interrupts = <17>;
183 status = "disabled";
184 };
185
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]186 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]188 reg = <0x53f84000 0x4000>;
189 interrupts = <50 51>;
190 gpio-controller;
191 #gpio-cells = <2>;
192 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]193 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]194 };
195
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]196 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]198 reg = <0x53f88000 0x4000>;
199 interrupts = <52 53>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]203 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]204 };
205
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]206 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]208 reg = <0x53f8c000 0x4000>;
209 interrupts = <54 55>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]213 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]214 };
215
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]216 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]217 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]218 reg = <0x53f90000 0x4000>;
219 interrupts = <56 57>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]223 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]224 };
225
226 wdog@53f98000 { /* WDOG1 */
227 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
228 reg = <0x53f98000 0x4000>;
229 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]230 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]231 };
232
233 wdog@53f9c000 { /* WDOG2 */
234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
235 reg = <0x53f9c000 0x4000>;
236 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]237 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]238 status = "disabled";
239 };
240
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]241 iomuxc@53fa8000 {
242 compatible = "fsl,imx53-iomuxc";
243 reg = <0x53fa8000 0x4000>;
244
245 audmux {
246 pinctrl_audmux_1: audmuxgrp-1 {
247 fsl,pins = <
248 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
249 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
250 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
251 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
252 >;
253 };
254 };
255
256 fec {
257 pinctrl_fec_1: fecgrp-1 {
258 fsl,pins = <
259 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
260 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
261 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
262 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
263 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
264 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
265 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
266 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
267 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
268 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
269 >;
270 };
271 };
272
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]273 ecspi1 {
274 pinctrl_ecspi1_1: ecspi1grp-1 {
275 fsl,pins = <
276 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
277 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
278 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
279 >;
280 };
281 };
282
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]283 esdhc1 {
284 pinctrl_esdhc1_1: esdhc1grp-1 {
285 fsl,pins = <
286 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
287 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
288 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
289 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
290 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
291 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
292 >;
293 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]294
295 pinctrl_esdhc1_2: esdhc1grp-2 {
296 fsl,pins = <
297 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
298 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
299 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
300 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
301 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
302 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
303 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
304 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
305 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
306 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
307 >;
308 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]309 };
310
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]311 esdhc2 {
312 pinctrl_esdhc2_1: esdhc2grp-1 {
313 fsl,pins = <
314 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
315 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
316 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
317 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
318 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
319 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
320 >;
321 };
322 };
323
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]324 esdhc3 {
325 pinctrl_esdhc3_1: esdhc3grp-1 {
326 fsl,pins = <
327 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
328 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
329 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
330 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
331 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
332 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
333 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
334 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
335 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
336 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
337 >;
338 };
339 };
340
341 i2c1 {
342 pinctrl_i2c1_1: i2c1grp-1 {
343 fsl,pins = <
344 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
345 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
346 >;
347 };
348 };
349
350 i2c2 {
351 pinctrl_i2c2_1: i2c2grp-1 {
352 fsl,pins = <
353 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
354 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
355 >;
356 };
357 };
358
359 uart1 {
360 pinctrl_uart1_1: uart1grp-1 {
361 fsl,pins = <
362 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
363 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
364 >;
365 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]366
367 pinctrl_uart1_2: uart1grp-2 {
368 fsl,pins = <
369 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
370 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
371 >;
372 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]373 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]374
375 uart2 {
376 pinctrl_uart2_1: uart2grp-1 {
377 fsl,pins = <
378 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
379 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
380 >;
381 };
382 };
383
384 uart3 {
385 pinctrl_uart3_1: uart3grp-1 {
386 fsl,pins = <
387 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
388 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
389 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
390 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
391 >;
392 };
393 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]394 };
395
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame^]396 pwm1: pwm@53fb4000 {
397 #pwm-cells = <2>;
398 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
399 reg = <0x53fb4000 0x4000>;
400 clocks = <&clks 37>, <&clks 38>;
401 clock-names = "ipg", "per";
402 interrupts = <61>;
403 };
404
405 pwm2: pwm@53fb8000 {
406 #pwm-cells = <2>;
407 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
408 reg = <0x53fb8000 0x4000>;
409 clocks = <&clks 39>, <&clks 40>;
410 clock-names = "ipg", "per";
411 interrupts = <94>;
412 };
413
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]414 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]415 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
416 reg = <0x53fbc000 0x4000>;
417 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]418 clocks = <&clks 28>, <&clks 29>;
419 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]420 status = "disabled";
421 };
422
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]423 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]424 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
425 reg = <0x53fc0000 0x4000>;
426 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]427 clocks = <&clks 30>, <&clks 31>;
428 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]429 status = "disabled";
430 };
431
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]432 can1: can@53fc8000 {
433 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
434 reg = <0x53fc8000 0x4000>;
435 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]436 clocks = <&clks 158>, <&clks 157>;
437 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]438 status = "disabled";
439 };
440
441 can2: can@53fcc000 {
442 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
443 reg = <0x53fcc000 0x4000>;
444 interrupts = <83>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]445 clocks = <&clks 158>, <&clks 157>;
446 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]447 status = "disabled";
448 };
449
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]450 clks: ccm@53fd4000{
451 compatible = "fsl,imx53-ccm";
452 reg = <0x53fd4000 0x4000>;
453 interrupts = <0 71 0x04 0 72 0x04>;
454 #clock-cells = <1>;
455 };
456
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]457 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]458 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]459 reg = <0x53fdc000 0x4000>;
460 interrupts = <103 104>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]464 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]465 };
466
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]467 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]468 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]469 reg = <0x53fe0000 0x4000>;
470 interrupts = <105 106>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]474 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]475 };
476
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]477 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]478 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]479 reg = <0x53fe4000 0x4000>;
480 interrupts = <107 108>;
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]484 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]485 };
486
487 i2c@53fec000 { /* I2C3 */
488 #address-cells = <1>;
489 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]490 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]491 reg = <0x53fec000 0x4000>;
492 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]493 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]494 status = "disabled";
495 };
496
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]497 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]498 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
499 reg = <0x53ff0000 0x4000>;
500 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]501 clocks = <&clks 65>, <&clks 66>;
502 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]503 status = "disabled";
504 };
505 };
506
507 aips@60000000 { /* AIPS2 */
508 compatible = "fsl,aips-bus", "simple-bus";
509 #address-cells = <1>;
510 #size-cells = <1>;
511 reg = <0x60000000 0x10000000>;
512 ranges;
513
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]514 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]515 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
516 reg = <0x63f90000 0x4000>;
517 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]518 clocks = <&clks 67>, <&clks 68>;
519 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]520 status = "disabled";
521 };
522
523 ecspi@63fac000 { /* ECSPI2 */
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
527 reg = <0x63fac000 0x4000>;
528 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]529 clocks = <&clks 53>, <&clks 54>;
530 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]531 status = "disabled";
532 };
533
534 sdma@63fb0000 {
535 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
536 reg = <0x63fb0000 0x4000>;
537 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]538 clocks = <&clks 56>, <&clks 56>;
539 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]541 };
542
543 cspi@63fc0000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
547 reg = <0x63fc0000 0x4000>;
548 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]549 clocks = <&clks 55>, <&clks 0>;
550 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]551 status = "disabled";
552 };
553
554 i2c@63fc4000 { /* I2C2 */
555 #address-cells = <1>;
556 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]557 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]558 reg = <0x63fc4000 0x4000>;
559 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]560 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]561 status = "disabled";
562 };
563
564 i2c@63fc8000 { /* I2C1 */
565 #address-cells = <1>;
566 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]567 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]568 reg = <0x63fc8000 0x4000>;
569 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]570 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]571 status = "disabled";
572 };
573
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]574 ssi1: ssi@63fcc000 {
575 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
576 reg = <0x63fcc000 0x4000>;
577 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]578 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]579 fsl,fifo-depth = <15>;
580 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
581 status = "disabled";
582 };
583
584 audmux@63fd0000 {
585 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
586 reg = <0x63fd0000 0x4000>;
587 status = "disabled";
588 };
589
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]590 nand@63fdb000 {
591 compatible = "fsl,imx53-nand";
592 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
593 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]594 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]595 status = "disabled";
596 };
597
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]598 ssi3: ssi@63fe8000 {
599 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
600 reg = <0x63fe8000 0x4000>;
601 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]602 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]603 fsl,fifo-depth = <15>;
604 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
605 status = "disabled";
606 };
607
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]608 ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]609 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
610 reg = <0x63fec000 0x4000>;
611 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]612 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
613 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]614 status = "disabled";
615 };
616 };
617 };
618};