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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / e16415313c9b00b1adc313e85c2c8a81febe0b98 / . / arch / arm / boot / dts / imx53.dtsi
blob: 98149ac5c841519ca5dc6e47c1f2565e5af6876d [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
76 };
77
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]78 aips@50000000 { /* AIPS1 */
79 compatible = "fsl,aips-bus", "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x50000000 0x10000000>;
83 ranges;
84
85 spba@50000000 {
86 compatible = "fsl,spba-bus", "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x50000000 0x40000>;
90 ranges;
91
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]92 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]93 compatible = "fsl,imx53-esdhc";
94 reg = <0x50004000 0x4000>;
95 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]96 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
97 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]98 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]99 status = "disabled";
100 };
101
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]102 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]103 compatible = "fsl,imx53-esdhc";
104 reg = <0x50008000 0x4000>;
105 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]106 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
107 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]108 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]109 status = "disabled";
110 };
111
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]112 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]113 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
114 reg = <0x5000c000 0x4000>;
115 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]116 clocks = <&clks 32>, <&clks 33>;
117 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]118 status = "disabled";
119 };
120
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]121 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]122 #address-cells = <1>;
123 #size-cells = <0>;
124 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
125 reg = <0x50010000 0x4000>;
126 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]127 clocks = <&clks 51>, <&clks 52>;
128 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]129 status = "disabled";
130 };
131
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]132 ssi2: ssi@50014000 {
133 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
134 reg = <0x50014000 0x4000>;
135 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]136 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]137 fsl,fifo-depth = <15>;
138 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
139 status = "disabled";
140 };
141
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]142 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]143 compatible = "fsl,imx53-esdhc";
144 reg = <0x50020000 0x4000>;
145 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]146 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
147 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]148 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]149 status = "disabled";
150 };
151
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]152 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]153 compatible = "fsl,imx53-esdhc";
154 reg = <0x50024000 0x4000>;
155 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]156 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
157 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]158 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]159 status = "disabled";
160 };
161 };
162
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]163 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]164 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
165 reg = <0x53f80000 0x0200>;
166 interrupts = <18>;
167 status = "disabled";
168 };
169
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]170 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]171 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
172 reg = <0x53f80200 0x0200>;
173 interrupts = <14>;
174 status = "disabled";
175 };
176
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]177 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]178 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
179 reg = <0x53f80400 0x0200>;
180 interrupts = <16>;
181 status = "disabled";
182 };
183
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]184 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]185 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
186 reg = <0x53f80600 0x0200>;
187 interrupts = <17>;
188 status = "disabled";
189 };
190
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]191 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]192 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]193 reg = <0x53f84000 0x4000>;
194 interrupts = <50 51>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]198 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]199 };
200
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]201 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]202 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]203 reg = <0x53f88000 0x4000>;
204 interrupts = <52 53>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]208 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]209 };
210
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]211 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]212 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]213 reg = <0x53f8c000 0x4000>;
214 interrupts = <54 55>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]218 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]219 };
220
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]221 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]222 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]223 reg = <0x53f90000 0x4000>;
224 interrupts = <56 57>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]228 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]229 };
230
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]231 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]232 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
233 reg = <0x53f98000 0x4000>;
234 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]235 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]236 };
237
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]238 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]239 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
240 reg = <0x53f9c000 0x4000>;
241 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]242 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]243 status = "disabled";
244 };
245
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]246 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]247 compatible = "fsl,imx53-iomuxc";
248 reg = <0x53fa8000 0x4000>;
249
250 audmux {
251 pinctrl_audmux_1: audmuxgrp-1 {
252 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]253 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
254 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
255 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
256 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]257 >;
258 };
259 };
260
261 fec {
262 pinctrl_fec_1: fecgrp-1 {
263 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]264 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
265 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
266 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
267 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
268 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
269 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
270 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
271 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
272 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
273 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]274 >;
275 };
276 };
277
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]278 csi {
279 pinctrl_csi_1: csigrp-1 {
280 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]281 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
282 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
283 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
284 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
285 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
286 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
287 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
288 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
289 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
290 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
291 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
292 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
293 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
294 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
295 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
296 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
297 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
298 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
299 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
300 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
301 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]302 >;
303 };
304 };
305
306 cspi {
307 pinctrl_cspi_1: cspigrp-1 {
308 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]309 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
310 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
311 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]312 >;
313 };
314 };
315
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]316 ecspi1 {
317 pinctrl_ecspi1_1: ecspi1grp-1 {
318 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]319 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
320 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
321 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]322 >;
323 };
324 };
325
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]326 esdhc1 {
327 pinctrl_esdhc1_1: esdhc1grp-1 {
328 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]329 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
330 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
331 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
332 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
333 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
334 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]335 >;
336 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]337
338 pinctrl_esdhc1_2: esdhc1grp-2 {
339 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]340 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
341 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
342 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
343 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
344 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
345 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
346 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
347 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
348 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
349 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]350 >;
351 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]352 };
353
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]354 esdhc2 {
355 pinctrl_esdhc2_1: esdhc2grp-1 {
356 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]357 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
358 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
359 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
360 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
361 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
362 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]363 >;
364 };
365 };
366
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]367 esdhc3 {
368 pinctrl_esdhc3_1: esdhc3grp-1 {
369 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]370 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
371 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
372 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
373 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
374 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
375 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
376 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
377 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
378 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
379 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]380 >;
381 };
382 };
383
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]384 can1 {
385 pinctrl_can1_1: can1grp-1 {
386 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]387 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
388 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]389 >;
390 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]391
392 pinctrl_can1_2: can1grp-2 {
393 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]394 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
395 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]396 >;
397 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]398 };
399
400 can2 {
401 pinctrl_can2_1: can2grp-1 {
402 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]403 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
404 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]405 >;
406 };
407 };
408
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]409 i2c1 {
410 pinctrl_i2c1_1: i2c1grp-1 {
411 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]412 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
413 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]414 >;
415 };
416 };
417
418 i2c2 {
419 pinctrl_i2c2_1: i2c2grp-1 {
420 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]421 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
422 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]423 >;
424 };
425 };
426
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]427 i2c3 {
428 pinctrl_i2c3_1: i2c3grp-1 {
429 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]430 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
431 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]432 >;
433 };
434 };
435
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]436 owire {
437 pinctrl_owire_1: owiregrp-1 {
438 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]439 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]440 >;
441 };
442 };
443
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]444 uart1 {
445 pinctrl_uart1_1: uart1grp-1 {
446 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]447 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
448 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]449 >;
450 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]451
452 pinctrl_uart1_2: uart1grp-2 {
453 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]454 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
455 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]456 >;
457 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]458 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]459
460 uart2 {
461 pinctrl_uart2_1: uart2grp-1 {
462 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]463 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
464 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]465 >;
466 };
467 };
468
469 uart3 {
470 pinctrl_uart3_1: uart3grp-1 {
471 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]472 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
473 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
474 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
475 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]476 >;
477 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]478
479 pinctrl_uart3_2: uart3grp-2 {
480 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]481 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
482 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]483 >;
484 };
485
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]486 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]487
488 uart4 {
489 pinctrl_uart4_1: uart4grp-1 {
490 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]491 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
492 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]493 >;
494 };
495 };
496
497 uart5 {
498 pinctrl_uart5_1: uart5grp-1 {
499 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]500 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
501 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]502 >;
503 };
504 };
505
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]506 };
507
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]508 pwm1: pwm@53fb4000 {
509 #pwm-cells = <2>;
510 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
511 reg = <0x53fb4000 0x4000>;
512 clocks = <&clks 37>, <&clks 38>;
513 clock-names = "ipg", "per";
514 interrupts = <61>;
515 };
516
517 pwm2: pwm@53fb8000 {
518 #pwm-cells = <2>;
519 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
520 reg = <0x53fb8000 0x4000>;
521 clocks = <&clks 39>, <&clks 40>;
522 clock-names = "ipg", "per";
523 interrupts = <94>;
524 };
525
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]526 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]527 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
528 reg = <0x53fbc000 0x4000>;
529 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]530 clocks = <&clks 28>, <&clks 29>;
531 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]532 status = "disabled";
533 };
534
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]535 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]536 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
537 reg = <0x53fc0000 0x4000>;
538 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]539 clocks = <&clks 30>, <&clks 31>;
540 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]541 status = "disabled";
542 };
543
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]544 can1: can@53fc8000 {
545 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
546 reg = <0x53fc8000 0x4000>;
547 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]548 clocks = <&clks 158>, <&clks 157>;
549 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]550 status = "disabled";
551 };
552
553 can2: can@53fcc000 {
554 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
555 reg = <0x53fcc000 0x4000>;
556 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]557 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]558 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]559 status = "disabled";
560 };
561
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]562 clks: ccm@53fd4000{
563 compatible = "fsl,imx53-ccm";
564 reg = <0x53fd4000 0x4000>;
565 interrupts = <0 71 0x04 0 72 0x04>;
566 #clock-cells = <1>;
567 };
568
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]569 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]570 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]571 reg = <0x53fdc000 0x4000>;
572 interrupts = <103 104>;
573 gpio-controller;
574 #gpio-cells = <2>;
575 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]576 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]577 };
578
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]579 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]580 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]581 reg = <0x53fe0000 0x4000>;
582 interrupts = <105 106>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]586 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]587 };
588
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]589 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]590 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]591 reg = <0x53fe4000 0x4000>;
592 interrupts = <107 108>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]596 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]597 };
598
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]599 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]600 #address-cells = <1>;
601 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]602 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]603 reg = <0x53fec000 0x4000>;
604 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]605 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]606 status = "disabled";
607 };
608
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]609 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]610 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
611 reg = <0x53ff0000 0x4000>;
612 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]613 clocks = <&clks 65>, <&clks 66>;
614 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]615 status = "disabled";
616 };
617 };
618
619 aips@60000000 { /* AIPS2 */
620 compatible = "fsl,aips-bus", "simple-bus";
621 #address-cells = <1>;
622 #size-cells = <1>;
623 reg = <0x60000000 0x10000000>;
624 ranges;
625
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]626 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]627 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
628 reg = <0x63f90000 0x4000>;
629 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]630 clocks = <&clks 67>, <&clks 68>;
631 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]632 status = "disabled";
633 };
634
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]635 owire: owire@63fa4000 {
636 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
637 reg = <0x63fa4000 0x4000>;
638 clocks = <&clks 159>;
639 status = "disabled";
640 };
641
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]642 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
646 reg = <0x63fac000 0x4000>;
647 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]648 clocks = <&clks 53>, <&clks 54>;
649 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]650 status = "disabled";
651 };
652
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]653 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]654 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
655 reg = <0x63fb0000 0x4000>;
656 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]657 clocks = <&clks 56>, <&clks 56>;
658 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]659 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]660 };
661
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]662 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]663 #address-cells = <1>;
664 #size-cells = <0>;
665 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
666 reg = <0x63fc0000 0x4000>;
667 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]668 clocks = <&clks 55>, <&clks 0>;
669 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]670 status = "disabled";
671 };
672
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]673 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]674 #address-cells = <1>;
675 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]676 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]677 reg = <0x63fc4000 0x4000>;
678 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]679 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]680 status = "disabled";
681 };
682
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]683 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]684 #address-cells = <1>;
685 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]686 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]687 reg = <0x63fc8000 0x4000>;
688 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]689 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]690 status = "disabled";
691 };
692
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]693 ssi1: ssi@63fcc000 {
694 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
695 reg = <0x63fcc000 0x4000>;
696 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]697 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]698 fsl,fifo-depth = <15>;
699 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
700 status = "disabled";
701 };
702
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]703 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]704 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
705 reg = <0x63fd0000 0x4000>;
706 status = "disabled";
707 };
708
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]709 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]710 compatible = "fsl,imx53-nand";
711 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
712 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]713 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]714 status = "disabled";
715 };
716
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]717 ssi3: ssi@63fe8000 {
718 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
719 reg = <0x63fe8000 0x4000>;
720 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]721 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]722 fsl,fifo-depth = <15>;
723 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
724 status = "disabled";
725 };
726
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]727 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]728 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
729 reg = <0x63fec000 0x4000>;
730 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]731 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
732 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]733 status = "disabled";
734 };
735 };
736 };
737};