Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 2 | # |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 3 | # MediaTek Clock Drivers |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 4 | # |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 5 | menu "Clock driver for MediaTek SoC" |
| 6 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 7 | |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 8 | config COMMON_CLK_MEDIATEK |
| 9 | bool |
Sean Wang | bc27360 | 2018-01-05 16:14:06 +0800 | [diff] [blame] | 10 | select RESET_CONTROLLER |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 11 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 12 | MediaTek SoCs' clock support. |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 13 | |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 14 | config COMMON_CLK_MT2701 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 15 | bool "Clock driver for MediaTek MT2701" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 16 | depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 17 | select COMMON_CLK_MEDIATEK |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 18 | default ARCH_MEDIATEK && ARM |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 19 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 20 | This driver supports MediaTek MT2701 basic clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 21 | |
| 22 | config COMMON_CLK_MT2701_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 23 | bool "Clock driver for MediaTek MT2701 mmsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 24 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 25 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 26 | This driver supports MediaTek MT2701 mmsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 27 | |
| 28 | config COMMON_CLK_MT2701_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 29 | bool "Clock driver for MediaTek MT2701 imgsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 30 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 31 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 32 | This driver supports MediaTek MT2701 imgsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 33 | |
| 34 | config COMMON_CLK_MT2701_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 35 | bool "Clock driver for MediaTek MT2701 vdecsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 36 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 37 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 38 | This driver supports MediaTek MT2701 vdecsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 39 | |
| 40 | config COMMON_CLK_MT2701_HIFSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 41 | bool "Clock driver for MediaTek MT2701 hifsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 42 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 43 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 44 | This driver supports MediaTek MT2701 hifsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 45 | |
| 46 | config COMMON_CLK_MT2701_ETHSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 47 | bool "Clock driver for MediaTek MT2701 ethsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 48 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 49 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 50 | This driver supports MediaTek MT2701 ethsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 51 | |
| 52 | config COMMON_CLK_MT2701_BDPSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 53 | bool "Clock driver for MediaTek MT2701 bdpsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 54 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 55 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 56 | This driver supports MediaTek MT2701 bdpsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 57 | |
Ryder Lee | b572f63 | 2018-03-20 11:16:52 +0800 | [diff] [blame] | 58 | config COMMON_CLK_MT2701_AUDSYS |
| 59 | bool "Clock driver for Mediatek MT2701 audsys" |
| 60 | depends on COMMON_CLK_MT2701 |
| 61 | ---help--- |
| 62 | This driver supports Mediatek MT2701 audsys clocks. |
| 63 | |
Sean Wang | a11ca68 | 2018-04-27 16:14:46 +0800 | [diff] [blame] | 64 | config COMMON_CLK_MT2701_G3DSYS |
| 65 | bool "Clock driver for MediaTek MT2701 g3dsys" |
| 66 | depends on COMMON_CLK_MT2701 |
| 67 | ---help--- |
| 68 | This driver supports MediaTek MT2701 g3dsys clocks. |
| 69 | |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 70 | config COMMON_CLK_MT2712 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 71 | bool "Clock driver for MediaTek MT2712" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 72 | depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| 73 | select COMMON_CLK_MEDIATEK |
| 74 | default ARCH_MEDIATEK && ARM64 |
| 75 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 76 | This driver supports MediaTek MT2712 basic clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 77 | |
| 78 | config COMMON_CLK_MT2712_BDPSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 79 | bool "Clock driver for MediaTek MT2712 bdpsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 80 | depends on COMMON_CLK_MT2712 |
| 81 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 82 | This driver supports MediaTek MT2712 bdpsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 83 | |
| 84 | config COMMON_CLK_MT2712_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 85 | bool "Clock driver for MediaTek MT2712 imgsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 86 | depends on COMMON_CLK_MT2712 |
| 87 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 88 | This driver supports MediaTek MT2712 imgsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 89 | |
| 90 | config COMMON_CLK_MT2712_JPGDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 91 | bool "Clock driver for MediaTek MT2712 jpgdecsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 92 | depends on COMMON_CLK_MT2712 |
| 93 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 94 | This driver supports MediaTek MT2712 jpgdecsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 95 | |
| 96 | config COMMON_CLK_MT2712_MFGCFG |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 97 | bool "Clock driver for MediaTek MT2712 mfgcfg" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 98 | depends on COMMON_CLK_MT2712 |
| 99 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 100 | This driver supports MediaTek MT2712 mfgcfg clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 101 | |
| 102 | config COMMON_CLK_MT2712_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 103 | bool "Clock driver for MediaTek MT2712 mmsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 104 | depends on COMMON_CLK_MT2712 |
| 105 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 106 | This driver supports MediaTek MT2712 mmsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 107 | |
| 108 | config COMMON_CLK_MT2712_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 109 | bool "Clock driver for MediaTek MT2712 vdecsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 110 | depends on COMMON_CLK_MT2712 |
| 111 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 112 | This driver supports MediaTek MT2712 vdecsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 113 | |
| 114 | config COMMON_CLK_MT2712_VENCSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 115 | bool "Clock driver for MediaTek MT2712 vencsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 116 | depends on COMMON_CLK_MT2712 |
| 117 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 118 | This driver supports MediaTek MT2712 vencsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 119 | |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 120 | config COMMON_CLK_MT6797 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 121 | bool "Clock driver for MediaTek MT6797" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 122 | depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| 123 | select COMMON_CLK_MEDIATEK |
| 124 | default ARCH_MEDIATEK && ARM64 |
| 125 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 126 | This driver supports MediaTek MT6797 basic clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 127 | |
| 128 | config COMMON_CLK_MT6797_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 129 | bool "Clock driver for MediaTek MT6797 mmsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 130 | depends on COMMON_CLK_MT6797 |
| 131 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 132 | This driver supports MediaTek MT6797 mmsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 133 | |
| 134 | config COMMON_CLK_MT6797_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 135 | bool "Clock driver for MediaTek MT6797 imgsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 136 | depends on COMMON_CLK_MT6797 |
| 137 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 138 | This driver supports MediaTek MT6797 imgsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 139 | |
| 140 | config COMMON_CLK_MT6797_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 141 | bool "Clock driver for MediaTek MT6797 vdecsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 142 | depends on COMMON_CLK_MT6797 |
| 143 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 144 | This driver supports MediaTek MT6797 vdecsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 145 | |
| 146 | config COMMON_CLK_MT6797_VENCSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 147 | bool "Clock driver for MediaTek MT6797 vencsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 148 | depends on COMMON_CLK_MT6797 |
| 149 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 150 | This driver supports MediaTek MT6797 vencsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 151 | |
Sean Wang | 2fc0a50 | 2017-10-05 11:50:24 +0800 | [diff] [blame] | 152 | config COMMON_CLK_MT7622 |
| 153 | bool "Clock driver for MediaTek MT7622" |
| 154 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 155 | select COMMON_CLK_MEDIATEK |
| 156 | default ARCH_MEDIATEK |
| 157 | ---help--- |
| 158 | This driver supports MediaTek MT7622 basic clocks and clocks |
| 159 | required for various periperals found on MediaTek. |
| 160 | |
| 161 | config COMMON_CLK_MT7622_ETHSYS |
| 162 | bool "Clock driver for MediaTek MT7622 ETHSYS" |
| 163 | depends on COMMON_CLK_MT7622 |
| 164 | ---help--- |
| 165 | This driver add support for clocks for Ethernet and SGMII |
| 166 | required on MediaTek MT7622 SoC. |
| 167 | |
| 168 | config COMMON_CLK_MT7622_HIFSYS |
| 169 | bool "Clock driver for MediaTek MT7622 HIFSYS" |
| 170 | depends on COMMON_CLK_MT7622 |
| 171 | ---help--- |
| 172 | This driver supports MediaTek MT7622 HIFSYS clocks providing |
| 173 | to PCI-E and USB. |
| 174 | |
| 175 | config COMMON_CLK_MT7622_AUDSYS |
| 176 | bool "Clock driver for MediaTek MT7622 AUDSYS" |
| 177 | depends on COMMON_CLK_MT7622 |
| 178 | ---help--- |
| 179 | This driver supports MediaTek MT7622 AUDSYS clocks providing |
| 180 | to audio consumers such as I2S and TDM. |
| 181 | |
Ryder Lee | 3b5e748 | 2018-11-05 16:43:55 +0800 | [diff] [blame] | 182 | config COMMON_CLK_MT7629 |
| 183 | bool "Clock driver for MediaTek MT7629" |
| 184 | depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST |
| 185 | select COMMON_CLK_MEDIATEK |
| 186 | default ARCH_MEDIATEK && ARM |
| 187 | ---help--- |
| 188 | This driver supports MediaTek MT7629 basic clocks and clocks |
| 189 | required for various periperals found on MediaTek. |
| 190 | |
| 191 | config COMMON_CLK_MT7629_ETHSYS |
| 192 | bool "Clock driver for MediaTek MT7629 ETHSYS" |
| 193 | depends on COMMON_CLK_MT7629 |
| 194 | ---help--- |
| 195 | This driver add support for clocks for Ethernet and SGMII |
| 196 | required on MediaTek MT7629 SoC. |
| 197 | |
| 198 | config COMMON_CLK_MT7629_HIFSYS |
| 199 | bool "Clock driver for MediaTek MT7629 HIFSYS" |
| 200 | depends on COMMON_CLK_MT7629 |
| 201 | ---help--- |
| 202 | This driver supports MediaTek MT7629 HIFSYS clocks providing |
| 203 | to PCI-E and USB. |
| 204 | |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 205 | config COMMON_CLK_MT8135 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 206 | bool "Clock driver for MediaTek MT8135" |
Jean Delvare | 3d21a4b | 2017-01-24 13:09:12 +0100 | [diff] [blame] | 207 | depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 208 | select COMMON_CLK_MEDIATEK |
Jean Delvare | 3d21a4b | 2017-01-24 13:09:12 +0100 | [diff] [blame] | 209 | default ARCH_MEDIATEK && ARM |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 210 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 211 | This driver supports MediaTek MT8135 clocks. |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 212 | |
| 213 | config COMMON_CLK_MT8173 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 214 | bool "Clock driver for MediaTek MT8173" |
Jean Delvare | 234d511 | 2016-10-14 14:44:13 +0200 | [diff] [blame] | 215 | depends on ARCH_MEDIATEK || COMPILE_TEST |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 216 | select COMMON_CLK_MEDIATEK |
| 217 | default ARCH_MEDIATEK |
| 218 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 219 | This driver supports MediaTek MT8173 clocks. |
Weiyi Lu | acddfc2 | 2019-03-05 13:05:45 +0800 | [diff] [blame] | 220 | |
| 221 | config COMMON_CLK_MT8183 |
| 222 | bool "Clock driver for MediaTek MT8183" |
| 223 | depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| 224 | select COMMON_CLK_MEDIATEK |
| 225 | default ARCH_MEDIATEK && ARM64 |
| 226 | help |
| 227 | This driver supports MediaTek MT8183 basic clocks. |
| 228 | |
| 229 | config COMMON_CLK_MT8183_AUDIOSYS |
| 230 | bool "Clock driver for MediaTek MT8183 audiosys" |
| 231 | depends on COMMON_CLK_MT8183 |
| 232 | help |
| 233 | This driver supports MediaTek MT8183 audiosys clocks. |
| 234 | |
| 235 | config COMMON_CLK_MT8183_CAMSYS |
| 236 | bool "Clock driver for MediaTek MT8183 camsys" |
| 237 | depends on COMMON_CLK_MT8183 |
| 238 | help |
| 239 | This driver supports MediaTek MT8183 camsys clocks. |
| 240 | |
| 241 | config COMMON_CLK_MT8183_IMGSYS |
| 242 | bool "Clock driver for MediaTek MT8183 imgsys" |
| 243 | depends on COMMON_CLK_MT8183 |
| 244 | help |
| 245 | This driver supports MediaTek MT8183 imgsys clocks. |
| 246 | |
| 247 | config COMMON_CLK_MT8183_IPU_CORE0 |
| 248 | bool "Clock driver for MediaTek MT8183 ipu_core0" |
| 249 | depends on COMMON_CLK_MT8183 |
| 250 | help |
| 251 | This driver supports MediaTek MT8183 ipu_core0 clocks. |
| 252 | |
| 253 | config COMMON_CLK_MT8183_IPU_CORE1 |
| 254 | bool "Clock driver for MediaTek MT8183 ipu_core1" |
| 255 | depends on COMMON_CLK_MT8183 |
| 256 | help |
| 257 | This driver supports MediaTek MT8183 ipu_core1 clocks. |
| 258 | |
| 259 | config COMMON_CLK_MT8183_IPU_ADL |
| 260 | bool "Clock driver for MediaTek MT8183 ipu_adl" |
| 261 | depends on COMMON_CLK_MT8183 |
| 262 | help |
| 263 | This driver supports MediaTek MT8183 ipu_adl clocks. |
| 264 | |
| 265 | config COMMON_CLK_MT8183_IPU_CONN |
| 266 | bool "Clock driver for MediaTek MT8183 ipu_conn" |
| 267 | depends on COMMON_CLK_MT8183 |
| 268 | help |
| 269 | This driver supports MediaTek MT8183 ipu_conn clocks. |
| 270 | |
| 271 | config COMMON_CLK_MT8183_MFGCFG |
| 272 | bool "Clock driver for MediaTek MT8183 mfgcfg" |
| 273 | depends on COMMON_CLK_MT8183 |
| 274 | help |
| 275 | This driver supports MediaTek MT8183 mfgcfg clocks. |
| 276 | |
| 277 | config COMMON_CLK_MT8183_MMSYS |
| 278 | bool "Clock driver for MediaTek MT8183 mmsys" |
| 279 | depends on COMMON_CLK_MT8183 |
| 280 | help |
| 281 | This driver supports MediaTek MT8183 mmsys clocks. |
| 282 | |
| 283 | config COMMON_CLK_MT8183_VDECSYS |
| 284 | bool "Clock driver for MediaTek MT8183 vdecsys" |
| 285 | depends on COMMON_CLK_MT8183 |
| 286 | help |
| 287 | This driver supports MediaTek MT8183 vdecsys clocks. |
| 288 | |
| 289 | config COMMON_CLK_MT8183_VENCSYS |
| 290 | bool "Clock driver for MediaTek MT8183 vencsys" |
| 291 | depends on COMMON_CLK_MT8183 |
| 292 | help |
| 293 | This driver supports MediaTek MT8183 vencsys clocks. |
| 294 | |
Fabien Parent | db077fe | 2019-03-23 22:16:02 +0100 | [diff] [blame] | 295 | config COMMON_CLK_MT8516 |
| 296 | bool "Clock driver for MediaTek MT8516" |
| 297 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 298 | select COMMON_CLK_MEDIATEK |
| 299 | default ARCH_MEDIATEK |
| 300 | help |
| 301 | This driver supports MediaTek MT8516 clocks. |
| 302 | |
Fabien Parent | 0fd4939 | 2019-05-02 14:18:43 +0200 | [diff] [blame] | 303 | config COMMON_CLK_MT8516_AUDSYS |
| 304 | bool "Clock driver for MediaTek MT8516 audsys" |
| 305 | depends on COMMON_CLK_MT8516 |
| 306 | help |
| 307 | This driver supports MediaTek MT8516 audsys clocks. |
| 308 | |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 309 | endmenu |