James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 1 | # |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 2 | # MediaTek Clock Drivers |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 3 | # |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 4 | menu "Clock driver for MediaTek SoC" |
| 5 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 6 | |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 7 | config COMMON_CLK_MEDIATEK |
| 8 | bool |
Sean Wang | bc27360 | 2018-01-05 16:14:06 +0800 | [diff] [blame^] | 9 | select RESET_CONTROLLER |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 10 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 11 | MediaTek SoCs' clock support. |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 12 | |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 13 | config COMMON_CLK_MT2701 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 14 | bool "Clock driver for MediaTek MT2701" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 15 | depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 16 | select COMMON_CLK_MEDIATEK |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 17 | default ARCH_MEDIATEK && ARM |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 18 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 19 | This driver supports MediaTek MT2701 basic clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 20 | |
| 21 | config COMMON_CLK_MT2701_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 22 | bool "Clock driver for MediaTek MT2701 mmsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 23 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 24 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 25 | This driver supports MediaTek MT2701 mmsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 26 | |
| 27 | config COMMON_CLK_MT2701_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 28 | bool "Clock driver for MediaTek MT2701 imgsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 29 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 30 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 31 | This driver supports MediaTek MT2701 imgsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 32 | |
| 33 | config COMMON_CLK_MT2701_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 34 | bool "Clock driver for MediaTek MT2701 vdecsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 35 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 36 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 37 | This driver supports MediaTek MT2701 vdecsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 38 | |
| 39 | config COMMON_CLK_MT2701_HIFSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 40 | bool "Clock driver for MediaTek MT2701 hifsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 41 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 42 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 43 | This driver supports MediaTek MT2701 hifsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 44 | |
| 45 | config COMMON_CLK_MT2701_ETHSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 46 | bool "Clock driver for MediaTek MT2701 ethsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 47 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 48 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 49 | This driver supports MediaTek MT2701 ethsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 50 | |
| 51 | config COMMON_CLK_MT2701_BDPSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 52 | bool "Clock driver for MediaTek MT2701 bdpsys" |
Jean Delvare | 6e9c0d5 | 2017-01-24 13:07:04 +0100 | [diff] [blame] | 53 | depends on COMMON_CLK_MT2701 |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 54 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 55 | This driver supports MediaTek MT2701 bdpsys clocks. |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 56 | |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 57 | config COMMON_CLK_MT2712 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 58 | bool "Clock driver for MediaTek MT2712" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 59 | depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| 60 | select COMMON_CLK_MEDIATEK |
| 61 | default ARCH_MEDIATEK && ARM64 |
| 62 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 63 | This driver supports MediaTek MT2712 basic clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 64 | |
| 65 | config COMMON_CLK_MT2712_BDPSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 66 | bool "Clock driver for MediaTek MT2712 bdpsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 67 | depends on COMMON_CLK_MT2712 |
| 68 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 69 | This driver supports MediaTek MT2712 bdpsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 70 | |
| 71 | config COMMON_CLK_MT2712_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 72 | bool "Clock driver for MediaTek MT2712 imgsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 73 | depends on COMMON_CLK_MT2712 |
| 74 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 75 | This driver supports MediaTek MT2712 imgsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 76 | |
| 77 | config COMMON_CLK_MT2712_JPGDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 78 | bool "Clock driver for MediaTek MT2712 jpgdecsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 79 | depends on COMMON_CLK_MT2712 |
| 80 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 81 | This driver supports MediaTek MT2712 jpgdecsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 82 | |
| 83 | config COMMON_CLK_MT2712_MFGCFG |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 84 | bool "Clock driver for MediaTek MT2712 mfgcfg" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 85 | depends on COMMON_CLK_MT2712 |
| 86 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 87 | This driver supports MediaTek MT2712 mfgcfg clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 88 | |
| 89 | config COMMON_CLK_MT2712_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 90 | bool "Clock driver for MediaTek MT2712 mmsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 91 | depends on COMMON_CLK_MT2712 |
| 92 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 93 | This driver supports MediaTek MT2712 mmsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 94 | |
| 95 | config COMMON_CLK_MT2712_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 96 | bool "Clock driver for MediaTek MT2712 vdecsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 97 | depends on COMMON_CLK_MT2712 |
| 98 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 99 | This driver supports MediaTek MT2712 vdecsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 100 | |
| 101 | config COMMON_CLK_MT2712_VENCSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 102 | bool "Clock driver for MediaTek MT2712 vencsys" |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 103 | depends on COMMON_CLK_MT2712 |
| 104 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 105 | This driver supports MediaTek MT2712 vencsys clocks. |
weiyi.lu@mediatek.com | e2f744a | 2017-10-23 12:10:34 +0800 | [diff] [blame] | 106 | |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 107 | config COMMON_CLK_MT6797 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 108 | bool "Clock driver for MediaTek MT6797" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 109 | depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| 110 | select COMMON_CLK_MEDIATEK |
| 111 | default ARCH_MEDIATEK && ARM64 |
| 112 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 113 | This driver supports MediaTek MT6797 basic clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 114 | |
| 115 | config COMMON_CLK_MT6797_MMSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 116 | bool "Clock driver for MediaTek MT6797 mmsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 117 | depends on COMMON_CLK_MT6797 |
| 118 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 119 | This driver supports MediaTek MT6797 mmsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 120 | |
| 121 | config COMMON_CLK_MT6797_IMGSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 122 | bool "Clock driver for MediaTek MT6797 imgsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 123 | depends on COMMON_CLK_MT6797 |
| 124 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 125 | This driver supports MediaTek MT6797 imgsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 126 | |
| 127 | config COMMON_CLK_MT6797_VDECSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 128 | bool "Clock driver for MediaTek MT6797 vdecsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 129 | depends on COMMON_CLK_MT6797 |
| 130 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 131 | This driver supports MediaTek MT6797 vdecsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 132 | |
| 133 | config COMMON_CLK_MT6797_VENCSYS |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 134 | bool "Clock driver for MediaTek MT6797 vencsys" |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 135 | depends on COMMON_CLK_MT6797 |
| 136 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 137 | This driver supports MediaTek MT6797 vencsys clocks. |
Kevin-CW Chen | 96596aa | 2017-04-08 09:20:30 +0800 | [diff] [blame] | 138 | |
Sean Wang | 2fc0a50 | 2017-10-05 11:50:24 +0800 | [diff] [blame] | 139 | config COMMON_CLK_MT7622 |
| 140 | bool "Clock driver for MediaTek MT7622" |
| 141 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 142 | select COMMON_CLK_MEDIATEK |
| 143 | default ARCH_MEDIATEK |
| 144 | ---help--- |
| 145 | This driver supports MediaTek MT7622 basic clocks and clocks |
| 146 | required for various periperals found on MediaTek. |
| 147 | |
| 148 | config COMMON_CLK_MT7622_ETHSYS |
| 149 | bool "Clock driver for MediaTek MT7622 ETHSYS" |
| 150 | depends on COMMON_CLK_MT7622 |
| 151 | ---help--- |
| 152 | This driver add support for clocks for Ethernet and SGMII |
| 153 | required on MediaTek MT7622 SoC. |
| 154 | |
| 155 | config COMMON_CLK_MT7622_HIFSYS |
| 156 | bool "Clock driver for MediaTek MT7622 HIFSYS" |
| 157 | depends on COMMON_CLK_MT7622 |
| 158 | ---help--- |
| 159 | This driver supports MediaTek MT7622 HIFSYS clocks providing |
| 160 | to PCI-E and USB. |
| 161 | |
| 162 | config COMMON_CLK_MT7622_AUDSYS |
| 163 | bool "Clock driver for MediaTek MT7622 AUDSYS" |
| 164 | depends on COMMON_CLK_MT7622 |
| 165 | ---help--- |
| 166 | This driver supports MediaTek MT7622 AUDSYS clocks providing |
| 167 | to audio consumers such as I2S and TDM. |
| 168 | |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 169 | config COMMON_CLK_MT8135 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 170 | bool "Clock driver for MediaTek MT8135" |
Jean Delvare | 3d21a4b | 2017-01-24 13:09:12 +0100 | [diff] [blame] | 171 | depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 172 | select COMMON_CLK_MEDIATEK |
Jean Delvare | 3d21a4b | 2017-01-24 13:09:12 +0100 | [diff] [blame] | 173 | default ARCH_MEDIATEK && ARM |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 174 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 175 | This driver supports MediaTek MT8135 clocks. |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 176 | |
| 177 | config COMMON_CLK_MT8173 |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 178 | bool "Clock driver for MediaTek MT8173" |
Jean Delvare | 234d511 | 2016-10-14 14:44:13 +0200 | [diff] [blame] | 179 | depends on ARCH_MEDIATEK || COMPILE_TEST |
James Liao | 2886c84 | 2016-08-19 13:34:49 +0800 | [diff] [blame] | 180 | select COMMON_CLK_MEDIATEK |
| 181 | default ARCH_MEDIATEK |
| 182 | ---help--- |
Sean Wang | 16a1ac1 | 2017-12-20 14:42:58 +0800 | [diff] [blame] | 183 | This driver supports MediaTek MT8173 clocks. |
| 184 | endmenu |