Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | /dts-v1/; |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 14 | #include "imx51.dtsi" |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 15 | |
| 16 | / { |
| 17 | model = "Freescale i.MX51 Babbage Board"; |
| 18 | compatible = "fsl,imx51-babbage", "fsl,imx51"; |
| 19 | |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 20 | memory { |
| 21 | reg = <0x90000000 0x20000000>; |
| 22 | }; |
| 23 | |
Russell King | 17b5001 | 2013-11-03 11:23:34 +0000 | [diff] [blame] | 24 | display0: display@di0 { |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 25 | compatible = "fsl,imx-parallel-display"; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 26 | interface-pix-fmt = "rgb24"; |
| 27 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 28 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
Fabio Estevam | 493a863 | 2013-10-08 15:52:12 -0300 | [diff] [blame] | 29 | display-timings { |
| 30 | native-mode = <&timing0>; |
| 31 | timing0: dvi { |
| 32 | clock-frequency = <65000000>; |
| 33 | hactive = <1024>; |
| 34 | vactive = <768>; |
| 35 | hback-porch = <220>; |
| 36 | hfront-porch = <40>; |
| 37 | vback-porch = <21>; |
| 38 | vfront-porch = <7>; |
| 39 | hsync-len = <60>; |
| 40 | vsync-len = <10>; |
| 41 | }; |
| 42 | }; |
Philipp Zabel | de10e04 | 2014-03-05 10:20:59 +0100 | [diff] [blame] | 43 | |
| 44 | port { |
| 45 | display0_in: endpoint { |
| 46 | remote-endpoint = <&ipu_di0_disp0>; |
| 47 | }; |
| 48 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 49 | }; |
Sascha Hauer | d6aef84 | 2012-11-12 15:39:01 +0100 | [diff] [blame] | 50 | |
Russell King | 17b5001 | 2013-11-03 11:23:34 +0000 | [diff] [blame] | 51 | display1: display@di1 { |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 52 | compatible = "fsl,imx-parallel-display"; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 53 | interface-pix-fmt = "rgb565"; |
| 54 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 55 | pinctrl-0 = <&pinctrl_ipu_disp2>; |
Fabio Estevam | 493a863 | 2013-10-08 15:52:12 -0300 | [diff] [blame] | 56 | status = "disabled"; |
| 57 | display-timings { |
| 58 | native-mode = <&timing1>; |
| 59 | timing1: claawvga { |
| 60 | clock-frequency = <27000000>; |
| 61 | hactive = <800>; |
| 62 | vactive = <480>; |
| 63 | hback-porch = <40>; |
| 64 | hfront-porch = <60>; |
| 65 | vback-porch = <10>; |
| 66 | vfront-porch = <10>; |
| 67 | hsync-len = <20>; |
| 68 | vsync-len = <10>; |
| 69 | hsync-active = <0>; |
| 70 | vsync-active = <0>; |
| 71 | de-active = <1>; |
| 72 | pixelclk-active = <0>; |
| 73 | }; |
| 74 | }; |
Philipp Zabel | de10e04 | 2014-03-05 10:20:59 +0100 | [diff] [blame] | 75 | |
| 76 | port { |
| 77 | display1_in: endpoint { |
| 78 | remote-endpoint = <&ipu_di1_disp1>; |
| 79 | }; |
| 80 | }; |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | gpio-keys { |
| 84 | compatible = "gpio-keys"; |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&pinctrl_gpio_keys>; |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 87 | |
| 88 | power { |
| 89 | label = "Power Button"; |
Alexander Shiyan | bdb3eec | 2013-11-19 15:47:27 +0400 | [diff] [blame] | 90 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 91 | linux,code = <116>; /* KEY_POWER */ |
| 92 | gpio-key,wakeup; |
| 93 | }; |
| 94 | }; |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 95 | |
Liu Ying | a198af2 | 2014-02-10 15:05:46 +0800 | [diff] [blame] | 96 | leds { |
| 97 | compatible = "gpio-leds"; |
| 98 | pinctrl-names = "default"; |
| 99 | pinctrl-0 = <&pinctrl_gpio_leds>; |
| 100 | |
| 101 | led-diagnostic { |
| 102 | label = "diagnostic"; |
| 103 | gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; |
| 104 | }; |
| 105 | }; |
| 106 | |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 107 | sound { |
| 108 | compatible = "fsl,imx51-babbage-sgtl5000", |
| 109 | "fsl,imx-audio-sgtl5000"; |
| 110 | model = "imx51-babbage-sgtl5000"; |
| 111 | ssi-controller = <&ssi2>; |
| 112 | audio-codec = <&sgtl5000>; |
| 113 | audio-routing = |
| 114 | "MIC_IN", "Mic Jack", |
| 115 | "Mic Jack", "Mic Bias", |
| 116 | "Headphone Jack", "HP_OUT"; |
| 117 | mux-int-port = <2>; |
| 118 | mux-ext-port = <3>; |
| 119 | }; |
Fabio Estevam | 84bb084 | 2013-06-09 22:07:47 -0300 | [diff] [blame] | 120 | |
| 121 | clocks { |
Alexander Shiyan | 677e28b | 2013-07-27 11:19:45 +0400 | [diff] [blame] | 122 | ckih1 { |
| 123 | clock-frequency = <22579200>; |
| 124 | }; |
| 125 | |
Fabio Estevam | 84bb084 | 2013-06-09 22:07:47 -0300 | [diff] [blame] | 126 | clk_26M: codec_clock { |
| 127 | compatible = "fixed-clock"; |
| 128 | reg=<0>; |
| 129 | #clock-cells = <0>; |
| 130 | clock-frequency = <26000000>; |
Alexander Shiyan | bdb3eec | 2013-11-19 15:47:27 +0400 | [diff] [blame] | 131 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; |
Fabio Estevam | 84bb084 | 2013-06-09 22:07:47 -0300 | [diff] [blame] | 132 | }; |
| 133 | }; |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 134 | |
| 135 | regulators { |
| 136 | compatible = "simple-bus"; |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | |
| 140 | reg_usb_vbus: regulator@0 { |
| 141 | compatible = "regulator-fixed"; |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 142 | pinctrl-names = "default"; |
| 143 | pinctrl-0 = <&pinctrl_usbreg>; |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 144 | reg = <0>; |
| 145 | regulator-name = "usb_vbus"; |
| 146 | regulator-min-microvolt = <5000000>; |
| 147 | regulator-max-microvolt = <5000000>; |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 148 | gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 149 | enable-active-high; |
| 150 | }; |
| 151 | }; |
| 152 | |
| 153 | usbphy { |
| 154 | #address-cells = <1>; |
| 155 | #size-cells = <0>; |
| 156 | compatible = "simple-bus"; |
| 157 | |
| 158 | usbh1phy: usbh1phy@0 { |
| 159 | compatible = "usb-nop-xceiv"; |
| 160 | reg = <0>; |
| 161 | clocks = <&clks 0>; |
| 162 | clock-names = "main_clk"; |
| 163 | }; |
| 164 | }; |
Shawn Guo | 9daaf31a | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 165 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 166 | |
| 167 | &esdhc1 { |
| 168 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 169 | pinctrl-0 = <&pinctrl_esdhc1>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 170 | fsl,cd-controller; |
| 171 | fsl,wp-controller; |
| 172 | status = "okay"; |
| 173 | }; |
| 174 | |
| 175 | &esdhc2 { |
| 176 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 177 | pinctrl-0 = <&pinctrl_esdhc2>; |
Alexander Shiyan | bdb3eec | 2013-11-19 15:47:27 +0400 | [diff] [blame] | 178 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
| 179 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 180 | status = "okay"; |
| 181 | }; |
| 182 | |
| 183 | &uart3 { |
| 184 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 185 | pinctrl-0 = <&pinctrl_uart3>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 186 | fsl,uart-has-rtscts; |
| 187 | status = "okay"; |
| 188 | }; |
| 189 | |
| 190 | &ecspi1 { |
| 191 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 192 | pinctrl-0 = <&pinctrl_ecspi1>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 193 | fsl,spi-num-chipselects = <2>; |
Alexander Shiyan | bdb3eec | 2013-11-19 15:47:27 +0400 | [diff] [blame] | 194 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, |
Alexander Shiyan | d2176f2 | 2013-11-27 15:55:45 +0400 | [diff] [blame] | 195 | <&gpio4 25 GPIO_ACTIVE_LOW>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 196 | status = "okay"; |
| 197 | |
| 198 | pmic: mc13892@0 { |
| 199 | #address-cells = <1>; |
| 200 | #size-cells = <0>; |
| 201 | compatible = "fsl,mc13892"; |
Alexander Shiyan | 1ddcff4 | 2014-04-16 11:24:52 +0400 | [diff] [blame^] | 202 | pinctrl-names = "default"; |
| 203 | pinctrl-0 = <&pinctrl_pmic>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 204 | spi-max-frequency = <6000000>; |
Sascha Hauer | dc07143 | 2013-06-25 15:51:59 +0200 | [diff] [blame] | 205 | spi-cs-high; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 206 | reg = <0>; |
| 207 | interrupt-parent = <&gpio1>; |
Alexander Shiyan | 1cbb74f | 2013-11-07 12:45:08 +0400 | [diff] [blame] | 208 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 209 | |
| 210 | regulators { |
| 211 | sw1_reg: sw1 { |
| 212 | regulator-min-microvolt = <600000>; |
| 213 | regulator-max-microvolt = <1375000>; |
| 214 | regulator-boot-on; |
| 215 | regulator-always-on; |
| 216 | }; |
| 217 | |
| 218 | sw2_reg: sw2 { |
| 219 | regulator-min-microvolt = <900000>; |
| 220 | regulator-max-microvolt = <1850000>; |
| 221 | regulator-boot-on; |
| 222 | regulator-always-on; |
| 223 | }; |
| 224 | |
| 225 | sw3_reg: sw3 { |
| 226 | regulator-min-microvolt = <1100000>; |
| 227 | regulator-max-microvolt = <1850000>; |
| 228 | regulator-boot-on; |
| 229 | regulator-always-on; |
| 230 | }; |
| 231 | |
| 232 | sw4_reg: sw4 { |
| 233 | regulator-min-microvolt = <1100000>; |
| 234 | regulator-max-microvolt = <1850000>; |
| 235 | regulator-boot-on; |
| 236 | regulator-always-on; |
| 237 | }; |
| 238 | |
| 239 | vpll_reg: vpll { |
| 240 | regulator-min-microvolt = <1050000>; |
| 241 | regulator-max-microvolt = <1800000>; |
| 242 | regulator-boot-on; |
| 243 | regulator-always-on; |
| 244 | }; |
| 245 | |
| 246 | vdig_reg: vdig { |
| 247 | regulator-min-microvolt = <1650000>; |
| 248 | regulator-max-microvolt = <1650000>; |
| 249 | regulator-boot-on; |
| 250 | }; |
| 251 | |
| 252 | vsd_reg: vsd { |
| 253 | regulator-min-microvolt = <1800000>; |
| 254 | regulator-max-microvolt = <3150000>; |
| 255 | }; |
| 256 | |
| 257 | vusb2_reg: vusb2 { |
| 258 | regulator-min-microvolt = <2400000>; |
| 259 | regulator-max-microvolt = <2775000>; |
| 260 | regulator-boot-on; |
| 261 | regulator-always-on; |
| 262 | }; |
| 263 | |
| 264 | vvideo_reg: vvideo { |
| 265 | regulator-min-microvolt = <2775000>; |
| 266 | regulator-max-microvolt = <2775000>; |
| 267 | }; |
| 268 | |
| 269 | vaudio_reg: vaudio { |
| 270 | regulator-min-microvolt = <2300000>; |
| 271 | regulator-max-microvolt = <3000000>; |
| 272 | }; |
| 273 | |
| 274 | vcam_reg: vcam { |
| 275 | regulator-min-microvolt = <2500000>; |
| 276 | regulator-max-microvolt = <3000000>; |
| 277 | }; |
| 278 | |
| 279 | vgen1_reg: vgen1 { |
| 280 | regulator-min-microvolt = <1200000>; |
| 281 | regulator-max-microvolt = <1200000>; |
| 282 | }; |
| 283 | |
| 284 | vgen2_reg: vgen2 { |
| 285 | regulator-min-microvolt = <1200000>; |
| 286 | regulator-max-microvolt = <3150000>; |
| 287 | regulator-always-on; |
| 288 | }; |
| 289 | |
| 290 | vgen3_reg: vgen3 { |
| 291 | regulator-min-microvolt = <1800000>; |
| 292 | regulator-max-microvolt = <2900000>; |
| 293 | regulator-always-on; |
| 294 | }; |
| 295 | }; |
| 296 | }; |
| 297 | |
| 298 | flash: at45db321d@1 { |
| 299 | #address-cells = <1>; |
| 300 | #size-cells = <1>; |
| 301 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; |
| 302 | spi-max-frequency = <25000000>; |
| 303 | reg = <1>; |
| 304 | |
| 305 | partition@0 { |
| 306 | label = "U-Boot"; |
| 307 | reg = <0x0 0x40000>; |
| 308 | read-only; |
| 309 | }; |
| 310 | |
| 311 | partition@40000 { |
| 312 | label = "Kernel"; |
| 313 | reg = <0x40000 0x3c0000>; |
| 314 | }; |
| 315 | }; |
| 316 | }; |
| 317 | |
Philipp Zabel | de10e04 | 2014-03-05 10:20:59 +0100 | [diff] [blame] | 318 | &ipu_di0_disp0 { |
| 319 | remote-endpoint = <&display0_in>; |
| 320 | }; |
| 321 | |
| 322 | &ipu_di1_disp1 { |
| 323 | remote-endpoint = <&display1_in>; |
| 324 | }; |
| 325 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 326 | &ssi2 { |
| 327 | fsl,mode = "i2s-slave"; |
| 328 | status = "okay"; |
| 329 | }; |
| 330 | |
| 331 | &iomuxc { |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 332 | imx51-babbage { |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 333 | pinctrl_audmux: audmuxgrp { |
| 334 | fsl,pins = < |
| 335 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 |
| 336 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 |
| 337 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 |
| 338 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 |
| 339 | >; |
| 340 | }; |
| 341 | |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 342 | pinctrl_clkcodec: clkcodecgrp { |
| 343 | fsl,pins = < |
| 344 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 |
| 345 | >; |
| 346 | }; |
| 347 | |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 348 | pinctrl_ecspi1: ecspi1grp { |
| 349 | fsl,pins = < |
| 350 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
| 351 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 |
| 352 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 353 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ |
| 354 | MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 355 | >; |
| 356 | }; |
| 357 | |
| 358 | pinctrl_esdhc1: esdhc1grp { |
| 359 | fsl,pins = < |
| 360 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
| 361 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 |
| 362 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 |
| 363 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 |
| 364 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 |
| 365 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 366 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 |
| 367 | MX51_PAD_GPIO1_1__SD1_WP 0x20d5 |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 368 | >; |
| 369 | }; |
| 370 | |
| 371 | pinctrl_esdhc2: esdhc2grp { |
| 372 | fsl,pins = < |
| 373 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
| 374 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 |
| 375 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 |
| 376 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 |
| 377 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 |
| 378 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 379 | MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ |
| 380 | MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 381 | >; |
| 382 | }; |
| 383 | |
| 384 | pinctrl_fec: fecgrp { |
| 385 | fsl,pins = < |
| 386 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 |
| 387 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 |
| 388 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 |
| 389 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 |
| 390 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 |
| 391 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 |
| 392 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 |
| 393 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 |
| 394 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 |
| 395 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 |
| 396 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 |
| 397 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 |
| 398 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 |
| 399 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 |
| 400 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 |
| 401 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 |
| 402 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 |
Alexander Shiyan | 0c33f66 | 2013-11-27 15:55:46 +0400 | [diff] [blame] | 403 | MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 404 | >; |
| 405 | }; |
| 406 | |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 407 | pinctrl_gpio_keys: gpiokeysgrp { |
| 408 | fsl,pins = < |
| 409 | MX51_PAD_EIM_A27__GPIO2_21 0x5 |
| 410 | >; |
| 411 | }; |
| 412 | |
Liu Ying | a198af2 | 2014-02-10 15:05:46 +0800 | [diff] [blame] | 413 | pinctrl_gpio_leds: gpioledsgrp { |
| 414 | fsl,pins = < |
| 415 | MX51_PAD_EIM_D22__GPIO2_6 0x80000000 |
| 416 | >; |
| 417 | }; |
| 418 | |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 419 | pinctrl_i2c2: i2c2grp { |
| 420 | fsl,pins = < |
| 421 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed |
| 422 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed |
| 423 | >; |
| 424 | }; |
| 425 | |
| 426 | pinctrl_ipu_disp1: ipudisp1grp { |
| 427 | fsl,pins = < |
| 428 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 |
| 429 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 |
| 430 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 |
| 431 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 |
| 432 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 |
| 433 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 |
| 434 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 |
| 435 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 |
| 436 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 |
| 437 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 |
| 438 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 |
| 439 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 |
| 440 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 |
| 441 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 |
| 442 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 |
| 443 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 |
| 444 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 |
| 445 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 |
| 446 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 |
| 447 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 |
| 448 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 |
| 449 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 |
| 450 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 |
| 451 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 |
| 452 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 |
| 453 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 |
| 454 | >; |
| 455 | }; |
| 456 | |
| 457 | pinctrl_ipu_disp2: ipudisp2grp { |
| 458 | fsl,pins = < |
| 459 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 |
| 460 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 |
| 461 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 |
| 462 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 |
| 463 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 |
| 464 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 |
| 465 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 |
| 466 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 |
| 467 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 |
| 468 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 |
| 469 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 |
| 470 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 |
| 471 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 |
| 472 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 |
| 473 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 |
| 474 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 |
| 475 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 |
| 476 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 |
| 477 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 |
| 478 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 |
| 479 | >; |
| 480 | }; |
| 481 | |
| 482 | pinctrl_kpp: kppgrp { |
| 483 | fsl,pins = < |
| 484 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 |
| 485 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 |
| 486 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 |
| 487 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 |
| 488 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 |
| 489 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 |
| 490 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 |
| 491 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 |
| 492 | >; |
| 493 | }; |
| 494 | |
Alexander Shiyan | 1ddcff4 | 2014-04-16 11:24:52 +0400 | [diff] [blame^] | 495 | pinctrl_pmic: pmicgrp { |
| 496 | fsl,pins = < |
| 497 | MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ |
| 498 | >; |
| 499 | }; |
| 500 | |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 501 | pinctrl_uart1: uart1grp { |
| 502 | fsl,pins = < |
| 503 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |
| 504 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 |
| 505 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 |
| 506 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 |
| 507 | >; |
| 508 | }; |
| 509 | |
| 510 | pinctrl_uart2: uart2grp { |
| 511 | fsl,pins = < |
| 512 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 |
| 513 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 |
| 514 | >; |
| 515 | }; |
| 516 | |
| 517 | pinctrl_uart3: uart3grp { |
| 518 | fsl,pins = < |
| 519 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 |
| 520 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 |
| 521 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 |
| 522 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 |
| 523 | >; |
| 524 | }; |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 525 | |
| 526 | pinctrl_usbh1: usbh1grp { |
| 527 | fsl,pins = < |
| 528 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 |
| 529 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 |
| 530 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 |
| 531 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 |
| 532 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 |
| 533 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 |
| 534 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 |
| 535 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 |
| 536 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 |
| 537 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 |
| 538 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 539 | >; |
| 540 | }; |
| 541 | |
| 542 | pinctrl_usbreg: usbreggrp { |
| 543 | fsl,pins = < |
| 544 | MX51_PAD_EIM_D21__GPIO2_5 0x85 |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 545 | >; |
| 546 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 547 | }; |
| 548 | }; |
| 549 | |
| 550 | &uart1 { |
| 551 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 552 | pinctrl-0 = <&pinctrl_uart1>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 553 | fsl,uart-has-rtscts; |
| 554 | status = "okay"; |
| 555 | }; |
| 556 | |
| 557 | &uart2 { |
| 558 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 559 | pinctrl-0 = <&pinctrl_uart2>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 560 | status = "okay"; |
| 561 | }; |
| 562 | |
| 563 | &i2c2 { |
| 564 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 565 | pinctrl-0 = <&pinctrl_i2c2>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 566 | status = "okay"; |
| 567 | |
| 568 | sgtl5000: codec@0a { |
| 569 | compatible = "fsl,sgtl5000"; |
Alexander Shiyan | 2ccc447 | 2014-04-16 11:24:51 +0400 | [diff] [blame] | 570 | pinctrl-names = "default"; |
| 571 | pinctrl-0 = <&pinctrl_clkcodec>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 572 | reg = <0x0a>; |
Fabio Estevam | 84bb084 | 2013-06-09 22:07:47 -0300 | [diff] [blame] | 573 | clocks = <&clk_26M>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 574 | VDDA-supply = <&vdig_reg>; |
| 575 | VDDIO-supply = <&vvideo_reg>; |
| 576 | }; |
| 577 | }; |
| 578 | |
| 579 | &audmux { |
| 580 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 581 | pinctrl-0 = <&pinctrl_audmux>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 582 | status = "okay"; |
| 583 | }; |
| 584 | |
| 585 | &fec { |
| 586 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 587 | pinctrl-0 = <&pinctrl_fec>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 588 | phy-mode = "mii"; |
Alexander Shiyan | 0c33f66 | 2013-11-27 15:55:46 +0400 | [diff] [blame] | 589 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; |
| 590 | phy-reset-duration = <1>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 591 | status = "okay"; |
| 592 | }; |
Liu Ying | 67eb7c0 | 2013-01-03 20:37:34 +0800 | [diff] [blame] | 593 | |
| 594 | &kpp { |
| 595 | pinctrl-names = "default"; |
Shawn Guo | 5a2a7d5 | 2013-11-04 16:05:37 +0800 | [diff] [blame] | 596 | pinctrl-0 = <&pinctrl_kpp>; |
Alexander Shiyan | 72d86d2 | 2014-01-11 10:54:19 +0400 | [diff] [blame] | 597 | linux,keymap = < |
| 598 | MATRIX_KEY(0, 0, KEY_UP) |
| 599 | MATRIX_KEY(0, 1, KEY_DOWN) |
| 600 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) |
| 601 | MATRIX_KEY(0, 3, KEY_HOME) |
| 602 | MATRIX_KEY(1, 0, KEY_RIGHT) |
| 603 | MATRIX_KEY(1, 1, KEY_LEFT) |
| 604 | MATRIX_KEY(1, 2, KEY_ENTER) |
| 605 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) |
| 606 | MATRIX_KEY(2, 0, KEY_F6) |
| 607 | MATRIX_KEY(2, 1, KEY_F8) |
| 608 | MATRIX_KEY(2, 2, KEY_F9) |
| 609 | MATRIX_KEY(2, 3, KEY_F10) |
| 610 | MATRIX_KEY(3, 0, KEY_F1) |
| 611 | MATRIX_KEY(3, 1, KEY_F2) |
| 612 | MATRIX_KEY(3, 2, KEY_F3) |
| 613 | MATRIX_KEY(3, 3, KEY_POWER) |
| 614 | >; |
Liu Ying | 67eb7c0 | 2013-01-03 20:37:34 +0800 | [diff] [blame] | 615 | status = "okay"; |
| 616 | }; |
Fabio Estevam | 9bf206a | 2014-03-26 11:54:38 -0300 | [diff] [blame] | 617 | |
| 618 | &usbh1 { |
| 619 | pinctrl-names = "default"; |
| 620 | pinctrl-0 = <&pinctrl_usbh1>; |
| 621 | vbus-supply = <®_usb_vbus>; |
| 622 | fsl,usbphy = <&usbh1phy>; |
| 623 | phy_type = "ulpi"; |
| 624 | status = "okay"; |
| 625 | }; |
Fabio Estevam | 7538d4f | 2014-03-26 11:54:39 -0300 | [diff] [blame] | 626 | |
| 627 | &usbotg { |
| 628 | dr_mode = "otg"; |
| 629 | disable-over-current; |
| 630 | phy_type = "utmi_wide"; |
| 631 | status = "okay"; |
| 632 | }; |