blob: ad143eb9b5a95d1b6a4c9d8f080bbc84942c146a [file] [log] [blame]
Shawn Guo9daaf31a2011-10-17 08:42:17 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +080014#include "imx51.dtsi"
Shawn Guo9daaf31a2011-10-17 08:42:17 +080015
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
Shawn Guo9daaf31a2011-10-17 08:42:17 +080020 memory {
21 reg = <0x90000000 0x20000000>;
22 };
23
Russell King17b50012013-11-03 11:23:34 +000024 display0: display@di0 {
Shawn Guobe4ccfc2012-12-31 11:32:48 +080025 compatible = "fsl,imx-parallel-display";
Shawn Guobe4ccfc2012-12-31 11:32:48 +080026 interface-pix-fmt = "rgb24";
27 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +080028 pinctrl-0 = <&pinctrl_ipu_disp1>;
Fabio Estevam493a8632013-10-08 15:52:12 -030029 display-timings {
30 native-mode = <&timing0>;
31 timing0: dvi {
32 clock-frequency = <65000000>;
33 hactive = <1024>;
34 vactive = <768>;
35 hback-porch = <220>;
36 hfront-porch = <40>;
37 vback-porch = <21>;
38 vfront-porch = <7>;
39 hsync-len = <60>;
40 vsync-len = <10>;
41 };
42 };
Philipp Zabelde10e042014-03-05 10:20:59 +010043
44 port {
45 display0_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +080049 };
Sascha Hauerd6aef842012-11-12 15:39:01 +010050
Russell King17b50012013-11-03 11:23:34 +000051 display1: display@di1 {
Shawn Guobe4ccfc2012-12-31 11:32:48 +080052 compatible = "fsl,imx-parallel-display";
Shawn Guobe4ccfc2012-12-31 11:32:48 +080053 interface-pix-fmt = "rgb565";
54 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +080055 pinctrl-0 = <&pinctrl_ipu_disp2>;
Fabio Estevam493a8632013-10-08 15:52:12 -030056 status = "disabled";
57 display-timings {
58 native-mode = <&timing1>;
59 timing1: claawvga {
60 clock-frequency = <27000000>;
61 hactive = <800>;
62 vactive = <480>;
63 hback-porch = <40>;
64 hfront-porch = <60>;
65 vback-porch = <10>;
66 vfront-porch = <10>;
67 hsync-len = <20>;
68 vsync-len = <10>;
69 hsync-active = <0>;
70 vsync-active = <0>;
71 de-active = <1>;
72 pixelclk-active = <0>;
73 };
74 };
Philipp Zabelde10e042014-03-05 10:20:59 +010075
76 port {
77 display1_in: endpoint {
78 remote-endpoint = <&ipu_di1_disp1>;
79 };
80 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +080081 };
82
83 gpio-keys {
84 compatible = "gpio-keys";
Alexander Shiyan2ccc4472014-04-16 11:24:51 +040085 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_gpio_keys>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +080087
88 power {
89 label = "Power Button";
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +040090 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +080091 linux,code = <116>; /* KEY_POWER */
92 gpio-key,wakeup;
93 };
94 };
Shawn Guoa15d9f82012-05-11 13:08:46 +080095
Liu Yinga198af22014-02-10 15:05:46 +080096 leds {
97 compatible = "gpio-leds";
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_gpio_leds>;
100
101 led-diagnostic {
102 label = "diagnostic";
103 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
104 };
105 };
106
Shawn Guoa15d9f82012-05-11 13:08:46 +0800107 sound {
108 compatible = "fsl,imx51-babbage-sgtl5000",
109 "fsl,imx-audio-sgtl5000";
110 model = "imx51-babbage-sgtl5000";
111 ssi-controller = <&ssi2>;
112 audio-codec = <&sgtl5000>;
113 audio-routing =
114 "MIC_IN", "Mic Jack",
115 "Mic Jack", "Mic Bias",
116 "Headphone Jack", "HP_OUT";
117 mux-int-port = <2>;
118 mux-ext-port = <3>;
119 };
Fabio Estevam84bb0842013-06-09 22:07:47 -0300120
121 clocks {
Alexander Shiyan677e28b2013-07-27 11:19:45 +0400122 ckih1 {
123 clock-frequency = <22579200>;
124 };
125
Fabio Estevam84bb0842013-06-09 22:07:47 -0300126 clk_26M: codec_clock {
127 compatible = "fixed-clock";
128 reg=<0>;
129 #clock-cells = <0>;
130 clock-frequency = <26000000>;
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +0400131 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
Fabio Estevam84bb0842013-06-09 22:07:47 -0300132 };
133 };
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300134
135 regulators {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 reg_usb_vbus: regulator@0 {
141 compatible = "regulator-fixed";
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usbreg>;
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300144 reg = <0>;
145 regulator-name = "usb_vbus";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400148 gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300149 enable-active-high;
150 };
151 };
152
153 usbphy {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "simple-bus";
157
158 usbh1phy: usbh1phy@0 {
159 compatible = "usb-nop-xceiv";
160 reg = <0>;
161 clocks = <&clks 0>;
162 clock-names = "main_clk";
163 };
164 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800165};
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800166
167&esdhc1 {
168 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800169 pinctrl-0 = <&pinctrl_esdhc1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800170 fsl,cd-controller;
171 fsl,wp-controller;
172 status = "okay";
173};
174
175&esdhc2 {
176 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800177 pinctrl-0 = <&pinctrl_esdhc2>;
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +0400178 cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
179 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800180 status = "okay";
181};
182
183&uart3 {
184 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800185 pinctrl-0 = <&pinctrl_uart3>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800186 fsl,uart-has-rtscts;
187 status = "okay";
188};
189
190&ecspi1 {
191 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800192 pinctrl-0 = <&pinctrl_ecspi1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800193 fsl,spi-num-chipselects = <2>;
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +0400194 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
Alexander Shiyand2176f22013-11-27 15:55:45 +0400195 <&gpio4 25 GPIO_ACTIVE_LOW>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800196 status = "okay";
197
198 pmic: mc13892@0 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "fsl,mc13892";
202 spi-max-frequency = <6000000>;
Sascha Hauerdc071432013-06-25 15:51:59 +0200203 spi-cs-high;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800204 reg = <0>;
205 interrupt-parent = <&gpio1>;
Alexander Shiyan1cbb74f2013-11-07 12:45:08 +0400206 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800207
208 regulators {
209 sw1_reg: sw1 {
210 regulator-min-microvolt = <600000>;
211 regulator-max-microvolt = <1375000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 sw2_reg: sw2 {
217 regulator-min-microvolt = <900000>;
218 regulator-max-microvolt = <1850000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 sw3_reg: sw3 {
224 regulator-min-microvolt = <1100000>;
225 regulator-max-microvolt = <1850000>;
226 regulator-boot-on;
227 regulator-always-on;
228 };
229
230 sw4_reg: sw4 {
231 regulator-min-microvolt = <1100000>;
232 regulator-max-microvolt = <1850000>;
233 regulator-boot-on;
234 regulator-always-on;
235 };
236
237 vpll_reg: vpll {
238 regulator-min-microvolt = <1050000>;
239 regulator-max-microvolt = <1800000>;
240 regulator-boot-on;
241 regulator-always-on;
242 };
243
244 vdig_reg: vdig {
245 regulator-min-microvolt = <1650000>;
246 regulator-max-microvolt = <1650000>;
247 regulator-boot-on;
248 };
249
250 vsd_reg: vsd {
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <3150000>;
253 };
254
255 vusb2_reg: vusb2 {
256 regulator-min-microvolt = <2400000>;
257 regulator-max-microvolt = <2775000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 vvideo_reg: vvideo {
263 regulator-min-microvolt = <2775000>;
264 regulator-max-microvolt = <2775000>;
265 };
266
267 vaudio_reg: vaudio {
268 regulator-min-microvolt = <2300000>;
269 regulator-max-microvolt = <3000000>;
270 };
271
272 vcam_reg: vcam {
273 regulator-min-microvolt = <2500000>;
274 regulator-max-microvolt = <3000000>;
275 };
276
277 vgen1_reg: vgen1 {
278 regulator-min-microvolt = <1200000>;
279 regulator-max-microvolt = <1200000>;
280 };
281
282 vgen2_reg: vgen2 {
283 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <3150000>;
285 regulator-always-on;
286 };
287
288 vgen3_reg: vgen3 {
289 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <2900000>;
291 regulator-always-on;
292 };
293 };
294 };
295
296 flash: at45db321d@1 {
297 #address-cells = <1>;
298 #size-cells = <1>;
299 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
300 spi-max-frequency = <25000000>;
301 reg = <1>;
302
303 partition@0 {
304 label = "U-Boot";
305 reg = <0x0 0x40000>;
306 read-only;
307 };
308
309 partition@40000 {
310 label = "Kernel";
311 reg = <0x40000 0x3c0000>;
312 };
313 };
314};
315
Philipp Zabelde10e042014-03-05 10:20:59 +0100316&ipu_di0_disp0 {
317 remote-endpoint = <&display0_in>;
318};
319
320&ipu_di1_disp1 {
321 remote-endpoint = <&display1_in>;
322};
323
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800324&ssi2 {
325 fsl,mode = "i2s-slave";
326 status = "okay";
327};
328
329&iomuxc {
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800330 imx51-babbage {
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800331 pinctrl_audmux: audmuxgrp {
332 fsl,pins = <
333 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
334 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
335 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
336 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
337 >;
338 };
339
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400340 pinctrl_clkcodec: clkcodecgrp {
341 fsl,pins = <
342 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
343 >;
344 };
345
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800346 pinctrl_ecspi1: ecspi1grp {
347 fsl,pins = <
348 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
349 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
350 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400351 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
352 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800353 >;
354 };
355
356 pinctrl_esdhc1: esdhc1grp {
357 fsl,pins = <
358 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
359 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
360 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
361 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
362 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
363 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400364 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
365 MX51_PAD_GPIO1_1__SD1_WP 0x20d5
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800366 >;
367 };
368
369 pinctrl_esdhc2: esdhc2grp {
370 fsl,pins = <
371 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
372 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
373 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
374 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
375 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
376 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400377 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
378 MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800379 >;
380 };
381
382 pinctrl_fec: fecgrp {
383 fsl,pins = <
384 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
385 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
386 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
387 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
388 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
389 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
390 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
391 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
392 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
393 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
394 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
395 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
396 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
397 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
398 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
399 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
400 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Alexander Shiyan0c33f662013-11-27 15:55:46 +0400401 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800402 >;
403 };
404
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400405 pinctrl_gpio_keys: gpiokeysgrp {
406 fsl,pins = <
407 MX51_PAD_EIM_A27__GPIO2_21 0x5
408 >;
409 };
410
Liu Yinga198af22014-02-10 15:05:46 +0800411 pinctrl_gpio_leds: gpioledsgrp {
412 fsl,pins = <
413 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
414 >;
415 };
416
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800417 pinctrl_i2c2: i2c2grp {
418 fsl,pins = <
419 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
420 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
421 >;
422 };
423
424 pinctrl_ipu_disp1: ipudisp1grp {
425 fsl,pins = <
426 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
427 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
428 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
429 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
430 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
431 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
432 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
433 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
434 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
435 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
436 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
437 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
438 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
439 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
440 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
441 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
442 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
443 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
444 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
445 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
446 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
447 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
448 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
449 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
450 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
451 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
452 >;
453 };
454
455 pinctrl_ipu_disp2: ipudisp2grp {
456 fsl,pins = <
457 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
458 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
459 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
460 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
461 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
462 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
463 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
464 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
465 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
466 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
467 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
468 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
469 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
470 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
471 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
472 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
473 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
474 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
475 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
476 MX51_PAD_DI_GP4__DI2_PIN15 0x5
477 >;
478 };
479
480 pinctrl_kpp: kppgrp {
481 fsl,pins = <
482 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
483 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
484 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
485 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
486 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
487 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
488 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
489 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
490 >;
491 };
492
493 pinctrl_uart1: uart1grp {
494 fsl,pins = <
495 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
496 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
497 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
498 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
499 >;
500 };
501
502 pinctrl_uart2: uart2grp {
503 fsl,pins = <
504 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
505 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
506 >;
507 };
508
509 pinctrl_uart3: uart3grp {
510 fsl,pins = <
511 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
512 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
513 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
514 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
515 >;
516 };
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300517
518 pinctrl_usbh1: usbh1grp {
519 fsl,pins = <
520 MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
521 MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
522 MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
523 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
524 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
525 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
526 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
527 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
528 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
529 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
530 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400531 >;
532 };
533
534 pinctrl_usbreg: usbreggrp {
535 fsl,pins = <
536 MX51_PAD_EIM_D21__GPIO2_5 0x85
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300537 >;
538 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800539 };
540};
541
542&uart1 {
543 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800544 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800545 fsl,uart-has-rtscts;
546 status = "okay";
547};
548
549&uart2 {
550 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800551 pinctrl-0 = <&pinctrl_uart2>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800552 status = "okay";
553};
554
555&i2c2 {
556 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800557 pinctrl-0 = <&pinctrl_i2c2>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800558 status = "okay";
559
560 sgtl5000: codec@0a {
561 compatible = "fsl,sgtl5000";
Alexander Shiyan2ccc4472014-04-16 11:24:51 +0400562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_clkcodec>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800564 reg = <0x0a>;
Fabio Estevam84bb0842013-06-09 22:07:47 -0300565 clocks = <&clk_26M>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800566 VDDA-supply = <&vdig_reg>;
567 VDDIO-supply = <&vvideo_reg>;
568 };
569};
570
571&audmux {
572 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800573 pinctrl-0 = <&pinctrl_audmux>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800574 status = "okay";
575};
576
577&fec {
578 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800579 pinctrl-0 = <&pinctrl_fec>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800580 phy-mode = "mii";
Alexander Shiyan0c33f662013-11-27 15:55:46 +0400581 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
582 phy-reset-duration = <1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800583 status = "okay";
584};
Liu Ying67eb7c02013-01-03 20:37:34 +0800585
586&kpp {
587 pinctrl-names = "default";
Shawn Guo5a2a7d52013-11-04 16:05:37 +0800588 pinctrl-0 = <&pinctrl_kpp>;
Alexander Shiyan72d86d22014-01-11 10:54:19 +0400589 linux,keymap = <
590 MATRIX_KEY(0, 0, KEY_UP)
591 MATRIX_KEY(0, 1, KEY_DOWN)
592 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
593 MATRIX_KEY(0, 3, KEY_HOME)
594 MATRIX_KEY(1, 0, KEY_RIGHT)
595 MATRIX_KEY(1, 1, KEY_LEFT)
596 MATRIX_KEY(1, 2, KEY_ENTER)
597 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
598 MATRIX_KEY(2, 0, KEY_F6)
599 MATRIX_KEY(2, 1, KEY_F8)
600 MATRIX_KEY(2, 2, KEY_F9)
601 MATRIX_KEY(2, 3, KEY_F10)
602 MATRIX_KEY(3, 0, KEY_F1)
603 MATRIX_KEY(3, 1, KEY_F2)
604 MATRIX_KEY(3, 2, KEY_F3)
605 MATRIX_KEY(3, 3, KEY_POWER)
606 >;
Liu Ying67eb7c02013-01-03 20:37:34 +0800607 status = "okay";
608};
Fabio Estevam9bf206a2014-03-26 11:54:38 -0300609
610&usbh1 {
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_usbh1>;
613 vbus-supply = <&reg_usb_vbus>;
614 fsl,usbphy = <&usbh1phy>;
615 phy_type = "ulpi";
616 status = "okay";
617};
Fabio Estevam7538d4f2014-03-26 11:54:39 -0300618
619&usbotg {
620 dr_mode = "otg";
621 disable-over-current;
622 phy_type = "utmi_wide";
623 status = "okay";
624};