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Shawn Guo9daaf31a2011-10-17 08:42:17 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +080014#include "imx51.dtsi"
Shawn Guo9daaf31a2011-10-17 08:42:17 +080015
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
Shawn Guo9daaf31a2011-10-17 08:42:17 +080020 memory {
21 reg = <0x90000000 0x20000000>;
22 };
23
Russell King17b50012013-11-03 11:23:34 +000024 display0: display@di0 {
Shawn Guobe4ccfc2012-12-31 11:32:48 +080025 compatible = "fsl,imx-parallel-display";
Shawn Guobe4ccfc2012-12-31 11:32:48 +080026 interface-pix-fmt = "rgb24";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
Fabio Estevam493a8632013-10-08 15:52:12 -030029 display-timings {
30 native-mode = <&timing0>;
31 timing0: dvi {
32 clock-frequency = <65000000>;
33 hactive = <1024>;
34 vactive = <768>;
35 hback-porch = <220>;
36 hfront-porch = <40>;
37 vback-porch = <21>;
38 vfront-porch = <7>;
39 hsync-len = <60>;
40 vsync-len = <10>;
41 };
42 };
Philipp Zabelde10e042014-03-05 10:20:59 +010043
44 port {
45 display0_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +080049 };
Sascha Hauerd6aef842012-11-12 15:39:01 +010050
Russell King17b50012013-11-03 11:23:34 +000051 display1: display@di1 {
Shawn Guobe4ccfc2012-12-31 11:32:48 +080052 compatible = "fsl,imx-parallel-display";
Shawn Guobe4ccfc2012-12-31 11:32:48 +080053 interface-pix-fmt = "rgb565";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
Fabio Estevam493a8632013-10-08 15:52:12 -030056 status = "disabled";
57 display-timings {
58 native-mode = <&timing1>;
59 timing1: claawvga {
60 clock-frequency = <27000000>;
61 hactive = <800>;
62 vactive = <480>;
63 hback-porch = <40>;
64 hfront-porch = <60>;
65 vback-porch = <10>;
66 vfront-porch = <10>;
67 hsync-len = <20>;
68 vsync-len = <10>;
69 hsync-active = <0>;
70 vsync-active = <0>;
71 de-active = <1>;
72 pixelclk-active = <0>;
73 };
74 };
Philipp Zabelde10e042014-03-05 10:20:59 +010075
76 port {
77 display1_in: endpoint {
78 remote-endpoint = <&ipu_di1_disp1>;
79 };
80 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +080081 };
82
83 gpio-keys {
84 compatible = "gpio-keys";
85
86 power {
87 label = "Power Button";
Richard Zhao4d191862011-12-14 09:26:44 +080088 gpios = <&gpio2 21 0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +080089 linux,code = <116>; /* KEY_POWER */
90 gpio-key,wakeup;
91 };
92 };
Shawn Guoa15d9f82012-05-11 13:08:46 +080093
94 sound {
95 compatible = "fsl,imx51-babbage-sgtl5000",
96 "fsl,imx-audio-sgtl5000";
97 model = "imx51-babbage-sgtl5000";
98 ssi-controller = <&ssi2>;
99 audio-codec = <&sgtl5000>;
100 audio-routing =
101 "MIC_IN", "Mic Jack",
102 "Mic Jack", "Mic Bias",
103 "Headphone Jack", "HP_OUT";
104 mux-int-port = <2>;
105 mux-ext-port = <3>;
106 };
Fabio Estevam84bb0842013-06-09 22:07:47 -0300107
108 clocks {
Alexander Shiyan677e28b2013-07-27 11:19:45 +0400109 ckih1 {
110 clock-frequency = <22579200>;
111 };
112
Fabio Estevam84bb0842013-06-09 22:07:47 -0300113 clk_26M: codec_clock {
114 compatible = "fixed-clock";
115 reg=<0>;
116 #clock-cells = <0>;
117 clock-frequency = <26000000>;
118 gpios = <&gpio4 26 1>;
119 };
120 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800121};
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800122
123&esdhc1 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_esdhc1_1>;
126 fsl,cd-controller;
127 fsl,wp-controller;
128 status = "okay";
129};
130
131&esdhc2 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_esdhc2_1>;
134 cd-gpios = <&gpio1 6 0>;
135 wp-gpios = <&gpio1 5 0>;
136 status = "okay";
137};
138
139&uart3 {
140 pinctrl-names = "default";
Alexander Shiyan727b8122013-08-21 11:28:23 +0400141 pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800142 fsl,uart-has-rtscts;
143 status = "okay";
144};
145
146&ecspi1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_ecspi1_1>;
149 fsl,spi-num-chipselects = <2>;
150 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
151 status = "okay";
152
153 pmic: mc13892@0 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "fsl,mc13892";
157 spi-max-frequency = <6000000>;
Sascha Hauerdc071432013-06-25 15:51:59 +0200158 spi-cs-high;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800159 reg = <0>;
160 interrupt-parent = <&gpio1>;
161 interrupts = <8 0x4>;
162
163 regulators {
164 sw1_reg: sw1 {
165 regulator-min-microvolt = <600000>;
166 regulator-max-microvolt = <1375000>;
167 regulator-boot-on;
168 regulator-always-on;
169 };
170
171 sw2_reg: sw2 {
172 regulator-min-microvolt = <900000>;
173 regulator-max-microvolt = <1850000>;
174 regulator-boot-on;
175 regulator-always-on;
176 };
177
178 sw3_reg: sw3 {
179 regulator-min-microvolt = <1100000>;
180 regulator-max-microvolt = <1850000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 sw4_reg: sw4 {
186 regulator-min-microvolt = <1100000>;
187 regulator-max-microvolt = <1850000>;
188 regulator-boot-on;
189 regulator-always-on;
190 };
191
192 vpll_reg: vpll {
193 regulator-min-microvolt = <1050000>;
194 regulator-max-microvolt = <1800000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 vdig_reg: vdig {
200 regulator-min-microvolt = <1650000>;
201 regulator-max-microvolt = <1650000>;
202 regulator-boot-on;
203 };
204
205 vsd_reg: vsd {
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <3150000>;
208 };
209
210 vusb2_reg: vusb2 {
211 regulator-min-microvolt = <2400000>;
212 regulator-max-microvolt = <2775000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 vvideo_reg: vvideo {
218 regulator-min-microvolt = <2775000>;
219 regulator-max-microvolt = <2775000>;
220 };
221
222 vaudio_reg: vaudio {
223 regulator-min-microvolt = <2300000>;
224 regulator-max-microvolt = <3000000>;
225 };
226
227 vcam_reg: vcam {
228 regulator-min-microvolt = <2500000>;
229 regulator-max-microvolt = <3000000>;
230 };
231
232 vgen1_reg: vgen1 {
233 regulator-min-microvolt = <1200000>;
234 regulator-max-microvolt = <1200000>;
235 };
236
237 vgen2_reg: vgen2 {
238 regulator-min-microvolt = <1200000>;
239 regulator-max-microvolt = <3150000>;
240 regulator-always-on;
241 };
242
243 vgen3_reg: vgen3 {
244 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <2900000>;
246 regulator-always-on;
247 };
248 };
249 };
250
251 flash: at45db321d@1 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
255 spi-max-frequency = <25000000>;
256 reg = <1>;
257
258 partition@0 {
259 label = "U-Boot";
260 reg = <0x0 0x40000>;
261 read-only;
262 };
263
264 partition@40000 {
265 label = "Kernel";
266 reg = <0x40000 0x3c0000>;
267 };
268 };
269};
270
Philipp Zabelde10e042014-03-05 10:20:59 +0100271&ipu_di0_disp0 {
272 remote-endpoint = <&display0_in>;
273};
274
275&ipu_di1_disp1 {
276 remote-endpoint = <&display1_in>;
277};
278
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800279&ssi2 {
280 fsl,mode = "i2s-slave";
281 status = "okay";
282};
283
284&iomuxc {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_hog>;
287
288 hog {
289 pinctrl_hog: hoggrp {
290 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800291 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
292 MX51_PAD_GPIO1_1__SD1_WP 0x20d5
293 MX51_PAD_GPIO1_5__GPIO1_5 0x100
294 MX51_PAD_GPIO1_6__GPIO1_6 0x100
295 MX51_PAD_EIM_A27__GPIO2_21 0x5
296 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
297 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
Fabio Estevam84bb0842013-06-09 22:07:47 -0300298 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800299 >;
300 };
301 };
302};
303
304&uart1 {
305 pinctrl-names = "default";
Alexander Shiyan727b8122013-08-21 11:28:23 +0400306 pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800307 fsl,uart-has-rtscts;
308 status = "okay";
309};
310
311&uart2 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart2_1>;
314 status = "okay";
315};
316
317&i2c2 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_i2c2_1>;
320 status = "okay";
321
322 sgtl5000: codec@0a {
323 compatible = "fsl,sgtl5000";
324 reg = <0x0a>;
Fabio Estevam84bb0842013-06-09 22:07:47 -0300325 clocks = <&clk_26M>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800326 VDDA-supply = <&vdig_reg>;
327 VDDIO-supply = <&vvideo_reg>;
328 };
329};
330
331&audmux {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_audmux_1>;
334 status = "okay";
335};
336
337&fec {
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_fec_1>;
340 phy-mode = "mii";
341 status = "okay";
342};
Liu Ying67eb7c02013-01-03 20:37:34 +0800343
344&kpp {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_kpp_1>;
347 linux,keymap = <0x00000067 /* KEY_UP */
348 0x0001006c /* KEY_DOWN */
349 0x00020072 /* KEY_VOLUMEDOWN */
350 0x00030066 /* KEY_HOME */
351 0x0100006a /* KEY_RIGHT */
352 0x01010069 /* KEY_LEFT */
353 0x0102001c /* KEY_ENTER */
354 0x01030073 /* KEY_VOLUMEUP */
355 0x02000040 /* KEY_F6 */
356 0x02010042 /* KEY_F8 */
357 0x02020043 /* KEY_F9 */
358 0x02030044 /* KEY_F10 */
359 0x0300003b /* KEY_F1 */
360 0x0301003c /* KEY_F2 */
361 0x0302003d /* KEY_F3 */
362 0x03030074>; /* KEY_POWER */
363 status = "okay";
364};