Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 1 | * Renesas R-Car Display Unit (DU) |
| 2 | |
| 3 | Required Properties: |
| 4 | |
| 5 | - compatible: must be one of the following. |
Fabrizio Castro | faf4a3f | 2017-10-13 16:22:19 +0100 | [diff] [blame] | 6 | - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU |
Biju Das | 5eb08d9 | 2018-09-21 19:08:28 +0100 | [diff] [blame] | 7 | - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU |
Fabrizio Castro | faf4a3f | 2017-10-13 16:22:19 +0100 | [diff] [blame] | 8 | - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU |
Fabrizio Castro | aab2b52 | 2018-09-21 19:08:27 +0100 | [diff] [blame] | 9 | - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU |
Biju Das | 2acd1d1 | 2019-04-12 13:38:02 +0100 | [diff] [blame] | 10 | - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU |
Biju Das | 2d4794f | 2019-09-30 10:15:02 +0100 | [diff] [blame] | 11 | - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU |
Fabrizio Castro | 8c9fde4 | 2018-12-13 20:20:45 +0000 | [diff] [blame] | 12 | - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 13 | - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU |
| 14 | - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU |
Laurent Pinchart | f1ceb84a | 2015-07-17 10:44:33 +0300 | [diff] [blame] | 15 | - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU |
Sergei Shtylyov | 73323dd | 2016-08-04 15:01:02 -0700 | [diff] [blame] | 16 | - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU |
Laurent Pinchart | f1ceb84a | 2015-07-17 10:44:33 +0300 | [diff] [blame] | 17 | - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU |
Laurent Pinchart | 090425c | 2015-07-17 10:44:33 +0300 | [diff] [blame] | 18 | - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU |
Laurent Pinchart | 2427b30 | 2015-09-07 17:34:26 +0300 | [diff] [blame] | 19 | - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU |
Laurent Pinchart | 63b5053 | 2016-09-06 02:11:43 +0300 | [diff] [blame] | 20 | - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU |
Kieran Bingham | dc81429 | 2018-04-26 17:53:31 +0100 | [diff] [blame] | 21 | - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU |
Sergei Shtylyov | 88fb4a0 | 2018-01-19 00:05:58 +0300 | [diff] [blame] | 22 | - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU |
Sergei Shtylyov | 4ffe5aa | 2018-06-04 22:04:59 +0300 | [diff] [blame] | 23 | - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU |
Laurent Pinchart | f48097d | 2018-08-20 17:07:25 +0300 | [diff] [blame] | 24 | - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU |
Kieran Bingham | b378b35 | 2018-02-15 08:38:17 +0000 | [diff] [blame] | 25 | - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 26 | |
Laurent Pinchart | 6d2ca85 | 2018-01-10 16:05:46 +0200 | [diff] [blame] | 27 | - reg: the memory-mapped I/O registers base address and length |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 28 | |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 29 | - interrupts: Interrupt specifiers for the DU interrupts. |
| 30 | |
| 31 | - clocks: A list of phandles + clock-specifier pairs, one for each entry in |
| 32 | the clock-names property. |
| 33 | - clock-names: Name of the clocks. This property is model-dependent. |
| 34 | - R8A7779 uses a single functional clock. The clock doesn't need to be |
| 35 | named. |
Laurent Pinchart | 6d2ca85 | 2018-01-10 16:05:46 +0200 | [diff] [blame] | 36 | - All other DU instances use one functional clock per channel The |
| 37 | functional clocks must be named "du.x" with "x" being the channel |
| 38 | numerical index. |
| 39 | - In addition to the functional clocks, all DU versions also support |
| 40 | externally supplied pixel clocks. Those clocks are optional. When |
| 41 | supplied they must be named "dclkin.x" with "x" being the input clock |
| 42 | numerical index. |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 43 | |
Jacopo Mondi | 6e2258b | 2019-10-16 10:55:42 +0200 | [diff] [blame] | 44 | - renesas,cmms: A list of phandles to the CMM instances present in the SoC, |
| 45 | one for each available DU channel. The property shall not be specified for |
| 46 | SoCs that do not provide any CMM (such as V3M and V3H). |
| 47 | |
Geert Uytterhoeven | c81456d | 2019-11-05 19:35:02 +0100 | [diff] [blame^] | 48 | - renesas,vsps: A list of phandle and channel index tuples to the VSPs that |
| 49 | handle the memory interfaces for the DU channels. The phandle identifies the |
| 50 | VSP instance that serves the DU channel, and the channel index identifies |
| 51 | the LIF instance in that VSP. |
| 52 | |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 53 | Required nodes: |
| 54 | |
| 55 | The connections to the DU output video ports are modeled using the OF graph |
| 56 | bindings specified in Documentation/devicetree/bindings/graph.txt. |
| 57 | |
| 58 | The following table lists for each supported model the port number |
| 59 | corresponding to each DU output. |
| 60 | |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 61 | Port0 Port1 Port2 Port3 |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 62 | ----------------------------------------------------------------------------- |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 63 | R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - |
Biju Das | 5eb08d9 | 2018-09-21 19:08:28 +0100 | [diff] [blame] | 64 | R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 65 | R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - |
Fabrizio Castro | aab2b52 | 2018-09-21 19:08:27 +0100 | [diff] [blame] | 66 | R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - |
Biju Das | 2acd1d1 | 2019-04-12 13:38:02 +0100 | [diff] [blame] | 67 | R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - |
Biju Das | 2d4794f | 2019-09-30 10:15:02 +0100 | [diff] [blame] | 68 | R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - |
Fabrizio Castro | 8c9fde4 | 2018-12-13 20:20:45 +0000 | [diff] [blame] | 69 | R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 70 | R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - |
| 71 | R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - |
| 72 | R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - |
| 73 | R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - |
| 74 | R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - |
| 75 | R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - |
| 76 | R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 |
| 77 | R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - |
Kieran Bingham | dc81429 | 2018-04-26 17:53:31 +0100 | [diff] [blame] | 78 | R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 79 | R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - |
Sergei Shtylyov | 4ffe5aa | 2018-06-04 22:04:59 +0300 | [diff] [blame] | 80 | R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - |
Laurent Pinchart | f48097d | 2018-08-20 17:07:25 +0300 | [diff] [blame] | 81 | R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - |
Kieran Bingham | a4af842 | 2018-04-26 17:53:30 +0100 | [diff] [blame] | 82 | R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 83 | |
| 84 | |
Laurent Pinchart | fd57d77 | 2017-07-12 11:43:36 +0300 | [diff] [blame] | 85 | Example: R8A7795 (R-Car H3) ES2.0 DU |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 86 | |
Laurent Pinchart | fd57d77 | 2017-07-12 11:43:36 +0300 | [diff] [blame] | 87 | du: display@feb00000 { |
| 88 | compatible = "renesas,du-r8a7795"; |
Laurent Pinchart | 6d2ca85 | 2018-01-10 16:05:46 +0200 | [diff] [blame] | 89 | reg = <0 0xfeb00000 0 0x80000>; |
Laurent Pinchart | fd57d77 | 2017-07-12 11:43:36 +0300 | [diff] [blame] | 90 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 91 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| 94 | clocks = <&cpg CPG_MOD 724>, |
| 95 | <&cpg CPG_MOD 723>, |
| 96 | <&cpg CPG_MOD 722>, |
Laurent Pinchart | 6d2ca85 | 2018-01-10 16:05:46 +0200 | [diff] [blame] | 97 | <&cpg CPG_MOD 721>; |
| 98 | clock-names = "du.0", "du.1", "du.2", "du.3"; |
Jacopo Mondi | 6e2258b | 2019-10-16 10:55:42 +0200 | [diff] [blame] | 99 | renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; |
Geert Uytterhoeven | c81456d | 2019-11-05 19:35:02 +0100 | [diff] [blame^] | 100 | renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 101 | |
| 102 | ports { |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <0>; |
| 105 | |
| 106 | port@0 { |
| 107 | reg = <0>; |
| 108 | du_out_rgb: endpoint { |
| 109 | }; |
| 110 | }; |
| 111 | port@1 { |
| 112 | reg = <1>; |
Laurent Pinchart | fd57d77 | 2017-07-12 11:43:36 +0300 | [diff] [blame] | 113 | du_out_hdmi0: endpoint { |
| 114 | remote-endpoint = <&dw_hdmi0_in>; |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 115 | }; |
| 116 | }; |
| 117 | port@2 { |
| 118 | reg = <2>; |
Laurent Pinchart | fd57d77 | 2017-07-12 11:43:36 +0300 | [diff] [blame] | 119 | du_out_hdmi1: endpoint { |
| 120 | remote-endpoint = <&dw_hdmi1_in>; |
| 121 | }; |
| 122 | }; |
| 123 | port@3 { |
| 124 | reg = <3>; |
| 125 | du_out_lvds0: endpoint { |
Laurent Pinchart | cd8968f | 2014-08-27 18:26:39 +0200 | [diff] [blame] | 126 | }; |
| 127 | }; |
| 128 | }; |
| 129 | }; |