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Laurent Pinchartcd8968f2014-08-27 18:26:39 +02001* Renesas R-Car Display Unit (DU)
2
3Required Properties:
4
5 - compatible: must be one of the following.
6 - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
7 - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
Laurent Pinchartf1ceb84a2015-07-17 10:44:33 +03008 - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
Sergei Shtylyov73323dd2016-08-04 15:01:02 -07009 - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
Laurent Pinchartf1ceb84a2015-07-17 10:44:33 +030010 - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
Laurent Pinchart090425c2015-07-17 10:44:33 +030011 - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
Laurent Pinchart2427b302015-09-07 17:34:26 +030012 - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
Laurent Pinchart63b50532016-09-06 02:11:43 +030013 - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
Laurent Pinchartcd8968f2014-08-27 18:26:39 +020014
15 - reg: A list of base address and length of each memory resource, one for
16 each entry in the reg-names property.
17 - reg-names: Name of the memory resources. The DU requires one memory
18 resource for the DU core (named "du") and one memory resource for each
19 LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
20 index).
21
22 - interrupt-parent: phandle of the parent interrupt controller.
23 - interrupts: Interrupt specifiers for the DU interrupts.
24
25 - clocks: A list of phandles + clock-specifier pairs, one for each entry in
26 the clock-names property.
27 - clock-names: Name of the clocks. This property is model-dependent.
28 - R8A7779 uses a single functional clock. The clock doesn't need to be
29 named.
Laurent Pinchart63b50532016-09-06 02:11:43 +030030 - R8A779[0123456] use one functional clock per channel and one clock per
31 LVDS encoder (if available). The functional clocks must be named "du.x"
32 with "x" being the channel numerical index. The LVDS clocks must be
33 named "lvds.x" with "x" being the LVDS encoder numerical index.
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +020034 - In addition to the functional and encoder clocks, all DU versions also
35 support externally supplied pixel clocks. Those clocks are optional.
36 When supplied they must be named "dclkin.x" with "x" being the input
37 clock numerical index.
Laurent Pinchartcd8968f2014-08-27 18:26:39 +020038
39Required nodes:
40
41The connections to the DU output video ports are modeled using the OF graph
42bindings specified in Documentation/devicetree/bindings/graph.txt.
43
44The following table lists for each supported model the port number
45corresponding to each DU output.
46
Laurent Pinchart2427b302015-09-07 17:34:26 +030047 Port 0 Port1 Port2 Port3
Laurent Pinchartcd8968f2014-08-27 18:26:39 +020048-----------------------------------------------------------------------------
Laurent Pinchart2427b302015-09-07 17:34:26 +030049 R8A7779 (H1) DPAD 0 DPAD 1 - -
50 R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
51 R8A7791 (M2-W) DPAD LVDS 0 - -
Sergei Shtylyov73323dd2016-08-04 15:01:02 -070052 R8A7792 (V2H) DPAD 0 DPAD 1 - -
Laurent Pinchart2427b302015-09-07 17:34:26 +030053 R8A7793 (M2-N) DPAD LVDS 0 - -
54 R8A7794 (E2) DPAD 0 DPAD 1 - -
55 R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
Laurent Pinchart63b50532016-09-06 02:11:43 +030056 R8A7796 (M3-W) DPAD HDMI LVDS -
Laurent Pinchartcd8968f2014-08-27 18:26:39 +020057
58
59Example: R8A7790 (R-Car H2) DU
60
61 du: du@feb00000 {
62 compatible = "renesas,du-r8a7790";
63 reg = <0 0xfeb00000 0 0x70000>,
64 <0 0xfeb90000 0 0x1c>,
65 <0 0xfeb94000 0 0x1c>;
66 reg-names = "du", "lvds.0", "lvds.1";
67 interrupt-parent = <&gic>;
68 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
69 <0 268 IRQ_TYPE_LEVEL_HIGH>,
70 <0 269 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
72 <&mstp7_clks R8A7790_CLK_DU1>,
73 <&mstp7_clks R8A7790_CLK_DU2>,
74 <&mstp7_clks R8A7790_CLK_LVDS0>,
75 <&mstp7_clks R8A7790_CLK_LVDS1>;
76 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
77
78 ports {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 port@0 {
83 reg = <0>;
84 du_out_rgb: endpoint {
85 };
86 };
87 port@1 {
88 reg = <1>;
89 du_out_lvds0: endpoint {
90 };
91 };
92 port@2 {
93 reg = <2>;
94 du_out_lvds1: endpoint {
95 };
96 };
97 };
98 };