blob: 92e54fbdbf9616ef380e7d8665ce4509add34075 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Justin P. Mattock79add622011-04-04 14:15:29 -07006 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
James Hogan61d73042014-03-04 10:23:57 +000010#include <linux/cpu_pm.h>
Ralf Baechlea754f702007-11-03 01:01:37 +000011#include <linux/hardirq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/init.h>
Ralf Baechledb813fe2007-09-27 18:26:43 +010013#include <linux/highmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/kernel.h>
Ralf Baechle641e97f2007-10-11 23:46:05 +010015#include <linux/linkage.h>
Ralf Baechleff522052013-09-17 12:44:31 +020016#include <linux/preempt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/sched.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010018#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/mm.h>
Chris Dearman35133692007-09-19 00:58:24 +010020#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/bitops.h>
22
23#include <asm/bcache.h>
24#include <asm/bootinfo.h>
Ralf Baechleec74e362005-07-13 11:48:45 +000025#include <asm/cache.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/cpu-features.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020029#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <asm/io.h>
31#include <asm/page.h>
32#include <asm/pgtable.h>
33#include <asm/r4kcache.h>
Ralf Baechlee001e522007-07-28 12:45:47 +010034#include <asm/sections.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/mmu_context.h>
36#include <asm/war.h>
Thiemo Seuferba5187d2005-04-25 16:36:23 +000037#include <asm/cacheflush.h> /* for run_uncached() */
David Daney9cd9669b2012-05-15 00:04:49 -070038#include <asm/traps.h>
Steven J. Hillb6d92b42013-03-25 13:47:29 -050039#include <asm/dma-coherence.h>
Markos Chandrascccf34e2015-07-10 09:29:10 +010040#include <asm/mips-cm.h>
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010041
42/*
43 * Special Variant of smp_call_function for use by cache functions:
44 *
45 * o No return value
46 * o collapses to normal function call on UP kernels
47 * o collapses to normal function call on systems with a single shared
48 * primary cache.
Ralf Baechlec8c5f3f2010-10-29 19:08:25 +010049 * o doesn't disable interrupts on the local CPU
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010050 */
Ralf Baechle48a26e62010-10-29 19:08:25 +010051static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010052{
53 preempt_disable();
54
Markos Chandrascccf34e2015-07-10 09:29:10 +010055 /*
56 * The Coherent Manager propagates address-based cache ops to other
57 * cores but not index-based ops. However, r4k_on_each_cpu is used
58 * in both cases so there is no easy way to tell what kind of op is
59 * executed to the other cores. The best we can probably do is
60 * to restrict that call when a CM is not present because both
61 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
62 */
63 if (!mips_cm_present())
64 smp_call_function_many(&cpu_foreign_map, func, info, 1);
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010065 func(info);
66 preempt_enable();
67}
68
Paul Burton0ee958e2014-01-15 10:31:53 +000069#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
Ralf Baechle39b8d522008-04-28 17:14:26 +010070#define cpu_has_safe_index_cacheops 0
71#else
72#define cpu_has_safe_index_cacheops 1
73#endif
74
Ralf Baechleec74e362005-07-13 11:48:45 +000075/*
76 * Must die.
77 */
78static unsigned long icache_size __read_mostly;
79static unsigned long dcache_size __read_mostly;
80static unsigned long scache_size __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82/*
83 * Dummy cache handling routines for machines without boardcaches
84 */
Chris Dearman73f40352006-06-20 18:06:52 +010085static void cache_noop(void) {}
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87static struct bcache_ops no_sc_ops = {
Chris Dearman73f40352006-06-20 18:06:52 +010088 .bc_enable = (void *)cache_noop,
89 .bc_disable = (void *)cache_noop,
90 .bc_wback_inv = (void *)cache_noop,
91 .bc_inv = (void *)cache_noop
Linus Torvalds1da177e2005-04-16 15:20:36 -070092};
93
94struct bcache_ops *bcops = &no_sc_ops;
95
Thiemo Seufer330cfe02005-09-01 18:33:58 +000096#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
97#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99#define R4600_HIT_CACHEOP_WAR_IMPL \
100do { \
101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
102 *(volatile unsigned long *)CKSEG1; \
103 if (R4600_V1_HIT_CACHEOP_WAR) \
104 __asm__ __volatile__("nop;nop;nop;nop"); \
105} while (0)
106
107static void (*r4k_blast_dcache_page)(unsigned long addr);
108
109static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
110{
111 R4600_HIT_CACHEOP_WAR_IMPL;
112 blast_dcache32_page(addr);
113}
114
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700115static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
116{
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700117 blast_dcache64_page(addr);
118}
119
David Daney18a8cd62014-05-28 23:52:09 +0200120static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
121{
122 blast_dcache128_page(addr);
123}
124
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000125static void r4k_blast_dcache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
127 unsigned long dc_lsize = cpu_dcache_line_size();
128
David Daney18a8cd62014-05-28 23:52:09 +0200129 switch (dc_lsize) {
130 case 0:
Chris Dearman73f40352006-06-20 18:06:52 +0100131 r4k_blast_dcache_page = (void *)cache_noop;
David Daney18a8cd62014-05-28 23:52:09 +0200132 break;
133 case 16:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 r4k_blast_dcache_page = blast_dcache16_page;
David Daney18a8cd62014-05-28 23:52:09 +0200135 break;
136 case 32:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
David Daney18a8cd62014-05-28 23:52:09 +0200138 break;
139 case 64:
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700140 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
David Daney18a8cd62014-05-28 23:52:09 +0200141 break;
142 case 128:
143 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
144 break;
145 default:
146 break;
147 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148}
149
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000150#ifndef CONFIG_EVA
151#define r4k_blast_dcache_user_page r4k_blast_dcache_page
152#else
153
154static void (*r4k_blast_dcache_user_page)(unsigned long addr);
155
156static void r4k_blast_dcache_user_page_setup(void)
157{
158 unsigned long dc_lsize = cpu_dcache_line_size();
159
160 if (dc_lsize == 0)
161 r4k_blast_dcache_user_page = (void *)cache_noop;
162 else if (dc_lsize == 16)
163 r4k_blast_dcache_user_page = blast_dcache16_user_page;
164 else if (dc_lsize == 32)
165 r4k_blast_dcache_user_page = blast_dcache32_user_page;
166 else if (dc_lsize == 64)
167 r4k_blast_dcache_user_page = blast_dcache64_user_page;
168}
169
170#endif
171
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
173
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000174static void r4k_blast_dcache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175{
176 unsigned long dc_lsize = cpu_dcache_line_size();
177
Chris Dearman73f40352006-06-20 18:06:52 +0100178 if (dc_lsize == 0)
179 r4k_blast_dcache_page_indexed = (void *)cache_noop;
180 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
182 else if (dc_lsize == 32)
183 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700184 else if (dc_lsize == 64)
185 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
David Daney18a8cd62014-05-28 23:52:09 +0200186 else if (dc_lsize == 128)
187 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188}
189
Sanjay Lalf2e36562012-11-21 18:34:10 -0800190void (* r4k_blast_dcache)(void);
191EXPORT_SYMBOL(r4k_blast_dcache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000193static void r4k_blast_dcache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194{
195 unsigned long dc_lsize = cpu_dcache_line_size();
196
Chris Dearman73f40352006-06-20 18:06:52 +0100197 if (dc_lsize == 0)
198 r4k_blast_dcache = (void *)cache_noop;
199 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 r4k_blast_dcache = blast_dcache16;
201 else if (dc_lsize == 32)
202 r4k_blast_dcache = blast_dcache32;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700203 else if (dc_lsize == 64)
204 r4k_blast_dcache = blast_dcache64;
David Daney18a8cd62014-05-28 23:52:09 +0200205 else if (dc_lsize == 128)
206 r4k_blast_dcache = blast_dcache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207}
208
209/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
210#define JUMP_TO_ALIGN(order) \
211 __asm__ __volatile__( \
212 "b\t1f\n\t" \
213 ".align\t" #order "\n\t" \
214 "1:\n\t" \
215 )
216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
Ralf Baechle70342282013-01-22 12:59:30 +0100217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219static inline void blast_r4600_v1_icache32(void)
220{
221 unsigned long flags;
222
223 local_irq_save(flags);
224 blast_icache32();
225 local_irq_restore(flags);
226}
227
228static inline void tx49_blast_icache32(void)
229{
230 unsigned long start = INDEX_BASE;
231 unsigned long end = start + current_cpu_data.icache.waysize;
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
233 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100234 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 unsigned long ws, addr;
236
237 CACHE32_UNROLL32_ALIGN2;
238 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700239 for (ws = 0; ws < ws_end; ws += ws_inc)
240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100241 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 CACHE32_UNROLL32_ALIGN;
243 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700244 for (ws = 0; ws < ws_end; ws += ws_inc)
245 for (addr = start; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100246 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247}
248
249static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
250{
251 unsigned long flags;
252
253 local_irq_save(flags);
254 blast_icache32_page_indexed(page);
255 local_irq_restore(flags);
256}
257
258static inline void tx49_blast_icache32_page_indexed(unsigned long page)
259{
Atsushi Nemoto67a3f6de2006-04-04 17:34:14 +0900260 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
261 unsigned long start = INDEX_BASE + (page & indexmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 unsigned long end = start + PAGE_SIZE;
263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
264 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100265 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 unsigned long ws, addr;
267
268 CACHE32_UNROLL32_ALIGN2;
269 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700270 for (ws = 0; ws < ws_end; ws += ws_inc)
271 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100272 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 CACHE32_UNROLL32_ALIGN;
274 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700275 for (ws = 0; ws < ws_end; ws += ws_inc)
276 for (addr = start; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100277 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278}
279
280static void (* r4k_blast_icache_page)(unsigned long addr);
281
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000282static void r4k_blast_icache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283{
284 unsigned long ic_lsize = cpu_icache_line_size();
285
Chris Dearman73f40352006-06-20 18:06:52 +0100286 if (ic_lsize == 0)
287 r4k_blast_icache_page = (void *)cache_noop;
288 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 r4k_blast_icache_page = blast_icache16_page;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800290 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
291 r4k_blast_icache_page = loongson2_blast_icache32_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 else if (ic_lsize == 32)
293 r4k_blast_icache_page = blast_icache32_page;
294 else if (ic_lsize == 64)
295 r4k_blast_icache_page = blast_icache64_page;
David Daney18a8cd62014-05-28 23:52:09 +0200296 else if (ic_lsize == 128)
297 r4k_blast_icache_page = blast_icache128_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298}
299
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000300#ifndef CONFIG_EVA
301#define r4k_blast_icache_user_page r4k_blast_icache_page
302#else
303
304static void (*r4k_blast_icache_user_page)(unsigned long addr);
305
Paul Gortmaker9a8f4ea2015-04-27 18:47:57 -0400306static void r4k_blast_icache_user_page_setup(void)
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000307{
308 unsigned long ic_lsize = cpu_icache_line_size();
309
310 if (ic_lsize == 0)
311 r4k_blast_icache_user_page = (void *)cache_noop;
312 else if (ic_lsize == 16)
313 r4k_blast_icache_user_page = blast_icache16_user_page;
314 else if (ic_lsize == 32)
315 r4k_blast_icache_user_page = blast_icache32_user_page;
316 else if (ic_lsize == 64)
317 r4k_blast_icache_user_page = blast_icache64_user_page;
318}
319
320#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
322static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
323
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000324static void r4k_blast_icache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325{
326 unsigned long ic_lsize = cpu_icache_line_size();
327
Chris Dearman73f40352006-06-20 18:06:52 +0100328 if (ic_lsize == 0)
329 r4k_blast_icache_page_indexed = (void *)cache_noop;
330 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
332 else if (ic_lsize == 32) {
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000333 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 r4k_blast_icache_page_indexed =
335 blast_icache32_r4600_v1_page_indexed;
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000336 else if (TX49XX_ICACHE_INDEX_INV_WAR)
337 r4k_blast_icache_page_indexed =
338 tx49_blast_icache32_page_indexed;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800339 else if (current_cpu_type() == CPU_LOONGSON2)
340 r4k_blast_icache_page_indexed =
341 loongson2_blast_icache32_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 else
343 r4k_blast_icache_page_indexed =
344 blast_icache32_page_indexed;
345 } else if (ic_lsize == 64)
346 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
347}
348
Sanjay Lalf2e36562012-11-21 18:34:10 -0800349void (* r4k_blast_icache)(void);
350EXPORT_SYMBOL(r4k_blast_icache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000352static void r4k_blast_icache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353{
354 unsigned long ic_lsize = cpu_icache_line_size();
355
Chris Dearman73f40352006-06-20 18:06:52 +0100356 if (ic_lsize == 0)
357 r4k_blast_icache = (void *)cache_noop;
358 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 r4k_blast_icache = blast_icache16;
360 else if (ic_lsize == 32) {
361 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
362 r4k_blast_icache = blast_r4600_v1_icache32;
363 else if (TX49XX_ICACHE_INDEX_INV_WAR)
364 r4k_blast_icache = tx49_blast_icache32;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800365 else if (current_cpu_type() == CPU_LOONGSON2)
366 r4k_blast_icache = loongson2_blast_icache32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 else
368 r4k_blast_icache = blast_icache32;
369 } else if (ic_lsize == 64)
370 r4k_blast_icache = blast_icache64;
David Daney18a8cd62014-05-28 23:52:09 +0200371 else if (ic_lsize == 128)
372 r4k_blast_icache = blast_icache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373}
374
375static void (* r4k_blast_scache_page)(unsigned long addr);
376
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000377static void r4k_blast_scache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378{
379 unsigned long sc_lsize = cpu_scache_line_size();
380
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000381 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100382 r4k_blast_scache_page = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000383 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 r4k_blast_scache_page = blast_scache16_page;
385 else if (sc_lsize == 32)
386 r4k_blast_scache_page = blast_scache32_page;
387 else if (sc_lsize == 64)
388 r4k_blast_scache_page = blast_scache64_page;
389 else if (sc_lsize == 128)
390 r4k_blast_scache_page = blast_scache128_page;
391}
392
393static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
394
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000395static void r4k_blast_scache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396{
397 unsigned long sc_lsize = cpu_scache_line_size();
398
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000399 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100400 r4k_blast_scache_page_indexed = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000401 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
403 else if (sc_lsize == 32)
404 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
405 else if (sc_lsize == 64)
406 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
407 else if (sc_lsize == 128)
408 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
409}
410
411static void (* r4k_blast_scache)(void);
412
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000413static void r4k_blast_scache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414{
415 unsigned long sc_lsize = cpu_scache_line_size();
416
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000417 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100418 r4k_blast_scache = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000419 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 r4k_blast_scache = blast_scache16;
421 else if (sc_lsize == 32)
422 r4k_blast_scache = blast_scache32;
423 else if (sc_lsize == 64)
424 r4k_blast_scache = blast_scache64;
425 else if (sc_lsize == 128)
426 r4k_blast_scache = blast_scache128;
427}
428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429static inline void local_r4k___flush_cache_all(void * args)
430{
Ralf Baechle10cc3522007-10-11 23:46:15 +0100431 switch (current_cpu_type()) {
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200432 case CPU_LOONGSON2:
Huacai Chenc579d312014-03-21 18:44:00 +0800433 case CPU_LOONGSON3:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434 case CPU_R4000SC:
435 case CPU_R4000MC:
436 case CPU_R4400SC:
437 case CPU_R4400MC:
438 case CPU_R10000:
439 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400440 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -0500441 case CPU_R16000:
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200442 /*
443 * These caches are inclusive caches, that is, if something
444 * is not cached in the S-cache, we know it also won't be
445 * in one of the primary caches.
446 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 r4k_blast_scache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200448 break;
449
450 default:
451 r4k_blast_dcache();
452 r4k_blast_icache();
453 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 }
455}
456
457static void r4k___flush_cache_all(void)
458{
Ralf Baechle48a26e62010-10-29 19:08:25 +0100459 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460}
461
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100462static inline int has_valid_asid(const struct mm_struct *mm)
463{
Ralf Baechleb6336482014-05-23 16:29:44 +0200464#ifdef CONFIG_MIPS_MT_SMP
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100465 int i;
466
467 for_each_online_cpu(i)
468 if (cpu_context(i, mm))
469 return 1;
470
471 return 0;
472#else
473 return cpu_context(smp_processor_id(), mm);
474#endif
475}
476
Ralf Baechle9c5a3d72008-04-05 15:13:23 +0100477static void r4k__flush_cache_vmap(void)
478{
479 r4k_blast_dcache();
480}
481
482static void r4k__flush_cache_vunmap(void)
483{
484 r4k_blast_dcache();
485}
486
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487static inline void local_r4k_flush_cache_range(void * args)
488{
489 struct vm_area_struct *vma = args;
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000490 int exec = vma->vm_flags & VM_EXEC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100492 if (!(has_valid_asid(vma->vm_mm)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 return;
494
James Hoganb2a3c5b2016-01-22 10:58:25 +0000495 /*
496 * If dcache can alias, we must blast it since mapping is changing.
497 * If executable, we must ensure any dirty lines are written back far
498 * enough to be visible to icache.
499 */
500 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
501 r4k_blast_dcache();
502 /* If executable, blast stale lines from icache */
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000503 if (exec)
504 r4k_blast_icache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505}
506
507static void r4k_flush_cache_range(struct vm_area_struct *vma,
508 unsigned long start, unsigned long end)
509{
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000510 int exec = vma->vm_flags & VM_EXEC;
Atsushi Nemoto0550d9d2006-08-22 21:15:47 +0900511
James Hoganb2a3c5b2016-01-22 10:58:25 +0000512 if (cpu_has_dc_aliases || exec)
Ralf Baechle48a26e62010-10-29 19:08:25 +0100513 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514}
515
516static inline void local_r4k_flush_cache_mm(void * args)
517{
518 struct mm_struct *mm = args;
519
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100520 if (!has_valid_asid(mm))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 return;
522
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 /*
524 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
Joshua Kinard30577392015-01-21 07:59:45 -0500525 * only flush the primary caches but R1x000 behave sane ...
Ralf Baechle617667b2006-11-30 01:14:48 +0000526 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
527 * caches, so we can bail out early.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 */
Ralf Baechle10cc3522007-10-11 23:46:15 +0100529 if (current_cpu_type() == CPU_R4000SC ||
530 current_cpu_type() == CPU_R4000MC ||
531 current_cpu_type() == CPU_R4400SC ||
532 current_cpu_type() == CPU_R4400MC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 r4k_blast_scache();
Ralf Baechle617667b2006-11-30 01:14:48 +0000534 return;
535 }
536
537 r4k_blast_dcache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538}
539
540static void r4k_flush_cache_mm(struct mm_struct *mm)
541{
542 if (!cpu_has_dc_aliases)
543 return;
544
Ralf Baechle48a26e62010-10-29 19:08:25 +0100545 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546}
547
548struct flush_cache_page_args {
549 struct vm_area_struct *vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100550 unsigned long addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900551 unsigned long pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552};
553
554static inline void local_r4k_flush_cache_page(void *args)
555{
556 struct flush_cache_page_args *fcp_args = args;
557 struct vm_area_struct *vma = fcp_args->vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100558 unsigned long addr = fcp_args->addr;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100559 struct page *page = pfn_to_page(fcp_args->pfn);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 int exec = vma->vm_flags & VM_EXEC;
561 struct mm_struct *mm = vma->vm_mm;
Ralf Baechlec9c50232008-06-14 22:22:08 +0100562 int map_coherent = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 pgd_t *pgdp;
Ralf Baechlec6e8b582005-02-10 12:19:59 +0000564 pud_t *pudp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 pmd_t *pmdp;
566 pte_t *ptep;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100567 void *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
Ralf Baechle79acf832005-02-10 13:54:37 +0000569 /*
570 * If ownes no valid ASID yet, cannot possibly have gotten
571 * this page into the cache.
572 */
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100573 if (!has_valid_asid(mm))
Ralf Baechle79acf832005-02-10 13:54:37 +0000574 return;
575
Ralf Baechle6ec25802005-10-12 00:02:34 +0100576 addr &= PAGE_MASK;
577 pgdp = pgd_offset(mm, addr);
578 pudp = pud_offset(pgdp, addr);
579 pmdp = pmd_offset(pudp, addr);
580 ptep = pte_offset(pmdp, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581
582 /*
583 * If the page isn't marked valid, the page cannot possibly be
584 * in the cache.
585 */
Ralf Baechle526af352008-01-29 10:14:55 +0000586 if (!(pte_present(*ptep)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 return;
588
Ralf Baechledb813fe2007-09-27 18:26:43 +0100589 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
590 vaddr = NULL;
591 else {
592 /*
593 * Use kmap_coherent or kmap_atomic to do flushes for
594 * another ASID than the current one.
595 */
Ralf Baechlec9c50232008-06-14 22:22:08 +0100596 map_coherent = (cpu_has_dc_aliases &&
Kirill A. Shutemove1534ae2016-01-15 16:53:46 -0800597 page_mapcount(page) &&
598 !Page_dcache_dirty(page));
Ralf Baechlec9c50232008-06-14 22:22:08 +0100599 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100600 vaddr = kmap_coherent(page, addr);
601 else
Cong Wang9c020482011-11-25 23:14:15 +0800602 vaddr = kmap_atomic(page);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100603 addr = (unsigned long)vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 }
605
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
Markos Chandras80ca69f2014-01-16 13:11:08 +0000607 vaddr ? r4k_blast_dcache_page(addr) :
608 r4k_blast_dcache_user_page(addr);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100609 if (exec && !cpu_icache_snoops_remote_store)
610 r4k_blast_scache_page(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 }
612 if (exec) {
Ralf Baechledb813fe2007-09-27 18:26:43 +0100613 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 int cpu = smp_processor_id();
615
Thiemo Seufer26a51b22005-02-19 13:32:02 +0000616 if (cpu_context(cpu, mm) != 0)
617 drop_mmu_context(mm, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618 } else
Markos Chandras80ca69f2014-01-16 13:11:08 +0000619 vaddr ? r4k_blast_icache_page(addr) :
620 r4k_blast_icache_user_page(addr);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100621 }
622
623 if (vaddr) {
Ralf Baechlec9c50232008-06-14 22:22:08 +0100624 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100625 kunmap_coherent();
626 else
Cong Wang9c020482011-11-25 23:14:15 +0800627 kunmap_atomic(vaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 }
629}
630
Ralf Baechle6ec25802005-10-12 00:02:34 +0100631static void r4k_flush_cache_page(struct vm_area_struct *vma,
632 unsigned long addr, unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633{
634 struct flush_cache_page_args args;
635
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 args.vma = vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100637 args.addr = addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900638 args.pfn = pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
Ralf Baechle48a26e62010-10-29 19:08:25 +0100640 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641}
642
643static inline void local_r4k_flush_data_cache_page(void * addr)
644{
645 r4k_blast_dcache_page((unsigned long) addr);
646}
647
648static void r4k_flush_data_cache_page(unsigned long addr)
649{
Ralf Baechlea754f702007-11-03 01:01:37 +0000650 if (in_atomic())
651 local_r4k_flush_data_cache_page((void *)addr);
652 else
Ralf Baechle48a26e62010-10-29 19:08:25 +0100653 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654}
655
656struct flush_icache_range_args {
Atsushi Nemotod4264f12006-01-29 02:27:51 +0900657 unsigned long start;
658 unsigned long end;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659};
660
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200661static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 if (!cpu_has_ic_fills_f_dc) {
Chris Dearman73f40352006-06-20 18:06:52 +0100664 if (end - start >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 r4k_blast_dcache();
666 } else {
Thiemo Seufer10a3dab2005-09-09 20:26:54 +0000667 R4600_HIT_CACHEOP_WAR_IMPL;
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900668 protected_blast_dcache_range(start, end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 }
671
672 if (end - start > icache_size)
673 r4k_blast_icache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200674 else {
675 switch (boot_cpu_type()) {
676 case CPU_LOONGSON2:
Huacai Chenbad009f2014-01-14 17:56:37 -0800677 protected_loongson2_blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200678 break;
679
680 default:
Huacai Chenbad009f2014-01-14 17:56:37 -0800681 protected_blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200682 break;
683 }
684 }
Leonid Yegoshin4676f932014-01-21 09:48:48 +0000685#ifdef CONFIG_EVA
686 /*
687 * Due to all possible segment mappings, there might cache aliases
688 * caused by the bootloader being in non-EVA mode, and the CPU switching
689 * to EVA during early kernel init. It's best to flush the scache
690 * to avoid having secondary cores fetching stale data and lead to
691 * kernel crashes.
692 */
693 bc_wback_inv(start, (end - start));
694 __sync();
695#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696}
697
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200698static inline void local_r4k_flush_icache_range_ipi(void *args)
699{
700 struct flush_icache_range_args *fir_args = args;
701 unsigned long start = fir_args->start;
702 unsigned long end = fir_args->end;
703
704 local_r4k_flush_icache_range(start, end);
705}
706
Atsushi Nemotod4264f12006-01-29 02:27:51 +0900707static void r4k_flush_icache_range(unsigned long start, unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708{
709 struct flush_icache_range_args args;
710
711 args.start = start;
712 args.end = end;
713
Ralf Baechle48a26e62010-10-29 19:08:25 +0100714 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
Ralf Baechlecc61c1f2005-07-12 18:35:38 +0000715 instruction_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716}
717
Manuel Lauss80057112014-02-20 14:59:22 +0100718#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
720static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
721{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 /* Catch bad driver code */
723 BUG_ON(size == 0);
724
Ralf Baechleff522052013-09-17 12:44:31 +0200725 preempt_disable();
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100726 if (cpu_has_inclusive_pcaches) {
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900727 if (size >= scache_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 r4k_blast_scache();
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900729 else
730 blast_scache_range(addr, addr + size);
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900731 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700732 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 return;
734 }
735
736 /*
737 * Either no secondary cache or the available caches don't have the
738 * subset property so we have to flush the primary caches
739 * explicitly
740 */
Ralf Baechle39b8d522008-04-28 17:14:26 +0100741 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742 r4k_blast_dcache();
743 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 R4600_HIT_CACHEOP_WAR_IMPL;
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900745 blast_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 }
Ralf Baechleff522052013-09-17 12:44:31 +0200747 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748
749 bc_wback_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700750 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751}
752
753static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
754{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 /* Catch bad driver code */
756 BUG_ON(size == 0);
757
Ralf Baechleff522052013-09-17 12:44:31 +0200758 preempt_disable();
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100759 if (cpu_has_inclusive_pcaches) {
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900760 if (size >= scache_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 r4k_blast_scache();
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000762 else {
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000763 /*
764 * There is no clearly documented alignment requirement
765 * for the cache instruction on MIPS processors and
766 * some processors, among them the RM5200 and RM7000
767 * QED processors will throw an address error for cache
Ralf Baechle70342282013-01-22 12:59:30 +0100768 * hit ops with insufficient alignment. Solved by
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000769 * aligning the address to cache line size.
770 */
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100771 blast_inv_scache_range(addr, addr + size);
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000772 }
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900773 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700774 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 return;
776 }
777
Ralf Baechle39b8d522008-04-28 17:14:26 +0100778 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 r4k_blast_dcache();
780 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 R4600_HIT_CACHEOP_WAR_IMPL;
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100782 blast_inv_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 }
Ralf Baechleff522052013-09-17 12:44:31 +0200784 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
786 bc_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700787 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788}
Manuel Lauss80057112014-02-20 14:59:22 +0100789#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790
791/*
792 * While we're protected against bad userland addresses we don't care
793 * very much about what happens in that case. Usually a segmentation
794 * fault will dump the process later on anyway ...
795 */
796static void local_r4k_flush_cache_sigtramp(void * arg)
797{
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000798 unsigned long ic_lsize = cpu_icache_line_size();
799 unsigned long dc_lsize = cpu_dcache_line_size();
800 unsigned long sc_lsize = cpu_scache_line_size();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 unsigned long addr = (unsigned long) arg;
802
803 R4600_HIT_CACHEOP_WAR_IMPL;
Chris Dearman73f40352006-06-20 18:06:52 +0100804 if (dc_lsize)
805 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000806 if (!cpu_icache_snoops_remote_store && scache_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
Chris Dearman73f40352006-06-20 18:06:52 +0100808 if (ic_lsize)
809 protected_flush_icache_line(addr & ~(ic_lsize - 1));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 if (MIPS4K_ICACHE_REFILL_WAR) {
811 __asm__ __volatile__ (
812 ".set push\n\t"
813 ".set noat\n\t"
Markos Chandras4ee48622014-12-02 15:30:19 +0000814 ".set "MIPS_ISA_LEVEL"\n\t"
Ralf Baechle875d43e2005-09-03 15:56:16 -0700815#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 "la $at,1f\n\t"
817#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700818#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 "dla $at,1f\n\t"
820#endif
821 "cache %0,($at)\n\t"
822 "nop; nop; nop\n"
823 "1:\n\t"
824 ".set pop"
825 :
826 : "i" (Hit_Invalidate_I));
827 }
828 if (MIPS_CACHE_SYNC_WAR)
829 __asm__ __volatile__ ("sync");
830}
831
832static void r4k_flush_cache_sigtramp(unsigned long addr)
833{
Ralf Baechle48a26e62010-10-29 19:08:25 +0100834 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835}
836
837static void r4k_flush_icache_all(void)
838{
839 if (cpu_has_vtag_icache)
840 r4k_blast_icache();
841}
842
Ralf Baechled9cdc9012011-06-17 16:20:28 +0100843struct flush_kernel_vmap_range_args {
844 unsigned long vaddr;
845 int size;
846};
847
848static inline void local_r4k_flush_kernel_vmap_range(void *args)
849{
850 struct flush_kernel_vmap_range_args *vmra = args;
851 unsigned long vaddr = vmra->vaddr;
852 int size = vmra->size;
853
854 /*
855 * Aliases only affect the primary caches so don't bother with
856 * S-caches or T-caches.
857 */
858 if (cpu_has_safe_index_cacheops && size >= dcache_size)
859 r4k_blast_dcache();
860 else {
861 R4600_HIT_CACHEOP_WAR_IMPL;
862 blast_dcache_range(vaddr, vaddr + size);
863 }
864}
865
866static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
867{
868 struct flush_kernel_vmap_range_args args;
869
870 args.vaddr = (unsigned long) vaddr;
871 args.size = size;
872
873 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
874}
875
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876static inline void rm7k_erratum31(void)
877{
878 const unsigned long ic_lsize = 32;
879 unsigned long addr;
880
881 /* RM7000 erratum #31. The icache is screwed at startup. */
882 write_c0_taglo(0);
883 write_c0_taghi(0);
884
885 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
886 __asm__ __volatile__ (
Thiemo Seuferd8748a32005-09-02 09:56:12 +0000887 ".set push\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888 ".set noreorder\n\t"
889 ".set mips3\n\t"
890 "cache\t%1, 0(%0)\n\t"
891 "cache\t%1, 0x1000(%0)\n\t"
892 "cache\t%1, 0x2000(%0)\n\t"
893 "cache\t%1, 0x3000(%0)\n\t"
894 "cache\t%2, 0(%0)\n\t"
895 "cache\t%2, 0x1000(%0)\n\t"
896 "cache\t%2, 0x2000(%0)\n\t"
897 "cache\t%2, 0x3000(%0)\n\t"
898 "cache\t%1, 0(%0)\n\t"
899 "cache\t%1, 0x1000(%0)\n\t"
900 "cache\t%1, 0x2000(%0)\n\t"
901 "cache\t%1, 0x3000(%0)\n\t"
Thiemo Seuferd8748a32005-09-02 09:56:12 +0000902 ".set pop\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 :
904 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
905 }
906}
907
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000908static inline int alias_74k_erratum(struct cpuinfo_mips *c)
Steven J. Hill006a8512012-06-26 04:11:03 +0000909{
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +0100910 unsigned int imp = c->processor_id & PRID_IMP_MASK;
911 unsigned int rev = c->processor_id & PRID_REV_MASK;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000912 int present = 0;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +0100913
Steven J. Hill006a8512012-06-26 04:11:03 +0000914 /*
915 * Early versions of the 74K do not update the cache tags on a
916 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000917 * aliases. In this case it is better to treat the cache as always
918 * having aliases. Also disable the synonym tag update feature
919 * where available. In this case no opportunistic tag update will
920 * happen where a load causes a virtual address miss but a physical
921 * address hit during a D-cache look-up.
Steven J. Hill006a8512012-06-26 04:11:03 +0000922 */
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +0100923 switch (imp) {
924 case PRID_IMP_74K:
925 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000926 present = 1;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +0100927 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
928 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
929 break;
930 case PRID_IMP_1074K:
931 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000932 present = 1;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +0100933 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
934 }
935 break;
936 default:
937 BUG();
Steven J. Hill006a8512012-06-26 04:11:03 +0000938 }
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000939
940 return present;
Steven J. Hill006a8512012-06-26 04:11:03 +0000941}
942
Kevin Cernekeed74b0172014-10-20 21:28:00 -0700943static void b5k_instruction_hazard(void)
944{
945 __sync();
946 __sync();
947 __asm__ __volatile__(
948 " nop; nop; nop; nop; nop; nop; nop; nop\n"
949 " nop; nop; nop; nop; nop; nop; nop; nop\n"
950 " nop; nop; nop; nop; nop; nop; nop; nop\n"
951 " nop; nop; nop; nop; nop; nop; nop; nop\n"
952 : : : "memory");
953}
954
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000955static char *way_string[] = { NULL, "direct mapped", "2-way",
Paul Burton1e18ac72015-07-09 10:40:41 +0100956 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
957 "9-way", "10-way", "11-way", "12-way",
958 "13-way", "14-way", "15-way", "16-way",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959};
960
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000961static void probe_pcache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962{
963 struct cpuinfo_mips *c = &current_cpu_data;
964 unsigned int config = read_c0_config();
965 unsigned int prid = read_c0_prid();
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +0000966 int has_74k_erratum = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967 unsigned long config1;
968 unsigned int lsize;
969
Ralf Baechle69f24d12013-09-17 10:25:47 +0200970 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971 case CPU_R4600: /* QED style two way caches? */
972 case CPU_R4700:
973 case CPU_R5000:
974 case CPU_NEVADA:
975 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
976 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
977 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +0900978 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979
980 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
981 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
982 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +0900983 c->dcache.waybit= __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984
985 c->options |= MIPS_CPU_CACHE_CDEX_P;
986 break;
987
988 case CPU_R5432:
989 case CPU_R5500:
990 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
991 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
992 c->icache.ways = 2;
993 c->icache.waybit= 0;
994
995 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
996 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
997 c->dcache.ways = 2;
998 c->dcache.waybit = 0;
999
Shinya Kuribayashi58648102009-03-18 09:04:01 +09001000 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 break;
1002
1003 case CPU_TX49XX:
1004 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1005 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1006 c->icache.ways = 4;
1007 c->icache.waybit= 0;
1008
1009 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1010 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1011 c->dcache.ways = 4;
1012 c->dcache.waybit = 0;
1013
1014 c->options |= MIPS_CPU_CACHE_CDEX_P;
Atsushi Nemotode862b42006-03-17 12:59:22 +09001015 c->options |= MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 break;
1017
1018 case CPU_R4000PC:
1019 case CPU_R4000SC:
1020 case CPU_R4000MC:
1021 case CPU_R4400PC:
1022 case CPU_R4400SC:
1023 case CPU_R4400MC:
1024 case CPU_R4300:
1025 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1026 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1027 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001028 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029
1030 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1031 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1032 c->dcache.ways = 1;
1033 c->dcache.waybit = 0; /* does not matter */
1034
1035 c->options |= MIPS_CPU_CACHE_CDEX_P;
1036 break;
1037
1038 case CPU_R10000:
1039 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001040 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001041 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1043 c->icache.linesz = 64;
1044 c->icache.ways = 2;
1045 c->icache.waybit = 0;
1046
1047 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1048 c->dcache.linesz = 32;
1049 c->dcache.ways = 2;
1050 c->dcache.waybit = 0;
1051
1052 c->options |= MIPS_CPU_PREFETCH;
1053 break;
1054
1055 case CPU_VR4133:
Yoichi Yuasa2874fe52006-07-08 00:42:12 +09001056 write_c0_config(config & ~VR41_CONF_P4K);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 case CPU_VR4131:
1058 /* Workaround for cache instruction bug of VR4131 */
1059 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1060 c->processor_id == 0x0c82U) {
Yoichi Yuasa4e8ab362006-07-04 22:59:41 +09001061 config |= 0x00400000U;
1062 if (c->processor_id == 0x0c80U)
1063 config |= VR41_CONF_BP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 write_c0_config(config);
Yoichi Yuasa1058ecd2006-07-08 00:42:01 +09001065 } else
1066 c->options |= MIPS_CPU_CACHE_CDEX_P;
1067
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1069 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1070 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001071 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
1073 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1074 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1075 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001076 c->dcache.waybit = __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 break;
1078
1079 case CPU_VR41XX:
1080 case CPU_VR4111:
1081 case CPU_VR4121:
1082 case CPU_VR4122:
1083 case CPU_VR4181:
1084 case CPU_VR4181A:
1085 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1086 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1087 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001088 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
1090 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1091 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1092 c->dcache.ways = 1;
1093 c->dcache.waybit = 0; /* does not matter */
1094
1095 c->options |= MIPS_CPU_CACHE_CDEX_P;
1096 break;
1097
1098 case CPU_RM7000:
1099 rm7k_erratum31();
1100
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1102 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1103 c->icache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001104 c->icache.waybit = __ffs(icache_size / c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105
1106 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1107 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1108 c->dcache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001109 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 c->options |= MIPS_CPU_CACHE_CDEX_P;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112 c->options |= MIPS_CPU_PREFETCH;
1113 break;
1114
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001115 case CPU_LOONGSON2:
1116 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1117 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1118 if (prid & 0x3)
1119 c->icache.ways = 4;
1120 else
1121 c->icache.ways = 2;
1122 c->icache.waybit = 0;
1123
1124 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1125 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1126 if (prid & 0x3)
1127 c->dcache.ways = 4;
1128 else
1129 c->dcache.ways = 2;
1130 c->dcache.waybit = 0;
1131 break;
1132
Huacai Chenc579d312014-03-21 18:44:00 +08001133 case CPU_LOONGSON3:
1134 config1 = read_c0_config1();
1135 lsize = (config1 >> 19) & 7;
1136 if (lsize)
1137 c->icache.linesz = 2 << lsize;
1138 else
1139 c->icache.linesz = 0;
1140 c->icache.sets = 64 << ((config1 >> 22) & 7);
1141 c->icache.ways = 1 + ((config1 >> 16) & 7);
1142 icache_size = c->icache.sets *
1143 c->icache.ways *
1144 c->icache.linesz;
1145 c->icache.waybit = 0;
1146
1147 lsize = (config1 >> 10) & 7;
1148 if (lsize)
1149 c->dcache.linesz = 2 << lsize;
1150 else
1151 c->dcache.linesz = 0;
1152 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1153 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1154 dcache_size = c->dcache.sets *
1155 c->dcache.ways *
1156 c->dcache.linesz;
1157 c->dcache.waybit = 0;
1158 break;
1159
David Daney18a8cd62014-05-28 23:52:09 +02001160 case CPU_CAVIUM_OCTEON3:
1161 /* For now lie about the number of ways. */
1162 c->icache.linesz = 128;
1163 c->icache.sets = 16;
1164 c->icache.ways = 8;
1165 c->icache.flags |= MIPS_CACHE_VTAG;
1166 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1167
1168 c->dcache.linesz = 128;
1169 c->dcache.ways = 8;
1170 c->dcache.sets = 8;
1171 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1172 c->options |= MIPS_CPU_PREFETCH;
1173 break;
1174
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175 default:
1176 if (!(config & MIPS_CONF_M))
1177 panic("Don't know how to probe P-caches on this cpu.");
1178
1179 /*
1180 * So we seem to be a MIPS32 or MIPS64 CPU
1181 * So let's probe the I-cache ...
1182 */
1183 config1 = read_c0_config1();
1184
Markos Chandras175cba82013-09-19 18:18:41 +01001185 lsize = (config1 >> 19) & 7;
1186
1187 /* IL == 7 is reserved */
1188 if (lsize == 7)
1189 panic("Invalid icache line size");
1190
1191 c->icache.linesz = lsize ? 2 << lsize : 0;
1192
Douglas Leungdc34b052012-07-19 09:11:13 +02001193 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 c->icache.ways = 1 + ((config1 >> 16) & 7);
1195
1196 icache_size = c->icache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001197 c->icache.ways *
1198 c->icache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001199 c->icache.waybit = __ffs(icache_size/c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200
1201 if (config & 0x8) /* VI bit */
1202 c->icache.flags |= MIPS_CACHE_VTAG;
1203
1204 /*
1205 * Now probe the MIPS32 / MIPS64 data cache.
1206 */
1207 c->dcache.flags = 0;
1208
Markos Chandras175cba82013-09-19 18:18:41 +01001209 lsize = (config1 >> 10) & 7;
1210
1211 /* DL == 7 is reserved */
1212 if (lsize == 7)
1213 panic("Invalid dcache line size");
1214
1215 c->dcache.linesz = lsize ? 2 << lsize : 0;
1216
Douglas Leungdc34b052012-07-19 09:11:13 +02001217 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1219
1220 dcache_size = c->dcache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001221 c->dcache.ways *
1222 c->dcache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001223 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224
1225 c->options |= MIPS_CPU_PREFETCH;
1226 break;
1227 }
1228
1229 /*
1230 * Processor configuration sanity check for the R4000SC erratum
Ralf Baechle70342282013-01-22 12:59:30 +01001231 * #5. With page sizes larger than 32kB there is no possibility
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232 * to get a VCE exception anymore so we don't care about this
1233 * misconfiguration. The case is rather theoretical anyway;
1234 * presumably no vendor is shipping his hardware in the "bad"
1235 * configuration.
1236 */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001237 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1238 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 !(config & CONF_SC) && c->icache.linesz != 16 &&
1240 PAGE_SIZE <= 0x8000)
1241 panic("Improper R4000SC processor configuration detected");
1242
1243 /* compute a couple of other cache variables */
1244 c->icache.waysize = icache_size / c->icache.ways;
1245 c->dcache.waysize = dcache_size / c->dcache.ways;
1246
Chris Dearman73f40352006-06-20 18:06:52 +01001247 c->icache.sets = c->icache.linesz ?
1248 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1249 c->dcache.sets = c->dcache.linesz ?
1250 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251
1252 /*
Joshua Kinard30577392015-01-21 07:59:45 -05001253 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1254 * virtually indexed so normally would suffer from aliases. So
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 * normally they'd suffer from aliases but magic in the hardware deals
1256 * with that for us so we don't need to take care ourselves.
1257 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001258 switch (current_cpu_type()) {
Ralf Baechlea95970f2005-02-07 21:41:32 +00001259 case CPU_20KC:
Ralf Baechle505403b2005-02-07 21:53:39 +00001260 case CPU_25KF:
Ralf Baechle641e97f2007-10-11 23:46:05 +01001261 case CPU_SB1:
1262 case CPU_SB1A:
Jayachandran Cefa0f812011-05-07 01:36:21 +05301263 case CPU_XLR:
Atsushi Nemotode628932006-03-13 18:23:03 +09001264 c->dcache.flags |= MIPS_CACHE_PINDEX;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001265 break;
1266
Ralf Baechled1e344e2005-02-04 15:51:26 +00001267 case CPU_R10000:
1268 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001269 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001270 case CPU_R16000:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001271 break;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001272
Maciej W. Rozyckibf4aac02014-06-28 23:28:08 +01001273 case CPU_74K:
1274 case CPU_1074K:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001275 has_74k_erratum = alias_74k_erratum(c);
Maciej W. Rozyckibf4aac02014-06-28 23:28:08 +01001276 /* Fall through. */
Steven J. Hill113c62d2012-07-06 23:56:00 +02001277 case CPU_M14KC:
Steven J. Hillf8fa4812012-12-07 03:51:35 +00001278 case CPU_M14KEC:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001279 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001280 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001281 case CPU_1004K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001282 case CPU_INTERAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001283 case CPU_P5600:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001284 case CPU_PROAPTIV:
Leonid Yegoshinf36c4722014-03-04 13:34:43 +00001285 case CPU_M5150:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001286 case CPU_QEMU_GENERIC:
Markos Chandras4e88a862015-07-09 10:40:36 +01001287 case CPU_I6400:
Paul Burton1091bfa2016-02-03 03:26:38 +00001288 case CPU_P6600:
Paul Burton1dbf6a82016-02-03 16:17:29 +00001289 case CPU_M6250:
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001290 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1291 (c->icache.waysize > PAGE_SIZE))
1292 c->icache.flags |= MIPS_CACHE_ALIASES;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001293 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001294 /*
1295 * Effectively physically indexed dcache,
1296 * thus no virtual aliases.
1297 */
Ralf Baechlebeab3752006-06-19 21:56:25 +01001298 c->dcache.flags |= MIPS_CACHE_PINDEX;
1299 break;
1300 }
Ralf Baechled1e344e2005-02-04 15:51:26 +00001301 default:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001302 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
Ralf Baechlebeab3752006-06-19 21:56:25 +01001303 c->dcache.flags |= MIPS_CACHE_ALIASES;
Ralf Baechled1e344e2005-02-04 15:51:26 +00001304 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305
Ralf Baechle69f24d12013-09-17 10:25:47 +02001306 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307 case CPU_20KC:
1308 /*
1309 * Some older 20Kc chips doesn't have the 'VI' bit in
1310 * the config register.
1311 */
1312 c->icache.flags |= MIPS_CACHE_VTAG;
1313 break;
1314
Manuel Lauss270717a2009-03-25 17:49:28 +01001315 case CPU_ALCHEMY:
James Hogan47f2ac52016-01-22 10:58:26 +00001316 case CPU_I6400:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1318 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319
Florian Fainellic130d2f2016-04-04 10:55:34 -07001320 case CPU_BMIPS5000:
1321 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1322 break;
1323
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001324 case CPU_LOONGSON2:
1325 /*
1326 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1327 * one op will act on all 4 ways
1328 */
1329 c->icache.ways = 1;
1330 }
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001331
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1333 icache_size >> 10,
Ralf Baechle7fc73162009-04-01 16:11:53 +02001334 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 way_string[c->icache.ways], c->icache.linesz);
1336
Ralf Baechle64bfca52007-10-15 16:35:45 +01001337 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1338 dcache_size >> 10, way_string[c->dcache.ways],
1339 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1340 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1341 "cache aliases" : "no aliases",
1342 c->dcache.linesz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343}
1344
1345/*
1346 * If you even _breathe_ on this function, look at the gcc output and make sure
1347 * it does not pop things on and off the stack for the cache sizing loop that
1348 * executes in KSEG1 space or else you will crash and burn badly. You have
1349 * been warned.
1350 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001351static int probe_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353 unsigned long flags, addr, begin, end, pow2;
1354 unsigned int config = read_c0_config();
1355 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356
1357 if (config & CONF_SC)
1358 return 0;
1359
Ralf Baechlee001e522007-07-28 12:45:47 +01001360 begin = (unsigned long) &_stext;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 begin &= ~((4 * 1024 * 1024) - 1);
1362 end = begin + (4 * 1024 * 1024);
1363
1364 /*
1365 * This is such a bitch, you'd think they would make it easy to do
1366 * this. Away you daemons of stupidity!
1367 */
1368 local_irq_save(flags);
1369
1370 /* Fill each size-multiple cache line with a valid tag. */
1371 pow2 = (64 * 1024);
1372 for (addr = begin; addr < end; addr = (begin + pow2)) {
1373 unsigned long *p = (unsigned long *) addr;
1374 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1375 pow2 <<= 1;
1376 }
1377
1378 /* Load first line with zero (therefore invalid) tag. */
1379 write_c0_taglo(0);
1380 write_c0_taghi(0);
1381 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1382 cache_op(Index_Store_Tag_I, begin);
1383 cache_op(Index_Store_Tag_D, begin);
1384 cache_op(Index_Store_Tag_SD, begin);
1385
1386 /* Now search for the wrap around point. */
1387 pow2 = (128 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1389 cache_op(Index_Load_Tag_SD, addr);
1390 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1391 if (!read_c0_taglo())
1392 break;
1393 pow2 <<= 1;
1394 }
1395 local_irq_restore(flags);
1396 addr -= begin;
1397
1398 scache_size = addr;
1399 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1400 c->scache.ways = 1;
Joshua Kinard755af332015-06-02 16:55:22 -04001401 c->scache.waybit = 0; /* does not matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402
1403 return 1;
1404}
1405
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001406static void __init loongson2_sc_init(void)
1407{
1408 struct cpuinfo_mips *c = &current_cpu_data;
1409
1410 scache_size = 512*1024;
1411 c->scache.linesz = 32;
1412 c->scache.ways = 4;
1413 c->scache.waybit = 0;
1414 c->scache.waysize = scache_size / (c->scache.ways);
1415 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1416 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1417 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1418
1419 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1420}
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001421
Huacai Chenc579d312014-03-21 18:44:00 +08001422static void __init loongson3_sc_init(void)
1423{
1424 struct cpuinfo_mips *c = &current_cpu_data;
1425 unsigned int config2, lsize;
1426
1427 config2 = read_c0_config2();
1428 lsize = (config2 >> 4) & 15;
1429 if (lsize)
1430 c->scache.linesz = 2 << lsize;
1431 else
1432 c->scache.linesz = 0;
1433 c->scache.sets = 64 << ((config2 >> 8) & 15);
1434 c->scache.ways = 1 + (config2 & 15);
1435
1436 scache_size = c->scache.sets *
1437 c->scache.ways *
1438 c->scache.linesz;
1439 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1440 scache_size *= 4;
1441 c->scache.waybit = 0;
1442 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1443 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1444 if (scache_size)
1445 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1446 return;
1447}
1448
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449extern int r5k_sc_init(void);
1450extern int rm7k_sc_init(void);
Chris Dearman9318c512006-06-20 17:15:20 +01001451extern int mips_sc_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001453static void setup_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454{
1455 struct cpuinfo_mips *c = &current_cpu_data;
1456 unsigned int config = read_c0_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 int sc_present = 0;
1458
1459 /*
1460 * Do the probing thing on R4000SC and R4400SC processors. Other
1461 * processors don't have a S-cache that would be relevant to the
Joe Perches603e82e2008-02-03 16:54:53 +02001462 * Linux memory management.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001464 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 case CPU_R4000SC:
1466 case CPU_R4000MC:
1467 case CPU_R4400SC:
1468 case CPU_R4400MC:
Thiemo Seuferba5187d2005-04-25 16:36:23 +00001469 sc_present = run_uncached(probe_scache);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 if (sc_present)
1471 c->options |= MIPS_CPU_CACHE_CDEX_S;
1472 break;
1473
1474 case CPU_R10000:
1475 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001476 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001477 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1479 c->scache.linesz = 64 << ((config >> 13) & 1);
1480 c->scache.ways = 2;
1481 c->scache.waybit= 0;
1482 sc_present = 1;
1483 break;
1484
1485 case CPU_R5000:
1486 case CPU_NEVADA:
1487#ifdef CONFIG_R5000_CPU_SCACHE
1488 r5k_sc_init();
1489#endif
Ralf Baechle70342282013-01-22 12:59:30 +01001490 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
1492 case CPU_RM7000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001493#ifdef CONFIG_RM7000_CPU_SCACHE
1494 rm7k_sc_init();
1495#endif
1496 return;
1497
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001498 case CPU_LOONGSON2:
1499 loongson2_sc_init();
1500 return;
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001501
Huacai Chenc579d312014-03-21 18:44:00 +08001502 case CPU_LOONGSON3:
1503 loongson3_sc_init();
1504 return;
1505
David Daney18a8cd62014-05-28 23:52:09 +02001506 case CPU_CAVIUM_OCTEON3:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001507 case CPU_XLP:
1508 /* don't need to worry about L2, fully coherent */
1509 return;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001510
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 default:
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00001512 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
Markos Chandrasb5ad2c22015-01-15 10:28:29 +00001513 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1514 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
Chris Dearman9318c512006-06-20 17:15:20 +01001515#ifdef CONFIG_MIPS_CPU_SCACHE
1516 if (mips_sc_init ()) {
1517 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1518 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1519 scache_size >> 10,
1520 way_string[c->scache.ways], c->scache.linesz);
1521 }
1522#else
1523 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1524 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1525#endif
1526 return;
1527 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528 sc_present = 0;
1529 }
1530
1531 if (!sc_present)
1532 return;
1533
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534 /* compute a couple of other cache variables */
1535 c->scache.waysize = scache_size / c->scache.ways;
1536
1537 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1538
1539 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1540 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1541
Ralf Baechlefc5d2d22006-07-06 13:04:01 +01001542 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543}
1544
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001545void au1x00_fixup_config_od(void)
1546{
1547 /*
1548 * c0_config.od (bit 19) was write only (and read as 0)
1549 * on the early revisions of Alchemy SOCs. It disables the bus
1550 * transaction overlapping and needs to be set to fix various errata.
1551 */
1552 switch (read_c0_prid()) {
1553 case 0x00030100: /* Au1000 DA */
1554 case 0x00030201: /* Au1000 HA */
1555 case 0x00030202: /* Au1000 HB */
1556 case 0x01030200: /* Au1500 AB */
1557 /*
1558 * Au1100 errata actually keeps silence about this bit, so we set it
1559 * just in case for those revisions that require it to be set according
Manuel Lauss270717a2009-03-25 17:49:28 +01001560 * to the (now gone) cpu table.
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001561 */
1562 case 0x02030200: /* Au1100 AB */
1563 case 0x02030201: /* Au1100 BA */
1564 case 0x02030202: /* Au1100 BC */
1565 set_c0_config(1 << 19);
1566 break;
1567 }
1568}
1569
Ralf Baechle89052bd2008-06-12 17:26:02 +01001570/* CP0 hazard avoidance. */
1571#define NXP_BARRIER() \
1572 __asm__ __volatile__( \
1573 ".set noreorder\n\t" \
1574 "nop; nop; nop; nop; nop; nop;\n\t" \
1575 ".set reorder\n\t")
1576
1577static void nxp_pr4450_fixup_config(void)
1578{
1579 unsigned long config0;
1580
1581 config0 = read_c0_config();
1582
1583 /* clear all three cache coherency fields */
1584 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1585 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1586 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1587 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1588 write_c0_config(config0);
1589 NXP_BARRIER();
1590}
1591
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001592static int cca = -1;
Chris Dearman35133692007-09-19 00:58:24 +01001593
1594static int __init cca_setup(char *str)
1595{
1596 get_option(&str, &cca);
1597
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001598 return 0;
Chris Dearman35133692007-09-19 00:58:24 +01001599}
1600
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001601early_param("cca", cca_setup);
Chris Dearman35133692007-09-19 00:58:24 +01001602
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001603static void coherency_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604{
Chris Dearman35133692007-09-19 00:58:24 +01001605 if (cca < 0 || cca > 7)
1606 cca = read_c0_config() & CONF_CM_CMASK;
1607 _page_cachable_default = cca << _CACHE_SHIFT;
1608
1609 pr_debug("Using cache attribute %d\n", cca);
1610 change_c0_config(CONF_CM_CMASK, cca);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611
1612 /*
1613 * c0_status.cu=0 specifies that updates by the sc instruction use
1614 * the coherency mode specified by the TLB; 1 means cachable
1615 * coherent update on write will be used. Not all processors have
1616 * this bit and; some wire it to zero, others like Toshiba had the
1617 * silly idea of putting something else there ...
1618 */
Ralf Baechle10cc3522007-10-11 23:46:15 +01001619 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620 case CPU_R4000PC:
1621 case CPU_R4000SC:
1622 case CPU_R4000MC:
1623 case CPU_R4400PC:
1624 case CPU_R4400SC:
1625 case CPU_R4400MC:
1626 clear_c0_config(CONF_CU);
1627 break;
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001628 /*
Ralf Baechledf586d52006-08-01 23:42:30 +01001629 * We need to catch the early Alchemy SOCs with
Manuel Lauss270717a2009-03-25 17:49:28 +01001630 * the write-only co_config.od bit and set it back to one on:
1631 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001632 */
Manuel Lauss270717a2009-03-25 17:49:28 +01001633 case CPU_ALCHEMY:
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001634 au1x00_fixup_config_od();
1635 break;
Ralf Baechle89052bd2008-06-12 17:26:02 +01001636
1637 case PRID_IMP_PR4450:
1638 nxp_pr4450_fixup_config();
1639 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640 }
1641}
1642
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001643static void r4k_cache_error_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644{
Ralf Baechle641e97f2007-10-11 23:46:05 +01001645 extern char __weak except_vec2_generic;
1646 extern char __weak except_vec2_sb1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647
Ralf Baechle69f24d12013-09-17 10:25:47 +02001648 switch (current_cpu_type()) {
Ralf Baechle641e97f2007-10-11 23:46:05 +01001649 case CPU_SB1:
1650 case CPU_SB1A:
1651 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1652 break;
1653
1654 default:
1655 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1656 break;
1657 }
David Daney9cd9669b2012-05-15 00:04:49 -07001658}
1659
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001660void r4k_cache_init(void)
David Daney9cd9669b2012-05-15 00:04:49 -07001661{
1662 extern void build_clear_page(void);
1663 extern void build_copy_page(void);
1664 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665
1666 probe_pcache();
1667 setup_scache();
1668
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 r4k_blast_dcache_page_setup();
1670 r4k_blast_dcache_page_indexed_setup();
1671 r4k_blast_dcache_setup();
1672 r4k_blast_icache_page_setup();
1673 r4k_blast_icache_page_indexed_setup();
1674 r4k_blast_icache_setup();
1675 r4k_blast_scache_page_setup();
1676 r4k_blast_scache_page_indexed_setup();
1677 r4k_blast_scache_setup();
Leonid Yegoshin4caa9062014-01-15 14:47:28 +00001678#ifdef CONFIG_EVA
1679 r4k_blast_dcache_user_page_setup();
1680 r4k_blast_icache_user_page_setup();
1681#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682
1683 /*
1684 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1685 * This code supports virtually indexed processors and will be
1686 * unnecessarily inefficient on physically indexed processors.
1687 */
Chris Dearman73f40352006-06-20 18:06:52 +01001688 if (c->dcache.linesz)
1689 shm_align_mask = max_t( unsigned long,
1690 c->dcache.sets * c->dcache.linesz - 1,
1691 PAGE_SIZE - 1);
1692 else
1693 shm_align_mask = PAGE_SIZE-1;
Ralf Baechle9c5a3d72008-04-05 15:13:23 +01001694
1695 __flush_cache_vmap = r4k__flush_cache_vmap;
1696 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1697
Ralf Baechledb813fe2007-09-27 18:26:43 +01001698 flush_cache_all = cache_noop;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001699 __flush_cache_all = r4k___flush_cache_all;
1700 flush_cache_mm = r4k_flush_cache_mm;
1701 flush_cache_page = r4k_flush_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702 flush_cache_range = r4k_flush_cache_range;
1703
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001704 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1705
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1707 flush_icache_all = r4k_flush_icache_all;
Ralf Baechle7e3bfc72006-04-05 20:42:04 +01001708 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709 flush_data_cache_page = r4k_flush_data_cache_page;
1710 flush_icache_range = r4k_flush_icache_range;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001711 local_flush_icache_range = local_r4k_flush_icache_range;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712
Manuel Lauss80057112014-02-20 14:59:22 +01001713#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
Ralf Baechle39b8d522008-04-28 17:14:26 +01001714 if (coherentio) {
1715 _dma_cache_wback_inv = (void *)cache_noop;
1716 _dma_cache_wback = (void *)cache_noop;
1717 _dma_cache_inv = (void *)cache_noop;
1718 } else {
1719 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1720 _dma_cache_wback = r4k_dma_cache_wback_inv;
1721 _dma_cache_inv = r4k_dma_cache_inv;
1722 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723#endif
1724
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725 build_clear_page();
1726 build_copy_page();
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001727
1728 /*
1729 * We want to run CMP kernels on core with and without coherent
1730 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1731 * or not to flush caches.
1732 */
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001733 local_r4k___flush_cache_all(NULL);
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001734
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001735 coherency_setup();
David Daney9cd9669b2012-05-15 00:04:49 -07001736 board_cache_error_setup = r4k_cache_error_setup;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001737
1738 /*
1739 * Per-CPU overrides
1740 */
1741 switch (current_cpu_type()) {
1742 case CPU_BMIPS4350:
1743 case CPU_BMIPS4380:
1744 /* No IPI is needed because all CPUs share the same D$ */
1745 flush_data_cache_page = r4k_blast_dcache_page;
1746 break;
1747 case CPU_BMIPS5000:
1748 /* We lose our superpowers if L2 is disabled */
1749 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1750 break;
1751
1752 /* I$ fills from D$ just by emptying the write buffers */
1753 flush_cache_page = (void *)b5k_instruction_hazard;
1754 flush_cache_range = (void *)b5k_instruction_hazard;
1755 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1756 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1757 flush_data_cache_page = (void *)b5k_instruction_hazard;
1758 flush_icache_range = (void *)b5k_instruction_hazard;
1759 local_flush_icache_range = (void *)b5k_instruction_hazard;
1760
1761 /* Cache aliases are handled in hardware; allow HIGHMEM */
1762 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
1763
1764 /* Optimization: an L2 flush implicitly flushes the L1 */
1765 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1766 break;
1767 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768}
James Hogan61d73042014-03-04 10:23:57 +00001769
1770static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1771 void *v)
1772{
1773 switch (cmd) {
1774 case CPU_PM_ENTER_FAILED:
1775 case CPU_PM_EXIT:
1776 coherency_setup();
1777 break;
1778 }
1779
1780 return NOTIFY_OK;
1781}
1782
1783static struct notifier_block r4k_cache_pm_notifier_block = {
1784 .notifier_call = r4k_cache_pm_notifier,
1785};
1786
1787int __init r4k_cache_init_pm(void)
1788{
1789 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1790}
1791arch_initcall(r4k_cache_init_pm);