Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Justin P. Mattock | 79add62 | 2011-04-04 14:15:29 -0700 | [diff] [blame] | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
| 8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
| 9 | */ |
James Hogan | 61d7304 | 2014-03-04 10:23:57 +0000 | [diff] [blame] | 10 | #include <linux/cpu_pm.h> |
Ralf Baechle | a754f70 | 2007-11-03 01:01:37 +0000 | [diff] [blame] | 11 | #include <linux/hardirq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/init.h> |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 13 | #include <linux/highmem.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/kernel.h> |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 15 | #include <linux/linkage.h> |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 16 | #include <linux/preempt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 18 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/mm.h> |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/bitops.h> |
| 22 | |
| 23 | #include <asm/bcache.h> |
| 24 | #include <asm/bootinfo.h> |
Ralf Baechle | ec74e36 | 2005-07-13 11:48:45 +0000 | [diff] [blame] | 25 | #include <asm/cache.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include <asm/cacheops.h> |
| 27 | #include <asm/cpu.h> |
| 28 | #include <asm/cpu-features.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 29 | #include <asm/cpu-type.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <asm/io.h> |
| 31 | #include <asm/page.h> |
| 32 | #include <asm/pgtable.h> |
| 33 | #include <asm/r4kcache.h> |
Ralf Baechle | e001e52 | 2007-07-28 12:45:47 +0100 | [diff] [blame] | 34 | #include <asm/sections.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/mmu_context.h> |
| 36 | #include <asm/war.h> |
Thiemo Seufer | ba5187d | 2005-04-25 16:36:23 +0000 | [diff] [blame] | 37 | #include <asm/cacheflush.h> /* for run_uncached() */ |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 38 | #include <asm/traps.h> |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 39 | #include <asm/dma-coherence.h> |
Markos Chandras | cccf34e | 2015-07-10 09:29:10 +0100 | [diff] [blame] | 40 | #include <asm/mips-cm.h> |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * Special Variant of smp_call_function for use by cache functions: |
| 44 | * |
| 45 | * o No return value |
| 46 | * o collapses to normal function call on UP kernels |
| 47 | * o collapses to normal function call on systems with a single shared |
| 48 | * primary cache. |
Ralf Baechle | c8c5f3f | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 49 | * o doesn't disable interrupts on the local CPU |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 50 | */ |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 51 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 52 | { |
| 53 | preempt_disable(); |
| 54 | |
Markos Chandras | cccf34e | 2015-07-10 09:29:10 +0100 | [diff] [blame] | 55 | /* |
| 56 | * The Coherent Manager propagates address-based cache ops to other |
| 57 | * cores but not index-based ops. However, r4k_on_each_cpu is used |
| 58 | * in both cases so there is no easy way to tell what kind of op is |
| 59 | * executed to the other cores. The best we can probably do is |
| 60 | * to restrict that call when a CM is not present because both |
| 61 | * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops. |
| 62 | */ |
| 63 | if (!mips_cm_present()) |
| 64 | smp_call_function_many(&cpu_foreign_map, func, info, 1); |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 65 | func(info); |
| 66 | preempt_enable(); |
| 67 | } |
| 68 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 69 | #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 70 | #define cpu_has_safe_index_cacheops 0 |
| 71 | #else |
| 72 | #define cpu_has_safe_index_cacheops 1 |
| 73 | #endif |
| 74 | |
Ralf Baechle | ec74e36 | 2005-07-13 11:48:45 +0000 | [diff] [blame] | 75 | /* |
| 76 | * Must die. |
| 77 | */ |
| 78 | static unsigned long icache_size __read_mostly; |
| 79 | static unsigned long dcache_size __read_mostly; |
| 80 | static unsigned long scache_size __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * Dummy cache handling routines for machines without boardcaches |
| 84 | */ |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 85 | static void cache_noop(void) {} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | static struct bcache_ops no_sc_ops = { |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 88 | .bc_enable = (void *)cache_noop, |
| 89 | .bc_disable = (void *)cache_noop, |
| 90 | .bc_wback_inv = (void *)cache_noop, |
| 91 | .bc_inv = (void *)cache_noop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | struct bcache_ops *bcops = &no_sc_ops; |
| 95 | |
Thiemo Seufer | 330cfe0 | 2005-09-01 18:33:58 +0000 | [diff] [blame] | 96 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
| 97 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | |
| 99 | #define R4600_HIT_CACHEOP_WAR_IMPL \ |
| 100 | do { \ |
| 101 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ |
| 102 | *(volatile unsigned long *)CKSEG1; \ |
| 103 | if (R4600_V1_HIT_CACHEOP_WAR) \ |
| 104 | __asm__ __volatile__("nop;nop;nop;nop"); \ |
| 105 | } while (0) |
| 106 | |
| 107 | static void (*r4k_blast_dcache_page)(unsigned long addr); |
| 108 | |
| 109 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) |
| 110 | { |
| 111 | R4600_HIT_CACHEOP_WAR_IMPL; |
| 112 | blast_dcache32_page(addr); |
| 113 | } |
| 114 | |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 115 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
| 116 | { |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 117 | blast_dcache64_page(addr); |
| 118 | } |
| 119 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 120 | static inline void r4k_blast_dcache_page_dc128(unsigned long addr) |
| 121 | { |
| 122 | blast_dcache128_page(addr); |
| 123 | } |
| 124 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 125 | static void r4k_blast_dcache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | { |
| 127 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 128 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 129 | switch (dc_lsize) { |
| 130 | case 0: |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 131 | r4k_blast_dcache_page = (void *)cache_noop; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 132 | break; |
| 133 | case 16: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | r4k_blast_dcache_page = blast_dcache16_page; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 135 | break; |
| 136 | case 32: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 138 | break; |
| 139 | case 64: |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 140 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 141 | break; |
| 142 | case 128: |
| 143 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; |
| 144 | break; |
| 145 | default: |
| 146 | break; |
| 147 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | } |
| 149 | |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 150 | #ifndef CONFIG_EVA |
| 151 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page |
| 152 | #else |
| 153 | |
| 154 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); |
| 155 | |
| 156 | static void r4k_blast_dcache_user_page_setup(void) |
| 157 | { |
| 158 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 159 | |
| 160 | if (dc_lsize == 0) |
| 161 | r4k_blast_dcache_user_page = (void *)cache_noop; |
| 162 | else if (dc_lsize == 16) |
| 163 | r4k_blast_dcache_user_page = blast_dcache16_user_page; |
| 164 | else if (dc_lsize == 32) |
| 165 | r4k_blast_dcache_user_page = blast_dcache32_user_page; |
| 166 | else if (dc_lsize == 64) |
| 167 | r4k_blast_dcache_user_page = blast_dcache64_user_page; |
| 168 | } |
| 169 | |
| 170 | #endif |
| 171 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
| 173 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 174 | static void r4k_blast_dcache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | { |
| 176 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 177 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 178 | if (dc_lsize == 0) |
| 179 | r4k_blast_dcache_page_indexed = (void *)cache_noop; |
| 180 | else if (dc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
| 182 | else if (dc_lsize == 32) |
| 183 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 184 | else if (dc_lsize == 64) |
| 185 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 186 | else if (dc_lsize == 128) |
| 187 | r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | } |
| 189 | |
Sanjay Lal | f2e3656 | 2012-11-21 18:34:10 -0800 | [diff] [blame] | 190 | void (* r4k_blast_dcache)(void); |
| 191 | EXPORT_SYMBOL(r4k_blast_dcache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 193 | static void r4k_blast_dcache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | { |
| 195 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 196 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 197 | if (dc_lsize == 0) |
| 198 | r4k_blast_dcache = (void *)cache_noop; |
| 199 | else if (dc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | r4k_blast_dcache = blast_dcache16; |
| 201 | else if (dc_lsize == 32) |
| 202 | r4k_blast_dcache = blast_dcache32; |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 203 | else if (dc_lsize == 64) |
| 204 | r4k_blast_dcache = blast_dcache64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 205 | else if (dc_lsize == 128) |
| 206 | r4k_blast_dcache = blast_dcache128; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ |
| 210 | #define JUMP_TO_ALIGN(order) \ |
| 211 | __asm__ __volatile__( \ |
| 212 | "b\t1f\n\t" \ |
| 213 | ".align\t" #order "\n\t" \ |
| 214 | "1:\n\t" \ |
| 215 | ) |
| 216 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 217 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | |
| 219 | static inline void blast_r4600_v1_icache32(void) |
| 220 | { |
| 221 | unsigned long flags; |
| 222 | |
| 223 | local_irq_save(flags); |
| 224 | blast_icache32(); |
| 225 | local_irq_restore(flags); |
| 226 | } |
| 227 | |
| 228 | static inline void tx49_blast_icache32(void) |
| 229 | { |
| 230 | unsigned long start = INDEX_BASE; |
| 231 | unsigned long end = start + current_cpu_data.icache.waysize; |
| 232 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; |
| 233 | unsigned long ws_end = current_cpu_data.icache.ways << |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 234 | current_cpu_data.icache.waybit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | unsigned long ws, addr; |
| 236 | |
| 237 | CACHE32_UNROLL32_ALIGN2; |
| 238 | /* I'm in even chunk. blast odd chunks */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 239 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 240 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 241 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | CACHE32_UNROLL32_ALIGN; |
| 243 | /* I'm in odd chunk. blast even chunks */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 244 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 245 | for (addr = start; addr < end; addr += 0x400 * 2) |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 246 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) |
| 250 | { |
| 251 | unsigned long flags; |
| 252 | |
| 253 | local_irq_save(flags); |
| 254 | blast_icache32_page_indexed(page); |
| 255 | local_irq_restore(flags); |
| 256 | } |
| 257 | |
| 258 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) |
| 259 | { |
Atsushi Nemoto | 67a3f6de | 2006-04-04 17:34:14 +0900 | [diff] [blame] | 260 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
| 261 | unsigned long start = INDEX_BASE + (page & indexmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | unsigned long end = start + PAGE_SIZE; |
| 263 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; |
| 264 | unsigned long ws_end = current_cpu_data.icache.ways << |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 265 | current_cpu_data.icache.waybit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | unsigned long ws, addr; |
| 267 | |
| 268 | CACHE32_UNROLL32_ALIGN2; |
| 269 | /* I'm in even chunk. blast odd chunks */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 270 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 271 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 272 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 273 | CACHE32_UNROLL32_ALIGN; |
| 274 | /* I'm in odd chunk. blast even chunks */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 275 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 276 | for (addr = start; addr < end; addr += 0x400 * 2) |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 277 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static void (* r4k_blast_icache_page)(unsigned long addr); |
| 281 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 282 | static void r4k_blast_icache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | { |
| 284 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 285 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 286 | if (ic_lsize == 0) |
| 287 | r4k_blast_icache_page = (void *)cache_noop; |
| 288 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | r4k_blast_icache_page = blast_icache16_page; |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 290 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
| 291 | r4k_blast_icache_page = loongson2_blast_icache32_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | else if (ic_lsize == 32) |
| 293 | r4k_blast_icache_page = blast_icache32_page; |
| 294 | else if (ic_lsize == 64) |
| 295 | r4k_blast_icache_page = blast_icache64_page; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 296 | else if (ic_lsize == 128) |
| 297 | r4k_blast_icache_page = blast_icache128_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | } |
| 299 | |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 300 | #ifndef CONFIG_EVA |
| 301 | #define r4k_blast_icache_user_page r4k_blast_icache_page |
| 302 | #else |
| 303 | |
| 304 | static void (*r4k_blast_icache_user_page)(unsigned long addr); |
| 305 | |
Paul Gortmaker | 9a8f4ea | 2015-04-27 18:47:57 -0400 | [diff] [blame] | 306 | static void r4k_blast_icache_user_page_setup(void) |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 307 | { |
| 308 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 309 | |
| 310 | if (ic_lsize == 0) |
| 311 | r4k_blast_icache_user_page = (void *)cache_noop; |
| 312 | else if (ic_lsize == 16) |
| 313 | r4k_blast_icache_user_page = blast_icache16_user_page; |
| 314 | else if (ic_lsize == 32) |
| 315 | r4k_blast_icache_user_page = blast_icache32_user_page; |
| 316 | else if (ic_lsize == 64) |
| 317 | r4k_blast_icache_user_page = blast_icache64_user_page; |
| 318 | } |
| 319 | |
| 320 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | |
| 322 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); |
| 323 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 324 | static void r4k_blast_icache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | { |
| 326 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 327 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 328 | if (ic_lsize == 0) |
| 329 | r4k_blast_icache_page_indexed = (void *)cache_noop; |
| 330 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
| 332 | else if (ic_lsize == 32) { |
Thiemo Seufer | 02fe2c9 | 2005-09-09 19:45:41 +0000 | [diff] [blame] | 333 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | r4k_blast_icache_page_indexed = |
| 335 | blast_icache32_r4600_v1_page_indexed; |
Thiemo Seufer | 02fe2c9 | 2005-09-09 19:45:41 +0000 | [diff] [blame] | 336 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
| 337 | r4k_blast_icache_page_indexed = |
| 338 | tx49_blast_icache32_page_indexed; |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 339 | else if (current_cpu_type() == CPU_LOONGSON2) |
| 340 | r4k_blast_icache_page_indexed = |
| 341 | loongson2_blast_icache32_page_indexed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | else |
| 343 | r4k_blast_icache_page_indexed = |
| 344 | blast_icache32_page_indexed; |
| 345 | } else if (ic_lsize == 64) |
| 346 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; |
| 347 | } |
| 348 | |
Sanjay Lal | f2e3656 | 2012-11-21 18:34:10 -0800 | [diff] [blame] | 349 | void (* r4k_blast_icache)(void); |
| 350 | EXPORT_SYMBOL(r4k_blast_icache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 352 | static void r4k_blast_icache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | { |
| 354 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 355 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 356 | if (ic_lsize == 0) |
| 357 | r4k_blast_icache = (void *)cache_noop; |
| 358 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | r4k_blast_icache = blast_icache16; |
| 360 | else if (ic_lsize == 32) { |
| 361 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
| 362 | r4k_blast_icache = blast_r4600_v1_icache32; |
| 363 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
| 364 | r4k_blast_icache = tx49_blast_icache32; |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 365 | else if (current_cpu_type() == CPU_LOONGSON2) |
| 366 | r4k_blast_icache = loongson2_blast_icache32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | else |
| 368 | r4k_blast_icache = blast_icache32; |
| 369 | } else if (ic_lsize == 64) |
| 370 | r4k_blast_icache = blast_icache64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 371 | else if (ic_lsize == 128) |
| 372 | r4k_blast_icache = blast_icache128; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | static void (* r4k_blast_scache_page)(unsigned long addr); |
| 376 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 377 | static void r4k_blast_scache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | { |
| 379 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 380 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 381 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 382 | r4k_blast_scache_page = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 383 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | r4k_blast_scache_page = blast_scache16_page; |
| 385 | else if (sc_lsize == 32) |
| 386 | r4k_blast_scache_page = blast_scache32_page; |
| 387 | else if (sc_lsize == 64) |
| 388 | r4k_blast_scache_page = blast_scache64_page; |
| 389 | else if (sc_lsize == 128) |
| 390 | r4k_blast_scache_page = blast_scache128_page; |
| 391 | } |
| 392 | |
| 393 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); |
| 394 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 395 | static void r4k_blast_scache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | { |
| 397 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 398 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 399 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 400 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 401 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
| 403 | else if (sc_lsize == 32) |
| 404 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; |
| 405 | else if (sc_lsize == 64) |
| 406 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; |
| 407 | else if (sc_lsize == 128) |
| 408 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; |
| 409 | } |
| 410 | |
| 411 | static void (* r4k_blast_scache)(void); |
| 412 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 413 | static void r4k_blast_scache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | { |
| 415 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 416 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 417 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 418 | r4k_blast_scache = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 419 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | r4k_blast_scache = blast_scache16; |
| 421 | else if (sc_lsize == 32) |
| 422 | r4k_blast_scache = blast_scache32; |
| 423 | else if (sc_lsize == 64) |
| 424 | r4k_blast_scache = blast_scache64; |
| 425 | else if (sc_lsize == 128) |
| 426 | r4k_blast_scache = blast_scache128; |
| 427 | } |
| 428 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | static inline void local_r4k___flush_cache_all(void * args) |
| 430 | { |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 431 | switch (current_cpu_type()) { |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 432 | case CPU_LOONGSON2: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 433 | case CPU_LOONGSON3: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | case CPU_R4000SC: |
| 435 | case CPU_R4000MC: |
| 436 | case CPU_R4400SC: |
| 437 | case CPU_R4400MC: |
| 438 | case CPU_R10000: |
| 439 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 440 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 441 | case CPU_R16000: |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 442 | /* |
| 443 | * These caches are inclusive caches, that is, if something |
| 444 | * is not cached in the S-cache, we know it also won't be |
| 445 | * in one of the primary caches. |
| 446 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | r4k_blast_scache(); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 448 | break; |
| 449 | |
| 450 | default: |
| 451 | r4k_blast_dcache(); |
| 452 | r4k_blast_icache(); |
| 453 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
| 457 | static void r4k___flush_cache_all(void) |
| 458 | { |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 459 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | } |
| 461 | |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 462 | static inline int has_valid_asid(const struct mm_struct *mm) |
| 463 | { |
Ralf Baechle | b633648 | 2014-05-23 16:29:44 +0200 | [diff] [blame] | 464 | #ifdef CONFIG_MIPS_MT_SMP |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 465 | int i; |
| 466 | |
| 467 | for_each_online_cpu(i) |
| 468 | if (cpu_context(i, mm)) |
| 469 | return 1; |
| 470 | |
| 471 | return 0; |
| 472 | #else |
| 473 | return cpu_context(smp_processor_id(), mm); |
| 474 | #endif |
| 475 | } |
| 476 | |
Ralf Baechle | 9c5a3d7 | 2008-04-05 15:13:23 +0100 | [diff] [blame] | 477 | static void r4k__flush_cache_vmap(void) |
| 478 | { |
| 479 | r4k_blast_dcache(); |
| 480 | } |
| 481 | |
| 482 | static void r4k__flush_cache_vunmap(void) |
| 483 | { |
| 484 | r4k_blast_dcache(); |
| 485 | } |
| 486 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | static inline void local_r4k_flush_cache_range(void * args) |
| 488 | { |
| 489 | struct vm_area_struct *vma = args; |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 490 | int exec = vma->vm_flags & VM_EXEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 492 | if (!(has_valid_asid(vma->vm_mm))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | return; |
| 494 | |
James Hogan | b2a3c5b | 2016-01-22 10:58:25 +0000 | [diff] [blame] | 495 | /* |
| 496 | * If dcache can alias, we must blast it since mapping is changing. |
| 497 | * If executable, we must ensure any dirty lines are written back far |
| 498 | * enough to be visible to icache. |
| 499 | */ |
| 500 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
| 501 | r4k_blast_dcache(); |
| 502 | /* If executable, blast stale lines from icache */ |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 503 | if (exec) |
| 504 | r4k_blast_icache(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | static void r4k_flush_cache_range(struct vm_area_struct *vma, |
| 508 | unsigned long start, unsigned long end) |
| 509 | { |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 510 | int exec = vma->vm_flags & VM_EXEC; |
Atsushi Nemoto | 0550d9d | 2006-08-22 21:15:47 +0900 | [diff] [blame] | 511 | |
James Hogan | b2a3c5b | 2016-01-22 10:58:25 +0000 | [diff] [blame] | 512 | if (cpu_has_dc_aliases || exec) |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 513 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | static inline void local_r4k_flush_cache_mm(void * args) |
| 517 | { |
| 518 | struct mm_struct *mm = args; |
| 519 | |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 520 | if (!has_valid_asid(mm)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | return; |
| 522 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | /* |
| 524 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 525 | * only flush the primary caches but R1x000 behave sane ... |
Ralf Baechle | 617667b | 2006-11-30 01:14:48 +0000 | [diff] [blame] | 526 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
| 527 | * caches, so we can bail out early. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | */ |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 529 | if (current_cpu_type() == CPU_R4000SC || |
| 530 | current_cpu_type() == CPU_R4000MC || |
| 531 | current_cpu_type() == CPU_R4400SC || |
| 532 | current_cpu_type() == CPU_R4400MC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | r4k_blast_scache(); |
Ralf Baechle | 617667b | 2006-11-30 01:14:48 +0000 | [diff] [blame] | 534 | return; |
| 535 | } |
| 536 | |
| 537 | r4k_blast_dcache(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | } |
| 539 | |
| 540 | static void r4k_flush_cache_mm(struct mm_struct *mm) |
| 541 | { |
| 542 | if (!cpu_has_dc_aliases) |
| 543 | return; |
| 544 | |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 545 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | struct flush_cache_page_args { |
| 549 | struct vm_area_struct *vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 550 | unsigned long addr; |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 551 | unsigned long pfn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | }; |
| 553 | |
| 554 | static inline void local_r4k_flush_cache_page(void *args) |
| 555 | { |
| 556 | struct flush_cache_page_args *fcp_args = args; |
| 557 | struct vm_area_struct *vma = fcp_args->vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 558 | unsigned long addr = fcp_args->addr; |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 559 | struct page *page = pfn_to_page(fcp_args->pfn); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | int exec = vma->vm_flags & VM_EXEC; |
| 561 | struct mm_struct *mm = vma->vm_mm; |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 562 | int map_coherent = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | pgd_t *pgdp; |
Ralf Baechle | c6e8b58 | 2005-02-10 12:19:59 +0000 | [diff] [blame] | 564 | pud_t *pudp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | pmd_t *pmdp; |
| 566 | pte_t *ptep; |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 567 | void *vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | |
Ralf Baechle | 79acf83 | 2005-02-10 13:54:37 +0000 | [diff] [blame] | 569 | /* |
| 570 | * If ownes no valid ASID yet, cannot possibly have gotten |
| 571 | * this page into the cache. |
| 572 | */ |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 573 | if (!has_valid_asid(mm)) |
Ralf Baechle | 79acf83 | 2005-02-10 13:54:37 +0000 | [diff] [blame] | 574 | return; |
| 575 | |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 576 | addr &= PAGE_MASK; |
| 577 | pgdp = pgd_offset(mm, addr); |
| 578 | pudp = pud_offset(pgdp, addr); |
| 579 | pmdp = pmd_offset(pudp, addr); |
| 580 | ptep = pte_offset(pmdp, addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | |
| 582 | /* |
| 583 | * If the page isn't marked valid, the page cannot possibly be |
| 584 | * in the cache. |
| 585 | */ |
Ralf Baechle | 526af35 | 2008-01-29 10:14:55 +0000 | [diff] [blame] | 586 | if (!(pte_present(*ptep))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 587 | return; |
| 588 | |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 589 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
| 590 | vaddr = NULL; |
| 591 | else { |
| 592 | /* |
| 593 | * Use kmap_coherent or kmap_atomic to do flushes for |
| 594 | * another ASID than the current one. |
| 595 | */ |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 596 | map_coherent = (cpu_has_dc_aliases && |
Kirill A. Shutemov | e1534ae | 2016-01-15 16:53:46 -0800 | [diff] [blame] | 597 | page_mapcount(page) && |
| 598 | !Page_dcache_dirty(page)); |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 599 | if (map_coherent) |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 600 | vaddr = kmap_coherent(page, addr); |
| 601 | else |
Cong Wang | 9c02048 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 602 | vaddr = kmap_atomic(page); |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 603 | addr = (unsigned long)vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | } |
| 605 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
Markos Chandras | 80ca69f | 2014-01-16 13:11:08 +0000 | [diff] [blame] | 607 | vaddr ? r4k_blast_dcache_page(addr) : |
| 608 | r4k_blast_dcache_user_page(addr); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 609 | if (exec && !cpu_icache_snoops_remote_store) |
| 610 | r4k_blast_scache_page(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | } |
| 612 | if (exec) { |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 613 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | int cpu = smp_processor_id(); |
| 615 | |
Thiemo Seufer | 26a51b2 | 2005-02-19 13:32:02 +0000 | [diff] [blame] | 616 | if (cpu_context(cpu, mm) != 0) |
| 617 | drop_mmu_context(mm, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | } else |
Markos Chandras | 80ca69f | 2014-01-16 13:11:08 +0000 | [diff] [blame] | 619 | vaddr ? r4k_blast_icache_page(addr) : |
| 620 | r4k_blast_icache_user_page(addr); |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | if (vaddr) { |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 624 | if (map_coherent) |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 625 | kunmap_coherent(); |
| 626 | else |
Cong Wang | 9c02048 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 627 | kunmap_atomic(vaddr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | } |
| 629 | } |
| 630 | |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 631 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
| 632 | unsigned long addr, unsigned long pfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | { |
| 634 | struct flush_cache_page_args args; |
| 635 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | args.vma = vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 637 | args.addr = addr; |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 638 | args.pfn = pfn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 640 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | static inline void local_r4k_flush_data_cache_page(void * addr) |
| 644 | { |
| 645 | r4k_blast_dcache_page((unsigned long) addr); |
| 646 | } |
| 647 | |
| 648 | static void r4k_flush_data_cache_page(unsigned long addr) |
| 649 | { |
Ralf Baechle | a754f70 | 2007-11-03 01:01:37 +0000 | [diff] [blame] | 650 | if (in_atomic()) |
| 651 | local_r4k_flush_data_cache_page((void *)addr); |
| 652 | else |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 653 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | struct flush_icache_range_args { |
Atsushi Nemoto | d4264f1 | 2006-01-29 02:27:51 +0900 | [diff] [blame] | 657 | unsigned long start; |
| 658 | unsigned long end; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 661 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | if (!cpu_has_ic_fills_f_dc) { |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 664 | if (end - start >= dcache_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | r4k_blast_dcache(); |
| 666 | } else { |
Thiemo Seufer | 10a3dab | 2005-09-09 20:26:54 +0000 | [diff] [blame] | 667 | R4600_HIT_CACHEOP_WAR_IMPL; |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 668 | protected_blast_dcache_range(start, end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | if (end - start > icache_size) |
| 673 | r4k_blast_icache(); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 674 | else { |
| 675 | switch (boot_cpu_type()) { |
| 676 | case CPU_LOONGSON2: |
Huacai Chen | bad009f | 2014-01-14 17:56:37 -0800 | [diff] [blame] | 677 | protected_loongson2_blast_icache_range(start, end); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 678 | break; |
| 679 | |
| 680 | default: |
Huacai Chen | bad009f | 2014-01-14 17:56:37 -0800 | [diff] [blame] | 681 | protected_blast_icache_range(start, end); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 682 | break; |
| 683 | } |
| 684 | } |
Leonid Yegoshin | 4676f93 | 2014-01-21 09:48:48 +0000 | [diff] [blame] | 685 | #ifdef CONFIG_EVA |
| 686 | /* |
| 687 | * Due to all possible segment mappings, there might cache aliases |
| 688 | * caused by the bootloader being in non-EVA mode, and the CPU switching |
| 689 | * to EVA during early kernel init. It's best to flush the scache |
| 690 | * to avoid having secondary cores fetching stale data and lead to |
| 691 | * kernel crashes. |
| 692 | */ |
| 693 | bc_wback_inv(start, (end - start)); |
| 694 | __sync(); |
| 695 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | } |
| 697 | |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 698 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
| 699 | { |
| 700 | struct flush_icache_range_args *fir_args = args; |
| 701 | unsigned long start = fir_args->start; |
| 702 | unsigned long end = fir_args->end; |
| 703 | |
| 704 | local_r4k_flush_icache_range(start, end); |
| 705 | } |
| 706 | |
Atsushi Nemoto | d4264f1 | 2006-01-29 02:27:51 +0900 | [diff] [blame] | 707 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 708 | { |
| 709 | struct flush_icache_range_args args; |
| 710 | |
| 711 | args.start = start; |
| 712 | args.end = end; |
| 713 | |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 714 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
Ralf Baechle | cc61c1f | 2005-07-12 18:35:38 +0000 | [diff] [blame] | 715 | instruction_hazard(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Manuel Lauss | 8005711 | 2014-02-20 14:59:22 +0100 | [diff] [blame] | 718 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | |
| 720 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) |
| 721 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 722 | /* Catch bad driver code */ |
| 723 | BUG_ON(size == 0); |
| 724 | |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 725 | preempt_disable(); |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 726 | if (cpu_has_inclusive_pcaches) { |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 727 | if (size >= scache_size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | r4k_blast_scache(); |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 729 | else |
| 730 | blast_scache_range(addr, addr + size); |
Yoichi Yuasa | 5596b0b | 2013-10-02 15:03:03 +0900 | [diff] [blame] | 731 | preempt_enable(); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 732 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | return; |
| 734 | } |
| 735 | |
| 736 | /* |
| 737 | * Either no secondary cache or the available caches don't have the |
| 738 | * subset property so we have to flush the primary caches |
| 739 | * explicitly |
| 740 | */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 741 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | r4k_blast_dcache(); |
| 743 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | R4600_HIT_CACHEOP_WAR_IMPL; |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 745 | blast_dcache_range(addr, addr + size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 746 | } |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 747 | preempt_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 748 | |
| 749 | bc_wback_inv(addr, size); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 750 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) |
| 754 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | /* Catch bad driver code */ |
| 756 | BUG_ON(size == 0); |
| 757 | |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 758 | preempt_disable(); |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 759 | if (cpu_has_inclusive_pcaches) { |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 760 | if (size >= scache_size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 761 | r4k_blast_scache(); |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 762 | else { |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 763 | /* |
| 764 | * There is no clearly documented alignment requirement |
| 765 | * for the cache instruction on MIPS processors and |
| 766 | * some processors, among them the RM5200 and RM7000 |
| 767 | * QED processors will throw an address error for cache |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 768 | * hit ops with insufficient alignment. Solved by |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 769 | * aligning the address to cache line size. |
| 770 | */ |
Thomas Bogendoerfer | e9c3357 | 2007-11-26 23:40:01 +0100 | [diff] [blame] | 771 | blast_inv_scache_range(addr, addr + size); |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 772 | } |
Yoichi Yuasa | 5596b0b | 2013-10-02 15:03:03 +0900 | [diff] [blame] | 773 | preempt_enable(); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 774 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | return; |
| 776 | } |
| 777 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 778 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | r4k_blast_dcache(); |
| 780 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | R4600_HIT_CACHEOP_WAR_IMPL; |
Thomas Bogendoerfer | e9c3357 | 2007-11-26 23:40:01 +0100 | [diff] [blame] | 782 | blast_inv_dcache_range(addr, addr + size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | } |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 784 | preempt_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 785 | |
| 786 | bc_inv(addr, size); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 787 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 788 | } |
Manuel Lauss | 8005711 | 2014-02-20 14:59:22 +0100 | [diff] [blame] | 789 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | |
| 791 | /* |
| 792 | * While we're protected against bad userland addresses we don't care |
| 793 | * very much about what happens in that case. Usually a segmentation |
| 794 | * fault will dump the process later on anyway ... |
| 795 | */ |
| 796 | static void local_r4k_flush_cache_sigtramp(void * arg) |
| 797 | { |
Thiemo Seufer | 02fe2c9 | 2005-09-09 19:45:41 +0000 | [diff] [blame] | 798 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 799 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 800 | unsigned long sc_lsize = cpu_scache_line_size(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | unsigned long addr = (unsigned long) arg; |
| 802 | |
| 803 | R4600_HIT_CACHEOP_WAR_IMPL; |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 804 | if (dc_lsize) |
| 805 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 806 | if (!cpu_icache_snoops_remote_store && scache_size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 808 | if (ic_lsize) |
| 809 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | if (MIPS4K_ICACHE_REFILL_WAR) { |
| 811 | __asm__ __volatile__ ( |
| 812 | ".set push\n\t" |
| 813 | ".set noat\n\t" |
Markos Chandras | 4ee4862 | 2014-12-02 15:30:19 +0000 | [diff] [blame] | 814 | ".set "MIPS_ISA_LEVEL"\n\t" |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 815 | #ifdef CONFIG_32BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | "la $at,1f\n\t" |
| 817 | #endif |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 818 | #ifdef CONFIG_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | "dla $at,1f\n\t" |
| 820 | #endif |
| 821 | "cache %0,($at)\n\t" |
| 822 | "nop; nop; nop\n" |
| 823 | "1:\n\t" |
| 824 | ".set pop" |
| 825 | : |
| 826 | : "i" (Hit_Invalidate_I)); |
| 827 | } |
| 828 | if (MIPS_CACHE_SYNC_WAR) |
| 829 | __asm__ __volatile__ ("sync"); |
| 830 | } |
| 831 | |
| 832 | static void r4k_flush_cache_sigtramp(unsigned long addr) |
| 833 | { |
Ralf Baechle | 48a26e6 | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 834 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | static void r4k_flush_icache_all(void) |
| 838 | { |
| 839 | if (cpu_has_vtag_icache) |
| 840 | r4k_blast_icache(); |
| 841 | } |
| 842 | |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 843 | struct flush_kernel_vmap_range_args { |
| 844 | unsigned long vaddr; |
| 845 | int size; |
| 846 | }; |
| 847 | |
| 848 | static inline void local_r4k_flush_kernel_vmap_range(void *args) |
| 849 | { |
| 850 | struct flush_kernel_vmap_range_args *vmra = args; |
| 851 | unsigned long vaddr = vmra->vaddr; |
| 852 | int size = vmra->size; |
| 853 | |
| 854 | /* |
| 855 | * Aliases only affect the primary caches so don't bother with |
| 856 | * S-caches or T-caches. |
| 857 | */ |
| 858 | if (cpu_has_safe_index_cacheops && size >= dcache_size) |
| 859 | r4k_blast_dcache(); |
| 860 | else { |
| 861 | R4600_HIT_CACHEOP_WAR_IMPL; |
| 862 | blast_dcache_range(vaddr, vaddr + size); |
| 863 | } |
| 864 | } |
| 865 | |
| 866 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) |
| 867 | { |
| 868 | struct flush_kernel_vmap_range_args args; |
| 869 | |
| 870 | args.vaddr = (unsigned long) vaddr; |
| 871 | args.size = size; |
| 872 | |
| 873 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); |
| 874 | } |
| 875 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 876 | static inline void rm7k_erratum31(void) |
| 877 | { |
| 878 | const unsigned long ic_lsize = 32; |
| 879 | unsigned long addr; |
| 880 | |
| 881 | /* RM7000 erratum #31. The icache is screwed at startup. */ |
| 882 | write_c0_taglo(0); |
| 883 | write_c0_taghi(0); |
| 884 | |
| 885 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { |
| 886 | __asm__ __volatile__ ( |
Thiemo Seufer | d8748a3 | 2005-09-02 09:56:12 +0000 | [diff] [blame] | 887 | ".set push\n\t" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | ".set noreorder\n\t" |
| 889 | ".set mips3\n\t" |
| 890 | "cache\t%1, 0(%0)\n\t" |
| 891 | "cache\t%1, 0x1000(%0)\n\t" |
| 892 | "cache\t%1, 0x2000(%0)\n\t" |
| 893 | "cache\t%1, 0x3000(%0)\n\t" |
| 894 | "cache\t%2, 0(%0)\n\t" |
| 895 | "cache\t%2, 0x1000(%0)\n\t" |
| 896 | "cache\t%2, 0x2000(%0)\n\t" |
| 897 | "cache\t%2, 0x3000(%0)\n\t" |
| 898 | "cache\t%1, 0(%0)\n\t" |
| 899 | "cache\t%1, 0x1000(%0)\n\t" |
| 900 | "cache\t%1, 0x2000(%0)\n\t" |
| 901 | "cache\t%1, 0x3000(%0)\n\t" |
Thiemo Seufer | d8748a3 | 2005-09-02 09:56:12 +0000 | [diff] [blame] | 902 | ".set pop\n" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | : |
| 904 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); |
| 905 | } |
| 906 | } |
| 907 | |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 908 | static inline int alias_74k_erratum(struct cpuinfo_mips *c) |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 909 | { |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 910 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
| 911 | unsigned int rev = c->processor_id & PRID_REV_MASK; |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 912 | int present = 0; |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 913 | |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 914 | /* |
| 915 | * Early versions of the 74K do not update the cache tags on a |
| 916 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 917 | * aliases. In this case it is better to treat the cache as always |
| 918 | * having aliases. Also disable the synonym tag update feature |
| 919 | * where available. In this case no opportunistic tag update will |
| 920 | * happen where a load causes a virtual address miss but a physical |
| 921 | * address hit during a D-cache look-up. |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 922 | */ |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 923 | switch (imp) { |
| 924 | case PRID_IMP_74K: |
| 925 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 926 | present = 1; |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 927 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) |
| 928 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
| 929 | break; |
| 930 | case PRID_IMP_1074K: |
| 931 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 932 | present = 1; |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 933 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
| 934 | } |
| 935 | break; |
| 936 | default: |
| 937 | BUG(); |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 938 | } |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 939 | |
| 940 | return present; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 941 | } |
| 942 | |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 943 | static void b5k_instruction_hazard(void) |
| 944 | { |
| 945 | __sync(); |
| 946 | __sync(); |
| 947 | __asm__ __volatile__( |
| 948 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 949 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 950 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 951 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 952 | : : : "memory"); |
| 953 | } |
| 954 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 955 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
Paul Burton | 1e18ac7 | 2015-07-09 10:40:41 +0100 | [diff] [blame] | 956 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", |
| 957 | "9-way", "10-way", "11-way", "12-way", |
| 958 | "13-way", "14-way", "15-way", "16-way", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 959 | }; |
| 960 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 961 | static void probe_pcache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | { |
| 963 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 964 | unsigned int config = read_c0_config(); |
| 965 | unsigned int prid = read_c0_prid(); |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 966 | int has_74k_erratum = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | unsigned long config1; |
| 968 | unsigned int lsize; |
| 969 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 970 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | case CPU_R4600: /* QED style two way caches? */ |
| 972 | case CPU_R4700: |
| 973 | case CPU_R5000: |
| 974 | case CPU_NEVADA: |
| 975 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 976 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 977 | c->icache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 978 | c->icache.waybit = __ffs(icache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 979 | |
| 980 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 981 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 982 | c->dcache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 983 | c->dcache.waybit= __ffs(dcache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | |
| 985 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 986 | break; |
| 987 | |
| 988 | case CPU_R5432: |
| 989 | case CPU_R5500: |
| 990 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 991 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 992 | c->icache.ways = 2; |
| 993 | c->icache.waybit= 0; |
| 994 | |
| 995 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 996 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 997 | c->dcache.ways = 2; |
| 998 | c->dcache.waybit = 0; |
| 999 | |
Shinya Kuribayashi | 5864810 | 2009-03-18 09:04:01 +0900 | [diff] [blame] | 1000 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | break; |
| 1002 | |
| 1003 | case CPU_TX49XX: |
| 1004 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1005 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1006 | c->icache.ways = 4; |
| 1007 | c->icache.waybit= 0; |
| 1008 | |
| 1009 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1010 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1011 | c->dcache.ways = 4; |
| 1012 | c->dcache.waybit = 0; |
| 1013 | |
| 1014 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
Atsushi Nemoto | de862b4 | 2006-03-17 12:59:22 +0900 | [diff] [blame] | 1015 | c->options |= MIPS_CPU_PREFETCH; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | break; |
| 1017 | |
| 1018 | case CPU_R4000PC: |
| 1019 | case CPU_R4000SC: |
| 1020 | case CPU_R4000MC: |
| 1021 | case CPU_R4400PC: |
| 1022 | case CPU_R4400SC: |
| 1023 | case CPU_R4400MC: |
| 1024 | case CPU_R4300: |
| 1025 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1026 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1027 | c->icache.ways = 1; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1028 | c->icache.waybit = 0; /* doesn't matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | |
| 1030 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1031 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1032 | c->dcache.ways = 1; |
| 1033 | c->dcache.waybit = 0; /* does not matter */ |
| 1034 | |
| 1035 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1036 | break; |
| 1037 | |
| 1038 | case CPU_R10000: |
| 1039 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1040 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1041 | case CPU_R16000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
| 1043 | c->icache.linesz = 64; |
| 1044 | c->icache.ways = 2; |
| 1045 | c->icache.waybit = 0; |
| 1046 | |
| 1047 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); |
| 1048 | c->dcache.linesz = 32; |
| 1049 | c->dcache.ways = 2; |
| 1050 | c->dcache.waybit = 0; |
| 1051 | |
| 1052 | c->options |= MIPS_CPU_PREFETCH; |
| 1053 | break; |
| 1054 | |
| 1055 | case CPU_VR4133: |
Yoichi Yuasa | 2874fe5 | 2006-07-08 00:42:12 +0900 | [diff] [blame] | 1056 | write_c0_config(config & ~VR41_CONF_P4K); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | case CPU_VR4131: |
| 1058 | /* Workaround for cache instruction bug of VR4131 */ |
| 1059 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || |
| 1060 | c->processor_id == 0x0c82U) { |
Yoichi Yuasa | 4e8ab36 | 2006-07-04 22:59:41 +0900 | [diff] [blame] | 1061 | config |= 0x00400000U; |
| 1062 | if (c->processor_id == 0x0c80U) |
| 1063 | config |= VR41_CONF_BP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | write_c0_config(config); |
Yoichi Yuasa | 1058ecd | 2006-07-08 00:42:01 +0900 | [diff] [blame] | 1065 | } else |
| 1066 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1067 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1068 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
| 1069 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1070 | c->icache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1071 | c->icache.waybit = __ffs(icache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1072 | |
| 1073 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); |
| 1074 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1075 | c->dcache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1076 | c->dcache.waybit = __ffs(dcache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | break; |
| 1078 | |
| 1079 | case CPU_VR41XX: |
| 1080 | case CPU_VR4111: |
| 1081 | case CPU_VR4121: |
| 1082 | case CPU_VR4122: |
| 1083 | case CPU_VR4181: |
| 1084 | case CPU_VR4181A: |
| 1085 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
| 1086 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1087 | c->icache.ways = 1; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1088 | c->icache.waybit = 0; /* doesn't matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | |
| 1090 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); |
| 1091 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1092 | c->dcache.ways = 1; |
| 1093 | c->dcache.waybit = 0; /* does not matter */ |
| 1094 | |
| 1095 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1096 | break; |
| 1097 | |
| 1098 | case CPU_RM7000: |
| 1099 | rm7k_erratum31(); |
| 1100 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1101 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1102 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1103 | c->icache.ways = 4; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1104 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1105 | |
| 1106 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1107 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1108 | c->dcache.ways = 4; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1109 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1111 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1112 | c->options |= MIPS_CPU_PREFETCH; |
| 1113 | break; |
| 1114 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1115 | case CPU_LOONGSON2: |
| 1116 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1117 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1118 | if (prid & 0x3) |
| 1119 | c->icache.ways = 4; |
| 1120 | else |
| 1121 | c->icache.ways = 2; |
| 1122 | c->icache.waybit = 0; |
| 1123 | |
| 1124 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1125 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1126 | if (prid & 0x3) |
| 1127 | c->dcache.ways = 4; |
| 1128 | else |
| 1129 | c->dcache.ways = 2; |
| 1130 | c->dcache.waybit = 0; |
| 1131 | break; |
| 1132 | |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1133 | case CPU_LOONGSON3: |
| 1134 | config1 = read_c0_config1(); |
| 1135 | lsize = (config1 >> 19) & 7; |
| 1136 | if (lsize) |
| 1137 | c->icache.linesz = 2 << lsize; |
| 1138 | else |
| 1139 | c->icache.linesz = 0; |
| 1140 | c->icache.sets = 64 << ((config1 >> 22) & 7); |
| 1141 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
| 1142 | icache_size = c->icache.sets * |
| 1143 | c->icache.ways * |
| 1144 | c->icache.linesz; |
| 1145 | c->icache.waybit = 0; |
| 1146 | |
| 1147 | lsize = (config1 >> 10) & 7; |
| 1148 | if (lsize) |
| 1149 | c->dcache.linesz = 2 << lsize; |
| 1150 | else |
| 1151 | c->dcache.linesz = 0; |
| 1152 | c->dcache.sets = 64 << ((config1 >> 13) & 7); |
| 1153 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
| 1154 | dcache_size = c->dcache.sets * |
| 1155 | c->dcache.ways * |
| 1156 | c->dcache.linesz; |
| 1157 | c->dcache.waybit = 0; |
| 1158 | break; |
| 1159 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 1160 | case CPU_CAVIUM_OCTEON3: |
| 1161 | /* For now lie about the number of ways. */ |
| 1162 | c->icache.linesz = 128; |
| 1163 | c->icache.sets = 16; |
| 1164 | c->icache.ways = 8; |
| 1165 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1166 | icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; |
| 1167 | |
| 1168 | c->dcache.linesz = 128; |
| 1169 | c->dcache.ways = 8; |
| 1170 | c->dcache.sets = 8; |
| 1171 | dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; |
| 1172 | c->options |= MIPS_CPU_PREFETCH; |
| 1173 | break; |
| 1174 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1175 | default: |
| 1176 | if (!(config & MIPS_CONF_M)) |
| 1177 | panic("Don't know how to probe P-caches on this cpu."); |
| 1178 | |
| 1179 | /* |
| 1180 | * So we seem to be a MIPS32 or MIPS64 CPU |
| 1181 | * So let's probe the I-cache ... |
| 1182 | */ |
| 1183 | config1 = read_c0_config1(); |
| 1184 | |
Markos Chandras | 175cba8 | 2013-09-19 18:18:41 +0100 | [diff] [blame] | 1185 | lsize = (config1 >> 19) & 7; |
| 1186 | |
| 1187 | /* IL == 7 is reserved */ |
| 1188 | if (lsize == 7) |
| 1189 | panic("Invalid icache line size"); |
| 1190 | |
| 1191 | c->icache.linesz = lsize ? 2 << lsize : 0; |
| 1192 | |
Douglas Leung | dc34b05 | 2012-07-19 09:11:13 +0200 | [diff] [blame] | 1193 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
| 1195 | |
| 1196 | icache_size = c->icache.sets * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1197 | c->icache.ways * |
| 1198 | c->icache.linesz; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1199 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | |
| 1201 | if (config & 0x8) /* VI bit */ |
| 1202 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1203 | |
| 1204 | /* |
| 1205 | * Now probe the MIPS32 / MIPS64 data cache. |
| 1206 | */ |
| 1207 | c->dcache.flags = 0; |
| 1208 | |
Markos Chandras | 175cba8 | 2013-09-19 18:18:41 +0100 | [diff] [blame] | 1209 | lsize = (config1 >> 10) & 7; |
| 1210 | |
| 1211 | /* DL == 7 is reserved */ |
| 1212 | if (lsize == 7) |
| 1213 | panic("Invalid dcache line size"); |
| 1214 | |
| 1215 | c->dcache.linesz = lsize ? 2 << lsize : 0; |
| 1216 | |
Douglas Leung | dc34b05 | 2012-07-19 09:11:13 +0200 | [diff] [blame] | 1217 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1218 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
| 1219 | |
| 1220 | dcache_size = c->dcache.sets * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1221 | c->dcache.ways * |
| 1222 | c->dcache.linesz; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1223 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1224 | |
| 1225 | c->options |= MIPS_CPU_PREFETCH; |
| 1226 | break; |
| 1227 | } |
| 1228 | |
| 1229 | /* |
| 1230 | * Processor configuration sanity check for the R4000SC erratum |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1231 | * #5. With page sizes larger than 32kB there is no possibility |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | * to get a VCE exception anymore so we don't care about this |
| 1233 | * misconfiguration. The case is rather theoretical anyway; |
| 1234 | * presumably no vendor is shipping his hardware in the "bad" |
| 1235 | * configuration. |
| 1236 | */ |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1237 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
| 1238 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1239 | !(config & CONF_SC) && c->icache.linesz != 16 && |
| 1240 | PAGE_SIZE <= 0x8000) |
| 1241 | panic("Improper R4000SC processor configuration detected"); |
| 1242 | |
| 1243 | /* compute a couple of other cache variables */ |
| 1244 | c->icache.waysize = icache_size / c->icache.ways; |
| 1245 | c->dcache.waysize = dcache_size / c->dcache.ways; |
| 1246 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 1247 | c->icache.sets = c->icache.linesz ? |
| 1248 | icache_size / (c->icache.linesz * c->icache.ways) : 0; |
| 1249 | c->dcache.sets = c->dcache.linesz ? |
| 1250 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1251 | |
| 1252 | /* |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1253 | * R1x000 P-caches are odd in a positive way. They're 32kB 2-way |
| 1254 | * virtually indexed so normally would suffer from aliases. So |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1255 | * normally they'd suffer from aliases but magic in the hardware deals |
| 1256 | * with that for us so we don't need to take care ourselves. |
| 1257 | */ |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1258 | switch (current_cpu_type()) { |
Ralf Baechle | a95970f | 2005-02-07 21:41:32 +0000 | [diff] [blame] | 1259 | case CPU_20KC: |
Ralf Baechle | 505403b | 2005-02-07 21:53:39 +0000 | [diff] [blame] | 1260 | case CPU_25KF: |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1261 | case CPU_SB1: |
| 1262 | case CPU_SB1A: |
Jayachandran C | efa0f81 | 2011-05-07 01:36:21 +0530 | [diff] [blame] | 1263 | case CPU_XLR: |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 1264 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1265 | break; |
| 1266 | |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1267 | case CPU_R10000: |
| 1268 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1269 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1270 | case CPU_R16000: |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1271 | break; |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1272 | |
Maciej W. Rozycki | bf4aac0 | 2014-06-28 23:28:08 +0100 | [diff] [blame] | 1273 | case CPU_74K: |
| 1274 | case CPU_1074K: |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1275 | has_74k_erratum = alias_74k_erratum(c); |
Maciej W. Rozycki | bf4aac0 | 2014-06-28 23:28:08 +0100 | [diff] [blame] | 1276 | /* Fall through. */ |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 1277 | case CPU_M14KC: |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 1278 | case CPU_M14KEC: |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1279 | case CPU_24K: |
Nigel Stephens | 98a41de | 2006-04-27 15:50:32 +0100 | [diff] [blame] | 1280 | case CPU_34K: |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1281 | case CPU_1004K: |
Leonid Yegoshin | 26ab96d | 2013-11-27 10:07:53 +0000 | [diff] [blame] | 1282 | case CPU_INTERAPTIV: |
James Hogan | aced4cb | 2014-01-22 16:19:38 +0000 | [diff] [blame] | 1283 | case CPU_P5600: |
Leonid Yegoshin | 708ac4b | 2013-11-14 16:12:27 +0000 | [diff] [blame] | 1284 | case CPU_PROAPTIV: |
Leonid Yegoshin | f36c472 | 2014-03-04 13:34:43 +0000 | [diff] [blame] | 1285 | case CPU_M5150: |
Leonid Yegoshin | 4695089 | 2014-11-24 12:59:01 +0000 | [diff] [blame] | 1286 | case CPU_QEMU_GENERIC: |
Markos Chandras | 4e88a86 | 2015-07-09 10:40:36 +0100 | [diff] [blame] | 1287 | case CPU_I6400: |
Paul Burton | 1091bfa | 2016-02-03 03:26:38 +0000 | [diff] [blame] | 1288 | case CPU_P6600: |
Paul Burton | 1dbf6a8 | 2016-02-03 16:17:29 +0000 | [diff] [blame] | 1289 | case CPU_M6250: |
Markos Chandras | 02dc6bf | 2014-01-30 17:21:29 +0000 | [diff] [blame] | 1290 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
| 1291 | (c->icache.waysize > PAGE_SIZE)) |
| 1292 | c->icache.flags |= MIPS_CACHE_ALIASES; |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1293 | if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { |
Markos Chandras | 02dc6bf | 2014-01-30 17:21:29 +0000 | [diff] [blame] | 1294 | /* |
| 1295 | * Effectively physically indexed dcache, |
| 1296 | * thus no virtual aliases. |
| 1297 | */ |
Ralf Baechle | beab375 | 2006-06-19 21:56:25 +0100 | [diff] [blame] | 1298 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
| 1299 | break; |
| 1300 | } |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1301 | default: |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1302 | if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) |
Ralf Baechle | beab375 | 2006-06-19 21:56:25 +0100 | [diff] [blame] | 1303 | c->dcache.flags |= MIPS_CACHE_ALIASES; |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1304 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1305 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1306 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1307 | case CPU_20KC: |
| 1308 | /* |
| 1309 | * Some older 20Kc chips doesn't have the 'VI' bit in |
| 1310 | * the config register. |
| 1311 | */ |
| 1312 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1313 | break; |
| 1314 | |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1315 | case CPU_ALCHEMY: |
James Hogan | 47f2ac5 | 2016-01-22 10:58:26 +0000 | [diff] [blame] | 1316 | case CPU_I6400: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
| 1318 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | |
Florian Fainelli | c130d2f | 2016-04-04 10:55:34 -0700 | [diff] [blame^] | 1320 | case CPU_BMIPS5000: |
| 1321 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
| 1322 | break; |
| 1323 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1324 | case CPU_LOONGSON2: |
| 1325 | /* |
| 1326 | * LOONGSON2 has 4 way icache, but when using indexed cache op, |
| 1327 | * one op will act on all 4 ways |
| 1328 | */ |
| 1329 | c->icache.ways = 1; |
| 1330 | } |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
| 1333 | icache_size >> 10, |
Ralf Baechle | 7fc7316 | 2009-04-01 16:11:53 +0200 | [diff] [blame] | 1334 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1335 | way_string[c->icache.ways], c->icache.linesz); |
| 1336 | |
Ralf Baechle | 64bfca5 | 2007-10-15 16:35:45 +0100 | [diff] [blame] | 1337 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
| 1338 | dcache_size >> 10, way_string[c->dcache.ways], |
| 1339 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", |
| 1340 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? |
| 1341 | "cache aliases" : "no aliases", |
| 1342 | c->dcache.linesz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1343 | } |
| 1344 | |
| 1345 | /* |
| 1346 | * If you even _breathe_ on this function, look at the gcc output and make sure |
| 1347 | * it does not pop things on and off the stack for the cache sizing loop that |
| 1348 | * executes in KSEG1 space or else you will crash and burn badly. You have |
| 1349 | * been warned. |
| 1350 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1351 | static int probe_scache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1353 | unsigned long flags, addr, begin, end, pow2; |
| 1354 | unsigned int config = read_c0_config(); |
| 1355 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | |
| 1357 | if (config & CONF_SC) |
| 1358 | return 0; |
| 1359 | |
Ralf Baechle | e001e52 | 2007-07-28 12:45:47 +0100 | [diff] [blame] | 1360 | begin = (unsigned long) &_stext; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1361 | begin &= ~((4 * 1024 * 1024) - 1); |
| 1362 | end = begin + (4 * 1024 * 1024); |
| 1363 | |
| 1364 | /* |
| 1365 | * This is such a bitch, you'd think they would make it easy to do |
| 1366 | * this. Away you daemons of stupidity! |
| 1367 | */ |
| 1368 | local_irq_save(flags); |
| 1369 | |
| 1370 | /* Fill each size-multiple cache line with a valid tag. */ |
| 1371 | pow2 = (64 * 1024); |
| 1372 | for (addr = begin; addr < end; addr = (begin + pow2)) { |
| 1373 | unsigned long *p = (unsigned long *) addr; |
| 1374 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ |
| 1375 | pow2 <<= 1; |
| 1376 | } |
| 1377 | |
| 1378 | /* Load first line with zero (therefore invalid) tag. */ |
| 1379 | write_c0_taglo(0); |
| 1380 | write_c0_taghi(0); |
| 1381 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ |
| 1382 | cache_op(Index_Store_Tag_I, begin); |
| 1383 | cache_op(Index_Store_Tag_D, begin); |
| 1384 | cache_op(Index_Store_Tag_SD, begin); |
| 1385 | |
| 1386 | /* Now search for the wrap around point. */ |
| 1387 | pow2 = (128 * 1024); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
| 1389 | cache_op(Index_Load_Tag_SD, addr); |
| 1390 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ |
| 1391 | if (!read_c0_taglo()) |
| 1392 | break; |
| 1393 | pow2 <<= 1; |
| 1394 | } |
| 1395 | local_irq_restore(flags); |
| 1396 | addr -= begin; |
| 1397 | |
| 1398 | scache_size = addr; |
| 1399 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); |
| 1400 | c->scache.ways = 1; |
Joshua Kinard | 755af33 | 2015-06-02 16:55:22 -0400 | [diff] [blame] | 1401 | c->scache.waybit = 0; /* does not matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | |
| 1403 | return 1; |
| 1404 | } |
| 1405 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1406 | static void __init loongson2_sc_init(void) |
| 1407 | { |
| 1408 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1409 | |
| 1410 | scache_size = 512*1024; |
| 1411 | c->scache.linesz = 32; |
| 1412 | c->scache.ways = 4; |
| 1413 | c->scache.waybit = 0; |
| 1414 | c->scache.waysize = scache_size / (c->scache.ways); |
| 1415 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); |
| 1416 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1417 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1418 | |
| 1419 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1420 | } |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1421 | |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1422 | static void __init loongson3_sc_init(void) |
| 1423 | { |
| 1424 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1425 | unsigned int config2, lsize; |
| 1426 | |
| 1427 | config2 = read_c0_config2(); |
| 1428 | lsize = (config2 >> 4) & 15; |
| 1429 | if (lsize) |
| 1430 | c->scache.linesz = 2 << lsize; |
| 1431 | else |
| 1432 | c->scache.linesz = 0; |
| 1433 | c->scache.sets = 64 << ((config2 >> 8) & 15); |
| 1434 | c->scache.ways = 1 + (config2 & 15); |
| 1435 | |
| 1436 | scache_size = c->scache.sets * |
| 1437 | c->scache.ways * |
| 1438 | c->scache.linesz; |
| 1439 | /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ |
| 1440 | scache_size *= 4; |
| 1441 | c->scache.waybit = 0; |
| 1442 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1443 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1444 | if (scache_size) |
| 1445 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1446 | return; |
| 1447 | } |
| 1448 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1449 | extern int r5k_sc_init(void); |
| 1450 | extern int rm7k_sc_init(void); |
Chris Dearman | 9318c51 | 2006-06-20 17:15:20 +0100 | [diff] [blame] | 1451 | extern int mips_sc_init(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1452 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1453 | static void setup_scache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1454 | { |
| 1455 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1456 | unsigned int config = read_c0_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1457 | int sc_present = 0; |
| 1458 | |
| 1459 | /* |
| 1460 | * Do the probing thing on R4000SC and R4400SC processors. Other |
| 1461 | * processors don't have a S-cache that would be relevant to the |
Joe Perches | 603e82e | 2008-02-03 16:54:53 +0200 | [diff] [blame] | 1462 | * Linux memory management. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1463 | */ |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1464 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1465 | case CPU_R4000SC: |
| 1466 | case CPU_R4000MC: |
| 1467 | case CPU_R4400SC: |
| 1468 | case CPU_R4400MC: |
Thiemo Seufer | ba5187d | 2005-04-25 16:36:23 +0000 | [diff] [blame] | 1469 | sc_present = run_uncached(probe_scache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1470 | if (sc_present) |
| 1471 | c->options |= MIPS_CPU_CACHE_CDEX_S; |
| 1472 | break; |
| 1473 | |
| 1474 | case CPU_R10000: |
| 1475 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1476 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1477 | case CPU_R16000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1478 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
| 1479 | c->scache.linesz = 64 << ((config >> 13) & 1); |
| 1480 | c->scache.ways = 2; |
| 1481 | c->scache.waybit= 0; |
| 1482 | sc_present = 1; |
| 1483 | break; |
| 1484 | |
| 1485 | case CPU_R5000: |
| 1486 | case CPU_NEVADA: |
| 1487 | #ifdef CONFIG_R5000_CPU_SCACHE |
| 1488 | r5k_sc_init(); |
| 1489 | #endif |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1490 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1491 | |
| 1492 | case CPU_RM7000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1493 | #ifdef CONFIG_RM7000_CPU_SCACHE |
| 1494 | rm7k_sc_init(); |
| 1495 | #endif |
| 1496 | return; |
| 1497 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1498 | case CPU_LOONGSON2: |
| 1499 | loongson2_sc_init(); |
| 1500 | return; |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1501 | |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1502 | case CPU_LOONGSON3: |
| 1503 | loongson3_sc_init(); |
| 1504 | return; |
| 1505 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 1506 | case CPU_CAVIUM_OCTEON3: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1507 | case CPU_XLP: |
| 1508 | /* don't need to worry about L2, fully coherent */ |
| 1509 | return; |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1510 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1511 | default: |
Deng-Cheng Zhu | adb3789 | 2013-04-01 18:14:28 +0000 | [diff] [blame] | 1512 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
Markos Chandras | b5ad2c2 | 2015-01-15 10:28:29 +0000 | [diff] [blame] | 1513 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | |
| 1514 | MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { |
Chris Dearman | 9318c51 | 2006-06-20 17:15:20 +0100 | [diff] [blame] | 1515 | #ifdef CONFIG_MIPS_CPU_SCACHE |
| 1516 | if (mips_sc_init ()) { |
| 1517 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; |
| 1518 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", |
| 1519 | scache_size >> 10, |
| 1520 | way_string[c->scache.ways], c->scache.linesz); |
| 1521 | } |
| 1522 | #else |
| 1523 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) |
| 1524 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); |
| 1525 | #endif |
| 1526 | return; |
| 1527 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1528 | sc_present = 0; |
| 1529 | } |
| 1530 | |
| 1531 | if (!sc_present) |
| 1532 | return; |
| 1533 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | /* compute a couple of other cache variables */ |
| 1535 | c->scache.waysize = scache_size / c->scache.ways; |
| 1536 | |
| 1537 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); |
| 1538 | |
| 1539 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1540 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1541 | |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 1542 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1543 | } |
| 1544 | |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1545 | void au1x00_fixup_config_od(void) |
| 1546 | { |
| 1547 | /* |
| 1548 | * c0_config.od (bit 19) was write only (and read as 0) |
| 1549 | * on the early revisions of Alchemy SOCs. It disables the bus |
| 1550 | * transaction overlapping and needs to be set to fix various errata. |
| 1551 | */ |
| 1552 | switch (read_c0_prid()) { |
| 1553 | case 0x00030100: /* Au1000 DA */ |
| 1554 | case 0x00030201: /* Au1000 HA */ |
| 1555 | case 0x00030202: /* Au1000 HB */ |
| 1556 | case 0x01030200: /* Au1500 AB */ |
| 1557 | /* |
| 1558 | * Au1100 errata actually keeps silence about this bit, so we set it |
| 1559 | * just in case for those revisions that require it to be set according |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1560 | * to the (now gone) cpu table. |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1561 | */ |
| 1562 | case 0x02030200: /* Au1100 AB */ |
| 1563 | case 0x02030201: /* Au1100 BA */ |
| 1564 | case 0x02030202: /* Au1100 BC */ |
| 1565 | set_c0_config(1 << 19); |
| 1566 | break; |
| 1567 | } |
| 1568 | } |
| 1569 | |
Ralf Baechle | 89052bd | 2008-06-12 17:26:02 +0100 | [diff] [blame] | 1570 | /* CP0 hazard avoidance. */ |
| 1571 | #define NXP_BARRIER() \ |
| 1572 | __asm__ __volatile__( \ |
| 1573 | ".set noreorder\n\t" \ |
| 1574 | "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 1575 | ".set reorder\n\t") |
| 1576 | |
| 1577 | static void nxp_pr4450_fixup_config(void) |
| 1578 | { |
| 1579 | unsigned long config0; |
| 1580 | |
| 1581 | config0 = read_c0_config(); |
| 1582 | |
| 1583 | /* clear all three cache coherency fields */ |
| 1584 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); |
| 1585 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | |
| 1586 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | |
| 1587 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); |
| 1588 | write_c0_config(config0); |
| 1589 | NXP_BARRIER(); |
| 1590 | } |
| 1591 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1592 | static int cca = -1; |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1593 | |
| 1594 | static int __init cca_setup(char *str) |
| 1595 | { |
| 1596 | get_option(&str, &cca); |
| 1597 | |
Shane McDonald | b5b64f2 | 2012-06-14 02:26:40 +0000 | [diff] [blame] | 1598 | return 0; |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1599 | } |
| 1600 | |
Shane McDonald | b5b64f2 | 2012-06-14 02:26:40 +0000 | [diff] [blame] | 1601 | early_param("cca", cca_setup); |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1602 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1603 | static void coherency_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | { |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1605 | if (cca < 0 || cca > 7) |
| 1606 | cca = read_c0_config() & CONF_CM_CMASK; |
| 1607 | _page_cachable_default = cca << _CACHE_SHIFT; |
| 1608 | |
| 1609 | pr_debug("Using cache attribute %d\n", cca); |
| 1610 | change_c0_config(CONF_CM_CMASK, cca); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1611 | |
| 1612 | /* |
| 1613 | * c0_status.cu=0 specifies that updates by the sc instruction use |
| 1614 | * the coherency mode specified by the TLB; 1 means cachable |
| 1615 | * coherent update on write will be used. Not all processors have |
| 1616 | * this bit and; some wire it to zero, others like Toshiba had the |
| 1617 | * silly idea of putting something else there ... |
| 1618 | */ |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1619 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1620 | case CPU_R4000PC: |
| 1621 | case CPU_R4000SC: |
| 1622 | case CPU_R4000MC: |
| 1623 | case CPU_R4400PC: |
| 1624 | case CPU_R4400SC: |
| 1625 | case CPU_R4400MC: |
| 1626 | clear_c0_config(CONF_CU); |
| 1627 | break; |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1628 | /* |
Ralf Baechle | df586d5 | 2006-08-01 23:42:30 +0100 | [diff] [blame] | 1629 | * We need to catch the early Alchemy SOCs with |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1630 | * the write-only co_config.od bit and set it back to one on: |
| 1631 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1632 | */ |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1633 | case CPU_ALCHEMY: |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1634 | au1x00_fixup_config_od(); |
| 1635 | break; |
Ralf Baechle | 89052bd | 2008-06-12 17:26:02 +0100 | [diff] [blame] | 1636 | |
| 1637 | case PRID_IMP_PR4450: |
| 1638 | nxp_pr4450_fixup_config(); |
| 1639 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1640 | } |
| 1641 | } |
| 1642 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1643 | static void r4k_cache_error_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1644 | { |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1645 | extern char __weak except_vec2_generic; |
| 1646 | extern char __weak except_vec2_sb1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1647 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1648 | switch (current_cpu_type()) { |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1649 | case CPU_SB1: |
| 1650 | case CPU_SB1A: |
| 1651 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); |
| 1652 | break; |
| 1653 | |
| 1654 | default: |
| 1655 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); |
| 1656 | break; |
| 1657 | } |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1658 | } |
| 1659 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1660 | void r4k_cache_init(void) |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1661 | { |
| 1662 | extern void build_clear_page(void); |
| 1663 | extern void build_copy_page(void); |
| 1664 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1665 | |
| 1666 | probe_pcache(); |
| 1667 | setup_scache(); |
| 1668 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1669 | r4k_blast_dcache_page_setup(); |
| 1670 | r4k_blast_dcache_page_indexed_setup(); |
| 1671 | r4k_blast_dcache_setup(); |
| 1672 | r4k_blast_icache_page_setup(); |
| 1673 | r4k_blast_icache_page_indexed_setup(); |
| 1674 | r4k_blast_icache_setup(); |
| 1675 | r4k_blast_scache_page_setup(); |
| 1676 | r4k_blast_scache_page_indexed_setup(); |
| 1677 | r4k_blast_scache_setup(); |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 1678 | #ifdef CONFIG_EVA |
| 1679 | r4k_blast_dcache_user_page_setup(); |
| 1680 | r4k_blast_icache_user_page_setup(); |
| 1681 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1682 | |
| 1683 | /* |
| 1684 | * Some MIPS32 and MIPS64 processors have physically indexed caches. |
| 1685 | * This code supports virtually indexed processors and will be |
| 1686 | * unnecessarily inefficient on physically indexed processors. |
| 1687 | */ |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 1688 | if (c->dcache.linesz) |
| 1689 | shm_align_mask = max_t( unsigned long, |
| 1690 | c->dcache.sets * c->dcache.linesz - 1, |
| 1691 | PAGE_SIZE - 1); |
| 1692 | else |
| 1693 | shm_align_mask = PAGE_SIZE-1; |
Ralf Baechle | 9c5a3d7 | 2008-04-05 15:13:23 +0100 | [diff] [blame] | 1694 | |
| 1695 | __flush_cache_vmap = r4k__flush_cache_vmap; |
| 1696 | __flush_cache_vunmap = r4k__flush_cache_vunmap; |
| 1697 | |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 1698 | flush_cache_all = cache_noop; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | __flush_cache_all = r4k___flush_cache_all; |
| 1700 | flush_cache_mm = r4k_flush_cache_mm; |
| 1701 | flush_cache_page = r4k_flush_cache_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1702 | flush_cache_range = r4k_flush_cache_range; |
| 1703 | |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 1704 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
| 1705 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1706 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
| 1707 | flush_icache_all = r4k_flush_icache_all; |
Ralf Baechle | 7e3bfc7 | 2006-04-05 20:42:04 +0100 | [diff] [blame] | 1708 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1709 | flush_data_cache_page = r4k_flush_data_cache_page; |
| 1710 | flush_icache_range = r4k_flush_icache_range; |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1711 | local_flush_icache_range = local_r4k_flush_icache_range; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1712 | |
Manuel Lauss | 8005711 | 2014-02-20 14:59:22 +0100 | [diff] [blame] | 1713 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1714 | if (coherentio) { |
| 1715 | _dma_cache_wback_inv = (void *)cache_noop; |
| 1716 | _dma_cache_wback = (void *)cache_noop; |
| 1717 | _dma_cache_inv = (void *)cache_noop; |
| 1718 | } else { |
| 1719 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; |
| 1720 | _dma_cache_wback = r4k_dma_cache_wback_inv; |
| 1721 | _dma_cache_inv = r4k_dma_cache_inv; |
| 1722 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1723 | #endif |
| 1724 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1725 | build_clear_page(); |
| 1726 | build_copy_page(); |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 1727 | |
| 1728 | /* |
| 1729 | * We want to run CMP kernels on core with and without coherent |
| 1730 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether |
| 1731 | * or not to flush caches. |
| 1732 | */ |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1733 | local_r4k___flush_cache_all(NULL); |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 1734 | |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1735 | coherency_setup(); |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1736 | board_cache_error_setup = r4k_cache_error_setup; |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1737 | |
| 1738 | /* |
| 1739 | * Per-CPU overrides |
| 1740 | */ |
| 1741 | switch (current_cpu_type()) { |
| 1742 | case CPU_BMIPS4350: |
| 1743 | case CPU_BMIPS4380: |
| 1744 | /* No IPI is needed because all CPUs share the same D$ */ |
| 1745 | flush_data_cache_page = r4k_blast_dcache_page; |
| 1746 | break; |
| 1747 | case CPU_BMIPS5000: |
| 1748 | /* We lose our superpowers if L2 is disabled */ |
| 1749 | if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) |
| 1750 | break; |
| 1751 | |
| 1752 | /* I$ fills from D$ just by emptying the write buffers */ |
| 1753 | flush_cache_page = (void *)b5k_instruction_hazard; |
| 1754 | flush_cache_range = (void *)b5k_instruction_hazard; |
| 1755 | flush_cache_sigtramp = (void *)b5k_instruction_hazard; |
| 1756 | local_flush_data_cache_page = (void *)b5k_instruction_hazard; |
| 1757 | flush_data_cache_page = (void *)b5k_instruction_hazard; |
| 1758 | flush_icache_range = (void *)b5k_instruction_hazard; |
| 1759 | local_flush_icache_range = (void *)b5k_instruction_hazard; |
| 1760 | |
| 1761 | /* Cache aliases are handled in hardware; allow HIGHMEM */ |
| 1762 | current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; |
| 1763 | |
| 1764 | /* Optimization: an L2 flush implicitly flushes the L1 */ |
| 1765 | current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1766 | break; |
| 1767 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1768 | } |
James Hogan | 61d7304 | 2014-03-04 10:23:57 +0000 | [diff] [blame] | 1769 | |
| 1770 | static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, |
| 1771 | void *v) |
| 1772 | { |
| 1773 | switch (cmd) { |
| 1774 | case CPU_PM_ENTER_FAILED: |
| 1775 | case CPU_PM_EXIT: |
| 1776 | coherency_setup(); |
| 1777 | break; |
| 1778 | } |
| 1779 | |
| 1780 | return NOTIFY_OK; |
| 1781 | } |
| 1782 | |
| 1783 | static struct notifier_block r4k_cache_pm_notifier_block = { |
| 1784 | .notifier_call = r4k_cache_pm_notifier, |
| 1785 | }; |
| 1786 | |
| 1787 | int __init r4k_cache_init_pm(void) |
| 1788 | { |
| 1789 | return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); |
| 1790 | } |
| 1791 | arch_initcall(r4k_cache_init_pm); |