Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 24 | /** |
| 25 | * DOC: Frame Buffer Compression (FBC) |
| 26 | * |
| 27 | * FBC tries to save memory bandwidth (and so power consumption) by |
| 28 | * compressing the amount of memory used by the display. It is total |
| 29 | * transparent to user space and completely handled in the kernel. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 30 | * |
| 31 | * The benefits of FBC are mostly visible with solid backgrounds and |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 32 | * variation-less patterns. It comes from keeping the memory footprint small |
| 33 | * and having fewer memory pages opened and accessed for refreshing the display. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 34 | * |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
| 36 | * offset on proper registers. The hardware takes care of all |
| 37 | * compress/decompress. However there are many known cases where we have to |
| 38 | * forcibly disable it to allow proper screen updates. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 39 | */ |
| 40 | |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 41 | #include "intel_drv.h" |
| 42 | #include "i915_drv.h" |
| 43 | |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
| 45 | { |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 46 | return HAS_FBC(dev_priv); |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 47 | } |
| 48 | |
Paulo Zanoni | 5710502 | 2015-11-04 17:10:46 -0200 | [diff] [blame] | 49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
| 50 | { |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 51 | return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; |
Paulo Zanoni | 5710502 | 2015-11-04 17:10:46 -0200 | [diff] [blame] | 52 | } |
| 53 | |
Paulo Zanoni | e6cd6dc | 2015-10-16 17:55:40 -0300 | [diff] [blame] | 54 | static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
| 55 | { |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 56 | return INTEL_GEN(dev_priv) < 4; |
Paulo Zanoni | e6cd6dc | 2015-10-16 17:55:40 -0300 | [diff] [blame] | 57 | } |
| 58 | |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 59 | static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) |
| 60 | { |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 61 | return INTEL_GEN(dev_priv) <= 3; |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 62 | } |
| 63 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 64 | /* |
| 65 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the |
| 66 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's |
| 67 | * origin so the x and y offsets can actually fit the registers. As a |
| 68 | * consequence, the fence doesn't really start exactly at the display plane |
| 69 | * address we program because it starts at the real start of the buffer, so we |
| 70 | * have to take this into consideration here. |
| 71 | */ |
| 72 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) |
| 73 | { |
| 74 | return crtc->base.y - crtc->adjusted_y; |
| 75 | } |
| 76 | |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 77 | /* |
| 78 | * For SKL+, the plane source size used by the hardware is based on the value we |
| 79 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
| 80 | * we wrote to PIPESRC. |
| 81 | */ |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 82 | static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 83 | int *width, int *height) |
| 84 | { |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 85 | if (width) |
Ville Syrjälä | 73714c0 | 2017-03-31 21:00:56 +0300 | [diff] [blame] | 86 | *width = cache->plane.src_w; |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 87 | if (height) |
Ville Syrjälä | 73714c0 | 2017-03-31 21:00:56 +0300 | [diff] [blame] | 88 | *height = cache->plane.src_h; |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 89 | } |
| 90 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 91 | static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, |
| 92 | struct intel_fbc_state_cache *cache) |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 93 | { |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 94 | int lines; |
| 95 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 96 | intel_fbc_get_plane_source_size(cache, NULL, &lines); |
Paulo Zanoni | 79f2624 | 2016-10-21 13:55:45 -0200 | [diff] [blame] | 97 | if (INTEL_GEN(dev_priv) == 7) |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 98 | lines = min(lines, 2048); |
Paulo Zanoni | 79f2624 | 2016-10-21 13:55:45 -0200 | [diff] [blame] | 99 | else if (INTEL_GEN(dev_priv) >= 8) |
| 100 | lines = min(lines, 2560); |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 101 | |
| 102 | /* Hardware needs the full buffer stride, not just the active area. */ |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 103 | return lines * cache->fb.stride; |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 104 | } |
| 105 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 106 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 107 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 108 | u32 fbc_ctl; |
| 109 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 110 | /* Disable compression */ |
| 111 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 112 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 113 | return; |
| 114 | |
| 115 | fbc_ctl &= ~FBC_CTL_EN; |
| 116 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 117 | |
| 118 | /* Wait for compressing bit to clear */ |
Chris Wilson | 8d90dfd | 2016-06-30 15:33:21 +0100 | [diff] [blame] | 119 | if (intel_wait_for_register(dev_priv, |
| 120 | FBC_STATUS, FBC_STAT_COMPRESSING, 0, |
| 121 | 10)) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 122 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 123 | return; |
| 124 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 125 | } |
| 126 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 127 | static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 128 | { |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 129 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 130 | int cfb_pitch; |
| 131 | int i; |
| 132 | u32 fbc_ctl; |
| 133 | |
Jani Nikula | 60ee5cd | 2015-02-05 12:04:27 +0200 | [diff] [blame] | 134 | /* Note: fbc.threshold == 1 for i8xx */ |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 135 | cfb_pitch = params->cfb_size / FBC_LL_SIZE; |
| 136 | if (params->fb.stride < cfb_pitch) |
| 137 | cfb_pitch = params->fb.stride; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 138 | |
| 139 | /* FBC_CTL wants 32B or 64B units */ |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 140 | if (IS_GEN2(dev_priv)) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 141 | cfb_pitch = (cfb_pitch / 32) - 1; |
| 142 | else |
| 143 | cfb_pitch = (cfb_pitch / 64) - 1; |
| 144 | |
| 145 | /* Clear old tags */ |
| 146 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
Ville Syrjälä | 4d110c7 | 2015-09-18 20:03:18 +0300 | [diff] [blame] | 147 | I915_WRITE(FBC_TAG(i), 0); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 148 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 149 | if (IS_GEN4(dev_priv)) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 150 | u32 fbc_ctl2; |
| 151 | |
| 152 | /* Set it up... */ |
| 153 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 154 | fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 155 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 156 | I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | /* enable it... */ |
| 160 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 161 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; |
| 162 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 163 | if (IS_I945GM(dev_priv)) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 164 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 165 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 166 | fbc_ctl |= params->vma->fence->id; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 167 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 168 | } |
| 169 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 170 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 171 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 172 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 173 | } |
| 174 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 175 | static void g4x_fbc_activate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 176 | { |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 177 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 178 | u32 dpfc_ctl; |
| 179 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 180 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN; |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 181 | if (params->fb.format->cpp[0] == 2) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 182 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 183 | else |
| 184 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 185 | |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 186 | if (params->vma->fence) { |
| 187 | dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id; |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 188 | I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
| 189 | } else { |
| 190 | I915_WRITE(DPFC_FENCE_YOFF, 0); |
| 191 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 192 | |
| 193 | /* enable it... */ |
| 194 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 195 | } |
| 196 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 197 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 198 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 199 | u32 dpfc_ctl; |
| 200 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 201 | /* Disable compression */ |
| 202 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 203 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 204 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 205 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 206 | } |
| 207 | } |
| 208 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 209 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 210 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 211 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 212 | } |
| 213 | |
Paulo Zanoni | d5ce416 | 2015-11-04 17:10:45 -0200 | [diff] [blame] | 214 | /* This function forces a CFB recompression through the nuke operation. */ |
| 215 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 216 | { |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 217 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
| 218 | POSTING_READ(MSG_FBC_REND_STATE); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 219 | } |
| 220 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 221 | static void ilk_fbc_activate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 222 | { |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 223 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 224 | u32 dpfc_ctl; |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 225 | int threshold = dev_priv->fbc.threshold; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 226 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 227 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane); |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 228 | if (params->fb.format->cpp[0] == 2) |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 229 | threshold++; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 230 | |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 231 | switch (threshold) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 232 | case 4: |
| 233 | case 3: |
| 234 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 235 | break; |
| 236 | case 2: |
| 237 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 238 | break; |
| 239 | case 1: |
| 240 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 241 | break; |
| 242 | } |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 243 | |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 244 | if (params->vma->fence) { |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 245 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
| 246 | if (IS_GEN5(dev_priv)) |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 247 | dpfc_ctl |= params->vma->fence->id; |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 248 | if (IS_GEN6(dev_priv)) { |
| 249 | I915_WRITE(SNB_DPFC_CTL_SA, |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 250 | SNB_CPU_FENCE_ENABLE | |
| 251 | params->vma->fence->id); |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 252 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, |
| 253 | params->crtc.fence_y_offset); |
| 254 | } |
| 255 | } else { |
| 256 | if (IS_GEN6(dev_priv)) { |
| 257 | I915_WRITE(SNB_DPFC_CTL_SA, 0); |
| 258 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); |
| 259 | } |
| 260 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 261 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 262 | I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 263 | I915_WRITE(ILK_FBC_RT_BASE, |
| 264 | i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 265 | /* enable it... */ |
| 266 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 267 | |
Paulo Zanoni | d5ce416 | 2015-11-04 17:10:45 -0200 | [diff] [blame] | 268 | intel_fbc_recompress(dev_priv); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 269 | } |
| 270 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 271 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 272 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 273 | u32 dpfc_ctl; |
| 274 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 275 | /* Disable compression */ |
| 276 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 277 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 278 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 279 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 280 | } |
| 281 | } |
| 282 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 283 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 284 | { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 285 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 286 | } |
| 287 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 288 | static void gen7_fbc_activate(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 289 | { |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 290 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 291 | u32 dpfc_ctl; |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 292 | int threshold = dev_priv->fbc.threshold; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 293 | |
Paulo Zanoni | d8514d6 | 2015-06-12 14:36:21 -0300 | [diff] [blame] | 294 | dpfc_ctl = 0; |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 295 | if (IS_IVYBRIDGE(dev_priv)) |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 296 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); |
Paulo Zanoni | d8514d6 | 2015-06-12 14:36:21 -0300 | [diff] [blame] | 297 | |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 298 | if (params->fb.format->cpp[0] == 2) |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 299 | threshold++; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 300 | |
Paulo Zanoni | ce65e47 | 2015-06-30 10:53:05 -0300 | [diff] [blame] | 301 | switch (threshold) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 302 | case 4: |
| 303 | case 3: |
| 304 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 305 | break; |
| 306 | case 2: |
| 307 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 308 | break; |
| 309 | case 1: |
| 310 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 311 | break; |
| 312 | } |
| 313 | |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 314 | if (params->vma->fence) { |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 315 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
| 316 | I915_WRITE(SNB_DPFC_CTL_SA, |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 317 | SNB_CPU_FENCE_ENABLE | |
| 318 | params->vma->fence->id); |
Chris Wilson | 12ecf4b | 2016-08-19 16:54:24 +0100 | [diff] [blame] | 319 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); |
| 320 | } else { |
| 321 | I915_WRITE(SNB_DPFC_CTL_SA,0); |
| 322 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); |
| 323 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 324 | |
| 325 | if (dev_priv->fbc.false_color) |
| 326 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; |
| 327 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 328 | if (IS_IVYBRIDGE(dev_priv)) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 329 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
| 330 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 331 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 332 | ILK_FBCQ_DIS); |
Paulo Zanoni | 40f4022 | 2015-09-14 15:20:01 -0300 | [diff] [blame] | 333 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 334 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 335 | I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe), |
| 336 | I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 337 | HSW_FBCQ_DIS); |
| 338 | } |
| 339 | |
Paulo Zanoni | 57012be9 | 2015-09-14 15:20:00 -0300 | [diff] [blame] | 340 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 341 | |
Paulo Zanoni | d5ce416 | 2015-11-04 17:10:45 -0200 | [diff] [blame] | 342 | intel_fbc_recompress(dev_priv); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 343 | } |
| 344 | |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 345 | static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) |
| 346 | { |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 347 | if (INTEL_GEN(dev_priv) >= 5) |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 348 | return ilk_fbc_is_active(dev_priv); |
| 349 | else if (IS_GM45(dev_priv)) |
| 350 | return g4x_fbc_is_active(dev_priv); |
| 351 | else |
| 352 | return i8xx_fbc_is_active(dev_priv); |
| 353 | } |
| 354 | |
| 355 | static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) |
| 356 | { |
Paulo Zanoni | 5375ce9 | 2016-01-29 18:57:40 -0200 | [diff] [blame] | 357 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 358 | |
| 359 | fbc->active = true; |
| 360 | |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 361 | if (INTEL_GEN(dev_priv) >= 7) |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 362 | gen7_fbc_activate(dev_priv); |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 363 | else if (INTEL_GEN(dev_priv) >= 5) |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 364 | ilk_fbc_activate(dev_priv); |
| 365 | else if (IS_GM45(dev_priv)) |
| 366 | g4x_fbc_activate(dev_priv); |
| 367 | else |
| 368 | i8xx_fbc_activate(dev_priv); |
| 369 | } |
| 370 | |
| 371 | static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) |
| 372 | { |
Paulo Zanoni | 5375ce9 | 2016-01-29 18:57:40 -0200 | [diff] [blame] | 373 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 374 | |
| 375 | fbc->active = false; |
| 376 | |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 377 | if (INTEL_GEN(dev_priv) >= 5) |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 378 | ilk_fbc_deactivate(dev_priv); |
| 379 | else if (IS_GM45(dev_priv)) |
| 380 | g4x_fbc_deactivate(dev_priv); |
| 381 | else |
| 382 | i8xx_fbc_deactivate(dev_priv); |
| 383 | } |
| 384 | |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 385 | /** |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 386 | * intel_fbc_is_active - Is FBC active? |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 387 | * @dev_priv: i915 device instance |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 388 | * |
| 389 | * This function is used to verify the current state of FBC. |
Daniel Vetter | 2e7a570 | 2016-06-01 23:40:36 +0200 | [diff] [blame] | 390 | * |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 391 | * FIXME: This should be tracked in the plane config eventually |
Daniel Vetter | 2e7a570 | 2016-06-01 23:40:36 +0200 | [diff] [blame] | 392 | * instead of queried at runtime for most callers. |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 393 | */ |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 394 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 395 | { |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 396 | return dev_priv->fbc.active; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 397 | } |
| 398 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 399 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 400 | { |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 401 | struct drm_i915_private *dev_priv = |
| 402 | container_of(__work, struct drm_i915_private, fbc.work.work); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 403 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 404 | struct intel_fbc_work *work = &fbc->work; |
| 405 | struct intel_crtc *crtc = fbc->crtc; |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 406 | struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe]; |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 407 | |
| 408 | if (drm_crtc_vblank_get(&crtc->base)) { |
| 409 | DRM_ERROR("vblank not available for FBC on pipe %c\n", |
| 410 | pipe_name(crtc->pipe)); |
| 411 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 412 | mutex_lock(&fbc->lock); |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 413 | work->scheduled = false; |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 414 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 415 | return; |
| 416 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 417 | |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 418 | retry: |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 419 | /* Delay the actual enabling to let pageflipping cease and the |
| 420 | * display to settle before starting the compression. Note that |
| 421 | * this delay also serves a second purpose: it allows for a |
| 422 | * vblank to pass after disabling the FBC before we attempt |
| 423 | * to modify the control registers. |
| 424 | * |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 425 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 426 | * |
| 427 | * It is also worth mentioning that since work->scheduled_vblank can be |
| 428 | * updated multiple times by the other threads, hitting the timeout is |
| 429 | * not an error condition. We'll just end up hitting the "goto retry" |
| 430 | * case below. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 431 | */ |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 432 | wait_event_timeout(vblank->queue, |
| 433 | drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank, |
| 434 | msecs_to_jiffies(50)); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 435 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 436 | mutex_lock(&fbc->lock); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 437 | |
| 438 | /* Were we cancelled? */ |
| 439 | if (!work->scheduled) |
| 440 | goto out; |
| 441 | |
| 442 | /* Were we delayed again while this function was sleeping? */ |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 443 | if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 444 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 445 | goto retry; |
| 446 | } |
| 447 | |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 448 | intel_fbc_hw_activate(dev_priv); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 449 | |
| 450 | work->scheduled = false; |
| 451 | |
| 452 | out: |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 453 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 454 | drm_crtc_vblank_put(&crtc->base); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 455 | } |
| 456 | |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 457 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
| 458 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 459 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 460 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 461 | struct intel_fbc_work *work = &fbc->work; |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 462 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 463 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 464 | |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 465 | if (drm_crtc_vblank_get(&crtc->base)) { |
| 466 | DRM_ERROR("vblank not available for FBC on pipe %c\n", |
| 467 | pipe_name(crtc->pipe)); |
| 468 | return; |
| 469 | } |
| 470 | |
Paulo Zanoni | e35be23 | 2016-01-18 15:56:58 -0200 | [diff] [blame] | 471 | /* It is useless to call intel_fbc_cancel_work() or cancel_work() in |
| 472 | * this function since we're not releasing fbc.lock, so it won't have an |
| 473 | * opportunity to grab it to discover that it was cancelled. So we just |
| 474 | * update the expected jiffy count. */ |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 475 | work->scheduled = true; |
Paulo Zanoni | ca18d51 | 2016-01-21 18:03:05 -0200 | [diff] [blame] | 476 | work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base); |
| 477 | drm_crtc_vblank_put(&crtc->base); |
Paulo Zanoni | 128d735 | 2015-10-26 16:27:49 -0200 | [diff] [blame] | 478 | |
| 479 | schedule_work(&work->work); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 480 | } |
| 481 | |
Paulo Zanoni | 60eb2cc | 2016-01-19 11:35:45 -0200 | [diff] [blame] | 482 | static void intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 483 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 484 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 485 | |
| 486 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 487 | |
Paulo Zanoni | e35be23 | 2016-01-18 15:56:58 -0200 | [diff] [blame] | 488 | /* Calling cancel_work() here won't help due to the fact that the work |
| 489 | * function grabs fbc->lock. Just set scheduled to false so the work |
| 490 | * function can know it was cancelled. */ |
| 491 | fbc->work.scheduled = false; |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 492 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 493 | if (fbc->active) |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 494 | intel_fbc_hw_deactivate(dev_priv); |
Paulo Zanoni | 754d113 | 2015-10-13 19:13:25 -0300 | [diff] [blame] | 495 | } |
| 496 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 497 | static bool multiple_pipes_ok(struct intel_crtc *crtc, |
| 498 | struct intel_plane_state *plane_state) |
Paulo Zanoni | 232fd93 | 2015-07-07 15:26:07 -0300 | [diff] [blame] | 499 | { |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 501 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 502 | enum pipe pipe = crtc->pipe; |
Paulo Zanoni | 232fd93 | 2015-07-07 15:26:07 -0300 | [diff] [blame] | 503 | |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 504 | /* Don't even bother tracking anything we don't need. */ |
| 505 | if (!no_fbc_on_multiple_pipes(dev_priv)) |
Paulo Zanoni | 232fd93 | 2015-07-07 15:26:07 -0300 | [diff] [blame] | 506 | return true; |
| 507 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 508 | if (plane_state->base.visible) |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 509 | fbc->visible_pipes_mask |= (1 << pipe); |
| 510 | else |
| 511 | fbc->visible_pipes_mask &= ~(1 << pipe); |
Paulo Zanoni | 232fd93 | 2015-07-07 15:26:07 -0300 | [diff] [blame] | 512 | |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 513 | return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0; |
Paulo Zanoni | 232fd93 | 2015-07-07 15:26:07 -0300 | [diff] [blame] | 514 | } |
| 515 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 516 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 517 | struct drm_mm_node *node, |
| 518 | int size, |
| 519 | int fb_cpp) |
| 520 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 521 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 522 | int compression_threshold = 1; |
| 523 | int ret; |
Paulo Zanoni | a9da512 | 2015-09-14 15:19:57 -0300 | [diff] [blame] | 524 | u64 end; |
| 525 | |
| 526 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen |
| 527 | * reserved range size, so it always assumes the maximum (8mb) is used. |
| 528 | * If we enable FBC using a CFB on that memory range we'll get FIFO |
| 529 | * underruns, even if that range is not reserved by the BIOS. */ |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 530 | if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 531 | end = ggtt->stolen_size - 8 * 1024 * 1024; |
Paulo Zanoni | a9da512 | 2015-09-14 15:19:57 -0300 | [diff] [blame] | 532 | else |
Paulo Zanoni | 3c6b29b | 2016-12-15 11:23:55 -0200 | [diff] [blame] | 533 | end = U64_MAX; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 534 | |
| 535 | /* HACK: This code depends on what we will do in *_enable_fbc. If that |
| 536 | * code changes, this code needs to change as well. |
| 537 | * |
| 538 | * The enable_fbc code will attempt to use one of our 2 compression |
| 539 | * thresholds, therefore, in that case, we only have 1 resort. |
| 540 | */ |
| 541 | |
| 542 | /* Try to over-allocate to reduce reallocations and fragmentation. */ |
Paulo Zanoni | a9da512 | 2015-09-14 15:19:57 -0300 | [diff] [blame] | 543 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
| 544 | 4096, 0, end); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 545 | if (ret == 0) |
| 546 | return compression_threshold; |
| 547 | |
| 548 | again: |
| 549 | /* HW's ability to limit the CFB is 1:4 */ |
| 550 | if (compression_threshold > 4 || |
| 551 | (fb_cpp == 2 && compression_threshold == 2)) |
| 552 | return 0; |
| 553 | |
Paulo Zanoni | a9da512 | 2015-09-14 15:19:57 -0300 | [diff] [blame] | 554 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
| 555 | 4096, 0, end); |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 556 | if (ret && INTEL_GEN(dev_priv) <= 4) { |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 557 | return 0; |
| 558 | } else if (ret) { |
| 559 | compression_threshold <<= 1; |
| 560 | goto again; |
| 561 | } else { |
| 562 | return compression_threshold; |
| 563 | } |
| 564 | } |
| 565 | |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 566 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 567 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 568 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 569 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 570 | struct drm_mm_node *uninitialized_var(compressed_llb); |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 571 | int size, fb_cpp, ret; |
| 572 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 573 | WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 574 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 575 | size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 576 | fb_cpp = fbc->state_cache.fb.format->cpp[0]; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 577 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 578 | ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 579 | size, fb_cpp); |
| 580 | if (!ret) |
| 581 | goto err_llb; |
| 582 | else if (ret > 1) { |
| 583 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); |
| 584 | |
| 585 | } |
| 586 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 587 | fbc->threshold = ret; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 588 | |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 589 | if (INTEL_GEN(dev_priv) >= 5) |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 590 | I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 591 | else if (IS_GM45(dev_priv)) { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 592 | I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 593 | } else { |
| 594 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); |
| 595 | if (!compressed_llb) |
| 596 | goto err_fb; |
| 597 | |
| 598 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, |
| 599 | 4096, 4096); |
| 600 | if (ret) |
| 601 | goto err_fb; |
| 602 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 603 | fbc->compressed_llb = compressed_llb; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 604 | |
| 605 | I915_WRITE(FBC_CFB_BASE, |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 606 | dev_priv->mm.stolen_base + fbc->compressed_fb.start); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 607 | I915_WRITE(FBC_LL_BASE, |
| 608 | dev_priv->mm.stolen_base + compressed_llb->start); |
| 609 | } |
| 610 | |
Paulo Zanoni | b8bf5d7 | 2015-09-14 15:19:58 -0300 | [diff] [blame] | 611 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 612 | fbc->compressed_fb.size, fbc->threshold); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 613 | |
| 614 | return 0; |
| 615 | |
| 616 | err_fb: |
| 617 | kfree(compressed_llb); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 618 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 619 | err_llb: |
Chris Wilson | 8d0e9bc | 2017-02-23 12:20:37 +0000 | [diff] [blame] | 620 | if (drm_mm_initialized(&dev_priv->mm.stolen)) |
| 621 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 622 | return -ENOSPC; |
| 623 | } |
| 624 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 625 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 626 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 627 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 628 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 629 | if (drm_mm_node_allocated(&fbc->compressed_fb)) |
| 630 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); |
| 631 | |
| 632 | if (fbc->compressed_llb) { |
| 633 | i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); |
| 634 | kfree(fbc->compressed_llb); |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 635 | } |
Paulo Zanoni | fc78672 | 2015-07-02 19:25:08 -0300 | [diff] [blame] | 636 | } |
| 637 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 638 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 639 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 640 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 641 | |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 642 | if (!fbc_supported(dev_priv)) |
Paulo Zanoni | 0bf73c3 | 2015-07-03 15:40:54 -0300 | [diff] [blame] | 643 | return; |
| 644 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 645 | mutex_lock(&fbc->lock); |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 646 | __intel_fbc_cleanup_cfb(dev_priv); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 647 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 648 | } |
| 649 | |
Paulo Zanoni | adf70c6 | 2015-09-14 15:19:56 -0300 | [diff] [blame] | 650 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
| 651 | unsigned int stride) |
| 652 | { |
| 653 | /* These should have been caught earlier. */ |
| 654 | WARN_ON(stride < 512); |
| 655 | WARN_ON((stride & (64 - 1)) != 0); |
| 656 | |
| 657 | /* Below are the additional FBC restrictions. */ |
| 658 | |
| 659 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) |
| 660 | return stride == 4096 || stride == 8192; |
| 661 | |
| 662 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) |
| 663 | return false; |
| 664 | |
| 665 | if (stride > 16384) |
| 666 | return false; |
| 667 | |
| 668 | return true; |
| 669 | } |
| 670 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 671 | static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, |
| 672 | uint32_t pixel_format) |
Paulo Zanoni | b9e831d | 2015-09-21 19:48:06 -0300 | [diff] [blame] | 673 | { |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 674 | switch (pixel_format) { |
Paulo Zanoni | b9e831d | 2015-09-21 19:48:06 -0300 | [diff] [blame] | 675 | case DRM_FORMAT_XRGB8888: |
| 676 | case DRM_FORMAT_XBGR8888: |
| 677 | return true; |
| 678 | case DRM_FORMAT_XRGB1555: |
| 679 | case DRM_FORMAT_RGB565: |
| 680 | /* 16bpp not supported on gen2 */ |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 681 | if (IS_GEN2(dev_priv)) |
Paulo Zanoni | b9e831d | 2015-09-21 19:48:06 -0300 | [diff] [blame] | 682 | return false; |
| 683 | /* WaFbcOnly1to1Ratio:ctg */ |
| 684 | if (IS_G4X(dev_priv)) |
| 685 | return false; |
| 686 | return true; |
| 687 | default: |
| 688 | return false; |
| 689 | } |
| 690 | } |
| 691 | |
Paulo Zanoni | 856312a | 2015-10-01 19:57:12 -0300 | [diff] [blame] | 692 | /* |
| 693 | * For some reason, the hardware tracking starts looking at whatever we |
| 694 | * programmed as the display plane base address register. It does not look at |
| 695 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} |
| 696 | * variables instead of just looking at the pipe/plane size. |
| 697 | */ |
| 698 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 699 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 700 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 701 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | 856312a | 2015-10-01 19:57:12 -0300 | [diff] [blame] | 702 | unsigned int effective_w, effective_h, max_w, max_h; |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 703 | |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 704 | if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 705 | max_w = 4096; |
| 706 | max_h = 4096; |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 707 | } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 708 | max_w = 4096; |
| 709 | max_h = 2048; |
| 710 | } else { |
| 711 | max_w = 2048; |
| 712 | max_h = 1536; |
| 713 | } |
| 714 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 715 | intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, |
| 716 | &effective_h); |
Paulo Zanoni | 856312a | 2015-10-01 19:57:12 -0300 | [diff] [blame] | 717 | effective_w += crtc->adjusted_x; |
| 718 | effective_h += crtc->adjusted_y; |
| 719 | |
| 720 | return effective_w <= max_w && effective_h <= max_h; |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 721 | } |
| 722 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 723 | static void intel_fbc_update_state_cache(struct intel_crtc *crtc, |
| 724 | struct intel_crtc_state *crtc_state, |
| 725 | struct intel_plane_state *plane_state) |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 726 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 727 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 728 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 729 | struct intel_fbc_state_cache *cache = &fbc->state_cache; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 730 | struct drm_framebuffer *fb = plane_state->base.fb; |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 731 | |
| 732 | cache->vma = NULL; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 733 | |
| 734 | cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; |
| 735 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
Ville Syrjälä | a7d1b3f | 2017-01-26 21:50:31 +0200 | [diff] [blame] | 736 | cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 737 | |
| 738 | cache->plane.rotation = plane_state->base.rotation; |
Ville Syrjälä | 73714c0 | 2017-03-31 21:00:56 +0300 | [diff] [blame] | 739 | /* |
| 740 | * Src coordinates are already rotated by 270 degrees for |
| 741 | * the 90/270 degree plane rotation cases (to match the |
| 742 | * GTT mapping), hence no need to account for rotation here. |
| 743 | */ |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 744 | cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; |
| 745 | cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; |
| 746 | cache->plane.visible = plane_state->base.visible; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 747 | |
| 748 | if (!cache->plane.visible) |
| 749 | return; |
| 750 | |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 751 | cache->fb.format = fb->format; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 752 | cache->fb.stride = fb->pitches[0]; |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 753 | |
| 754 | cache->vma = plane_state->vma; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 755 | } |
| 756 | |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 757 | static bool intel_fbc_can_activate(struct intel_crtc *crtc) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 758 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 759 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 760 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 761 | struct intel_fbc_state_cache *cache = &fbc->state_cache; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 762 | |
Paulo Zanoni | 61a585d | 2016-09-13 10:38:57 -0300 | [diff] [blame] | 763 | /* We don't need to use a state cache here since this information is |
| 764 | * global for all CRTC. |
| 765 | */ |
| 766 | if (fbc->underrun_detected) { |
| 767 | fbc->no_fbc_reason = "underrun detected"; |
| 768 | return false; |
| 769 | } |
| 770 | |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 771 | if (!cache->vma) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 772 | fbc->no_fbc_reason = "primary plane not visible"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 773 | return false; |
| 774 | } |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 775 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 776 | if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) || |
| 777 | (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 778 | fbc->no_fbc_reason = "incompatible mode"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 779 | return false; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 780 | } |
| 781 | |
Paulo Zanoni | 45b32a2 | 2015-11-04 17:10:49 -0200 | [diff] [blame] | 782 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 783 | fbc->no_fbc_reason = "mode too large for compression"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 784 | return false; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 785 | } |
Paulo Zanoni | 3c5f174 | 2015-09-23 12:52:24 -0300 | [diff] [blame] | 786 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 787 | /* The use of a CPU fence is mandatory in order to detect writes |
| 788 | * by the CPU to the scanout and trigger updates to the FBC. |
Chris Wilson | 2efb813 | 2016-08-18 17:17:06 +0100 | [diff] [blame] | 789 | * |
| 790 | * Note that is possible for a tiled surface to be unmappable (and |
| 791 | * so have no fence associated with it) due to aperture constaints |
| 792 | * at the time of pinning. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 793 | */ |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 794 | if (!cache->vma->fence) { |
Chris Wilson | c82dd88 | 2016-08-24 19:00:53 +0100 | [diff] [blame] | 795 | fbc->no_fbc_reason = "framebuffer not tiled or fenced"; |
| 796 | return false; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 797 | } |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 798 | if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && |
Robert Foss | c2c446a | 2017-05-19 16:50:17 -0400 | [diff] [blame] | 799 | cache->plane.rotation != DRM_MODE_ROTATE_0) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 800 | fbc->no_fbc_reason = "rotation unsupported"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 801 | return false; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 802 | } |
| 803 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 804 | if (!stride_is_valid(dev_priv, cache->fb.stride)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 805 | fbc->no_fbc_reason = "framebuffer stride not supported"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 806 | return false; |
Paulo Zanoni | adf70c6 | 2015-09-14 15:19:56 -0300 | [diff] [blame] | 807 | } |
| 808 | |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 809 | if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 810 | fbc->no_fbc_reason = "pixel format is invalid"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 811 | return false; |
Paulo Zanoni | b9e831d | 2015-09-21 19:48:06 -0300 | [diff] [blame] | 812 | } |
| 813 | |
Paulo Zanoni | 7b24c9a | 2015-09-14 15:19:59 -0300 | [diff] [blame] | 814 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
| 815 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && |
Ville Syrjälä | 49cd97a | 2017-02-07 20:33:45 +0200 | [diff] [blame] | 816 | cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 817 | fbc->no_fbc_reason = "pixel rate is too big"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 818 | return false; |
Paulo Zanoni | 7b24c9a | 2015-09-14 15:19:59 -0300 | [diff] [blame] | 819 | } |
| 820 | |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 821 | /* It is possible for the required CFB size change without a |
| 822 | * crtc->disable + crtc->enable since it is possible to change the |
| 823 | * stride without triggering a full modeset. Since we try to |
| 824 | * over-allocate the CFB, there's a chance we may keep FBC enabled even |
| 825 | * if this happens, but if we exceed the current CFB size we'll have to |
| 826 | * disable FBC. Notice that it would be possible to disable FBC, wait |
| 827 | * for a frame, free the stolen node, then try to reenable FBC in case |
| 828 | * we didn't get any invalidate/deactivate calls, but this would require |
| 829 | * a lot of tracking just for a specific case. If we conclude it's an |
| 830 | * important case, we can implement it later. */ |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 831 | if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 832 | fbc->compressed_fb.size * fbc->threshold) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 833 | fbc->no_fbc_reason = "CFB requirements changed"; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 834 | return false; |
| 835 | } |
| 836 | |
| 837 | return true; |
| 838 | } |
| 839 | |
Paulo Zanoni | ee2be30 | 2016-11-11 14:57:37 -0200 | [diff] [blame] | 840 | static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 44a8a25 | 2016-01-19 11:35:36 -0200 | [diff] [blame] | 841 | { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 842 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | 44a8a25 | 2016-01-19 11:35:36 -0200 | [diff] [blame] | 843 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 844 | if (intel_vgpu_active(dev_priv)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 845 | fbc->no_fbc_reason = "VGPU is active"; |
Paulo Zanoni | 44a8a25 | 2016-01-19 11:35:36 -0200 | [diff] [blame] | 846 | return false; |
| 847 | } |
| 848 | |
Paulo Zanoni | 44a8a25 | 2016-01-19 11:35:36 -0200 | [diff] [blame] | 849 | if (!i915.enable_fbc) { |
Paulo Zanoni | 80788a0 | 2016-04-13 16:01:09 -0300 | [diff] [blame] | 850 | fbc->no_fbc_reason = "disabled per module param or by default"; |
Paulo Zanoni | 44a8a25 | 2016-01-19 11:35:36 -0200 | [diff] [blame] | 851 | return false; |
| 852 | } |
| 853 | |
Paulo Zanoni | 61a585d | 2016-09-13 10:38:57 -0300 | [diff] [blame] | 854 | if (fbc->underrun_detected) { |
| 855 | fbc->no_fbc_reason = "underrun detected"; |
| 856 | return false; |
| 857 | } |
| 858 | |
Paulo Zanoni | ee2be30 | 2016-11-11 14:57:37 -0200 | [diff] [blame] | 859 | return true; |
| 860 | } |
| 861 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 862 | static void intel_fbc_get_reg_params(struct intel_crtc *crtc, |
| 863 | struct intel_fbc_reg_params *params) |
| 864 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 865 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 866 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 867 | struct intel_fbc_state_cache *cache = &fbc->state_cache; |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 868 | |
| 869 | /* Since all our fields are integer types, use memset here so the |
| 870 | * comparison function can rely on memcmp because the padding will be |
| 871 | * zero. */ |
| 872 | memset(params, 0, sizeof(*params)); |
| 873 | |
Chris Wilson | be1e341 | 2017-01-16 15:21:27 +0000 | [diff] [blame] | 874 | params->vma = cache->vma; |
| 875 | |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 876 | params->crtc.pipe = crtc->pipe; |
| 877 | params->crtc.plane = crtc->plane; |
| 878 | params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc); |
| 879 | |
Ville Syrjälä | 801c8fe | 2016-11-18 21:53:04 +0200 | [diff] [blame] | 880 | params->fb.format = cache->fb.format; |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 881 | params->fb.stride = cache->fb.stride; |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 882 | |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 883 | params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, |
| 887 | struct intel_fbc_reg_params *params2) |
| 888 | { |
| 889 | /* We can use this since intel_fbc_get_reg_params() does a memset. */ |
| 890 | return memcmp(params1, params2, sizeof(*params1)) == 0; |
| 891 | } |
| 892 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 893 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
| 894 | struct intel_crtc_state *crtc_state, |
| 895 | struct intel_plane_state *plane_state) |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 896 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 897 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 898 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 899 | |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 900 | if (!fbc_supported(dev_priv)) |
| 901 | return; |
| 902 | |
| 903 | mutex_lock(&fbc->lock); |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 904 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 905 | if (!multiple_pipes_ok(crtc, plane_state)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 906 | fbc->no_fbc_reason = "more than one pipe active"; |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 907 | goto deactivate; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 908 | } |
| 909 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 910 | if (!fbc->enabled || fbc->crtc != crtc) |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 911 | goto unlock; |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 912 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 913 | intel_fbc_update_state_cache(crtc, crtc_state, plane_state); |
Paulo Zanoni | aaf78d2 | 2016-01-19 11:35:42 -0200 | [diff] [blame] | 914 | |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 915 | deactivate: |
Paulo Zanoni | 60eb2cc | 2016-01-19 11:35:45 -0200 | [diff] [blame] | 916 | intel_fbc_deactivate(dev_priv); |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 917 | unlock: |
| 918 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 919 | } |
| 920 | |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 921 | static void __intel_fbc_post_update(struct intel_crtc *crtc) |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 922 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 923 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 924 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 925 | struct intel_fbc_reg_params old_params; |
| 926 | |
| 927 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
| 928 | |
| 929 | if (!fbc->enabled || fbc->crtc != crtc) |
| 930 | return; |
| 931 | |
| 932 | if (!intel_fbc_can_activate(crtc)) { |
| 933 | WARN_ON(fbc->active); |
| 934 | return; |
| 935 | } |
Paulo Zanoni | 615b40d7 | 2016-01-19 11:35:35 -0200 | [diff] [blame] | 936 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 937 | old_params = fbc->params; |
| 938 | intel_fbc_get_reg_params(crtc, &fbc->params); |
Paulo Zanoni | b183b3f | 2015-12-23 18:28:11 -0200 | [diff] [blame] | 939 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 940 | /* If the scanout has not changed, don't modify the FBC settings. |
| 941 | * Note that we make the fundamental assumption that the fb->obj |
| 942 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 943 | * without first being decoupled from the scanout and FBC disabled. |
| 944 | */ |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 945 | if (fbc->active && |
| 946 | intel_fbc_reg_params_equal(&old_params, &fbc->params)) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 947 | return; |
| 948 | |
Paulo Zanoni | 60eb2cc | 2016-01-19 11:35:45 -0200 | [diff] [blame] | 949 | intel_fbc_deactivate(dev_priv); |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 950 | intel_fbc_schedule_activation(crtc); |
Paulo Zanoni | 212890c | 2016-01-19 11:35:43 -0200 | [diff] [blame] | 951 | fbc->no_fbc_reason = "FBC enabled (active or scheduled)"; |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 952 | } |
| 953 | |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 954 | void intel_fbc_post_update(struct intel_crtc *crtc) |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 955 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 956 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 957 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | 754d113 | 2015-10-13 19:13:25 -0300 | [diff] [blame] | 958 | |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 959 | if (!fbc_supported(dev_priv)) |
Paulo Zanoni | 0bf73c3 | 2015-07-03 15:40:54 -0300 | [diff] [blame] | 960 | return; |
| 961 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 962 | mutex_lock(&fbc->lock); |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 963 | __intel_fbc_post_update(crtc); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 964 | mutex_unlock(&fbc->lock); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 965 | } |
| 966 | |
Paulo Zanoni | 261fe99 | 2016-01-19 11:35:40 -0200 | [diff] [blame] | 967 | static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) |
| 968 | { |
| 969 | if (fbc->enabled) |
| 970 | return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit; |
| 971 | else |
| 972 | return fbc->possible_framebuffer_bits; |
| 973 | } |
| 974 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 975 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
| 976 | unsigned int frontbuffer_bits, |
| 977 | enum fb_op_origin origin) |
| 978 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 979 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 980 | |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 981 | if (!fbc_supported(dev_priv)) |
Paulo Zanoni | 0bf73c3 | 2015-07-03 15:40:54 -0300 | [diff] [blame] | 982 | return; |
| 983 | |
Paulo Zanoni | 0dd8154 | 2016-01-19 11:35:39 -0200 | [diff] [blame] | 984 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 985 | return; |
| 986 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 987 | mutex_lock(&fbc->lock); |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 988 | |
Paulo Zanoni | 261fe99 | 2016-01-19 11:35:40 -0200 | [diff] [blame] | 989 | fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 990 | |
Paulo Zanoni | 5bc4047 | 2016-01-19 11:35:53 -0200 | [diff] [blame] | 991 | if (fbc->enabled && fbc->busy_bits) |
Paulo Zanoni | 60eb2cc | 2016-01-19 11:35:45 -0200 | [diff] [blame] | 992 | intel_fbc_deactivate(dev_priv); |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 993 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 994 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 995 | } |
| 996 | |
| 997 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 6f4551f | 2015-07-14 16:29:10 -0300 | [diff] [blame] | 998 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 999 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1000 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 1001 | |
Paulo Zanoni | 9f21833 | 2015-09-23 12:52:27 -0300 | [diff] [blame] | 1002 | if (!fbc_supported(dev_priv)) |
Paulo Zanoni | 0bf73c3 | 2015-07-03 15:40:54 -0300 | [diff] [blame] | 1003 | return; |
| 1004 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1005 | mutex_lock(&fbc->lock); |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1006 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1007 | fbc->busy_bits &= ~frontbuffer_bits; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1008 | |
Paulo Zanoni | ab28a54 | 2016-04-04 18:17:15 -0300 | [diff] [blame] | 1009 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
| 1010 | goto out; |
| 1011 | |
Paulo Zanoni | 261fe99 | 2016-01-19 11:35:40 -0200 | [diff] [blame] | 1012 | if (!fbc->busy_bits && fbc->enabled && |
| 1013 | (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { |
Paulo Zanoni | 0dd8154 | 2016-01-19 11:35:39 -0200 | [diff] [blame] | 1014 | if (fbc->active) |
Paulo Zanoni | ee7d6cfa | 2015-11-11 14:46:22 -0200 | [diff] [blame] | 1015 | intel_fbc_recompress(dev_priv); |
Paulo Zanoni | 0dd8154 | 2016-01-19 11:35:39 -0200 | [diff] [blame] | 1016 | else |
Paulo Zanoni | 1eb5223 | 2016-01-19 11:35:44 -0200 | [diff] [blame] | 1017 | __intel_fbc_post_update(fbc->crtc); |
Paulo Zanoni | 6f4551f | 2015-07-14 16:29:10 -0300 | [diff] [blame] | 1018 | } |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1019 | |
Paulo Zanoni | ab28a54 | 2016-04-04 18:17:15 -0300 | [diff] [blame] | 1020 | out: |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1021 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1022 | } |
| 1023 | |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 1024 | /** |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1025 | * intel_fbc_choose_crtc - select a CRTC to enable FBC on |
| 1026 | * @dev_priv: i915 device instance |
| 1027 | * @state: the atomic state structure |
| 1028 | * |
| 1029 | * This function looks at the proposed state for CRTCs and planes, then chooses |
| 1030 | * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to |
| 1031 | * true. |
| 1032 | * |
| 1033 | * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe |
| 1034 | * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. |
| 1035 | */ |
| 1036 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
| 1037 | struct drm_atomic_state *state) |
| 1038 | { |
| 1039 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1040 | struct drm_plane *plane; |
| 1041 | struct drm_plane_state *plane_state; |
Paulo Zanoni | 4f8f225 | 2016-11-11 14:57:39 -0200 | [diff] [blame] | 1042 | bool crtc_chosen = false; |
Paulo Zanoni | ba67fab | 2016-11-11 14:57:36 -0200 | [diff] [blame] | 1043 | int i; |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1044 | |
| 1045 | mutex_lock(&fbc->lock); |
| 1046 | |
Paulo Zanoni | 4f8f225 | 2016-11-11 14:57:39 -0200 | [diff] [blame] | 1047 | /* Does this atomic commit involve the CRTC currently tied to FBC? */ |
| 1048 | if (fbc->crtc && |
| 1049 | !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base)) |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1050 | goto out; |
| 1051 | |
Paulo Zanoni | ee2be30 | 2016-11-11 14:57:37 -0200 | [diff] [blame] | 1052 | if (!intel_fbc_can_enable(dev_priv)) |
| 1053 | goto out; |
| 1054 | |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1055 | /* Simply choose the first CRTC that is compatible and has a visible |
| 1056 | * plane. We could go for fancier schemes such as checking the plane |
| 1057 | * size, but this would just affect the few platforms that don't tie FBC |
| 1058 | * to pipe or plane A. */ |
Maarten Lankhorst | e96b206 | 2017-03-09 15:52:02 +0100 | [diff] [blame] | 1059 | for_each_new_plane_in_state(state, plane, plane_state, i) { |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1060 | struct intel_plane_state *intel_plane_state = |
| 1061 | to_intel_plane_state(plane_state); |
Paulo Zanoni | ba67fab | 2016-11-11 14:57:36 -0200 | [diff] [blame] | 1062 | struct intel_crtc_state *intel_crtc_state; |
Paulo Zanoni | f7e9b00 | 2016-11-11 14:57:38 -0200 | [diff] [blame] | 1063 | struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc); |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1064 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 1065 | if (!intel_plane_state->base.visible) |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1066 | continue; |
| 1067 | |
Paulo Zanoni | f7e9b00 | 2016-11-11 14:57:38 -0200 | [diff] [blame] | 1068 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) |
| 1069 | continue; |
| 1070 | |
| 1071 | if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) |
Paulo Zanoni | 03e3910 | 2016-11-11 14:57:35 -0200 | [diff] [blame] | 1072 | continue; |
| 1073 | |
Paulo Zanoni | ba67fab | 2016-11-11 14:57:36 -0200 | [diff] [blame] | 1074 | intel_crtc_state = to_intel_crtc_state( |
Paulo Zanoni | f7e9b00 | 2016-11-11 14:57:38 -0200 | [diff] [blame] | 1075 | drm_atomic_get_existing_crtc_state(state, &crtc->base)); |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1076 | |
Paulo Zanoni | ba67fab | 2016-11-11 14:57:36 -0200 | [diff] [blame] | 1077 | intel_crtc_state->enable_fbc = true; |
Paulo Zanoni | f7e9b00 | 2016-11-11 14:57:38 -0200 | [diff] [blame] | 1078 | crtc_chosen = true; |
Paulo Zanoni | ba67fab | 2016-11-11 14:57:36 -0200 | [diff] [blame] | 1079 | break; |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1080 | } |
| 1081 | |
Paulo Zanoni | f7e9b00 | 2016-11-11 14:57:38 -0200 | [diff] [blame] | 1082 | if (!crtc_chosen) |
| 1083 | fbc->no_fbc_reason = "no suitable CRTC for FBC"; |
| 1084 | |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1085 | out: |
| 1086 | mutex_unlock(&fbc->lock); |
| 1087 | } |
| 1088 | |
| 1089 | /** |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1090 | * intel_fbc_enable: tries to enable FBC on the CRTC |
| 1091 | * @crtc: the CRTC |
Daniel Vetter | 62f90b3 | 2016-07-15 21:48:07 +0200 | [diff] [blame] | 1092 | * @crtc_state: corresponding &drm_crtc_state for @crtc |
| 1093 | * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1094 | * |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1095 | * This function checks if the given CRTC was chosen for FBC, then enables it if |
Paulo Zanoni | 49227c4 | 2016-01-19 11:35:52 -0200 | [diff] [blame] | 1096 | * possible. Notice that it doesn't activate FBC. It is valid to call |
| 1097 | * intel_fbc_enable multiple times for the same pipe without an |
| 1098 | * intel_fbc_disable in the middle, as long as it is deactivated. |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1099 | */ |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 1100 | void intel_fbc_enable(struct intel_crtc *crtc, |
| 1101 | struct intel_crtc_state *crtc_state, |
| 1102 | struct intel_plane_state *plane_state) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1103 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1104 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1105 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1106 | |
| 1107 | if (!fbc_supported(dev_priv)) |
| 1108 | return; |
| 1109 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1110 | mutex_lock(&fbc->lock); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1111 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1112 | if (fbc->enabled) { |
Paulo Zanoni | 49227c4 | 2016-01-19 11:35:52 -0200 | [diff] [blame] | 1113 | WARN_ON(fbc->crtc == NULL); |
| 1114 | if (fbc->crtc == crtc) { |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 1115 | WARN_ON(!crtc_state->enable_fbc); |
Paulo Zanoni | 49227c4 | 2016-01-19 11:35:52 -0200 | [diff] [blame] | 1116 | WARN_ON(fbc->active); |
| 1117 | } |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1118 | goto out; |
| 1119 | } |
| 1120 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 1121 | if (!crtc_state->enable_fbc) |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 1122 | goto out; |
| 1123 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1124 | WARN_ON(fbc->active); |
| 1125 | WARN_ON(fbc->crtc != NULL); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1126 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 1127 | intel_fbc_update_state_cache(crtc, crtc_state, plane_state); |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 1128 | if (intel_fbc_alloc_cfb(crtc)) { |
Paulo Zanoni | 913a3a6 | 2016-01-19 11:35:54 -0200 | [diff] [blame] | 1129 | fbc->no_fbc_reason = "not enough stolen memory"; |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 1130 | goto out; |
| 1131 | } |
| 1132 | |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1133 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1134 | fbc->no_fbc_reason = "FBC enabled but not active yet\n"; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1135 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1136 | fbc->enabled = true; |
| 1137 | fbc->crtc = crtc; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1138 | out: |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1139 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1140 | } |
| 1141 | |
| 1142 | /** |
| 1143 | * __intel_fbc_disable - disable FBC |
| 1144 | * @dev_priv: i915 device instance |
| 1145 | * |
| 1146 | * This is the low level function that actually disables FBC. Callers should |
| 1147 | * grab the FBC lock. |
| 1148 | */ |
| 1149 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
| 1150 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1151 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 1152 | struct intel_crtc *crtc = fbc->crtc; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1153 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1154 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
| 1155 | WARN_ON(!fbc->enabled); |
| 1156 | WARN_ON(fbc->active); |
Paulo Zanoni | 58f9c0b | 2016-01-19 11:35:51 -0200 | [diff] [blame] | 1157 | WARN_ON(crtc->active); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1158 | |
| 1159 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
| 1160 | |
Paulo Zanoni | c5ecd46 | 2015-10-15 14:19:21 -0300 | [diff] [blame] | 1161 | __intel_fbc_cleanup_cfb(dev_priv); |
| 1162 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1163 | fbc->enabled = false; |
| 1164 | fbc->crtc = NULL; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1165 | } |
| 1166 | |
| 1167 | /** |
Paulo Zanoni | c937ab3e5 | 2016-01-19 11:35:46 -0200 | [diff] [blame] | 1168 | * intel_fbc_disable - disable FBC if it's associated with crtc |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1169 | * @crtc: the CRTC |
| 1170 | * |
| 1171 | * This function disables FBC if it's associated with the provided CRTC. |
| 1172 | */ |
Paulo Zanoni | c937ab3e5 | 2016-01-19 11:35:46 -0200 | [diff] [blame] | 1173 | void intel_fbc_disable(struct intel_crtc *crtc) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1174 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1175 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1176 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1177 | |
| 1178 | if (!fbc_supported(dev_priv)) |
| 1179 | return; |
| 1180 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1181 | mutex_lock(&fbc->lock); |
Matthew Auld | 4da4561 | 2016-07-05 10:28:34 +0100 | [diff] [blame] | 1182 | if (fbc->crtc == crtc) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1183 | __intel_fbc_disable(dev_priv); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1184 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | 65c7600 | 2016-01-19 11:35:47 -0200 | [diff] [blame] | 1185 | |
| 1186 | cancel_work_sync(&fbc->work.work); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | /** |
Paulo Zanoni | c937ab3e5 | 2016-01-19 11:35:46 -0200 | [diff] [blame] | 1190 | * intel_fbc_global_disable - globally disable FBC |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1191 | * @dev_priv: i915 device instance |
| 1192 | * |
| 1193 | * This function disables FBC regardless of which CRTC is associated with it. |
| 1194 | */ |
Paulo Zanoni | c937ab3e5 | 2016-01-19 11:35:46 -0200 | [diff] [blame] | 1195 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1196 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1197 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 1198 | |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1199 | if (!fbc_supported(dev_priv)) |
| 1200 | return; |
| 1201 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1202 | mutex_lock(&fbc->lock); |
| 1203 | if (fbc->enabled) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1204 | __intel_fbc_disable(dev_priv); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1205 | mutex_unlock(&fbc->lock); |
Paulo Zanoni | 65c7600 | 2016-01-19 11:35:47 -0200 | [diff] [blame] | 1206 | |
| 1207 | cancel_work_sync(&fbc->work.work); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1208 | } |
| 1209 | |
Paulo Zanoni | 61a585d | 2016-09-13 10:38:57 -0300 | [diff] [blame] | 1210 | static void intel_fbc_underrun_work_fn(struct work_struct *work) |
| 1211 | { |
| 1212 | struct drm_i915_private *dev_priv = |
| 1213 | container_of(work, struct drm_i915_private, fbc.underrun_work); |
| 1214 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 1215 | |
| 1216 | mutex_lock(&fbc->lock); |
| 1217 | |
| 1218 | /* Maybe we were scheduled twice. */ |
| 1219 | if (fbc->underrun_detected) |
| 1220 | goto out; |
| 1221 | |
| 1222 | DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); |
| 1223 | fbc->underrun_detected = true; |
| 1224 | |
| 1225 | intel_fbc_deactivate(dev_priv); |
| 1226 | out: |
| 1227 | mutex_unlock(&fbc->lock); |
| 1228 | } |
| 1229 | |
| 1230 | /** |
| 1231 | * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun |
| 1232 | * @dev_priv: i915 device instance |
| 1233 | * |
| 1234 | * Without FBC, most underruns are harmless and don't really cause too many |
| 1235 | * problems, except for an annoying message on dmesg. With FBC, underruns can |
| 1236 | * become black screens or even worse, especially when paired with bad |
| 1237 | * watermarks. So in order for us to be on the safe side, completely disable FBC |
| 1238 | * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe |
| 1239 | * already suggests that watermarks may be bad, so try to be as safe as |
| 1240 | * possible. |
| 1241 | * |
| 1242 | * This function is called from the IRQ handler. |
| 1243 | */ |
| 1244 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) |
| 1245 | { |
| 1246 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 1247 | |
| 1248 | if (!fbc_supported(dev_priv)) |
| 1249 | return; |
| 1250 | |
| 1251 | /* There's no guarantee that underrun_detected won't be set to true |
| 1252 | * right after this check and before the work is scheduled, but that's |
| 1253 | * not a problem since we'll check it again under the work function |
| 1254 | * while FBC is locked. This check here is just to prevent us from |
| 1255 | * unnecessarily scheduling the work, and it relies on the fact that we |
| 1256 | * never switch underrun_detect back to false after it's true. */ |
| 1257 | if (READ_ONCE(fbc->underrun_detected)) |
| 1258 | return; |
| 1259 | |
| 1260 | schedule_work(&fbc->underrun_work); |
| 1261 | } |
| 1262 | |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 1263 | /** |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 1264 | * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking |
| 1265 | * @dev_priv: i915 device instance |
| 1266 | * |
| 1267 | * The FBC code needs to track CRTC visibility since the older platforms can't |
| 1268 | * have FBC enabled while multiple pipes are used. This function does the |
| 1269 | * initial setup at driver load to make sure FBC is matching the real hardware. |
| 1270 | */ |
| 1271 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv) |
| 1272 | { |
| 1273 | struct intel_crtc *crtc; |
| 1274 | |
| 1275 | /* Don't even bother tracking anything if we don't need. */ |
| 1276 | if (!no_fbc_on_multiple_pipes(dev_priv)) |
| 1277 | return; |
| 1278 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1279 | for_each_intel_crtc(&dev_priv->drm, crtc) |
Ville Syrjälä | 525b931 | 2016-10-31 22:37:02 +0200 | [diff] [blame] | 1280 | if (intel_crtc_active(crtc) && |
Maarten Lankhorst | 1d4258d | 2017-01-12 10:43:45 +0100 | [diff] [blame] | 1281 | crtc->base.primary->state->visible) |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 1282 | dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe); |
| 1283 | } |
| 1284 | |
Paulo Zanoni | 80788a0 | 2016-04-13 16:01:09 -0300 | [diff] [blame] | 1285 | /* |
| 1286 | * The DDX driver changes its behavior depending on the value it reads from |
| 1287 | * i915.enable_fbc, so sanitize it by translating the default value into either |
| 1288 | * 0 or 1 in order to allow it to know what's going on. |
| 1289 | * |
| 1290 | * Notice that this is done at driver initialization and we still allow user |
| 1291 | * space to change the value during runtime without sanitizing it again. IGT |
| 1292 | * relies on being able to change i915.enable_fbc at runtime. |
| 1293 | */ |
| 1294 | static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) |
| 1295 | { |
| 1296 | if (i915.enable_fbc >= 0) |
| 1297 | return !!i915.enable_fbc; |
| 1298 | |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1299 | if (!HAS_FBC(dev_priv)) |
| 1300 | return 0; |
| 1301 | |
Paulo Zanoni | fd7d6c5 | 2016-12-23 10:23:58 -0200 | [diff] [blame] | 1302 | if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) |
Paulo Zanoni | 80788a0 | 2016-04-13 16:01:09 -0300 | [diff] [blame] | 1303 | return 1; |
| 1304 | |
| 1305 | return 0; |
| 1306 | } |
| 1307 | |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1308 | static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) |
| 1309 | { |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1310 | /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ |
Chris Wilson | 80debff | 2017-05-25 13:16:12 +0100 | [diff] [blame] | 1311 | if (intel_vtd_active() && |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1312 | (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { |
| 1313 | DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); |
| 1314 | return true; |
| 1315 | } |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1316 | |
| 1317 | return false; |
| 1318 | } |
| 1319 | |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 1320 | /** |
Rodrigo Vivi | 94b8395 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 1321 | * intel_fbc_init - Initialize FBC |
| 1322 | * @dev_priv: the i915 device |
| 1323 | * |
| 1324 | * This function might be called during PM init process. |
| 1325 | */ |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1326 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
| 1327 | { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1328 | struct intel_fbc *fbc = &dev_priv->fbc; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1329 | enum pipe pipe; |
| 1330 | |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1331 | INIT_WORK(&fbc->work.work, intel_fbc_work_fn); |
Paulo Zanoni | 61a585d | 2016-09-13 10:38:57 -0300 | [diff] [blame] | 1332 | INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1333 | mutex_init(&fbc->lock); |
| 1334 | fbc->enabled = false; |
| 1335 | fbc->active = false; |
| 1336 | fbc->work.scheduled = false; |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1337 | |
Chris Wilson | 36dbc4d | 2016-08-04 08:43:53 +0100 | [diff] [blame] | 1338 | if (need_fbc_vtd_wa(dev_priv)) |
| 1339 | mkwrite_device_info(dev_priv)->has_fbc = false; |
| 1340 | |
Paulo Zanoni | 80788a0 | 2016-04-13 16:01:09 -0300 | [diff] [blame] | 1341 | i915.enable_fbc = intel_sanitize_fbc_option(dev_priv); |
| 1342 | DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc); |
| 1343 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1344 | if (!HAS_FBC(dev_priv)) { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1345 | fbc->no_fbc_reason = "unsupported by this chipset"; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1346 | return; |
| 1347 | } |
| 1348 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1349 | for_each_pipe(dev_priv, pipe) { |
Paulo Zanoni | ab34a7e | 2016-01-11 17:44:36 -0200 | [diff] [blame] | 1350 | fbc->possible_framebuffer_bits |= |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1351 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
| 1352 | |
Paulo Zanoni | 5710502 | 2015-11-04 17:10:46 -0200 | [diff] [blame] | 1353 | if (fbc_on_pipe_a_only(dev_priv)) |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 1354 | break; |
| 1355 | } |
| 1356 | |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 1357 | /* This value was pulled out of someone's hat */ |
Paulo Zanoni | 5697d60 | 2016-11-11 14:57:41 -0200 | [diff] [blame] | 1358 | if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1359 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1360 | |
Paulo Zanoni | b07ea0f | 2015-11-04 17:10:52 -0200 | [diff] [blame] | 1361 | /* We still don't have any sort of hardware state readout for FBC, so |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 1362 | * deactivate it in case the BIOS activated it to make sure software |
| 1363 | * matches the hardware state. */ |
Paulo Zanoni | 8c40074 | 2016-01-29 18:57:39 -0200 | [diff] [blame] | 1364 | if (intel_fbc_hw_is_active(dev_priv)) |
| 1365 | intel_fbc_hw_deactivate(dev_priv); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1366 | } |