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Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
Rodrigo Vivi94b83952014-12-08 06:46:31 -080024/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020030 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
Rodrigo Vivi94b83952014-12-08 06:46:31 -080032 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020034 *
Rodrigo Vivi94b83952014-12-08 06:46:31 -080035 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020039 */
40
Rodrigo Vivi94b83952014-12-08 06:46:31 -080041#include "intel_drv.h"
42#include "i915_drv.h"
43
Paulo Zanoni9f218332015-09-23 12:52:27 -030044static inline bool fbc_supported(struct drm_i915_private *dev_priv)
45{
Paulo Zanoni8c400742016-01-29 18:57:39 -020046 return HAS_FBC(dev_priv);
Paulo Zanoni9f218332015-09-23 12:52:27 -030047}
48
Paulo Zanoni57105022015-11-04 17:10:46 -020049static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
50{
Paulo Zanoni5697d602016-11-11 14:57:41 -020051 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
Paulo Zanoni57105022015-11-04 17:10:46 -020052}
53
Paulo Zanonie6cd6dc2015-10-16 17:55:40 -030054static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
55{
Paulo Zanoni5697d602016-11-11 14:57:41 -020056 return INTEL_GEN(dev_priv) < 4;
Paulo Zanonie6cd6dc2015-10-16 17:55:40 -030057}
58
Paulo Zanoni010cf732016-01-19 11:35:48 -020059static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
60{
Paulo Zanoni5697d602016-11-11 14:57:41 -020061 return INTEL_GEN(dev_priv) <= 3;
Paulo Zanoni010cf732016-01-19 11:35:48 -020062}
63
Paulo Zanoni2db33662015-09-14 15:20:03 -030064/*
65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67 * origin so the x and y offsets can actually fit the registers. As a
68 * consequence, the fence doesn't really start exactly at the display plane
69 * address we program because it starts at the real start of the buffer, so we
70 * have to take this into consideration here.
71 */
72static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
73{
74 return crtc->base.y - crtc->adjusted_y;
75}
76
Paulo Zanonic5ecd462015-10-15 14:19:21 -030077/*
78 * For SKL+, the plane source size used by the hardware is based on the value we
79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80 * we wrote to PIPESRC.
81 */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020082static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
Paulo Zanonic5ecd462015-10-15 14:19:21 -030083 int *width, int *height)
84{
Paulo Zanonic5ecd462015-10-15 14:19:21 -030085 if (width)
Ville Syrjälä73714c02017-03-31 21:00:56 +030086 *width = cache->plane.src_w;
Paulo Zanonic5ecd462015-10-15 14:19:21 -030087 if (height)
Ville Syrjälä73714c02017-03-31 21:00:56 +030088 *height = cache->plane.src_h;
Paulo Zanonic5ecd462015-10-15 14:19:21 -030089}
90
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020091static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
92 struct intel_fbc_state_cache *cache)
Paulo Zanonic5ecd462015-10-15 14:19:21 -030093{
Paulo Zanonic5ecd462015-10-15 14:19:21 -030094 int lines;
95
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020096 intel_fbc_get_plane_source_size(cache, NULL, &lines);
Paulo Zanoni79f26242016-10-21 13:55:45 -020097 if (INTEL_GEN(dev_priv) == 7)
Paulo Zanonic5ecd462015-10-15 14:19:21 -030098 lines = min(lines, 2048);
Paulo Zanoni79f26242016-10-21 13:55:45 -020099 else if (INTEL_GEN(dev_priv) >= 8)
100 lines = min(lines, 2560);
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300101
102 /* Hardware needs the full buffer stride, not just the active area. */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200103 return lines * cache->fb.stride;
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300104}
105
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300106static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200107{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200108 u32 fbc_ctl;
109
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200110 /* Disable compression */
111 fbc_ctl = I915_READ(FBC_CONTROL);
112 if ((fbc_ctl & FBC_CTL_EN) == 0)
113 return;
114
115 fbc_ctl &= ~FBC_CTL_EN;
116 I915_WRITE(FBC_CONTROL, fbc_ctl);
117
118 /* Wait for compressing bit to clear */
Chris Wilson8d90dfd2016-06-30 15:33:21 +0100119 if (intel_wait_for_register(dev_priv,
120 FBC_STATUS, FBC_STAT_COMPRESSING, 0,
121 10)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200122 DRM_DEBUG_KMS("FBC idle timed out\n");
123 return;
124 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200125}
126
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200127static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200128{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200129 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200130 int cfb_pitch;
131 int i;
132 u32 fbc_ctl;
133
Jani Nikula60ee5cd2015-02-05 12:04:27 +0200134 /* Note: fbc.threshold == 1 for i8xx */
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200135 cfb_pitch = params->cfb_size / FBC_LL_SIZE;
136 if (params->fb.stride < cfb_pitch)
137 cfb_pitch = params->fb.stride;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200138
139 /* FBC_CTL wants 32B or 64B units */
Paulo Zanoni7733b492015-07-07 15:26:04 -0300140 if (IS_GEN2(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200141 cfb_pitch = (cfb_pitch / 32) - 1;
142 else
143 cfb_pitch = (cfb_pitch / 64) - 1;
144
145 /* Clear old tags */
146 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
Ville Syrjälä4d110c72015-09-18 20:03:18 +0300147 I915_WRITE(FBC_TAG(i), 0);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200148
Paulo Zanoni7733b492015-07-07 15:26:04 -0300149 if (IS_GEN4(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200150 u32 fbc_ctl2;
151
152 /* Set it up... */
153 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200154 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200155 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200156 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200157 }
158
159 /* enable it... */
160 fbc_ctl = I915_READ(FBC_CONTROL);
161 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
162 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
Paulo Zanoni7733b492015-07-07 15:26:04 -0300163 if (IS_I945GM(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200164 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
165 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000166 fbc_ctl |= params->vma->fence->id;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200167 I915_WRITE(FBC_CONTROL, fbc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200168}
169
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300170static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200171{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200172 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
173}
174
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200175static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200176{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200177 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200178 u32 dpfc_ctl;
179
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200180 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200181 if (params->fb.format->cpp[0] == 2)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200182 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
183 else
184 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200185
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000186 if (params->vma->fence) {
187 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100188 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
189 } else {
190 I915_WRITE(DPFC_FENCE_YOFF, 0);
191 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200192
193 /* enable it... */
194 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200195}
196
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300197static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200198{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200199 u32 dpfc_ctl;
200
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200201 /* Disable compression */
202 dpfc_ctl = I915_READ(DPFC_CONTROL);
203 if (dpfc_ctl & DPFC_CTL_EN) {
204 dpfc_ctl &= ~DPFC_CTL_EN;
205 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200206 }
207}
208
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300209static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200210{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200211 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
212}
213
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200214/* This function forces a CFB recompression through the nuke operation. */
215static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200216{
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200217 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
218 POSTING_READ(MSG_FBC_REND_STATE);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200219}
220
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200221static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200222{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200223 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200224 u32 dpfc_ctl;
Paulo Zanonice65e472015-06-30 10:53:05 -0300225 int threshold = dev_priv->fbc.threshold;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200226
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200227 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200228 if (params->fb.format->cpp[0] == 2)
Paulo Zanonice65e472015-06-30 10:53:05 -0300229 threshold++;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200230
Paulo Zanonice65e472015-06-30 10:53:05 -0300231 switch (threshold) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100243
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000244 if (params->vma->fence) {
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100245 dpfc_ctl |= DPFC_CTL_FENCE_EN;
246 if (IS_GEN5(dev_priv))
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000247 dpfc_ctl |= params->vma->fence->id;
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100248 if (IS_GEN6(dev_priv)) {
249 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000250 SNB_CPU_FENCE_ENABLE |
251 params->vma->fence->id);
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100252 I915_WRITE(DPFC_CPU_FENCE_OFFSET,
253 params->crtc.fence_y_offset);
254 }
255 } else {
256 if (IS_GEN6(dev_priv)) {
257 I915_WRITE(SNB_DPFC_CTL_SA, 0);
258 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
259 }
260 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200261
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200262 I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000263 I915_WRITE(ILK_FBC_RT_BASE,
264 i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200265 /* enable it... */
266 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
267
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200268 intel_fbc_recompress(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200269}
270
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300271static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200272{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200273 u32 dpfc_ctl;
274
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200275 /* Disable compression */
276 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
277 if (dpfc_ctl & DPFC_CTL_EN) {
278 dpfc_ctl &= ~DPFC_CTL_EN;
279 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200280 }
281}
282
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300283static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200284{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200285 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
286}
287
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200288static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200289{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200290 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200291 u32 dpfc_ctl;
Paulo Zanonice65e472015-06-30 10:53:05 -0300292 int threshold = dev_priv->fbc.threshold;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200293
Paulo Zanonid8514d62015-06-12 14:36:21 -0300294 dpfc_ctl = 0;
Paulo Zanoni7733b492015-07-07 15:26:04 -0300295 if (IS_IVYBRIDGE(dev_priv))
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200296 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
Paulo Zanonid8514d62015-06-12 14:36:21 -0300297
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200298 if (params->fb.format->cpp[0] == 2)
Paulo Zanonice65e472015-06-30 10:53:05 -0300299 threshold++;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200300
Paulo Zanonice65e472015-06-30 10:53:05 -0300301 switch (threshold) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200302 case 4:
303 case 3:
304 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
305 break;
306 case 2:
307 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
308 break;
309 case 1:
310 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
311 break;
312 }
313
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000314 if (params->vma->fence) {
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100315 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
316 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000317 SNB_CPU_FENCE_ENABLE |
318 params->vma->fence->id);
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100319 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
320 } else {
321 I915_WRITE(SNB_DPFC_CTL_SA,0);
322 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
323 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200324
325 if (dev_priv->fbc.false_color)
326 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
327
Paulo Zanoni7733b492015-07-07 15:26:04 -0300328 if (IS_IVYBRIDGE(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200329 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
330 I915_WRITE(ILK_DISPLAY_CHICKEN1,
331 I915_READ(ILK_DISPLAY_CHICKEN1) |
332 ILK_FBCQ_DIS);
Paulo Zanoni40f40222015-09-14 15:20:01 -0300333 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200334 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200335 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
336 I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200337 HSW_FBCQ_DIS);
338 }
339
Paulo Zanoni57012be92015-09-14 15:20:00 -0300340 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
341
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200342 intel_fbc_recompress(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200343}
344
Paulo Zanoni8c400742016-01-29 18:57:39 -0200345static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
346{
Paulo Zanoni5697d602016-11-11 14:57:41 -0200347 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200348 return ilk_fbc_is_active(dev_priv);
349 else if (IS_GM45(dev_priv))
350 return g4x_fbc_is_active(dev_priv);
351 else
352 return i8xx_fbc_is_active(dev_priv);
353}
354
355static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
356{
Paulo Zanoni5375ce92016-01-29 18:57:40 -0200357 struct intel_fbc *fbc = &dev_priv->fbc;
358
359 fbc->active = true;
360
Paulo Zanoni5697d602016-11-11 14:57:41 -0200361 if (INTEL_GEN(dev_priv) >= 7)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200362 gen7_fbc_activate(dev_priv);
Paulo Zanoni5697d602016-11-11 14:57:41 -0200363 else if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200364 ilk_fbc_activate(dev_priv);
365 else if (IS_GM45(dev_priv))
366 g4x_fbc_activate(dev_priv);
367 else
368 i8xx_fbc_activate(dev_priv);
369}
370
371static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
372{
Paulo Zanoni5375ce92016-01-29 18:57:40 -0200373 struct intel_fbc *fbc = &dev_priv->fbc;
374
375 fbc->active = false;
376
Paulo Zanoni5697d602016-11-11 14:57:41 -0200377 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200378 ilk_fbc_deactivate(dev_priv);
379 else if (IS_GM45(dev_priv))
380 g4x_fbc_deactivate(dev_priv);
381 else
382 i8xx_fbc_deactivate(dev_priv);
383}
384
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800385/**
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300386 * intel_fbc_is_active - Is FBC active?
Paulo Zanoni7733b492015-07-07 15:26:04 -0300387 * @dev_priv: i915 device instance
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800388 *
389 * This function is used to verify the current state of FBC.
Daniel Vetter2e7a5702016-06-01 23:40:36 +0200390 *
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800391 * FIXME: This should be tracked in the plane config eventually
Daniel Vetter2e7a5702016-06-01 23:40:36 +0200392 * instead of queried at runtime for most callers.
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800393 */
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300394bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200395{
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300396 return dev_priv->fbc.active;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200397}
398
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200399static void intel_fbc_work_fn(struct work_struct *__work)
400{
Paulo Zanoni128d7352015-10-26 16:27:49 -0200401 struct drm_i915_private *dev_priv =
402 container_of(__work, struct drm_i915_private, fbc.work.work);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200403 struct intel_fbc *fbc = &dev_priv->fbc;
404 struct intel_fbc_work *work = &fbc->work;
405 struct intel_crtc *crtc = fbc->crtc;
Chris Wilson91c8a322016-07-05 10:40:23 +0100406 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
Paulo Zanonica18d512016-01-21 18:03:05 -0200407
408 if (drm_crtc_vblank_get(&crtc->base)) {
409 DRM_ERROR("vblank not available for FBC on pipe %c\n",
410 pipe_name(crtc->pipe));
411
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200412 mutex_lock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200413 work->scheduled = false;
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200414 mutex_unlock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200415 return;
416 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200417
Paulo Zanoni128d7352015-10-26 16:27:49 -0200418retry:
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200419 /* Delay the actual enabling to let pageflipping cease and the
420 * display to settle before starting the compression. Note that
421 * this delay also serves a second purpose: it allows for a
422 * vblank to pass after disabling the FBC before we attempt
423 * to modify the control registers.
424 *
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200425 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
Paulo Zanonica18d512016-01-21 18:03:05 -0200426 *
427 * It is also worth mentioning that since work->scheduled_vblank can be
428 * updated multiple times by the other threads, hitting the timeout is
429 * not an error condition. We'll just end up hitting the "goto retry"
430 * case below.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200431 */
Paulo Zanonica18d512016-01-21 18:03:05 -0200432 wait_event_timeout(vblank->queue,
433 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
434 msecs_to_jiffies(50));
Paulo Zanoni128d7352015-10-26 16:27:49 -0200435
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200436 mutex_lock(&fbc->lock);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200437
438 /* Were we cancelled? */
439 if (!work->scheduled)
440 goto out;
441
442 /* Were we delayed again while this function was sleeping? */
Paulo Zanonica18d512016-01-21 18:03:05 -0200443 if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200444 mutex_unlock(&fbc->lock);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200445 goto retry;
446 }
447
Paulo Zanoni8c400742016-01-29 18:57:39 -0200448 intel_fbc_hw_activate(dev_priv);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200449
450 work->scheduled = false;
451
452out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200453 mutex_unlock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200454 drm_crtc_vblank_put(&crtc->base);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200455}
456
Paulo Zanoni128d7352015-10-26 16:27:49 -0200457static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
458{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100459 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200460 struct intel_fbc *fbc = &dev_priv->fbc;
461 struct intel_fbc_work *work = &fbc->work;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200462
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200463 WARN_ON(!mutex_is_locked(&fbc->lock));
Paulo Zanoni128d7352015-10-26 16:27:49 -0200464
Paulo Zanonica18d512016-01-21 18:03:05 -0200465 if (drm_crtc_vblank_get(&crtc->base)) {
466 DRM_ERROR("vblank not available for FBC on pipe %c\n",
467 pipe_name(crtc->pipe));
468 return;
469 }
470
Paulo Zanonie35be232016-01-18 15:56:58 -0200471 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
472 * this function since we're not releasing fbc.lock, so it won't have an
473 * opportunity to grab it to discover that it was cancelled. So we just
474 * update the expected jiffy count. */
Paulo Zanoni128d7352015-10-26 16:27:49 -0200475 work->scheduled = true;
Paulo Zanonica18d512016-01-21 18:03:05 -0200476 work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
477 drm_crtc_vblank_put(&crtc->base);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200478
479 schedule_work(&work->work);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200480}
481
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200482static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300483{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200484 struct intel_fbc *fbc = &dev_priv->fbc;
485
486 WARN_ON(!mutex_is_locked(&fbc->lock));
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300487
Paulo Zanonie35be232016-01-18 15:56:58 -0200488 /* Calling cancel_work() here won't help due to the fact that the work
489 * function grabs fbc->lock. Just set scheduled to false so the work
490 * function can know it was cancelled. */
491 fbc->work.scheduled = false;
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300492
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200493 if (fbc->active)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200494 intel_fbc_hw_deactivate(dev_priv);
Paulo Zanoni754d1132015-10-13 19:13:25 -0300495}
496
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200497static bool multiple_pipes_ok(struct intel_crtc *crtc,
498 struct intel_plane_state *plane_state)
Paulo Zanoni232fd932015-07-07 15:26:07 -0300499{
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoni010cf732016-01-19 11:35:48 -0200501 struct intel_fbc *fbc = &dev_priv->fbc;
502 enum pipe pipe = crtc->pipe;
Paulo Zanoni232fd932015-07-07 15:26:07 -0300503
Paulo Zanoni010cf732016-01-19 11:35:48 -0200504 /* Don't even bother tracking anything we don't need. */
505 if (!no_fbc_on_multiple_pipes(dev_priv))
Paulo Zanoni232fd932015-07-07 15:26:07 -0300506 return true;
507
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300508 if (plane_state->base.visible)
Paulo Zanoni010cf732016-01-19 11:35:48 -0200509 fbc->visible_pipes_mask |= (1 << pipe);
510 else
511 fbc->visible_pipes_mask &= ~(1 << pipe);
Paulo Zanoni232fd932015-07-07 15:26:07 -0300512
Paulo Zanoni010cf732016-01-19 11:35:48 -0200513 return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
Paulo Zanoni232fd932015-07-07 15:26:07 -0300514}
515
Paulo Zanoni7733b492015-07-07 15:26:04 -0300516static int find_compression_threshold(struct drm_i915_private *dev_priv,
Paulo Zanonifc786722015-07-02 19:25:08 -0300517 struct drm_mm_node *node,
518 int size,
519 int fb_cpp)
520{
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300521 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Paulo Zanonifc786722015-07-02 19:25:08 -0300522 int compression_threshold = 1;
523 int ret;
Paulo Zanonia9da5122015-09-14 15:19:57 -0300524 u64 end;
525
526 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
527 * reserved range size, so it always assumes the maximum (8mb) is used.
528 * If we enable FBC using a CFB on that memory range we'll get FIFO
529 * underruns, even if that range is not reserved by the BIOS. */
Rodrigo Vivib976dc52017-01-23 10:32:37 -0800530 if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300531 end = ggtt->stolen_size - 8 * 1024 * 1024;
Paulo Zanonia9da5122015-09-14 15:19:57 -0300532 else
Paulo Zanoni3c6b29b2016-12-15 11:23:55 -0200533 end = U64_MAX;
Paulo Zanonifc786722015-07-02 19:25:08 -0300534
535 /* HACK: This code depends on what we will do in *_enable_fbc. If that
536 * code changes, this code needs to change as well.
537 *
538 * The enable_fbc code will attempt to use one of our 2 compression
539 * thresholds, therefore, in that case, we only have 1 resort.
540 */
541
542 /* Try to over-allocate to reduce reallocations and fragmentation. */
Paulo Zanonia9da5122015-09-14 15:19:57 -0300543 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
544 4096, 0, end);
Paulo Zanonifc786722015-07-02 19:25:08 -0300545 if (ret == 0)
546 return compression_threshold;
547
548again:
549 /* HW's ability to limit the CFB is 1:4 */
550 if (compression_threshold > 4 ||
551 (fb_cpp == 2 && compression_threshold == 2))
552 return 0;
553
Paulo Zanonia9da5122015-09-14 15:19:57 -0300554 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
555 4096, 0, end);
Paulo Zanoni5697d602016-11-11 14:57:41 -0200556 if (ret && INTEL_GEN(dev_priv) <= 4) {
Paulo Zanonifc786722015-07-02 19:25:08 -0300557 return 0;
558 } else if (ret) {
559 compression_threshold <<= 1;
560 goto again;
561 } else {
562 return compression_threshold;
563 }
564}
565
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300566static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
Paulo Zanonifc786722015-07-02 19:25:08 -0300567{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200569 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonifc786722015-07-02 19:25:08 -0300570 struct drm_mm_node *uninitialized_var(compressed_llb);
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300571 int size, fb_cpp, ret;
572
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200573 WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300574
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200575 size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200576 fb_cpp = fbc->state_cache.fb.format->cpp[0];
Paulo Zanonifc786722015-07-02 19:25:08 -0300577
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200578 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
Paulo Zanonifc786722015-07-02 19:25:08 -0300579 size, fb_cpp);
580 if (!ret)
581 goto err_llb;
582 else if (ret > 1) {
583 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
584
585 }
586
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200587 fbc->threshold = ret;
Paulo Zanonifc786722015-07-02 19:25:08 -0300588
Paulo Zanoni5697d602016-11-11 14:57:41 -0200589 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200590 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300591 else if (IS_GM45(dev_priv)) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200592 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
Paulo Zanonifc786722015-07-02 19:25:08 -0300593 } else {
594 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
595 if (!compressed_llb)
596 goto err_fb;
597
598 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
599 4096, 4096);
600 if (ret)
601 goto err_fb;
602
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200603 fbc->compressed_llb = compressed_llb;
Paulo Zanonifc786722015-07-02 19:25:08 -0300604
605 I915_WRITE(FBC_CFB_BASE,
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200606 dev_priv->mm.stolen_base + fbc->compressed_fb.start);
Paulo Zanonifc786722015-07-02 19:25:08 -0300607 I915_WRITE(FBC_LL_BASE,
608 dev_priv->mm.stolen_base + compressed_llb->start);
609 }
610
Paulo Zanonib8bf5d72015-09-14 15:19:58 -0300611 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200612 fbc->compressed_fb.size, fbc->threshold);
Paulo Zanonifc786722015-07-02 19:25:08 -0300613
614 return 0;
615
616err_fb:
617 kfree(compressed_llb);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200618 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
Paulo Zanonifc786722015-07-02 19:25:08 -0300619err_llb:
Chris Wilson8d0e9bc2017-02-23 12:20:37 +0000620 if (drm_mm_initialized(&dev_priv->mm.stolen))
621 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
Paulo Zanonifc786722015-07-02 19:25:08 -0300622 return -ENOSPC;
623}
624
Paulo Zanoni7733b492015-07-07 15:26:04 -0300625static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
Paulo Zanonifc786722015-07-02 19:25:08 -0300626{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200627 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonifc786722015-07-02 19:25:08 -0300628
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200629 if (drm_mm_node_allocated(&fbc->compressed_fb))
630 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
631
632 if (fbc->compressed_llb) {
633 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
634 kfree(fbc->compressed_llb);
Paulo Zanonifc786722015-07-02 19:25:08 -0300635 }
Paulo Zanonifc786722015-07-02 19:25:08 -0300636}
637
Paulo Zanoni7733b492015-07-07 15:26:04 -0300638void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300639{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200640 struct intel_fbc *fbc = &dev_priv->fbc;
641
Paulo Zanoni9f218332015-09-23 12:52:27 -0300642 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300643 return;
644
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200645 mutex_lock(&fbc->lock);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300646 __intel_fbc_cleanup_cfb(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200647 mutex_unlock(&fbc->lock);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300648}
649
Paulo Zanoniadf70c62015-09-14 15:19:56 -0300650static bool stride_is_valid(struct drm_i915_private *dev_priv,
651 unsigned int stride)
652{
653 /* These should have been caught earlier. */
654 WARN_ON(stride < 512);
655 WARN_ON((stride & (64 - 1)) != 0);
656
657 /* Below are the additional FBC restrictions. */
658
659 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
660 return stride == 4096 || stride == 8192;
661
662 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
663 return false;
664
665 if (stride > 16384)
666 return false;
667
668 return true;
669}
670
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200671static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
672 uint32_t pixel_format)
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300673{
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200674 switch (pixel_format) {
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300675 case DRM_FORMAT_XRGB8888:
676 case DRM_FORMAT_XBGR8888:
677 return true;
678 case DRM_FORMAT_XRGB1555:
679 case DRM_FORMAT_RGB565:
680 /* 16bpp not supported on gen2 */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200681 if (IS_GEN2(dev_priv))
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300682 return false;
683 /* WaFbcOnly1to1Ratio:ctg */
684 if (IS_G4X(dev_priv))
685 return false;
686 return true;
687 default:
688 return false;
689 }
690}
691
Paulo Zanoni856312a2015-10-01 19:57:12 -0300692/*
693 * For some reason, the hardware tracking starts looking at whatever we
694 * programmed as the display plane base address register. It does not look at
695 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
696 * variables instead of just looking at the pipe/plane size.
697 */
698static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300699{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200701 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni856312a2015-10-01 19:57:12 -0300702 unsigned int effective_w, effective_h, max_w, max_h;
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300703
Paulo Zanoni5697d602016-11-11 14:57:41 -0200704 if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300705 max_w = 4096;
706 max_h = 4096;
Paulo Zanoni5697d602016-11-11 14:57:41 -0200707 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300708 max_w = 4096;
709 max_h = 2048;
710 } else {
711 max_w = 2048;
712 max_h = 1536;
713 }
714
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200715 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
716 &effective_h);
Paulo Zanoni856312a2015-10-01 19:57:12 -0300717 effective_w += crtc->adjusted_x;
718 effective_h += crtc->adjusted_y;
719
720 return effective_w <= max_w && effective_h <= max_h;
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300721}
722
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200723static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
724 struct intel_crtc_state *crtc_state,
725 struct intel_plane_state *plane_state)
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200726{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200728 struct intel_fbc *fbc = &dev_priv->fbc;
729 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200730 struct drm_framebuffer *fb = plane_state->base.fb;
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000731
732 cache->vma = NULL;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200733
734 cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
735 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjäläa7d1b3f2017-01-26 21:50:31 +0200736 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200737
738 cache->plane.rotation = plane_state->base.rotation;
Ville Syrjälä73714c02017-03-31 21:00:56 +0300739 /*
740 * Src coordinates are already rotated by 270 degrees for
741 * the 90/270 degree plane rotation cases (to match the
742 * GTT mapping), hence no need to account for rotation here.
743 */
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300744 cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
745 cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
746 cache->plane.visible = plane_state->base.visible;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200747
748 if (!cache->plane.visible)
749 return;
750
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200751 cache->fb.format = fb->format;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200752 cache->fb.stride = fb->pitches[0];
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000753
754 cache->vma = plane_state->vma;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200755}
756
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200757static bool intel_fbc_can_activate(struct intel_crtc *crtc)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200758{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100759 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200760 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200761 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200762
Paulo Zanoni61a585d2016-09-13 10:38:57 -0300763 /* We don't need to use a state cache here since this information is
764 * global for all CRTC.
765 */
766 if (fbc->underrun_detected) {
767 fbc->no_fbc_reason = "underrun detected";
768 return false;
769 }
770
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000771 if (!cache->vma) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200772 fbc->no_fbc_reason = "primary plane not visible";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200773 return false;
774 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200775
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200776 if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
777 (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200778 fbc->no_fbc_reason = "incompatible mode";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200779 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200780 }
781
Paulo Zanoni45b32a22015-11-04 17:10:49 -0200782 if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200783 fbc->no_fbc_reason = "mode too large for compression";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200784 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200785 }
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300786
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200787 /* The use of a CPU fence is mandatory in order to detect writes
788 * by the CPU to the scanout and trigger updates to the FBC.
Chris Wilson2efb8132016-08-18 17:17:06 +0100789 *
790 * Note that is possible for a tiled surface to be unmappable (and
791 * so have no fence associated with it) due to aperture constaints
792 * at the time of pinning.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200793 */
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000794 if (!cache->vma->fence) {
Chris Wilsonc82dd882016-08-24 19:00:53 +0100795 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
796 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200797 }
Paulo Zanoni5697d602016-11-11 14:57:41 -0200798 if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
Robert Fossc2c446a2017-05-19 16:50:17 -0400799 cache->plane.rotation != DRM_MODE_ROTATE_0) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200800 fbc->no_fbc_reason = "rotation unsupported";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200801 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200802 }
803
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200804 if (!stride_is_valid(dev_priv, cache->fb.stride)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200805 fbc->no_fbc_reason = "framebuffer stride not supported";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200806 return false;
Paulo Zanoniadf70c62015-09-14 15:19:56 -0300807 }
808
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200809 if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200810 fbc->no_fbc_reason = "pixel format is invalid";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200811 return false;
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300812 }
813
Paulo Zanoni7b24c9a2015-09-14 15:19:59 -0300814 /* WaFbcExceedCdClockThreshold:hsw,bdw */
815 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
Ville Syrjälä49cd97a2017-02-07 20:33:45 +0200816 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200817 fbc->no_fbc_reason = "pixel rate is too big";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200818 return false;
Paulo Zanoni7b24c9a2015-09-14 15:19:59 -0300819 }
820
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300821 /* It is possible for the required CFB size change without a
822 * crtc->disable + crtc->enable since it is possible to change the
823 * stride without triggering a full modeset. Since we try to
824 * over-allocate the CFB, there's a chance we may keep FBC enabled even
825 * if this happens, but if we exceed the current CFB size we'll have to
826 * disable FBC. Notice that it would be possible to disable FBC, wait
827 * for a frame, free the stolen node, then try to reenable FBC in case
828 * we didn't get any invalidate/deactivate calls, but this would require
829 * a lot of tracking just for a specific case. If we conclude it's an
830 * important case, we can implement it later. */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200831 if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200832 fbc->compressed_fb.size * fbc->threshold) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200833 fbc->no_fbc_reason = "CFB requirements changed";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200834 return false;
835 }
836
837 return true;
838}
839
Paulo Zanoniee2be302016-11-11 14:57:37 -0200840static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200841{
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200842 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200843
Chris Wilsonc0336662016-05-06 15:40:21 +0100844 if (intel_vgpu_active(dev_priv)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200845 fbc->no_fbc_reason = "VGPU is active";
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200846 return false;
847 }
848
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200849 if (!i915.enable_fbc) {
Paulo Zanoni80788a02016-04-13 16:01:09 -0300850 fbc->no_fbc_reason = "disabled per module param or by default";
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200851 return false;
852 }
853
Paulo Zanoni61a585d2016-09-13 10:38:57 -0300854 if (fbc->underrun_detected) {
855 fbc->no_fbc_reason = "underrun detected";
856 return false;
857 }
858
Paulo Zanoniee2be302016-11-11 14:57:37 -0200859 return true;
860}
861
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200862static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
863 struct intel_fbc_reg_params *params)
864{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100865 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200866 struct intel_fbc *fbc = &dev_priv->fbc;
867 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200868
869 /* Since all our fields are integer types, use memset here so the
870 * comparison function can rely on memcmp because the padding will be
871 * zero. */
872 memset(params, 0, sizeof(*params));
873
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000874 params->vma = cache->vma;
875
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200876 params->crtc.pipe = crtc->pipe;
877 params->crtc.plane = crtc->plane;
878 params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
879
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200880 params->fb.format = cache->fb.format;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200881 params->fb.stride = cache->fb.stride;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200882
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200883 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200884}
885
886static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
887 struct intel_fbc_reg_params *params2)
888{
889 /* We can use this since intel_fbc_get_reg_params() does a memset. */
890 return memcmp(params1, params2, sizeof(*params1)) == 0;
891}
892
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200893void intel_fbc_pre_update(struct intel_crtc *crtc,
894 struct intel_crtc_state *crtc_state,
895 struct intel_plane_state *plane_state)
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200896{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200898 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200899
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200900 if (!fbc_supported(dev_priv))
901 return;
902
903 mutex_lock(&fbc->lock);
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200904
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200905 if (!multiple_pipes_ok(crtc, plane_state)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200906 fbc->no_fbc_reason = "more than one pipe active";
Paulo Zanoni212890c2016-01-19 11:35:43 -0200907 goto deactivate;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200908 }
909
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200910 if (!fbc->enabled || fbc->crtc != crtc)
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200911 goto unlock;
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200912
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200913 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200914
Paulo Zanoni212890c2016-01-19 11:35:43 -0200915deactivate:
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200916 intel_fbc_deactivate(dev_priv);
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200917unlock:
918 mutex_unlock(&fbc->lock);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200919}
920
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200921static void __intel_fbc_post_update(struct intel_crtc *crtc)
Paulo Zanoni212890c2016-01-19 11:35:43 -0200922{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200924 struct intel_fbc *fbc = &dev_priv->fbc;
925 struct intel_fbc_reg_params old_params;
926
927 WARN_ON(!mutex_is_locked(&fbc->lock));
928
929 if (!fbc->enabled || fbc->crtc != crtc)
930 return;
931
932 if (!intel_fbc_can_activate(crtc)) {
933 WARN_ON(fbc->active);
934 return;
935 }
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200936
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200937 old_params = fbc->params;
938 intel_fbc_get_reg_params(crtc, &fbc->params);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200939
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200940 /* If the scanout has not changed, don't modify the FBC settings.
941 * Note that we make the fundamental assumption that the fb->obj
942 * cannot be unpinned (and have its GTT offset and fence revoked)
943 * without first being decoupled from the scanout and FBC disabled.
944 */
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200945 if (fbc->active &&
946 intel_fbc_reg_params_equal(&old_params, &fbc->params))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200947 return;
948
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200949 intel_fbc_deactivate(dev_priv);
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300950 intel_fbc_schedule_activation(crtc);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200951 fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300952}
953
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200954void intel_fbc_post_update(struct intel_crtc *crtc)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300955{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200957 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni754d1132015-10-13 19:13:25 -0300958
Paulo Zanoni9f218332015-09-23 12:52:27 -0300959 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300960 return;
961
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200962 mutex_lock(&fbc->lock);
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200963 __intel_fbc_post_update(crtc);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200964 mutex_unlock(&fbc->lock);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200965}
966
Paulo Zanoni261fe992016-01-19 11:35:40 -0200967static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
968{
969 if (fbc->enabled)
970 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
971 else
972 return fbc->possible_framebuffer_bits;
973}
974
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200975void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
976 unsigned int frontbuffer_bits,
977 enum fb_op_origin origin)
978{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200979 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200980
Paulo Zanoni9f218332015-09-23 12:52:27 -0300981 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300982 return;
983
Paulo Zanoni0dd81542016-01-19 11:35:39 -0200984 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200985 return;
986
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200987 mutex_lock(&fbc->lock);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300988
Paulo Zanoni261fe992016-01-19 11:35:40 -0200989 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200990
Paulo Zanoni5bc40472016-01-19 11:35:53 -0200991 if (fbc->enabled && fbc->busy_bits)
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200992 intel_fbc_deactivate(dev_priv);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300993
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200994 mutex_unlock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200995}
996
997void intel_fbc_flush(struct drm_i915_private *dev_priv,
Paulo Zanoni6f4551f2015-07-14 16:29:10 -0300998 unsigned int frontbuffer_bits, enum fb_op_origin origin)
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200999{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001000 struct intel_fbc *fbc = &dev_priv->fbc;
1001
Paulo Zanoni9f218332015-09-23 12:52:27 -03001002 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -03001003 return;
1004
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001005 mutex_lock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001006
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001007 fbc->busy_bits &= ~frontbuffer_bits;
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001008
Paulo Zanoniab28a542016-04-04 18:17:15 -03001009 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1010 goto out;
1011
Paulo Zanoni261fe992016-01-19 11:35:40 -02001012 if (!fbc->busy_bits && fbc->enabled &&
1013 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
Paulo Zanoni0dd81542016-01-19 11:35:39 -02001014 if (fbc->active)
Paulo Zanoniee7d6cfa2015-11-11 14:46:22 -02001015 intel_fbc_recompress(dev_priv);
Paulo Zanoni0dd81542016-01-19 11:35:39 -02001016 else
Paulo Zanoni1eb52232016-01-19 11:35:44 -02001017 __intel_fbc_post_update(fbc->crtc);
Paulo Zanoni6f4551f2015-07-14 16:29:10 -03001018 }
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001019
Paulo Zanoniab28a542016-04-04 18:17:15 -03001020out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001021 mutex_unlock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001022}
1023
Rodrigo Vivi94b83952014-12-08 06:46:31 -08001024/**
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001025 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1026 * @dev_priv: i915 device instance
1027 * @state: the atomic state structure
1028 *
1029 * This function looks at the proposed state for CRTCs and planes, then chooses
1030 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1031 * true.
1032 *
1033 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1034 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1035 */
1036void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1037 struct drm_atomic_state *state)
1038{
1039 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001040 struct drm_plane *plane;
1041 struct drm_plane_state *plane_state;
Paulo Zanoni4f8f2252016-11-11 14:57:39 -02001042 bool crtc_chosen = false;
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001043 int i;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001044
1045 mutex_lock(&fbc->lock);
1046
Paulo Zanoni4f8f2252016-11-11 14:57:39 -02001047 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1048 if (fbc->crtc &&
1049 !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001050 goto out;
1051
Paulo Zanoniee2be302016-11-11 14:57:37 -02001052 if (!intel_fbc_can_enable(dev_priv))
1053 goto out;
1054
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001055 /* Simply choose the first CRTC that is compatible and has a visible
1056 * plane. We could go for fancier schemes such as checking the plane
1057 * size, but this would just affect the few platforms that don't tie FBC
1058 * to pipe or plane A. */
Maarten Lankhorste96b2062017-03-09 15:52:02 +01001059 for_each_new_plane_in_state(state, plane, plane_state, i) {
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001060 struct intel_plane_state *intel_plane_state =
1061 to_intel_plane_state(plane_state);
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001062 struct intel_crtc_state *intel_crtc_state;
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001063 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001064
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001065 if (!intel_plane_state->base.visible)
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001066 continue;
1067
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001068 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1069 continue;
1070
1071 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
Paulo Zanoni03e39102016-11-11 14:57:35 -02001072 continue;
1073
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001074 intel_crtc_state = to_intel_crtc_state(
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001075 drm_atomic_get_existing_crtc_state(state, &crtc->base));
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001076
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001077 intel_crtc_state->enable_fbc = true;
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001078 crtc_chosen = true;
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001079 break;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001080 }
1081
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001082 if (!crtc_chosen)
1083 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1084
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001085out:
1086 mutex_unlock(&fbc->lock);
1087}
1088
1089/**
Paulo Zanonid029bca2015-10-15 10:44:46 -03001090 * intel_fbc_enable: tries to enable FBC on the CRTC
1091 * @crtc: the CRTC
Daniel Vetter62f90b32016-07-15 21:48:07 +02001092 * @crtc_state: corresponding &drm_crtc_state for @crtc
1093 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
Paulo Zanonid029bca2015-10-15 10:44:46 -03001094 *
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001095 * This function checks if the given CRTC was chosen for FBC, then enables it if
Paulo Zanoni49227c42016-01-19 11:35:52 -02001096 * possible. Notice that it doesn't activate FBC. It is valid to call
1097 * intel_fbc_enable multiple times for the same pipe without an
1098 * intel_fbc_disable in the middle, as long as it is deactivated.
Paulo Zanonid029bca2015-10-15 10:44:46 -03001099 */
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001100void intel_fbc_enable(struct intel_crtc *crtc,
1101 struct intel_crtc_state *crtc_state,
1102 struct intel_plane_state *plane_state)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001103{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001104 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001105 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001106
1107 if (!fbc_supported(dev_priv))
1108 return;
1109
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001110 mutex_lock(&fbc->lock);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001111
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001112 if (fbc->enabled) {
Paulo Zanoni49227c42016-01-19 11:35:52 -02001113 WARN_ON(fbc->crtc == NULL);
1114 if (fbc->crtc == crtc) {
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001115 WARN_ON(!crtc_state->enable_fbc);
Paulo Zanoni49227c42016-01-19 11:35:52 -02001116 WARN_ON(fbc->active);
1117 }
Paulo Zanonid029bca2015-10-15 10:44:46 -03001118 goto out;
1119 }
1120
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001121 if (!crtc_state->enable_fbc)
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001122 goto out;
1123
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001124 WARN_ON(fbc->active);
1125 WARN_ON(fbc->crtc != NULL);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001126
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001127 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001128 if (intel_fbc_alloc_cfb(crtc)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -02001129 fbc->no_fbc_reason = "not enough stolen memory";
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001130 goto out;
1131 }
1132
Paulo Zanonid029bca2015-10-15 10:44:46 -03001133 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001134 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
Paulo Zanonid029bca2015-10-15 10:44:46 -03001135
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001136 fbc->enabled = true;
1137 fbc->crtc = crtc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001138out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001139 mutex_unlock(&fbc->lock);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001140}
1141
1142/**
1143 * __intel_fbc_disable - disable FBC
1144 * @dev_priv: i915 device instance
1145 *
1146 * This is the low level function that actually disables FBC. Callers should
1147 * grab the FBC lock.
1148 */
1149static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1150{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001151 struct intel_fbc *fbc = &dev_priv->fbc;
1152 struct intel_crtc *crtc = fbc->crtc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001153
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001154 WARN_ON(!mutex_is_locked(&fbc->lock));
1155 WARN_ON(!fbc->enabled);
1156 WARN_ON(fbc->active);
Paulo Zanoni58f9c0b2016-01-19 11:35:51 -02001157 WARN_ON(crtc->active);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001158
1159 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1160
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001161 __intel_fbc_cleanup_cfb(dev_priv);
1162
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001163 fbc->enabled = false;
1164 fbc->crtc = NULL;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001165}
1166
1167/**
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001168 * intel_fbc_disable - disable FBC if it's associated with crtc
Paulo Zanonid029bca2015-10-15 10:44:46 -03001169 * @crtc: the CRTC
1170 *
1171 * This function disables FBC if it's associated with the provided CRTC.
1172 */
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001173void intel_fbc_disable(struct intel_crtc *crtc)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001174{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001176 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001177
1178 if (!fbc_supported(dev_priv))
1179 return;
1180
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001181 mutex_lock(&fbc->lock);
Matthew Auld4da45612016-07-05 10:28:34 +01001182 if (fbc->crtc == crtc)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001183 __intel_fbc_disable(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001184 mutex_unlock(&fbc->lock);
Paulo Zanoni65c76002016-01-19 11:35:47 -02001185
1186 cancel_work_sync(&fbc->work.work);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001187}
1188
1189/**
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001190 * intel_fbc_global_disable - globally disable FBC
Paulo Zanonid029bca2015-10-15 10:44:46 -03001191 * @dev_priv: i915 device instance
1192 *
1193 * This function disables FBC regardless of which CRTC is associated with it.
1194 */
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001195void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001196{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001197 struct intel_fbc *fbc = &dev_priv->fbc;
1198
Paulo Zanonid029bca2015-10-15 10:44:46 -03001199 if (!fbc_supported(dev_priv))
1200 return;
1201
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001202 mutex_lock(&fbc->lock);
1203 if (fbc->enabled)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001204 __intel_fbc_disable(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001205 mutex_unlock(&fbc->lock);
Paulo Zanoni65c76002016-01-19 11:35:47 -02001206
1207 cancel_work_sync(&fbc->work.work);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001208}
1209
Paulo Zanoni61a585d2016-09-13 10:38:57 -03001210static void intel_fbc_underrun_work_fn(struct work_struct *work)
1211{
1212 struct drm_i915_private *dev_priv =
1213 container_of(work, struct drm_i915_private, fbc.underrun_work);
1214 struct intel_fbc *fbc = &dev_priv->fbc;
1215
1216 mutex_lock(&fbc->lock);
1217
1218 /* Maybe we were scheduled twice. */
1219 if (fbc->underrun_detected)
1220 goto out;
1221
1222 DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1223 fbc->underrun_detected = true;
1224
1225 intel_fbc_deactivate(dev_priv);
1226out:
1227 mutex_unlock(&fbc->lock);
1228}
1229
1230/**
1231 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1232 * @dev_priv: i915 device instance
1233 *
1234 * Without FBC, most underruns are harmless and don't really cause too many
1235 * problems, except for an annoying message on dmesg. With FBC, underruns can
1236 * become black screens or even worse, especially when paired with bad
1237 * watermarks. So in order for us to be on the safe side, completely disable FBC
1238 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1239 * already suggests that watermarks may be bad, so try to be as safe as
1240 * possible.
1241 *
1242 * This function is called from the IRQ handler.
1243 */
1244void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1245{
1246 struct intel_fbc *fbc = &dev_priv->fbc;
1247
1248 if (!fbc_supported(dev_priv))
1249 return;
1250
1251 /* There's no guarantee that underrun_detected won't be set to true
1252 * right after this check and before the work is scheduled, but that's
1253 * not a problem since we'll check it again under the work function
1254 * while FBC is locked. This check here is just to prevent us from
1255 * unnecessarily scheduling the work, and it relies on the fact that we
1256 * never switch underrun_detect back to false after it's true. */
1257 if (READ_ONCE(fbc->underrun_detected))
1258 return;
1259
1260 schedule_work(&fbc->underrun_work);
1261}
1262
Paulo Zanonid029bca2015-10-15 10:44:46 -03001263/**
Paulo Zanoni010cf732016-01-19 11:35:48 -02001264 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1265 * @dev_priv: i915 device instance
1266 *
1267 * The FBC code needs to track CRTC visibility since the older platforms can't
1268 * have FBC enabled while multiple pipes are used. This function does the
1269 * initial setup at driver load to make sure FBC is matching the real hardware.
1270 */
1271void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1272{
1273 struct intel_crtc *crtc;
1274
1275 /* Don't even bother tracking anything if we don't need. */
1276 if (!no_fbc_on_multiple_pipes(dev_priv))
1277 return;
1278
Chris Wilson91c8a322016-07-05 10:40:23 +01001279 for_each_intel_crtc(&dev_priv->drm, crtc)
Ville Syrjälä525b9312016-10-31 22:37:02 +02001280 if (intel_crtc_active(crtc) &&
Maarten Lankhorst1d4258d2017-01-12 10:43:45 +01001281 crtc->base.primary->state->visible)
Paulo Zanoni010cf732016-01-19 11:35:48 -02001282 dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1283}
1284
Paulo Zanoni80788a02016-04-13 16:01:09 -03001285/*
1286 * The DDX driver changes its behavior depending on the value it reads from
1287 * i915.enable_fbc, so sanitize it by translating the default value into either
1288 * 0 or 1 in order to allow it to know what's going on.
1289 *
1290 * Notice that this is done at driver initialization and we still allow user
1291 * space to change the value during runtime without sanitizing it again. IGT
1292 * relies on being able to change i915.enable_fbc at runtime.
1293 */
1294static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1295{
1296 if (i915.enable_fbc >= 0)
1297 return !!i915.enable_fbc;
1298
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001299 if (!HAS_FBC(dev_priv))
1300 return 0;
1301
Paulo Zanonifd7d6c52016-12-23 10:23:58 -02001302 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
Paulo Zanoni80788a02016-04-13 16:01:09 -03001303 return 1;
1304
1305 return 0;
1306}
1307
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001308static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1309{
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001310 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
Chris Wilson80debff2017-05-25 13:16:12 +01001311 if (intel_vtd_active() &&
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001312 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1313 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1314 return true;
1315 }
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001316
1317 return false;
1318}
1319
Paulo Zanoni010cf732016-01-19 11:35:48 -02001320/**
Rodrigo Vivi94b83952014-12-08 06:46:31 -08001321 * intel_fbc_init - Initialize FBC
1322 * @dev_priv: the i915 device
1323 *
1324 * This function might be called during PM init process.
1325 */
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001326void intel_fbc_init(struct drm_i915_private *dev_priv)
1327{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001328 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001329 enum pipe pipe;
1330
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001331 INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
Paulo Zanoni61a585d2016-09-13 10:38:57 -03001332 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001333 mutex_init(&fbc->lock);
1334 fbc->enabled = false;
1335 fbc->active = false;
1336 fbc->work.scheduled = false;
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001337
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001338 if (need_fbc_vtd_wa(dev_priv))
1339 mkwrite_device_info(dev_priv)->has_fbc = false;
1340
Paulo Zanoni80788a02016-04-13 16:01:09 -03001341 i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1342 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1343
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001344 if (!HAS_FBC(dev_priv)) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001345 fbc->no_fbc_reason = "unsupported by this chipset";
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001346 return;
1347 }
1348
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001349 for_each_pipe(dev_priv, pipe) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001350 fbc->possible_framebuffer_bits |=
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001351 INTEL_FRONTBUFFER_PRIMARY(pipe);
1352
Paulo Zanoni57105022015-11-04 17:10:46 -02001353 if (fbc_on_pipe_a_only(dev_priv))
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001354 break;
1355 }
1356
Paulo Zanoni8c400742016-01-29 18:57:39 -02001357 /* This value was pulled out of someone's hat */
Paulo Zanoni5697d602016-11-11 14:57:41 -02001358 if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001359 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001360
Paulo Zanonib07ea0f2015-11-04 17:10:52 -02001361 /* We still don't have any sort of hardware state readout for FBC, so
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03001362 * deactivate it in case the BIOS activated it to make sure software
1363 * matches the hardware state. */
Paulo Zanoni8c400742016-01-29 18:57:39 -02001364 if (intel_fbc_hw_is_active(dev_priv))
1365 intel_fbc_hw_deactivate(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001366}