Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 3 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 5 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 6 | * |
Pierre Ossman | 84c46a5 | 2007-12-02 19:58:16 +0100 | [diff] [blame] | 7 | * Thanks to the following companies for their support: |
| 8 | * |
| 9 | * - JMicron (hardware and technical support) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 10 | */ |
| 11 | |
Masahiro Yamada | fa09101 | 2020-03-12 20:00:50 +0900 | [diff] [blame] | 12 | #include <linux/bitfield.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 13 | #include <linux/delay.h> |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 14 | #include <linux/dmaengine.h> |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 15 | #include <linux/ktime.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 16 | #include <linux/highmem.h> |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 17 | #include <linux/io.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 18 | #include <linux/module.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 19 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 20 | #include <linux/slab.h> |
Ralf Baechle | 1176360 | 2007-10-23 20:42:11 +0200 | [diff] [blame] | 21 | #include <linux/scatterlist.h> |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 22 | #include <linux/sizes.h> |
Ulf Hansson | 250dcd1 | 2017-11-27 11:28:50 +0100 | [diff] [blame] | 23 | #include <linux/swiotlb.h> |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 24 | #include <linux/regulator/consumer.h> |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 25 | #include <linux/pm_runtime.h> |
Zach Brown | 92e0c44 | 2016-11-02 10:26:16 -0500 | [diff] [blame] | 26 | #include <linux/of.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 27 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 28 | #include <linux/leds.h> |
| 29 | |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 30 | #include <linux/mmc/mmc.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 31 | #include <linux/mmc/host.h> |
Aaron Lu | 473b095 | 2012-07-03 17:27:49 +0800 | [diff] [blame] | 32 | #include <linux/mmc/card.h> |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 33 | #include <linux/mmc/sdio.h> |
Guennadi Liakhovetski | bec9d4e | 2012-09-17 16:45:10 +0800 | [diff] [blame] | 34 | #include <linux/mmc/slot-gpio.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 35 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 36 | #include "sdhci.h" |
| 37 | |
| 38 | #define DRIVER_NAME "sdhci" |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 39 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 40 | #define DBG(f, x...) \ |
Adrian Hunter | f421865 | 2017-03-20 19:50:39 +0200 | [diff] [blame] | 41 | pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 42 | |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 43 | #define SDHCI_DUMP(f, x...) \ |
| 44 | pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) |
| 45 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 46 | #define MAX_TUNING_LOOP 40 |
| 47 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 48 | static unsigned int debug_quirks = 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 49 | static unsigned int debug_quirks2; |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 50 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 51 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 52 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 53 | static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); |
Adrian Hunter | a374a72 | 2020-04-12 12:03:46 +0300 | [diff] [blame] | 54 | |
Adrian Hunter | d289817 | 2017-03-20 19:50:43 +0200 | [diff] [blame] | 55 | void sdhci_dumpregs(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 56 | { |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 57 | SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 58 | |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 59 | SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n", |
| 60 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
| 61 | sdhci_readw(host, SDHCI_HOST_VERSION)); |
| 62 | SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
| 63 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
| 64 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); |
| 65 | SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n", |
| 66 | sdhci_readl(host, SDHCI_ARGUMENT), |
| 67 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); |
| 68 | SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n", |
| 69 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
| 70 | sdhci_readb(host, SDHCI_HOST_CONTROL)); |
| 71 | SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n", |
| 72 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
| 73 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); |
| 74 | SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n", |
| 75 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
| 76 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); |
| 77 | SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n", |
| 78 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
| 79 | sdhci_readl(host, SDHCI_INT_STATUS)); |
| 80 | SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n", |
| 81 | sdhci_readl(host, SDHCI_INT_ENABLE), |
| 82 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); |
Adrian Hunter | 869f8a6 | 2018-11-15 15:53:42 +0200 | [diff] [blame] | 83 | SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n", |
| 84 | sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 85 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); |
| 86 | SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n", |
| 87 | sdhci_readl(host, SDHCI_CAPABILITIES), |
| 88 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
| 89 | SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n", |
| 90 | sdhci_readw(host, SDHCI_COMMAND), |
| 91 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
| 92 | SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n", |
Adrian Hunter | 7962302 | 2017-03-20 19:50:40 +0200 | [diff] [blame] | 93 | sdhci_readl(host, SDHCI_RESPONSE), |
| 94 | sdhci_readl(host, SDHCI_RESPONSE + 4)); |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 95 | SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n", |
Adrian Hunter | 7962302 | 2017-03-20 19:50:40 +0200 | [diff] [blame] | 96 | sdhci_readl(host, SDHCI_RESPONSE + 8), |
| 97 | sdhci_readl(host, SDHCI_RESPONSE + 12)); |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 98 | SDHCI_DUMP("Host ctl2: 0x%08x\n", |
| 99 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 100 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 101 | if (host->flags & SDHCI_USE_ADMA) { |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 102 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 103 | SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", |
| 104 | sdhci_readl(host, SDHCI_ADMA_ERROR), |
| 105 | sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI), |
| 106 | sdhci_readl(host, SDHCI_ADMA_ADDRESS)); |
| 107 | } else { |
| 108 | SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
| 109 | sdhci_readl(host, SDHCI_ADMA_ERROR), |
| 110 | sdhci_readl(host, SDHCI_ADMA_ADDRESS)); |
| 111 | } |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 112 | } |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 113 | |
Sarthak Garg | d1fe076 | 2020-05-22 15:02:29 +0530 | [diff] [blame] | 114 | if (host->ops->dump_vendor_regs) |
| 115 | host->ops->dump_vendor_regs(host); |
| 116 | |
Adrian Hunter | 85ad90e | 2017-03-20 19:50:42 +0200 | [diff] [blame] | 117 | SDHCI_DUMP("============================================\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 118 | } |
Adrian Hunter | d289817 | 2017-03-20 19:50:43 +0200 | [diff] [blame] | 119 | EXPORT_SYMBOL_GPL(sdhci_dumpregs); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 120 | |
| 121 | /*****************************************************************************\ |
| 122 | * * |
| 123 | * Low level functions * |
| 124 | * * |
| 125 | \*****************************************************************************/ |
| 126 | |
Chunyan Zhang | b3f80b4 | 2018-08-30 16:21:38 +0800 | [diff] [blame] | 127 | static void sdhci_do_enable_v4_mode(struct sdhci_host *host) |
| 128 | { |
| 129 | u16 ctrl2; |
| 130 | |
Sowjanya Komatineni | 97207c1 | 2018-12-13 12:34:06 -0800 | [diff] [blame] | 131 | ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Chunyan Zhang | b3f80b4 | 2018-08-30 16:21:38 +0800 | [diff] [blame] | 132 | if (ctrl2 & SDHCI_CTRL_V4_MODE) |
| 133 | return; |
| 134 | |
| 135 | ctrl2 |= SDHCI_CTRL_V4_MODE; |
Sowjanya Komatineni | 97207c1 | 2018-12-13 12:34:06 -0800 | [diff] [blame] | 136 | sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); |
Chunyan Zhang | b3f80b4 | 2018-08-30 16:21:38 +0800 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /* |
| 140 | * This can be called before sdhci_add_host() by Vendor's host controller |
| 141 | * driver to enable v4 mode if supported. |
| 142 | */ |
| 143 | void sdhci_enable_v4_mode(struct sdhci_host *host) |
| 144 | { |
| 145 | host->v4_mode = true; |
| 146 | sdhci_do_enable_v4_mode(host); |
| 147 | } |
| 148 | EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); |
| 149 | |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 150 | static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) |
| 151 | { |
| 152 | return cmd->data || cmd->flags & MMC_RSP_BUSY; |
| 153 | } |
| 154 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 155 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
| 156 | { |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 157 | u32 present; |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 158 | |
Adrian Hunter | c79396c | 2011-12-27 15:48:42 +0200 | [diff] [blame] | 159 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
Haibo Chen | e65bb38 | 2020-02-19 16:22:40 +0800 | [diff] [blame] | 160 | !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 161 | return; |
| 162 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 163 | if (enable) { |
| 164 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 165 | SDHCI_CARD_PRESENT; |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 166 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 167 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 168 | SDHCI_INT_CARD_INSERT; |
| 169 | } else { |
| 170 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
| 171 | } |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 172 | |
| 173 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 174 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
| 178 | { |
| 179 | sdhci_set_card_detection(host, true); |
| 180 | } |
| 181 | |
| 182 | static void sdhci_disable_card_detection(struct sdhci_host *host) |
| 183 | { |
| 184 | sdhci_set_card_detection(host, false); |
| 185 | } |
| 186 | |
Ulf Hansson | 02d0b68 | 2016-04-11 15:32:41 +0200 | [diff] [blame] | 187 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
| 188 | { |
| 189 | if (host->bus_on) |
| 190 | return; |
| 191 | host->bus_on = true; |
| 192 | pm_runtime_get_noresume(host->mmc->parent); |
| 193 | } |
| 194 | |
| 195 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) |
| 196 | { |
| 197 | if (!host->bus_on) |
| 198 | return; |
| 199 | host->bus_on = false; |
| 200 | pm_runtime_put_noidle(host->mmc->parent); |
| 201 | } |
| 202 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 203 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 204 | { |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 205 | ktime_t timeout; |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 206 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 207 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 208 | |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 209 | if (mask & SDHCI_RESET_ALL) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 210 | host->clock = 0; |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 211 | /* Reset-all turns off SD Bus Power */ |
| 212 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 213 | sdhci_runtime_pm_bus_off(host); |
| 214 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 215 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 216 | /* Wait max 100 ms */ |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 217 | timeout = ktime_add_ms(ktime_get(), 100); |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 218 | |
| 219 | /* hw clears the bit when it's done */ |
Alek Du | b704441 | 2018-12-06 17:24:59 +0800 | [diff] [blame] | 220 | while (1) { |
| 221 | bool timedout = ktime_after(ktime_get(), timeout); |
| 222 | |
| 223 | if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) |
| 224 | break; |
| 225 | if (timedout) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 226 | pr_err("%s: Reset 0x%x never completed.\n", |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 227 | mmc_hostname(host->mmc), (int)mask); |
| 228 | sdhci_dumpregs(host); |
| 229 | return; |
| 230 | } |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 231 | udelay(10); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 232 | } |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 233 | } |
| 234 | EXPORT_SYMBOL_GPL(sdhci_reset); |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 235 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 236 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) |
| 237 | { |
| 238 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 239 | struct mmc_host *mmc = host->mmc; |
| 240 | |
| 241 | if (!mmc->ops->get_cd(mmc)) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 242 | return; |
| 243 | } |
| 244 | |
| 245 | host->ops->reset(host, mask); |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 246 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 247 | if (mask & SDHCI_RESET_ALL) { |
| 248 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 249 | if (host->ops->enable_dma) |
| 250 | host->ops->enable_dma(host); |
| 251 | } |
| 252 | |
| 253 | /* Resetting the controller clears many */ |
| 254 | host->preset_enabled = false; |
Shaohui Xie | 3abc1e80 | 2011-12-29 16:33:00 +0800 | [diff] [blame] | 255 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 256 | } |
| 257 | |
Adrian Hunter | f5c1ab8 | 2017-03-20 19:50:46 +0200 | [diff] [blame] | 258 | static void sdhci_set_default_irqs(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 259 | { |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 260 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
| 261 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | |
| 262 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | |
| 263 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | |
| 264 | SDHCI_INT_RESPONSE; |
| 265 | |
Dong Aisheng | f37b20e | 2016-07-12 15:46:17 +0800 | [diff] [blame] | 266 | if (host->tuning_mode == SDHCI_TUNING_MODE_2 || |
| 267 | host->tuning_mode == SDHCI_TUNING_MODE_3) |
| 268 | host->ier |= SDHCI_INT_RETUNE; |
| 269 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 270 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 271 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | f5c1ab8 | 2017-03-20 19:50:46 +0200 | [diff] [blame] | 272 | } |
| 273 | |
Chunyan Zhang | 685e444 | 2018-08-30 16:21:40 +0800 | [diff] [blame] | 274 | static void sdhci_config_dma(struct sdhci_host *host) |
| 275 | { |
| 276 | u8 ctrl; |
| 277 | u16 ctrl2; |
| 278 | |
| 279 | if (host->version < SDHCI_SPEC_200) |
| 280 | return; |
| 281 | |
| 282 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 283 | |
| 284 | /* |
| 285 | * Always adjust the DMA selection as some controllers |
| 286 | * (e.g. JMicron) can't do PIO properly when the selection |
| 287 | * is ADMA. |
| 288 | */ |
| 289 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
| 290 | if (!(host->flags & SDHCI_REQ_USE_DMA)) |
| 291 | goto out; |
| 292 | |
| 293 | /* Note if DMA Select is zero then SDMA is selected */ |
| 294 | if (host->flags & SDHCI_USE_ADMA) |
| 295 | ctrl |= SDHCI_CTRL_ADMA32; |
| 296 | |
| 297 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 298 | /* |
| 299 | * If v4 mode, all supported DMA can be 64-bit addressing if |
| 300 | * controller supports 64-bit system address, otherwise only |
| 301 | * ADMA can support 64-bit addressing. |
| 302 | */ |
| 303 | if (host->v4_mode) { |
| 304 | ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 305 | ctrl2 |= SDHCI_CTRL_64BIT_ADDR; |
| 306 | sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); |
| 307 | } else if (host->flags & SDHCI_USE_ADMA) { |
| 308 | /* |
| 309 | * Don't need to undo SDHCI_CTRL_ADMA32 in order to |
| 310 | * set SDHCI_CTRL_ADMA64. |
| 311 | */ |
| 312 | ctrl |= SDHCI_CTRL_ADMA64; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | out: |
| 317 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 318 | } |
| 319 | |
Adrian Hunter | f5c1ab8 | 2017-03-20 19:50:46 +0200 | [diff] [blame] | 320 | static void sdhci_init(struct sdhci_host *host, int soft) |
| 321 | { |
| 322 | struct mmc_host *mmc = host->mmc; |
Haibo Chen | 49769d4 | 2020-04-15 17:00:55 +0800 | [diff] [blame] | 323 | unsigned long flags; |
Adrian Hunter | f5c1ab8 | 2017-03-20 19:50:46 +0200 | [diff] [blame] | 324 | |
| 325 | if (soft) |
| 326 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
| 327 | else |
| 328 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
| 329 | |
Chunyan Zhang | b3f80b4 | 2018-08-30 16:21:38 +0800 | [diff] [blame] | 330 | if (host->v4_mode) |
| 331 | sdhci_do_enable_v4_mode(host); |
| 332 | |
Haibo Chen | 49769d4 | 2020-04-15 17:00:55 +0800 | [diff] [blame] | 333 | spin_lock_irqsave(&host->lock, flags); |
Adrian Hunter | f5c1ab8 | 2017-03-20 19:50:46 +0200 | [diff] [blame] | 334 | sdhci_set_default_irqs(host); |
Haibo Chen | 49769d4 | 2020-04-15 17:00:55 +0800 | [diff] [blame] | 335 | spin_unlock_irqrestore(&host->lock, flags); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 336 | |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 337 | host->cqe_on = false; |
| 338 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 339 | if (soft) { |
| 340 | /* force clock reconfiguration */ |
| 341 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 342 | mmc->ops->set_ios(mmc, &mmc->ios); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 343 | } |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 344 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 345 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 346 | static void sdhci_reinit(struct sdhci_host *host) |
| 347 | { |
Raul E Rangel | dcaac3f | 2019-09-04 10:46:24 -0600 | [diff] [blame] | 348 | u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
| 349 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 350 | sdhci_init(host, 0); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 351 | sdhci_enable_card_detection(host); |
Raul E Rangel | dcaac3f | 2019-09-04 10:46:24 -0600 | [diff] [blame] | 352 | |
| 353 | /* |
| 354 | * A change to the card detect bits indicates a change in present state, |
| 355 | * refer sdhci_set_card_detection(). A card detect interrupt might have |
| 356 | * been missed while the host controller was being reset, so trigger a |
| 357 | * rescan to check. |
| 358 | */ |
| 359 | if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT))) |
| 360 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 361 | } |
| 362 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 363 | static void __sdhci_led_activate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 364 | { |
| 365 | u8 ctrl; |
| 366 | |
Adrian Hunter | bd29f58 | 2018-12-11 15:10:42 +0200 | [diff] [blame] | 367 | if (host->quirks & SDHCI_QUIRK_NO_LED) |
| 368 | return; |
| 369 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 370 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 371 | ctrl |= SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 372 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 373 | } |
| 374 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 375 | static void __sdhci_led_deactivate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 376 | { |
| 377 | u8 ctrl; |
| 378 | |
Adrian Hunter | bd29f58 | 2018-12-11 15:10:42 +0200 | [diff] [blame] | 379 | if (host->quirks & SDHCI_QUIRK_NO_LED) |
| 380 | return; |
| 381 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 382 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 383 | ctrl &= ~SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 384 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 385 | } |
| 386 | |
Masahiro Yamada | 4f78230 | 2016-04-14 13:19:39 +0900 | [diff] [blame] | 387 | #if IS_REACHABLE(CONFIG_LEDS_CLASS) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 388 | static void sdhci_led_control(struct led_classdev *led, |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 389 | enum led_brightness brightness) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 390 | { |
| 391 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); |
| 392 | unsigned long flags; |
| 393 | |
| 394 | spin_lock_irqsave(&host->lock, flags); |
| 395 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 396 | if (host->runtime_suspended) |
| 397 | goto out; |
| 398 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 399 | if (brightness == LED_OFF) |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 400 | __sdhci_led_deactivate(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 401 | else |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 402 | __sdhci_led_activate(host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 403 | out: |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 404 | spin_unlock_irqrestore(&host->lock, flags); |
| 405 | } |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 406 | |
| 407 | static int sdhci_led_register(struct sdhci_host *host) |
| 408 | { |
| 409 | struct mmc_host *mmc = host->mmc; |
| 410 | |
Adrian Hunter | bd29f58 | 2018-12-11 15:10:42 +0200 | [diff] [blame] | 411 | if (host->quirks & SDHCI_QUIRK_NO_LED) |
| 412 | return 0; |
| 413 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 414 | snprintf(host->led_name, sizeof(host->led_name), |
| 415 | "%s::", mmc_hostname(mmc)); |
| 416 | |
| 417 | host->led.name = host->led_name; |
| 418 | host->led.brightness = LED_OFF; |
| 419 | host->led.default_trigger = mmc_hostname(mmc); |
| 420 | host->led.brightness_set = sdhci_led_control; |
| 421 | |
| 422 | return led_classdev_register(mmc_dev(mmc), &host->led); |
| 423 | } |
| 424 | |
| 425 | static void sdhci_led_unregister(struct sdhci_host *host) |
| 426 | { |
Adrian Hunter | bd29f58 | 2018-12-11 15:10:42 +0200 | [diff] [blame] | 427 | if (host->quirks & SDHCI_QUIRK_NO_LED) |
| 428 | return; |
| 429 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 430 | led_classdev_unregister(&host->led); |
| 431 | } |
| 432 | |
| 433 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 434 | { |
| 435 | } |
| 436 | |
| 437 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 438 | { |
| 439 | } |
| 440 | |
| 441 | #else |
| 442 | |
| 443 | static inline int sdhci_led_register(struct sdhci_host *host) |
| 444 | { |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static inline void sdhci_led_unregister(struct sdhci_host *host) |
| 449 | { |
| 450 | } |
| 451 | |
| 452 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 453 | { |
| 454 | __sdhci_led_activate(host); |
| 455 | } |
| 456 | |
| 457 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 458 | { |
| 459 | __sdhci_led_deactivate(host); |
| 460 | } |
| 461 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 462 | #endif |
| 463 | |
Adrian Hunter | 97a1aba | 2019-04-05 15:40:17 +0300 | [diff] [blame] | 464 | static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, |
| 465 | unsigned long timeout) |
| 466 | { |
| 467 | if (sdhci_data_line_cmd(mrq->cmd)) |
| 468 | mod_timer(&host->data_timer, timeout); |
| 469 | else |
| 470 | mod_timer(&host->timer, timeout); |
| 471 | } |
| 472 | |
| 473 | static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) |
| 474 | { |
| 475 | if (sdhci_data_line_cmd(mrq->cmd)) |
| 476 | del_timer(&host->data_timer); |
| 477 | else |
| 478 | del_timer(&host->timer); |
| 479 | } |
| 480 | |
| 481 | static inline bool sdhci_has_requests(struct sdhci_host *host) |
| 482 | { |
| 483 | return host->cmd || host->data_cmd; |
| 484 | } |
| 485 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 486 | /*****************************************************************************\ |
| 487 | * * |
| 488 | * Core functions * |
| 489 | * * |
| 490 | \*****************************************************************************/ |
| 491 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 492 | static void sdhci_read_block_pio(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 493 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 494 | unsigned long flags; |
| 495 | size_t blksize, len, chunk; |
Kees Cook | 3f649ab | 2020-06-03 13:09:38 -0700 | [diff] [blame] | 496 | u32 scratch; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 497 | u8 *buf; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 498 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 499 | DBG("PIO reading\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 500 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 501 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 502 | chunk = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 503 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 504 | local_irq_save(flags); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 505 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 506 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 507 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 508 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 509 | len = min(host->sg_miter.length, blksize); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 510 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 511 | blksize -= len; |
| 512 | host->sg_miter.consumed = len; |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 513 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 514 | buf = host->sg_miter.addr; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 515 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 516 | while (len) { |
| 517 | if (chunk == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 518 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 519 | chunk = 4; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 520 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 521 | |
| 522 | *buf = scratch & 0xFF; |
| 523 | |
| 524 | buf++; |
| 525 | scratch >>= 8; |
| 526 | chunk--; |
| 527 | len--; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 528 | } |
| 529 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 530 | |
| 531 | sg_miter_stop(&host->sg_miter); |
| 532 | |
| 533 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 534 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 535 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 536 | static void sdhci_write_block_pio(struct sdhci_host *host) |
| 537 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 538 | unsigned long flags; |
| 539 | size_t blksize, len, chunk; |
| 540 | u32 scratch; |
| 541 | u8 *buf; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 542 | |
| 543 | DBG("PIO writing\n"); |
| 544 | |
| 545 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 546 | chunk = 0; |
| 547 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 548 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 549 | local_irq_save(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 550 | |
| 551 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 552 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 553 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 554 | len = min(host->sg_miter.length, blksize); |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 555 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 556 | blksize -= len; |
| 557 | host->sg_miter.consumed = len; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 558 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 559 | buf = host->sg_miter.addr; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 560 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 561 | while (len) { |
| 562 | scratch |= (u32)*buf << (chunk * 8); |
| 563 | |
| 564 | buf++; |
| 565 | chunk++; |
| 566 | len--; |
| 567 | |
| 568 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 569 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 570 | chunk = 0; |
| 571 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 572 | } |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 573 | } |
| 574 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 575 | |
| 576 | sg_miter_stop(&host->sg_miter); |
| 577 | |
| 578 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | static void sdhci_transfer_pio(struct sdhci_host *host) |
| 582 | { |
| 583 | u32 mask; |
| 584 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 585 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 586 | return; |
| 587 | |
| 588 | if (host->data->flags & MMC_DATA_READ) |
| 589 | mask = SDHCI_DATA_AVAILABLE; |
| 590 | else |
| 591 | mask = SDHCI_SPACE_AVAILABLE; |
| 592 | |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 593 | /* |
| 594 | * Some controllers (JMicron JMB38x) mess up the buffer bits |
| 595 | * for transfers < 4 bytes. As long as it is just one block, |
| 596 | * we can ignore the bits. |
| 597 | */ |
| 598 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && |
| 599 | (host->data->blocks == 1)) |
| 600 | mask = ~0; |
| 601 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 602 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 603 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
| 604 | udelay(100); |
| 605 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 606 | if (host->data->flags & MMC_DATA_READ) |
| 607 | sdhci_read_block_pio(host); |
| 608 | else |
| 609 | sdhci_write_block_pio(host); |
| 610 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 611 | host->blocks--; |
| 612 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 613 | break; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 614 | } |
| 615 | |
| 616 | DBG("PIO transfer complete.\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 617 | } |
| 618 | |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 619 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 620 | struct mmc_data *data, int cookie) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 621 | { |
| 622 | int sg_count; |
| 623 | |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 624 | /* |
| 625 | * If the data buffers are already mapped, return the previous |
| 626 | * dma_map_sg() result. |
| 627 | */ |
| 628 | if (data->host_cookie == COOKIE_PRE_MAPPED) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 629 | return data->sg_count; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 630 | |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 631 | /* Bounce write requests to the bounce buffer */ |
| 632 | if (host->bounce_buffer) { |
| 633 | unsigned int length = data->blksz * data->blocks; |
| 634 | |
| 635 | if (length > host->bounce_buffer_size) { |
| 636 | pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n", |
| 637 | mmc_hostname(host->mmc), length, |
| 638 | host->bounce_buffer_size); |
| 639 | return -EIO; |
| 640 | } |
| 641 | if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) { |
| 642 | /* Copy the data to the bounce buffer */ |
Angelo Dureghello | e93577e | 2020-05-18 21:17:40 +0200 | [diff] [blame] | 643 | if (host->ops->copy_to_bounce_buffer) { |
| 644 | host->ops->copy_to_bounce_buffer(host, |
| 645 | data, length); |
| 646 | } else { |
| 647 | sg_copy_to_buffer(data->sg, data->sg_len, |
| 648 | host->bounce_buffer, length); |
| 649 | } |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 650 | } |
| 651 | /* Switch ownership to the DMA */ |
| 652 | dma_sync_single_for_device(host->mmc->parent, |
| 653 | host->bounce_addr, |
| 654 | host->bounce_buffer_size, |
| 655 | mmc_get_dma_dir(data)); |
| 656 | /* Just a dummy value */ |
| 657 | sg_count = 1; |
| 658 | } else { |
| 659 | /* Just access the data directly from memory */ |
| 660 | sg_count = dma_map_sg(mmc_dev(host->mmc), |
| 661 | data->sg, data->sg_len, |
| 662 | mmc_get_dma_dir(data)); |
| 663 | } |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 664 | |
| 665 | if (sg_count == 0) |
| 666 | return -ENOSPC; |
| 667 | |
| 668 | data->sg_count = sg_count; |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 669 | data->host_cookie = cookie; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 670 | |
| 671 | return sg_count; |
| 672 | } |
| 673 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 674 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
| 675 | { |
| 676 | local_irq_save(*flags); |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 677 | return kmap_atomic(sg_page(sg)) + sg->offset; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 678 | } |
| 679 | |
| 680 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) |
| 681 | { |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 682 | kunmap_atomic(buffer); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 683 | local_irq_restore(*flags); |
| 684 | } |
| 685 | |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 686 | void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, |
| 687 | dma_addr_t addr, int len, unsigned int cmd) |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 688 | { |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 689 | struct sdhci_adma2_64_desc *dma_desc = *desc; |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 690 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 691 | /* 32-bit and 64-bit descriptors have these members in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 692 | dma_desc->cmd = cpu_to_le16(cmd); |
| 693 | dma_desc->len = cpu_to_le16(len); |
Masahiro Yamada | 38eee2e | 2019-08-29 20:22:06 +0900 | [diff] [blame] | 694 | dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr)); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 695 | |
| 696 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
Masahiro Yamada | 38eee2e | 2019-08-29 20:22:06 +0900 | [diff] [blame] | 697 | dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr)); |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 698 | |
| 699 | *desc += host->desc_sz; |
| 700 | } |
| 701 | EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); |
| 702 | |
| 703 | static inline void __sdhci_adma_write_desc(struct sdhci_host *host, |
| 704 | void **desc, dma_addr_t addr, |
| 705 | int len, unsigned int cmd) |
| 706 | { |
| 707 | if (host->ops->adma_write_desc) |
| 708 | host->ops->adma_write_desc(host, desc, addr, len, cmd); |
Jisheng Zhang | 07be55b | 2018-09-17 13:30:41 +0800 | [diff] [blame] | 709 | else |
| 710 | sdhci_adma_write_desc(host, desc, addr, len, cmd); |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 711 | } |
| 712 | |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 713 | static void sdhci_adma_mark_end(void *desc) |
| 714 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 715 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 716 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 717 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 718 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 719 | } |
| 720 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 721 | static void sdhci_adma_table_pre(struct sdhci_host *host, |
| 722 | struct mmc_data *data, int sg_count) |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 723 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 724 | struct scatterlist *sg; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 725 | unsigned long flags; |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 726 | dma_addr_t addr, align_addr; |
| 727 | void *desc, *align; |
| 728 | char *buffer; |
| 729 | int len, offset, i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 730 | |
| 731 | /* |
| 732 | * The spec does not specify endianness of descriptor table. |
| 733 | * We currently guess that it is LE. |
| 734 | */ |
| 735 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 736 | host->sg_count = sg_count; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 737 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 738 | desc = host->adma_table; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 739 | align = host->align_buffer; |
| 740 | |
| 741 | align_addr = host->align_addr; |
| 742 | |
| 743 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 744 | addr = sg_dma_address(sg); |
| 745 | len = sg_dma_len(sg); |
| 746 | |
| 747 | /* |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 748 | * The SDHCI specification states that ADMA addresses must |
| 749 | * be 32-bit aligned. If they aren't, then we use a bounce |
| 750 | * buffer for the (up to three) bytes that screw up the |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 751 | * alignment. |
| 752 | */ |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 753 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
| 754 | SDHCI_ADMA2_MASK; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 755 | if (offset) { |
| 756 | if (data->flags & MMC_DATA_WRITE) { |
| 757 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 758 | memcpy(align, buffer, offset); |
| 759 | sdhci_kunmap_atomic(buffer, &flags); |
| 760 | } |
| 761 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 762 | /* tran, valid */ |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 763 | __sdhci_adma_write_desc(host, &desc, align_addr, |
| 764 | offset, ADMA2_TRAN_VALID); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 765 | |
| 766 | BUG_ON(offset > 65536); |
| 767 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 768 | align += SDHCI_ADMA2_ALIGN; |
| 769 | align_addr += SDHCI_ADMA2_ALIGN; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 770 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 771 | addr += offset; |
| 772 | len -= offset; |
| 773 | } |
| 774 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 775 | BUG_ON(len > 65536); |
| 776 | |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 777 | /* tran, valid */ |
| 778 | if (len) |
| 779 | __sdhci_adma_write_desc(host, &desc, addr, len, |
| 780 | ADMA2_TRAN_VALID); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 781 | |
| 782 | /* |
| 783 | * If this triggers then we have a calculation bug |
| 784 | * somewhere. :/ |
| 785 | */ |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 786 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 787 | } |
| 788 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 789 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 790 | /* Mark the last descriptor as the terminating descriptor */ |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 791 | if (desc != host->adma_table) { |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 792 | desc -= host->desc_sz; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 793 | sdhci_adma_mark_end(desc); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 794 | } |
| 795 | } else { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 796 | /* Add a terminating entry - nop, end, valid */ |
Jisheng Zhang | 54552e4 | 2018-08-28 17:47:23 +0800 | [diff] [blame] | 797 | __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 798 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | static void sdhci_adma_table_post(struct sdhci_host *host, |
| 802 | struct mmc_data *data) |
| 803 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 804 | struct scatterlist *sg; |
| 805 | int i, size; |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 806 | void *align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 807 | char *buffer; |
| 808 | unsigned long flags; |
| 809 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 810 | if (data->flags & MMC_DATA_READ) { |
| 811 | bool has_unaligned = false; |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 812 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 813 | /* Do a quick scan of the SG list for any unaligned mappings */ |
| 814 | for_each_sg(data->sg, sg, host->sg_count, i) |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 815 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 816 | has_unaligned = true; |
| 817 | break; |
| 818 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 819 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 820 | if (has_unaligned) { |
| 821 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
Russell King | f55c98f | 2016-01-26 13:40:11 +0000 | [diff] [blame] | 822 | data->sg_len, DMA_FROM_DEVICE); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 823 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 824 | align = host->align_buffer; |
| 825 | |
| 826 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 827 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
| 828 | size = SDHCI_ADMA2_ALIGN - |
| 829 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); |
| 830 | |
| 831 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 832 | memcpy(buffer, align, size); |
| 833 | sdhci_kunmap_atomic(buffer, &flags); |
| 834 | |
| 835 | align += SDHCI_ADMA2_ALIGN; |
| 836 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 837 | } |
| 838 | } |
| 839 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 840 | } |
| 841 | |
Masahiro Yamada | 38eee2e | 2019-08-29 20:22:06 +0900 | [diff] [blame] | 842 | static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr) |
| 843 | { |
| 844 | sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS); |
| 845 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 846 | sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); |
| 847 | } |
| 848 | |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 849 | static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 850 | { |
| 851 | if (host->bounce_buffer) |
| 852 | return host->bounce_addr; |
| 853 | else |
| 854 | return sg_dma_address(host->data->sg); |
| 855 | } |
| 856 | |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 857 | static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) |
| 858 | { |
Masahiro Yamada | 38eee2e | 2019-08-29 20:22:06 +0900 | [diff] [blame] | 859 | if (host->v4_mode) |
| 860 | sdhci_set_adma_addr(host, addr); |
| 861 | else |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 862 | sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 863 | } |
| 864 | |
Adrian Hunter | 0bb28d7 | 2018-04-27 17:17:16 +0530 | [diff] [blame] | 865 | static unsigned int sdhci_target_timeout(struct sdhci_host *host, |
| 866 | struct mmc_command *cmd, |
| 867 | struct mmc_data *data) |
| 868 | { |
| 869 | unsigned int target_timeout; |
| 870 | |
| 871 | /* timeout in us */ |
| 872 | if (!data) { |
| 873 | target_timeout = cmd->busy_timeout * 1000; |
| 874 | } else { |
| 875 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
| 876 | if (host->clock && data->timeout_clks) { |
| 877 | unsigned long long val; |
| 878 | |
| 879 | /* |
| 880 | * data->timeout_clks is in units of clock cycles. |
| 881 | * host->clock is in Hz. target_timeout is in us. |
| 882 | * Hence, us = 1000000 * cycles / Hz. Round up. |
| 883 | */ |
| 884 | val = 1000000ULL * data->timeout_clks; |
| 885 | if (do_div(val, host->clock)) |
| 886 | target_timeout++; |
| 887 | target_timeout += val; |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | return target_timeout; |
| 892 | } |
| 893 | |
Kishon Vijay Abraham I | fc1fa1b | 2018-04-27 17:17:17 +0530 | [diff] [blame] | 894 | static void sdhci_calc_sw_timeout(struct sdhci_host *host, |
| 895 | struct mmc_command *cmd) |
| 896 | { |
| 897 | struct mmc_data *data = cmd->data; |
| 898 | struct mmc_host *mmc = host->mmc; |
| 899 | struct mmc_ios *ios = &mmc->ios; |
| 900 | unsigned char bus_width = 1 << ios->bus_width; |
| 901 | unsigned int blksz; |
| 902 | unsigned int freq; |
| 903 | u64 target_timeout; |
| 904 | u64 transfer_time; |
| 905 | |
| 906 | target_timeout = sdhci_target_timeout(host, cmd, data); |
| 907 | target_timeout *= NSEC_PER_USEC; |
| 908 | |
| 909 | if (data) { |
| 910 | blksz = data->blksz; |
| 911 | freq = host->mmc->actual_clock ? : host->clock; |
| 912 | transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width); |
| 913 | do_div(transfer_time, freq); |
| 914 | /* multiply by '2' to account for any unknowns */ |
| 915 | transfer_time = transfer_time * 2; |
| 916 | /* calculate timeout for the entire data */ |
| 917 | host->data_timeout = data->blocks * target_timeout + |
| 918 | transfer_time; |
| 919 | } else { |
| 920 | host->data_timeout = target_timeout; |
| 921 | } |
| 922 | |
| 923 | if (host->data_timeout) |
| 924 | host->data_timeout += MMC_CMD_TRANSFER_TIME; |
| 925 | } |
| 926 | |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 927 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd, |
| 928 | bool *too_big) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 929 | { |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 930 | u8 count; |
BOUGH CHEN | 401059d | 2019-01-07 10:11:36 +0000 | [diff] [blame] | 931 | struct mmc_data *data; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 932 | unsigned target_timeout, current_timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 933 | |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 934 | *too_big = true; |
| 935 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 936 | /* |
| 937 | * If the host controller provides us with an incorrect timeout |
| 938 | * value, just skip the check and use 0xE. The hardware may take |
| 939 | * longer to time out, but that's much better than having a too-short |
| 940 | * timeout value. |
| 941 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 942 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 943 | return 0xE; |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 944 | |
BOUGH CHEN | 401059d | 2019-01-07 10:11:36 +0000 | [diff] [blame] | 945 | /* Unspecified command, asume max */ |
| 946 | if (cmd == NULL) |
| 947 | return 0xE; |
| 948 | |
| 949 | data = cmd->data; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 950 | /* Unspecified timeout, assume max */ |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 951 | if (!data && !cmd->busy_timeout) |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 952 | return 0xE; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 953 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 954 | /* timeout in us */ |
Adrian Hunter | 0bb28d7 | 2018-04-27 17:17:16 +0530 | [diff] [blame] | 955 | target_timeout = sdhci_target_timeout(host, cmd, data); |
Anton Vorontsov | 81b3980 | 2009-09-22 16:45:13 -0700 | [diff] [blame] | 956 | |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 957 | /* |
| 958 | * Figure out needed cycles. |
| 959 | * We do this in steps in order to fit inside a 32 bit int. |
| 960 | * The first step is the minimum timeout, which will have a |
| 961 | * minimum resolution of 6 bits: |
| 962 | * (1) 2^13*1000 > 2^22, |
| 963 | * (2) host->timeout_clk < 2^16 |
| 964 | * => |
| 965 | * (1) / (2) > 2^6 |
| 966 | */ |
| 967 | count = 0; |
| 968 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; |
| 969 | while (current_timeout < target_timeout) { |
| 970 | count++; |
| 971 | current_timeout <<= 1; |
| 972 | if (count >= 0xF) |
| 973 | break; |
| 974 | } |
| 975 | |
| 976 | if (count >= 0xF) { |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 977 | if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) |
| 978 | DBG("Too large timeout 0x%x requested for CMD%d!\n", |
| 979 | count, cmd->opcode); |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 980 | count = 0xE; |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 981 | } else { |
| 982 | *too_big = false; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 983 | } |
| 984 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 985 | return count; |
| 986 | } |
| 987 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 988 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
| 989 | { |
| 990 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; |
| 991 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
| 992 | |
| 993 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 994 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 995 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 996 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
| 997 | |
Adrian Hunter | af849c8 | 2018-11-15 15:53:43 +0200 | [diff] [blame] | 998 | if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12)) |
| 999 | host->ier |= SDHCI_INT_AUTO_CMD_ERR; |
| 1000 | else |
| 1001 | host->ier &= ~SDHCI_INT_AUTO_CMD_ERR; |
| 1002 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1003 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 1004 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 1005 | } |
| 1006 | |
Faiz Abbas | 7907ebe | 2020-01-16 16:21:49 +0530 | [diff] [blame] | 1007 | void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable) |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 1008 | { |
| 1009 | if (enable) |
| 1010 | host->ier |= SDHCI_INT_DATA_TIMEOUT; |
| 1011 | else |
| 1012 | host->ier &= ~SDHCI_INT_DATA_TIMEOUT; |
| 1013 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 1014 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
| 1015 | } |
Faiz Abbas | 7907ebe | 2020-01-16 16:21:49 +0530 | [diff] [blame] | 1016 | EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq); |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 1017 | |
Faiz Abbas | 7d76ed7 | 2020-01-16 16:21:50 +0530 | [diff] [blame] | 1018 | void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
| 1019 | { |
| 1020 | bool too_big = false; |
| 1021 | u8 count = sdhci_calc_timeout(host, cmd, &too_big); |
| 1022 | |
| 1023 | if (too_big && |
| 1024 | host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { |
| 1025 | sdhci_calc_sw_timeout(host, cmd); |
| 1026 | sdhci_set_data_timeout_irq(host, false); |
| 1027 | } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) { |
| 1028 | sdhci_set_data_timeout_irq(host, true); |
| 1029 | } |
| 1030 | |
| 1031 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
| 1032 | } |
| 1033 | EXPORT_SYMBOL_GPL(__sdhci_set_timeout); |
| 1034 | |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 1035 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 1036 | { |
Faiz Abbas | 7d76ed7 | 2020-01-16 16:21:50 +0530 | [diff] [blame] | 1037 | if (host->ops->set_timeout) |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 1038 | host->ops->set_timeout(host, cmd); |
Faiz Abbas | 7d76ed7 | 2020-01-16 16:21:50 +0530 | [diff] [blame] | 1039 | else |
| 1040 | __sdhci_set_timeout(host, cmd); |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 1041 | } |
| 1042 | |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1043 | static void sdhci_initialize_data(struct sdhci_host *host, |
| 1044 | struct mmc_data *data) |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 1045 | { |
Adrian Hunter | 43dea09 | 2016-06-29 16:24:26 +0300 | [diff] [blame] | 1046 | WARN_ON(host->data); |
| 1047 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 1048 | /* Sanity checks */ |
| 1049 | BUG_ON(data->blksz * data->blocks > 524288); |
| 1050 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
| 1051 | BUG_ON(data->blocks > 65535); |
| 1052 | |
| 1053 | host->data = data; |
| 1054 | host->data_early = 0; |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 1055 | host->data->bytes_xfered = 0; |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1056 | } |
| 1057 | |
| 1058 | static inline void sdhci_set_block_info(struct sdhci_host *host, |
| 1059 | struct mmc_data *data) |
| 1060 | { |
| 1061 | /* Set the DMA boundary value and block size */ |
| 1062 | sdhci_writew(host, |
| 1063 | SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), |
| 1064 | SDHCI_BLOCK_SIZE); |
| 1065 | /* |
| 1066 | * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count |
| 1067 | * can be supported, in that case 16-bit block count register must be 0. |
| 1068 | */ |
| 1069 | if (host->version >= SDHCI_SPEC_410 && host->v4_mode && |
| 1070 | (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { |
| 1071 | if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) |
| 1072 | sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); |
| 1073 | sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); |
| 1074 | } else { |
| 1075 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
| 1076 | } |
| 1077 | } |
| 1078 | |
| 1079 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
| 1080 | { |
| 1081 | struct mmc_data *data = cmd->data; |
| 1082 | |
| 1083 | sdhci_initialize_data(host, data); |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 1084 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 1085 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1086 | struct scatterlist *sg; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1087 | unsigned int length_mask, offset_mask; |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1088 | int i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1089 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 1090 | host->flags |= SDHCI_REQ_USE_DMA; |
| 1091 | |
| 1092 | /* |
| 1093 | * FIXME: This doesn't account for merging when mapping the |
| 1094 | * scatterlist. |
| 1095 | * |
| 1096 | * The assumption here being that alignment and lengths are |
| 1097 | * the same after DMA mapping to device address space. |
| 1098 | */ |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1099 | length_mask = 0; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1100 | offset_mask = 0; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1101 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1102 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1103 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1104 | /* |
| 1105 | * As we use up to 3 byte chunks to work |
| 1106 | * around alignment problems, we need to |
| 1107 | * check the offset as well. |
| 1108 | */ |
| 1109 | offset_mask = 3; |
| 1110 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1111 | } else { |
| 1112 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1113 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1114 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
| 1115 | offset_mask = 3; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1116 | } |
| 1117 | |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 1118 | if (unlikely(length_mask | offset_mask)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1119 | for_each_sg(data->sg, sg, data->sg_len, i) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1120 | if (sg->length & length_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1121 | DBG("Reverting to PIO because of transfer size (%d)\n", |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1122 | sg->length); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1123 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 1124 | break; |
| 1125 | } |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 1126 | if (sg->offset & offset_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1127 | DBG("Reverting to PIO because of bad alignment\n"); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 1128 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 1129 | break; |
| 1130 | } |
| 1131 | } |
| 1132 | } |
| 1133 | } |
| 1134 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 1135 | if (host->flags & SDHCI_REQ_USE_DMA) { |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 1136 | int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 1137 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 1138 | if (sg_cnt <= 0) { |
| 1139 | /* |
| 1140 | * This only happens when someone fed |
| 1141 | * us an invalid request. |
| 1142 | */ |
| 1143 | WARN_ON(1); |
| 1144 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 1145 | } else if (host->flags & SDHCI_USE_ADMA) { |
| 1146 | sdhci_adma_table_pre(host, data, sg_cnt); |
Masahiro Yamada | 38eee2e | 2019-08-29 20:22:06 +0900 | [diff] [blame] | 1147 | sdhci_set_adma_addr(host, host->adma_addr); |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 1148 | } else { |
| 1149 | WARN_ON(sg_cnt != 1); |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 1150 | sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 1151 | } |
| 1152 | } |
| 1153 | |
Chunyan Zhang | 685e444 | 2018-08-30 16:21:40 +0800 | [diff] [blame] | 1154 | sdhci_config_dma(host); |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 1155 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 1156 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
Sebastian Andrzej Siewior | da60a91 | 2009-06-18 09:33:32 +0200 | [diff] [blame] | 1157 | int flags; |
| 1158 | |
| 1159 | flags = SG_MITER_ATOMIC; |
| 1160 | if (host->data->flags & MMC_DATA_READ) |
| 1161 | flags |= SG_MITER_TO_SG; |
| 1162 | else |
| 1163 | flags |= SG_MITER_FROM_SG; |
| 1164 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 1165 | host->blocks = data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1166 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1167 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 1168 | sdhci_set_transfer_irqs(host); |
| 1169 | |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1170 | sdhci_set_block_info(host, data); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1171 | } |
| 1172 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 1173 | #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) |
| 1174 | |
| 1175 | static int sdhci_external_dma_init(struct sdhci_host *host) |
| 1176 | { |
| 1177 | int ret = 0; |
| 1178 | struct mmc_host *mmc = host->mmc; |
| 1179 | |
| 1180 | host->tx_chan = dma_request_chan(mmc->parent, "tx"); |
| 1181 | if (IS_ERR(host->tx_chan)) { |
| 1182 | ret = PTR_ERR(host->tx_chan); |
| 1183 | if (ret != -EPROBE_DEFER) |
| 1184 | pr_warn("Failed to request TX DMA channel.\n"); |
| 1185 | host->tx_chan = NULL; |
| 1186 | return ret; |
| 1187 | } |
| 1188 | |
| 1189 | host->rx_chan = dma_request_chan(mmc->parent, "rx"); |
| 1190 | if (IS_ERR(host->rx_chan)) { |
| 1191 | if (host->tx_chan) { |
| 1192 | dma_release_channel(host->tx_chan); |
| 1193 | host->tx_chan = NULL; |
| 1194 | } |
| 1195 | |
| 1196 | ret = PTR_ERR(host->rx_chan); |
| 1197 | if (ret != -EPROBE_DEFER) |
| 1198 | pr_warn("Failed to request RX DMA channel.\n"); |
| 1199 | host->rx_chan = NULL; |
| 1200 | } |
| 1201 | |
| 1202 | return ret; |
| 1203 | } |
| 1204 | |
| 1205 | static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, |
| 1206 | struct mmc_data *data) |
| 1207 | { |
| 1208 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; |
| 1209 | } |
| 1210 | |
| 1211 | static int sdhci_external_dma_setup(struct sdhci_host *host, |
| 1212 | struct mmc_command *cmd) |
| 1213 | { |
| 1214 | int ret, i; |
Chunyan Zhang | 1215c02 | 2020-01-20 11:32:23 +0800 | [diff] [blame] | 1215 | enum dma_transfer_direction dir; |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 1216 | struct dma_async_tx_descriptor *desc; |
| 1217 | struct mmc_data *data = cmd->data; |
| 1218 | struct dma_chan *chan; |
| 1219 | struct dma_slave_config cfg; |
| 1220 | dma_cookie_t cookie; |
| 1221 | int sg_cnt; |
| 1222 | |
| 1223 | if (!host->mapbase) |
| 1224 | return -EINVAL; |
| 1225 | |
| 1226 | cfg.src_addr = host->mapbase + SDHCI_BUFFER; |
| 1227 | cfg.dst_addr = host->mapbase + SDHCI_BUFFER; |
| 1228 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 1229 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 1230 | cfg.src_maxburst = data->blksz / 4; |
| 1231 | cfg.dst_maxburst = data->blksz / 4; |
| 1232 | |
| 1233 | /* Sanity check: all the SG entries must be aligned by block size. */ |
| 1234 | for (i = 0; i < data->sg_len; i++) { |
| 1235 | if ((data->sg + i)->length % data->blksz) |
| 1236 | return -EINVAL; |
| 1237 | } |
| 1238 | |
| 1239 | chan = sdhci_external_dma_channel(host, data); |
| 1240 | |
| 1241 | ret = dmaengine_slave_config(chan, &cfg); |
| 1242 | if (ret) |
| 1243 | return ret; |
| 1244 | |
| 1245 | sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
| 1246 | if (sg_cnt <= 0) |
| 1247 | return -EINVAL; |
| 1248 | |
Chunyan Zhang | 1215c02 | 2020-01-20 11:32:23 +0800 | [diff] [blame] | 1249 | dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; |
| 1250 | desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir, |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 1251 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1252 | if (!desc) |
| 1253 | return -EINVAL; |
| 1254 | |
| 1255 | desc->callback = NULL; |
| 1256 | desc->callback_param = NULL; |
| 1257 | |
| 1258 | cookie = dmaengine_submit(desc); |
| 1259 | if (dma_submit_error(cookie)) |
| 1260 | ret = cookie; |
| 1261 | |
| 1262 | return ret; |
| 1263 | } |
| 1264 | |
| 1265 | static void sdhci_external_dma_release(struct sdhci_host *host) |
| 1266 | { |
| 1267 | if (host->tx_chan) { |
| 1268 | dma_release_channel(host->tx_chan); |
| 1269 | host->tx_chan = NULL; |
| 1270 | } |
| 1271 | |
| 1272 | if (host->rx_chan) { |
| 1273 | dma_release_channel(host->rx_chan); |
| 1274 | host->rx_chan = NULL; |
| 1275 | } |
| 1276 | |
| 1277 | sdhci_switch_external_dma(host, false); |
| 1278 | } |
| 1279 | |
| 1280 | static void __sdhci_external_dma_prepare_data(struct sdhci_host *host, |
| 1281 | struct mmc_command *cmd) |
| 1282 | { |
| 1283 | struct mmc_data *data = cmd->data; |
| 1284 | |
| 1285 | sdhci_initialize_data(host, data); |
| 1286 | |
| 1287 | host->flags |= SDHCI_REQ_USE_DMA; |
| 1288 | sdhci_set_transfer_irqs(host); |
| 1289 | |
| 1290 | sdhci_set_block_info(host, data); |
| 1291 | } |
| 1292 | |
| 1293 | static void sdhci_external_dma_prepare_data(struct sdhci_host *host, |
| 1294 | struct mmc_command *cmd) |
| 1295 | { |
| 1296 | if (!sdhci_external_dma_setup(host, cmd)) { |
| 1297 | __sdhci_external_dma_prepare_data(host, cmd); |
| 1298 | } else { |
| 1299 | sdhci_external_dma_release(host); |
| 1300 | pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n", |
| 1301 | mmc_hostname(host->mmc)); |
| 1302 | sdhci_prepare_data(host, cmd); |
| 1303 | } |
| 1304 | } |
| 1305 | |
| 1306 | static void sdhci_external_dma_pre_transfer(struct sdhci_host *host, |
| 1307 | struct mmc_command *cmd) |
| 1308 | { |
| 1309 | struct dma_chan *chan; |
| 1310 | |
| 1311 | if (!cmd->data) |
| 1312 | return; |
| 1313 | |
| 1314 | chan = sdhci_external_dma_channel(host, cmd->data); |
| 1315 | if (chan) |
| 1316 | dma_async_issue_pending(chan); |
| 1317 | } |
| 1318 | |
| 1319 | #else |
| 1320 | |
| 1321 | static inline int sdhci_external_dma_init(struct sdhci_host *host) |
| 1322 | { |
| 1323 | return -EOPNOTSUPP; |
| 1324 | } |
| 1325 | |
| 1326 | static inline void sdhci_external_dma_release(struct sdhci_host *host) |
| 1327 | { |
| 1328 | } |
| 1329 | |
| 1330 | static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host, |
| 1331 | struct mmc_command *cmd) |
| 1332 | { |
| 1333 | /* This should never happen */ |
| 1334 | WARN_ON_ONCE(1); |
| 1335 | } |
| 1336 | |
| 1337 | static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host, |
| 1338 | struct mmc_command *cmd) |
| 1339 | { |
| 1340 | } |
| 1341 | |
| 1342 | static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, |
| 1343 | struct mmc_data *data) |
| 1344 | { |
| 1345 | return NULL; |
| 1346 | } |
| 1347 | |
| 1348 | #endif |
| 1349 | |
| 1350 | void sdhci_switch_external_dma(struct sdhci_host *host, bool en) |
| 1351 | { |
| 1352 | host->use_external_dma = en; |
| 1353 | } |
| 1354 | EXPORT_SYMBOL_GPL(sdhci_switch_external_dma); |
| 1355 | |
Adrian Hunter | 0293d50 | 2016-06-29 16:24:35 +0300 | [diff] [blame] | 1356 | static inline bool sdhci_auto_cmd12(struct sdhci_host *host, |
| 1357 | struct mmc_request *mrq) |
| 1358 | { |
Adrian Hunter | 20845be | 2016-08-16 13:44:13 +0300 | [diff] [blame] | 1359 | return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && |
| 1360 | !mrq->cap_cmd_during_tfr; |
Adrian Hunter | 0293d50 | 2016-06-29 16:24:35 +0300 | [diff] [blame] | 1361 | } |
| 1362 | |
Adrian Hunter | ed63303 | 2020-04-12 12:03:45 +0300 | [diff] [blame] | 1363 | static inline bool sdhci_auto_cmd23(struct sdhci_host *host, |
| 1364 | struct mmc_request *mrq) |
| 1365 | { |
| 1366 | return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); |
| 1367 | } |
| 1368 | |
| 1369 | static inline bool sdhci_manual_cmd23(struct sdhci_host *host, |
| 1370 | struct mmc_request *mrq) |
| 1371 | { |
| 1372 | return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23); |
| 1373 | } |
| 1374 | |
Chunyan Zhang | 427b651 | 2018-08-30 16:21:42 +0800 | [diff] [blame] | 1375 | static inline void sdhci_auto_cmd_select(struct sdhci_host *host, |
| 1376 | struct mmc_command *cmd, |
| 1377 | u16 *mode) |
| 1378 | { |
| 1379 | bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && |
| 1380 | (cmd->opcode != SD_IO_RW_EXTENDED); |
Adrian Hunter | ed63303 | 2020-04-12 12:03:45 +0300 | [diff] [blame] | 1381 | bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq); |
Chunyan Zhang | 427b651 | 2018-08-30 16:21:42 +0800 | [diff] [blame] | 1382 | u16 ctrl2; |
| 1383 | |
| 1384 | /* |
| 1385 | * In case of Version 4.10 or later, use of 'Auto CMD Auto |
| 1386 | * Select' is recommended rather than use of 'Auto CMD12 |
| 1387 | * Enable' or 'Auto CMD23 Enable'. |
| 1388 | */ |
| 1389 | if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { |
| 1390 | *mode |= SDHCI_TRNS_AUTO_SEL; |
| 1391 | |
| 1392 | ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1393 | if (use_cmd23) |
| 1394 | ctrl2 |= SDHCI_CMD23_ENABLE; |
| 1395 | else |
| 1396 | ctrl2 &= ~SDHCI_CMD23_ENABLE; |
| 1397 | sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); |
| 1398 | |
| 1399 | return; |
| 1400 | } |
| 1401 | |
| 1402 | /* |
| 1403 | * If we are sending CMD23, CMD12 never gets sent |
| 1404 | * on successful completion (so no Auto-CMD12). |
| 1405 | */ |
| 1406 | if (use_cmd12) |
| 1407 | *mode |= SDHCI_TRNS_AUTO_CMD12; |
| 1408 | else if (use_cmd23) |
| 1409 | *mode |= SDHCI_TRNS_AUTO_CMD23; |
| 1410 | } |
| 1411 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1412 | static void sdhci_set_transfer_mode(struct sdhci_host *host, |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1413 | struct mmc_command *cmd) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1414 | { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 1415 | u16 mode = 0; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1416 | struct mmc_data *data = cmd->data; |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1417 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 1418 | if (data == NULL) { |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 1419 | if (host->quirks2 & |
| 1420 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { |
ernest.zhang | 0086fc2 | 2018-07-16 14:26:54 +0800 | [diff] [blame] | 1421 | /* must not clear SDHCI_TRANSFER_MODE when tuning */ |
| 1422 | if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) |
| 1423 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 1424 | } else { |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 1425 | /* clear Auto CMD settings for no data CMDs */ |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 1426 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
| 1427 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 1428 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 1429 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1430 | return; |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 1431 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1432 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1433 | WARN_ON(!host->data); |
| 1434 | |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 1435 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
| 1436 | mode = SDHCI_TRNS_BLK_CNT_EN; |
| 1437 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1438 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 1439 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
Chunyan Zhang | 427b651 | 2018-08-30 16:21:42 +0800 | [diff] [blame] | 1440 | sdhci_auto_cmd_select(host, cmd, &mode); |
Adrian Hunter | ed63303 | 2020-04-12 12:03:45 +0300 | [diff] [blame] | 1441 | if (sdhci_auto_cmd23(host, cmd->mrq)) |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1442 | sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 1443 | } |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 1444 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1445 | if (data->flags & MMC_DATA_READ) |
| 1446 | mode |= SDHCI_TRNS_READ; |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 1447 | if (host->flags & SDHCI_REQ_USE_DMA) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1448 | mode |= SDHCI_TRNS_DMA; |
| 1449 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1450 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1451 | } |
| 1452 | |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 1453 | static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) |
| 1454 | { |
| 1455 | return (!(host->flags & SDHCI_DEVICE_DEAD) && |
| 1456 | ((mrq->cmd && mrq->cmd->error) || |
| 1457 | (mrq->sbc && mrq->sbc->error) || |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 1458 | (mrq->data && mrq->data->stop && mrq->data->stop->error) || |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 1459 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); |
| 1460 | } |
| 1461 | |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1462 | static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 1463 | { |
| 1464 | int i; |
| 1465 | |
| 1466 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 1467 | if (host->mrqs_done[i] == mrq) { |
| 1468 | WARN_ON(1); |
| 1469 | return; |
| 1470 | } |
| 1471 | } |
| 1472 | |
| 1473 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 1474 | if (!host->mrqs_done[i]) { |
| 1475 | host->mrqs_done[i] = mrq; |
| 1476 | break; |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | WARN_ON(i >= SDHCI_MAX_MRQS); |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1481 | } |
| 1482 | |
| 1483 | static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) |
| 1484 | { |
| 1485 | if (host->cmd && host->cmd->mrq == mrq) |
| 1486 | host->cmd = NULL; |
| 1487 | |
| 1488 | if (host->data_cmd && host->data_cmd->mrq == mrq) |
| 1489 | host->data_cmd = NULL; |
| 1490 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1491 | if (host->deferred_cmd && host->deferred_cmd->mrq == mrq) |
| 1492 | host->deferred_cmd = NULL; |
| 1493 | |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1494 | if (host->data && host->data->mrq == mrq) |
| 1495 | host->data = NULL; |
| 1496 | |
| 1497 | if (sdhci_needs_reset(host, mrq)) |
| 1498 | host->pending_reset = true; |
| 1499 | |
| 1500 | sdhci_set_mrq_done(host, mrq); |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 1501 | |
Adrian Hunter | e9a0729 | 2019-04-05 15:40:18 +0300 | [diff] [blame] | 1502 | sdhci_del_timer(host, mrq); |
| 1503 | |
| 1504 | if (!sdhci_has_requests(host)) |
| 1505 | sdhci_led_deactivate(host); |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 1506 | } |
| 1507 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1508 | static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) |
| 1509 | { |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 1510 | __sdhci_finish_mrq(host, mrq); |
Adrian Hunter | 2e72ab9 | 2019-04-05 15:40:16 +0300 | [diff] [blame] | 1511 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 1512 | queue_work(host->complete_wq, &host->complete_work); |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1513 | } |
| 1514 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1515 | static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1516 | { |
Adrian Hunter | 33a57ad | 2016-06-29 16:24:36 +0300 | [diff] [blame] | 1517 | struct mmc_command *data_cmd = host->data_cmd; |
| 1518 | struct mmc_data *data = host->data; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1519 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1520 | host->data = NULL; |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 1521 | host->data_cmd = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1522 | |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 1523 | /* |
| 1524 | * The controller needs a reset of internal state machines upon error |
| 1525 | * conditions. |
| 1526 | */ |
| 1527 | if (data->error) { |
| 1528 | if (!host->cmd || host->cmd == data_cmd) |
| 1529 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 1530 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
| 1531 | } |
| 1532 | |
Russell King | add8913 | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 1533 | if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == |
| 1534 | (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) |
| 1535 | sdhci_adma_table_post(host, data); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1536 | |
| 1537 | /* |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1538 | * The specification states that the block count register must |
| 1539 | * be updated, but it does not specify at what point in the |
| 1540 | * data flow. That makes the register entirely useless to read |
| 1541 | * back so we have to assume that nothing made it to the card |
| 1542 | * in the event of an error. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1543 | */ |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1544 | if (data->error) |
| 1545 | data->bytes_xfered = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1546 | else |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1547 | data->bytes_xfered = data->blksz * data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1548 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1549 | /* |
| 1550 | * Need to send CMD12 if - |
Yangbo Lu | fdbbe6c | 2019-11-14 19:18:14 +0800 | [diff] [blame] | 1551 | * a) open-ended multiblock transfer not using auto CMD12 (no CMD23) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1552 | * b) error in multiblock transfer |
| 1553 | */ |
| 1554 | if (data->stop && |
Yangbo Lu | fdbbe6c | 2019-11-14 19:18:14 +0800 | [diff] [blame] | 1555 | ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) || |
| 1556 | data->error)) { |
Adrian Hunter | 20845be | 2016-08-16 13:44:13 +0300 | [diff] [blame] | 1557 | /* |
| 1558 | * 'cap_cmd_during_tfr' request must not use the command line |
| 1559 | * after mmc_command_done() has been called. It is upper layer's |
| 1560 | * responsibility to send the stop command if required. |
| 1561 | */ |
| 1562 | if (data->mrq->cap_cmd_during_tfr) { |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 1563 | __sdhci_finish_mrq(host, data->mrq); |
Adrian Hunter | 20845be | 2016-08-16 13:44:13 +0300 | [diff] [blame] | 1564 | } else { |
| 1565 | /* Avoid triggering warning in sdhci_send_command() */ |
| 1566 | host->cmd = NULL; |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1567 | if (!sdhci_send_command(host, data->stop)) { |
| 1568 | if (sw_data_timeout) { |
| 1569 | /* |
| 1570 | * This is anyway a sw data timeout, so |
| 1571 | * give up now. |
| 1572 | */ |
| 1573 | data->stop->error = -EIO; |
| 1574 | __sdhci_finish_mrq(host, data->mrq); |
| 1575 | } else { |
| 1576 | WARN_ON(host->deferred_cmd); |
| 1577 | host->deferred_cmd = data->stop; |
| 1578 | } |
| 1579 | } |
Adrian Hunter | 20845be | 2016-08-16 13:44:13 +0300 | [diff] [blame] | 1580 | } |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1581 | } else { |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 1582 | __sdhci_finish_mrq(host, data->mrq); |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1583 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1584 | } |
| 1585 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1586 | static void sdhci_finish_data(struct sdhci_host *host) |
| 1587 | { |
| 1588 | __sdhci_finish_data(host, false); |
| 1589 | } |
| 1590 | |
| 1591 | static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1592 | { |
| 1593 | int flags; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1594 | u32 mask; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1595 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1596 | |
| 1597 | WARN_ON(host->cmd); |
| 1598 | |
Russell King | 9677620 | 2016-01-26 13:39:34 +0000 | [diff] [blame] | 1599 | /* Initially, a command has no error */ |
| 1600 | cmd->error = 0; |
| 1601 | |
Adrian Hunter | fc605f1 | 2016-10-05 12:11:21 +0300 | [diff] [blame] | 1602 | if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
| 1603 | cmd->opcode == MMC_STOP_TRANSMISSION) |
| 1604 | cmd->flags |= MMC_RSP_BUSY; |
| 1605 | |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1606 | mask = SDHCI_CMD_INHIBIT; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 1607 | if (sdhci_data_line_cmd(cmd)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1608 | mask |= SDHCI_DATA_INHIBIT; |
| 1609 | |
| 1610 | /* We shouldn't wait for data inihibit for stop commands, even |
| 1611 | though they might use busy signaling */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1612 | if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1613 | mask &= ~SDHCI_DATA_INHIBIT; |
| 1614 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1615 | if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) |
| 1616 | return false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1617 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1618 | host->cmd = cmd; |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1619 | host->data_timeout = 0; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 1620 | if (sdhci_data_line_cmd(cmd)) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 1621 | WARN_ON(host->data_cmd); |
| 1622 | host->data_cmd = cmd; |
Faiz Abbas | 15db183 | 2020-01-16 16:21:46 +0530 | [diff] [blame] | 1623 | sdhci_set_timeout(host, cmd); |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 1624 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1625 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 1626 | if (cmd->data) { |
| 1627 | if (host->use_external_dma) |
| 1628 | sdhci_external_dma_prepare_data(host, cmd); |
| 1629 | else |
| 1630 | sdhci_prepare_data(host, cmd); |
| 1631 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1632 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1633 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1634 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1635 | sdhci_set_transfer_mode(host, cmd); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1636 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1637 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1638 | WARN_ONCE(1, "Unsupported response type!\n"); |
| 1639 | /* |
| 1640 | * This does not happen in practice because 136-bit response |
| 1641 | * commands never have busy waiting, so rather than complicate |
| 1642 | * the error path, just remove busy waiting and continue. |
| 1643 | */ |
| 1644 | cmd->flags &= ~MMC_RSP_BUSY; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1645 | } |
| 1646 | |
| 1647 | if (!(cmd->flags & MMC_RSP_PRESENT)) |
| 1648 | flags = SDHCI_CMD_RESP_NONE; |
| 1649 | else if (cmd->flags & MMC_RSP_136) |
| 1650 | flags = SDHCI_CMD_RESP_LONG; |
| 1651 | else if (cmd->flags & MMC_RSP_BUSY) |
| 1652 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 1653 | else |
| 1654 | flags = SDHCI_CMD_RESP_SHORT; |
| 1655 | |
| 1656 | if (cmd->flags & MMC_RSP_CRC) |
| 1657 | flags |= SDHCI_CMD_CRC; |
| 1658 | if (cmd->flags & MMC_RSP_OPCODE) |
| 1659 | flags |= SDHCI_CMD_INDEX; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1660 | |
| 1661 | /* CMD19 is special in that the Data Present Select should be set */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1662 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
| 1663 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1664 | flags |= SDHCI_CMD_DATA; |
| 1665 | |
Kishon Vijay Abraham I | fc1fa1b | 2018-04-27 17:17:17 +0530 | [diff] [blame] | 1666 | timeout = jiffies; |
| 1667 | if (host->data_timeout) |
| 1668 | timeout += nsecs_to_jiffies(host->data_timeout); |
| 1669 | else if (!cmd->data && cmd->busy_timeout > 9000) |
| 1670 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; |
| 1671 | else |
| 1672 | timeout += 10 * HZ; |
| 1673 | sdhci_mod_timer(host, cmd->mrq, timeout); |
| 1674 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 1675 | if (host->use_external_dma) |
| 1676 | sdhci_external_dma_pre_transfer(host, cmd); |
| 1677 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1678 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1679 | |
| 1680 | return true; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1681 | } |
| 1682 | |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 1683 | static bool sdhci_present_error(struct sdhci_host *host, |
| 1684 | struct mmc_command *cmd, bool present) |
| 1685 | { |
| 1686 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
| 1687 | cmd->error = -ENOMEDIUM; |
| 1688 | return true; |
| 1689 | } |
| 1690 | |
| 1691 | return false; |
| 1692 | } |
| 1693 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1694 | static bool sdhci_send_command_retry(struct sdhci_host *host, |
| 1695 | struct mmc_command *cmd, |
| 1696 | unsigned long flags) |
| 1697 | __releases(host->lock) |
| 1698 | __acquires(host->lock) |
| 1699 | { |
| 1700 | struct mmc_command *deferred_cmd = host->deferred_cmd; |
| 1701 | int timeout = 10; /* Approx. 10 ms */ |
| 1702 | bool present; |
| 1703 | |
| 1704 | while (!sdhci_send_command(host, cmd)) { |
| 1705 | if (!timeout--) { |
| 1706 | pr_err("%s: Controller never released inhibit bit(s).\n", |
| 1707 | mmc_hostname(host->mmc)); |
| 1708 | sdhci_dumpregs(host); |
| 1709 | cmd->error = -EIO; |
| 1710 | return false; |
| 1711 | } |
| 1712 | |
| 1713 | spin_unlock_irqrestore(&host->lock, flags); |
| 1714 | |
| 1715 | usleep_range(1000, 1250); |
| 1716 | |
| 1717 | present = host->mmc->ops->get_cd(host->mmc); |
| 1718 | |
| 1719 | spin_lock_irqsave(&host->lock, flags); |
| 1720 | |
| 1721 | /* A deferred command might disappear, handle that */ |
| 1722 | if (cmd == deferred_cmd && cmd != host->deferred_cmd) |
| 1723 | return true; |
| 1724 | |
| 1725 | if (sdhci_present_error(host, cmd, present)) |
| 1726 | return false; |
| 1727 | } |
| 1728 | |
| 1729 | if (cmd == host->deferred_cmd) |
| 1730 | host->deferred_cmd = NULL; |
| 1731 | |
| 1732 | return true; |
| 1733 | } |
| 1734 | |
Adrian Hunter | 4a5fc11 | 2017-08-21 13:11:28 +0530 | [diff] [blame] | 1735 | static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd) |
| 1736 | { |
| 1737 | int i, reg; |
| 1738 | |
| 1739 | for (i = 0; i < 4; i++) { |
| 1740 | reg = SDHCI_RESPONSE + (3 - i) * 4; |
| 1741 | cmd->resp[i] = sdhci_readl(host, reg); |
| 1742 | } |
| 1743 | |
Kishon Vijay Abraham I | 1284c24 | 2017-08-21 13:11:29 +0530 | [diff] [blame] | 1744 | if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC) |
| 1745 | return; |
| 1746 | |
Adrian Hunter | 4a5fc11 | 2017-08-21 13:11:28 +0530 | [diff] [blame] | 1747 | /* CRC is stripped so we need to do some shifting */ |
| 1748 | for (i = 0; i < 4; i++) { |
| 1749 | cmd->resp[i] <<= 8; |
| 1750 | if (i != 3) |
| 1751 | cmd->resp[i] |= cmd->resp[i + 1] >> 24; |
| 1752 | } |
| 1753 | } |
| 1754 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1755 | static void sdhci_finish_command(struct sdhci_host *host) |
| 1756 | { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1757 | struct mmc_command *cmd = host->cmd; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1758 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1759 | host->cmd = NULL; |
| 1760 | |
| 1761 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 1762 | if (cmd->flags & MMC_RSP_136) { |
Adrian Hunter | 4a5fc11 | 2017-08-21 13:11:28 +0530 | [diff] [blame] | 1763 | sdhci_read_rsp_136(host, cmd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1764 | } else { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1765 | cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1766 | } |
| 1767 | } |
| 1768 | |
Adrian Hunter | 20845be | 2016-08-16 13:44:13 +0300 | [diff] [blame] | 1769 | if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) |
| 1770 | mmc_command_done(host->mmc, cmd->mrq); |
| 1771 | |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1772 | /* |
| 1773 | * The host can send and interrupt when the busy state has |
| 1774 | * ended, allowing us to wait without wasting CPU cycles. |
| 1775 | * The busy signal uses DAT0 so this is similar to waiting |
| 1776 | * for data to complete. |
| 1777 | * |
| 1778 | * Note: The 1.0 specification is a bit ambiguous about this |
| 1779 | * feature so there might be some problems with older |
| 1780 | * controllers. |
| 1781 | */ |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1782 | if (cmd->flags & MMC_RSP_BUSY) { |
| 1783 | if (cmd->data) { |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1784 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
| 1785 | } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 1786 | cmd == host->data_cmd) { |
| 1787 | /* Command complete before busy is ended */ |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1788 | return; |
| 1789 | } |
| 1790 | } |
| 1791 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1792 | /* Finished CMD23, now send actual command. */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1793 | if (cmd == cmd->mrq->sbc) { |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 1794 | if (!sdhci_send_command(host, cmd->mrq->cmd)) { |
| 1795 | WARN_ON(host->deferred_cmd); |
| 1796 | host->deferred_cmd = cmd->mrq->cmd; |
| 1797 | } |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1798 | } else { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1799 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1800 | /* Processed actual command. */ |
| 1801 | if (host->data && host->data_early) |
| 1802 | sdhci_finish_data(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1803 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1804 | if (!cmd->data) |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 1805 | __sdhci_finish_mrq(host, cmd->mrq); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1806 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1807 | } |
| 1808 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1809 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
| 1810 | { |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1811 | u16 preset = 0; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1812 | |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1813 | switch (host->timing) { |
| 1814 | case MMC_TIMING_UHS_SDR12: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1815 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1816 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1817 | case MMC_TIMING_UHS_SDR25: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1818 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
| 1819 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1820 | case MMC_TIMING_UHS_SDR50: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1821 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
| 1822 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1823 | case MMC_TIMING_UHS_SDR104: |
| 1824 | case MMC_TIMING_MMC_HS200: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1825 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
| 1826 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1827 | case MMC_TIMING_UHS_DDR50: |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1828 | case MMC_TIMING_MMC_DDR52: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1829 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
| 1830 | break; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1831 | case MMC_TIMING_MMC_HS400: |
| 1832 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); |
| 1833 | break; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1834 | default: |
| 1835 | pr_warn("%s: Invalid UHS-I mode selected\n", |
| 1836 | mmc_hostname(host->mmc)); |
| 1837 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1838 | break; |
| 1839 | } |
| 1840 | return preset; |
| 1841 | } |
| 1842 | |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1843 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
| 1844 | unsigned int *actual_clock) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1845 | { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1846 | int div = 0; /* Initialized for compiler warning */ |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1847 | int real_div = div, clk_mul = 1; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1848 | u16 clk = 0; |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1849 | bool switch_base_clk = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1850 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1851 | if (host->version >= SDHCI_SPEC_300) { |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1852 | if (host->preset_enabled) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1853 | u16 pre_val; |
| 1854 | |
| 1855 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1856 | pre_val = sdhci_get_preset_value(host); |
Masahiro Yamada | fa09101 | 2020-03-12 20:00:50 +0900 | [diff] [blame] | 1857 | div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1858 | if (host->clk_mul && |
Masahiro Yamada | fa09101 | 2020-03-12 20:00:50 +0900 | [diff] [blame] | 1859 | (pre_val & SDHCI_PRESET_CLKGEN_SEL)) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1860 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1861 | real_div = div + 1; |
| 1862 | clk_mul = host->clk_mul; |
| 1863 | } else { |
| 1864 | real_div = max_t(int, 1, div << 1); |
| 1865 | } |
| 1866 | goto clock_set; |
| 1867 | } |
| 1868 | |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1869 | /* |
| 1870 | * Check if the Host Controller supports Programmable Clock |
| 1871 | * Mode. |
| 1872 | */ |
| 1873 | if (host->clk_mul) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1874 | for (div = 1; div <= 1024; div++) { |
| 1875 | if ((host->max_clk * host->clk_mul / div) |
| 1876 | <= clock) |
| 1877 | break; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1878 | } |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1879 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
| 1880 | /* |
| 1881 | * Set Programmable Clock Mode in the Clock |
| 1882 | * Control register. |
| 1883 | */ |
| 1884 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1885 | real_div = div; |
| 1886 | clk_mul = host->clk_mul; |
| 1887 | div--; |
| 1888 | } else { |
| 1889 | /* |
| 1890 | * Divisor can be too small to reach clock |
| 1891 | * speed requirement. Then use the base clock. |
| 1892 | */ |
| 1893 | switch_base_clk = true; |
| 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | if (!host->clk_mul || switch_base_clk) { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1898 | /* Version 3.00 divisors must be a multiple of 2. */ |
| 1899 | if (host->max_clk <= clock) |
| 1900 | div = 1; |
| 1901 | else { |
| 1902 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; |
| 1903 | div += 2) { |
| 1904 | if ((host->max_clk / div) <= clock) |
| 1905 | break; |
| 1906 | } |
| 1907 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1908 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1909 | div >>= 1; |
Suneel Garapati | d1955c3 | 2015-06-09 13:01:50 +0530 | [diff] [blame] | 1910 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
| 1911 | && !div && host->max_clk <= 25000000) |
| 1912 | div = 1; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1913 | } |
| 1914 | } else { |
| 1915 | /* Version 2.00 divisors must be a power of 2. */ |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 1916 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1917 | if ((host->max_clk / div) <= clock) |
| 1918 | break; |
| 1919 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1920 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1921 | div >>= 1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1922 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1923 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1924 | clock_set: |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1925 | if (real_div) |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1926 | *actual_clock = (host->max_clk * clk_mul) / real_div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1927 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1928 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 1929 | << SDHCI_DIVIDER_HI_SHIFT; |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1930 | |
| 1931 | return clk; |
| 1932 | } |
| 1933 | EXPORT_SYMBOL_GPL(sdhci_calc_clk); |
| 1934 | |
Ritesh Harjani | fec7967 | 2016-11-21 12:07:19 +0530 | [diff] [blame] | 1935 | void sdhci_enable_clk(struct sdhci_host *host, u16 clk) |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1936 | { |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 1937 | ktime_t timeout; |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1938 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1939 | clk |= SDHCI_CLOCK_INT_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1940 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1941 | |
Ben Chuang | 4a9e0d1 | 2019-08-27 08:32:42 +0800 | [diff] [blame] | 1942 | /* Wait max 150 ms */ |
| 1943 | timeout = ktime_add_ms(ktime_get(), 150); |
Alek Du | b704441 | 2018-12-06 17:24:59 +0800 | [diff] [blame] | 1944 | while (1) { |
| 1945 | bool timedout = ktime_after(ktime_get(), timeout); |
| 1946 | |
| 1947 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1948 | if (clk & SDHCI_CLOCK_INT_STABLE) |
| 1949 | break; |
| 1950 | if (timedout) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1951 | pr_err("%s: Internal clock never stabilised.\n", |
| 1952 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1953 | sdhci_dumpregs(host); |
| 1954 | return; |
| 1955 | } |
Adrian Hunter | 5a436cc | 2017-03-20 19:50:31 +0200 | [diff] [blame] | 1956 | udelay(10); |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1957 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1958 | |
Ben Chuang | 1beabbd | 2019-08-27 08:32:55 +0800 | [diff] [blame] | 1959 | if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { |
| 1960 | clk |= SDHCI_CLOCK_PLL_EN; |
| 1961 | clk &= ~SDHCI_CLOCK_INT_STABLE; |
| 1962 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1963 | |
| 1964 | /* Wait max 150 ms */ |
| 1965 | timeout = ktime_add_ms(ktime_get(), 150); |
| 1966 | while (1) { |
| 1967 | bool timedout = ktime_after(ktime_get(), timeout); |
| 1968 | |
| 1969 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1970 | if (clk & SDHCI_CLOCK_INT_STABLE) |
| 1971 | break; |
| 1972 | if (timedout) { |
| 1973 | pr_err("%s: PLL clock never stabilised.\n", |
| 1974 | mmc_hostname(host->mmc)); |
| 1975 | sdhci_dumpregs(host); |
| 1976 | return; |
| 1977 | } |
| 1978 | udelay(10); |
| 1979 | } |
| 1980 | } |
| 1981 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1982 | clk |= SDHCI_CLOCK_CARD_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1983 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1984 | } |
Ritesh Harjani | fec7967 | 2016-11-21 12:07:19 +0530 | [diff] [blame] | 1985 | EXPORT_SYMBOL_GPL(sdhci_enable_clk); |
| 1986 | |
| 1987 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| 1988 | { |
| 1989 | u16 clk; |
| 1990 | |
| 1991 | host->mmc->actual_clock = 0; |
| 1992 | |
| 1993 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
| 1994 | |
| 1995 | if (clock == 0) |
| 1996 | return; |
| 1997 | |
| 1998 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); |
| 1999 | sdhci_enable_clk(host, clk); |
| 2000 | } |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2001 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2002 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2003 | static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, |
| 2004 | unsigned short vdd) |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2005 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 2006 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2007 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2008 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2009 | |
| 2010 | if (mode != MMC_POWER_OFF) |
| 2011 | sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); |
| 2012 | else |
| 2013 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
| 2014 | } |
| 2015 | |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2016 | void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, |
| 2017 | unsigned short vdd) |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2018 | { |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 2019 | u8 pwr = 0; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2020 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 2021 | if (mode != MMC_POWER_OFF) { |
| 2022 | switch (1 << vdd) { |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 2023 | case MMC_VDD_165_195: |
Andy Shevchenko | 2a609ab | 2018-01-11 15:51:58 +0200 | [diff] [blame] | 2024 | /* |
| 2025 | * Without a regulator, SDHCI does not support 2.0v |
| 2026 | * so we only get here if the driver deliberately |
| 2027 | * added the 2.0v range to ocr_avail. Map it to 1.8v |
| 2028 | * for the purpose of turning on the power. |
| 2029 | */ |
| 2030 | case MMC_VDD_20_21: |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 2031 | pwr = SDHCI_POWER_180; |
| 2032 | break; |
| 2033 | case MMC_VDD_29_30: |
| 2034 | case MMC_VDD_30_31: |
| 2035 | pwr = SDHCI_POWER_300; |
| 2036 | break; |
| 2037 | case MMC_VDD_32_33: |
| 2038 | case MMC_VDD_33_34: |
| 2039 | pwr = SDHCI_POWER_330; |
| 2040 | break; |
| 2041 | default: |
Adrian Hunter | 9d5de93 | 2015-11-26 14:00:46 +0200 | [diff] [blame] | 2042 | WARN(1, "%s: Invalid vdd %#x\n", |
| 2043 | mmc_hostname(host->mmc), vdd); |
| 2044 | break; |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 2045 | } |
| 2046 | } |
| 2047 | |
| 2048 | if (host->pwr == pwr) |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2049 | return; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2050 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 2051 | host->pwr = pwr; |
| 2052 | |
| 2053 | if (pwr == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2054 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 2055 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 2056 | sdhci_runtime_pm_bus_off(host); |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2057 | } else { |
| 2058 | /* |
| 2059 | * Spec says that we should clear the power reg before setting |
| 2060 | * a new value. Some controllers don't seem to like this though. |
| 2061 | */ |
| 2062 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
| 2063 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Darren Salt | 9e9dc5f | 2007-01-27 15:32:31 +0100 | [diff] [blame] | 2064 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2065 | /* |
| 2066 | * At least the Marvell CaFe chip gets confused if we set the |
| 2067 | * voltage and set turn on power at the same time, so set the |
| 2068 | * voltage first. |
| 2069 | */ |
| 2070 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
| 2071 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2072 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2073 | pwr |= SDHCI_POWER_ON; |
| 2074 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 2075 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 2076 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2077 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 2078 | sdhci_runtime_pm_bus_on(host); |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 2079 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 2080 | /* |
| 2081 | * Some controllers need an extra 10ms delay of 10ms before |
| 2082 | * they can apply clock after applying power |
| 2083 | */ |
| 2084 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
| 2085 | mdelay(10); |
| 2086 | } |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2087 | } |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2088 | EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); |
Jisheng Zhang | 918f4cb | 2015-12-11 21:36:29 +0800 | [diff] [blame] | 2089 | |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2090 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 2091 | unsigned short vdd) |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2092 | { |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2093 | if (IS_ERR(host->mmc->supply.vmmc)) |
| 2094 | sdhci_set_power_noreg(host, mode, vdd); |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 2095 | else |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2096 | sdhci_set_power_reg(host, mode, vdd); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2097 | } |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2098 | EXPORT_SYMBOL_GPL(sdhci_set_power); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2099 | |
Nicolas Saenz Julienne | 6c92ae1 | 2020-03-06 18:44:03 +0100 | [diff] [blame] | 2100 | /* |
| 2101 | * Some controllers need to configure a valid bus voltage on their power |
| 2102 | * register regardless of whether an external regulator is taking care of power |
| 2103 | * supply. This helper function takes care of it if set as the controller's |
| 2104 | * sdhci_ops.set_power callback. |
| 2105 | */ |
| 2106 | void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, |
| 2107 | unsigned char mode, |
| 2108 | unsigned short vdd) |
| 2109 | { |
| 2110 | if (!IS_ERR(host->mmc->supply.vmmc)) { |
| 2111 | struct mmc_host *mmc = host->mmc; |
| 2112 | |
| 2113 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
| 2114 | } |
| 2115 | sdhci_set_power_noreg(host, mode, vdd); |
| 2116 | } |
| 2117 | EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage); |
| 2118 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2119 | /*****************************************************************************\ |
| 2120 | * * |
| 2121 | * MMC callbacks * |
| 2122 | * * |
| 2123 | \*****************************************************************************/ |
| 2124 | |
Aapo Vienamo | d462c1b | 2018-08-20 12:23:32 +0300 | [diff] [blame] | 2125 | void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2126 | { |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 2127 | struct sdhci_host *host = mmc_priv(mmc); |
| 2128 | struct mmc_command *cmd; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2129 | unsigned long flags; |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 2130 | bool present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2131 | |
Scott Branden | 04e079cf | 2015-03-10 11:35:10 -0700 | [diff] [blame] | 2132 | /* Firstly check card presence */ |
Adrian Hunter | 8d28b7a | 2016-02-09 16:12:36 +0200 | [diff] [blame] | 2133 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2134 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2135 | spin_lock_irqsave(&host->lock, flags); |
| 2136 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 2137 | sdhci_led_activate(host); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 2138 | |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 2139 | if (sdhci_present_error(host, mrq->cmd, present)) |
| 2140 | goto out_finish; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2141 | |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 2142 | cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd; |
| 2143 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 2144 | if (!sdhci_send_command_retry(host, cmd, flags)) |
| 2145 | goto out_finish; |
Adrian Hunter | e872f1e | 2020-04-12 12:03:48 +0300 | [diff] [blame] | 2146 | |
| 2147 | spin_unlock_irqrestore(&host->lock, flags); |
| 2148 | |
| 2149 | return; |
| 2150 | |
| 2151 | out_finish: |
| 2152 | sdhci_finish_mrq(host, mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2153 | spin_unlock_irqrestore(&host->lock, flags); |
| 2154 | } |
Aapo Vienamo | d462c1b | 2018-08-20 12:23:32 +0300 | [diff] [blame] | 2155 | EXPORT_SYMBOL_GPL(sdhci_request); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2156 | |
Baolin Wang | 48ef8a2 | 2020-04-13 10:46:04 +0800 | [diff] [blame] | 2157 | int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq) |
| 2158 | { |
| 2159 | struct sdhci_host *host = mmc_priv(mmc); |
| 2160 | struct mmc_command *cmd; |
| 2161 | unsigned long flags; |
| 2162 | int ret = 0; |
| 2163 | |
| 2164 | spin_lock_irqsave(&host->lock, flags); |
| 2165 | |
| 2166 | if (sdhci_present_error(host, mrq->cmd, true)) { |
| 2167 | sdhci_finish_mrq(host, mrq); |
| 2168 | goto out_finish; |
| 2169 | } |
| 2170 | |
| 2171 | cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd; |
| 2172 | |
| 2173 | /* |
| 2174 | * The HSQ may send a command in interrupt context without polling |
| 2175 | * the busy signaling, which means we should return BUSY if controller |
| 2176 | * has not released inhibit bits to allow HSQ trying to send request |
| 2177 | * again in non-atomic context. So we should not finish this request |
| 2178 | * here. |
| 2179 | */ |
| 2180 | if (!sdhci_send_command(host, cmd)) |
| 2181 | ret = -EBUSY; |
| 2182 | else |
| 2183 | sdhci_led_activate(host); |
| 2184 | |
| 2185 | out_finish: |
| 2186 | spin_unlock_irqrestore(&host->lock, flags); |
| 2187 | return ret; |
| 2188 | } |
| 2189 | EXPORT_SYMBOL_GPL(sdhci_request_atomic); |
| 2190 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 2191 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
| 2192 | { |
| 2193 | u8 ctrl; |
| 2194 | |
| 2195 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 2196 | if (width == MMC_BUS_WIDTH_8) { |
| 2197 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
Michał Mirosław | 98f94ea | 2017-08-14 22:00:24 +0200 | [diff] [blame] | 2198 | ctrl |= SDHCI_CTRL_8BITBUS; |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 2199 | } else { |
Michał Mirosław | 98f94ea | 2017-08-14 22:00:24 +0200 | [diff] [blame] | 2200 | if (host->mmc->caps & MMC_CAP_8_BIT_DATA) |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 2201 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 2202 | if (width == MMC_BUS_WIDTH_4) |
| 2203 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 2204 | else |
| 2205 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 2206 | } |
| 2207 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 2208 | } |
| 2209 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); |
| 2210 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 2211 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
| 2212 | { |
| 2213 | u16 ctrl_2; |
| 2214 | |
| 2215 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2216 | /* Select Bus Speed Mode for host */ |
| 2217 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 2218 | if ((timing == MMC_TIMING_MMC_HS200) || |
| 2219 | (timing == MMC_TIMING_UHS_SDR104)) |
| 2220 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2221 | else if (timing == MMC_TIMING_UHS_SDR12) |
| 2222 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
Faiz Abbas | 07bcc41 | 2019-11-28 16:34:22 +0530 | [diff] [blame] | 2223 | else if (timing == MMC_TIMING_UHS_SDR25) |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 2224 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 2225 | else if (timing == MMC_TIMING_UHS_SDR50) |
| 2226 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 2227 | else if ((timing == MMC_TIMING_UHS_DDR50) || |
| 2228 | (timing == MMC_TIMING_MMC_DDR52)) |
| 2229 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 2230 | else if (timing == MMC_TIMING_MMC_HS400) |
| 2231 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 2232 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 2233 | } |
| 2234 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); |
| 2235 | |
Hu Ziji | 6a6d4ce | 2017-03-30 17:22:55 +0200 | [diff] [blame] | 2236 | void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2237 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2238 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2239 | u8 ctrl; |
| 2240 | |
Adrian Hunter | 84ec048 | 2016-12-19 15:33:11 +0200 | [diff] [blame] | 2241 | if (ios->power_mode == MMC_POWER_UNDEFINED) |
| 2242 | return; |
| 2243 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 2244 | if (host->flags & SDHCI_DEVICE_DEAD) { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 2245 | if (!IS_ERR(mmc->supply.vmmc) && |
| 2246 | ios->power_mode == MMC_POWER_OFF) |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 2247 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 2248 | return; |
| 2249 | } |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2250 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2251 | /* |
| 2252 | * Reset the chip on each power off. |
| 2253 | * Should clear out any weird states. |
| 2254 | */ |
| 2255 | if (ios->power_mode == MMC_POWER_OFF) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2256 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2257 | sdhci_reinit(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2258 | } |
| 2259 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2260 | if (host->version >= SDHCI_SPEC_300 && |
Dong Aisheng | 372c463 | 2013-10-18 19:48:50 +0800 | [diff] [blame] | 2261 | (ios->power_mode == MMC_POWER_UP) && |
| 2262 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2263 | sdhci_enable_preset_value(host, false); |
| 2264 | |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 2265 | if (!ios->clock || ios->clock != host->clock) { |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2266 | host->ops->set_clock(host, ios->clock); |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 2267 | host->clock = ios->clock; |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 2268 | |
| 2269 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && |
| 2270 | host->clock) { |
| 2271 | host->timeout_clk = host->mmc->actual_clock ? |
| 2272 | host->mmc->actual_clock / 1000 : |
| 2273 | host->clock / 1000; |
| 2274 | host->mmc->max_busy_timeout = |
| 2275 | host->ops->get_max_timeout_count ? |
| 2276 | host->ops->get_max_timeout_count(host) : |
| 2277 | 1 << 27; |
| 2278 | host->mmc->max_busy_timeout /= host->timeout_clk; |
| 2279 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 2280 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2281 | |
Adrian Hunter | 606d313 | 2016-10-05 12:11:22 +0300 | [diff] [blame] | 2282 | if (host->ops->set_power) |
| 2283 | host->ops->set_power(host, ios->power_mode, ios->vdd); |
| 2284 | else |
| 2285 | sdhci_set_power(host, ios->power_mode, ios->vdd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2286 | |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 2287 | if (host->ops->platform_send_init_74_clocks) |
| 2288 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
| 2289 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 2290 | host->ops->set_bus_width(host, ios->bus_width); |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 2291 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2292 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 2293 | |
yangbo lu | 501639b | 2017-08-15 10:16:47 +0800 | [diff] [blame] | 2294 | if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) { |
| 2295 | if (ios->timing == MMC_TIMING_SD_HS || |
| 2296 | ios->timing == MMC_TIMING_MMC_HS || |
| 2297 | ios->timing == MMC_TIMING_MMC_HS400 || |
| 2298 | ios->timing == MMC_TIMING_MMC_HS200 || |
| 2299 | ios->timing == MMC_TIMING_MMC_DDR52 || |
| 2300 | ios->timing == MMC_TIMING_UHS_SDR50 || |
| 2301 | ios->timing == MMC_TIMING_UHS_SDR104 || |
| 2302 | ios->timing == MMC_TIMING_UHS_DDR50 || |
| 2303 | ios->timing == MMC_TIMING_UHS_SDR25) |
| 2304 | ctrl |= SDHCI_CTRL_HISPD; |
| 2305 | else |
| 2306 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 2307 | } |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 2308 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2309 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2310 | u16 clk, ctrl_2; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2311 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2312 | if (!host->preset_enabled) { |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 2313 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2314 | /* |
| 2315 | * We only need to set Driver Strength if the |
| 2316 | * preset value enable is not set. |
| 2317 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2318 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2319 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
| 2320 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
| 2321 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 2322 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
| 2323 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2324 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
| 2325 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 2326 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
| 2327 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; |
| 2328 | else { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2329 | pr_warn("%s: invalid driver type, default to driver type B\n", |
| 2330 | mmc_hostname(mmc)); |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 2331 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
| 2332 | } |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2333 | |
| 2334 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 2335 | } else { |
| 2336 | /* |
| 2337 | * According to SDHC Spec v3.00, if the Preset Value |
| 2338 | * Enable in the Host Control 2 register is set, we |
| 2339 | * need to reset SD Clock Enable before changing High |
| 2340 | * Speed Enable to avoid generating clock gliches. |
| 2341 | */ |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 2342 | |
| 2343 | /* Reset SD Clock Enable */ |
| 2344 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 2345 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 2346 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 2347 | |
| 2348 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 2349 | |
| 2350 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2351 | host->ops->set_clock(host, host->clock); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2352 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2353 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2354 | /* Reset SD Clock Enable */ |
| 2355 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 2356 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 2357 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 2358 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 2359 | host->ops->set_uhs_signaling(host, ios->timing); |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 2360 | host->timing = ios->timing; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2361 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2362 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
| 2363 | ((ios->timing == MMC_TIMING_UHS_SDR12) || |
| 2364 | (ios->timing == MMC_TIMING_UHS_SDR25) || |
| 2365 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
| 2366 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 2367 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
| 2368 | (ios->timing == MMC_TIMING_MMC_DDR52))) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2369 | u16 preset; |
| 2370 | |
| 2371 | sdhci_enable_preset_value(host, true); |
| 2372 | preset = sdhci_get_preset_value(host); |
Masahiro Yamada | fa09101 | 2020-03-12 20:00:50 +0900 | [diff] [blame] | 2373 | ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK, |
| 2374 | preset); |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2375 | } |
| 2376 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 2377 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2378 | host->ops->set_clock(host, host->clock); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 2379 | } else |
| 2380 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2381 | |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 2382 | /* |
| 2383 | * Some (ENE) controllers go apeshit on some ios operation, |
| 2384 | * signalling timeout and CRC errors even on CMD0. Resetting |
| 2385 | * it on each ios seems to solve the problem. |
| 2386 | */ |
Mohammad Jamal | c63705e | 2015-01-13 20:47:24 +0530 | [diff] [blame] | 2387 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2388 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2389 | } |
Hu Ziji | 6a6d4ce | 2017-03-30 17:22:55 +0200 | [diff] [blame] | 2390 | EXPORT_SYMBOL_GPL(sdhci_set_ios); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2391 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2392 | static int sdhci_get_cd(struct mmc_host *mmc) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2393 | { |
| 2394 | struct sdhci_host *host = mmc_priv(mmc); |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2395 | int gpio_cd = mmc_gpio_get_cd(mmc); |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2396 | |
| 2397 | if (host->flags & SDHCI_DEVICE_DEAD) |
| 2398 | return 0; |
| 2399 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 2400 | /* If nonremovable, assume that the card is always present. */ |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 2401 | if (!mmc_card_is_removable(host->mmc)) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2402 | return 1; |
| 2403 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 2404 | /* |
| 2405 | * Try slot gpio detect, if defined it take precedence |
| 2406 | * over build in controller functionality |
| 2407 | */ |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 2408 | if (gpio_cd >= 0) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2409 | return !!gpio_cd; |
| 2410 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 2411 | /* If polling, assume that the card is always present. */ |
| 2412 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 2413 | return 1; |
| 2414 | |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2415 | /* Host native card detect */ |
| 2416 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); |
| 2417 | } |
| 2418 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2419 | static int sdhci_check_ro(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2420 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2421 | unsigned long flags; |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 2422 | int is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2423 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2424 | spin_lock_irqsave(&host->lock, flags); |
| 2425 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2426 | if (host->flags & SDHCI_DEVICE_DEAD) |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 2427 | is_readonly = 0; |
| 2428 | else if (host->ops->get_ro) |
| 2429 | is_readonly = host->ops->get_ro(host); |
Thomas Petazzoni | 6d5cd06 | 2019-02-12 15:07:35 +0100 | [diff] [blame] | 2430 | else if (mmc_can_gpio_ro(host->mmc)) |
| 2431 | is_readonly = mmc_gpio_get_ro(host->mmc); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2432 | else |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 2433 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
| 2434 | & SDHCI_WRITE_PROTECT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2435 | |
| 2436 | spin_unlock_irqrestore(&host->lock, flags); |
| 2437 | |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 2438 | /* This quirk needs to be replaced by a callback-function later */ |
| 2439 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? |
| 2440 | !is_readonly : is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2441 | } |
| 2442 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2443 | #define SAMPLE_COUNT 5 |
| 2444 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2445 | static int sdhci_get_ro(struct mmc_host *mmc) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2446 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2447 | struct sdhci_host *host = mmc_priv(mmc); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2448 | int i, ro_count; |
| 2449 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2450 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2451 | return sdhci_check_ro(host); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2452 | |
| 2453 | ro_count = 0; |
| 2454 | for (i = 0; i < SAMPLE_COUNT; i++) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2455 | if (sdhci_check_ro(host)) { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 2456 | if (++ro_count > SAMPLE_COUNT / 2) |
| 2457 | return 1; |
| 2458 | } |
| 2459 | msleep(30); |
| 2460 | } |
| 2461 | return 0; |
| 2462 | } |
| 2463 | |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 2464 | static void sdhci_hw_reset(struct mmc_host *mmc) |
| 2465 | { |
| 2466 | struct sdhci_host *host = mmc_priv(mmc); |
| 2467 | |
| 2468 | if (host->ops && host->ops->hw_reset) |
| 2469 | host->ops->hw_reset(host); |
| 2470 | } |
| 2471 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2472 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
| 2473 | { |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 2474 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2475 | if (enable) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2476 | host->ier |= SDHCI_INT_CARD_INT; |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2477 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2478 | host->ier &= ~SDHCI_INT_CARD_INT; |
| 2479 | |
| 2480 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2481 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2482 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2483 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2484 | |
Hu Ziji | 2f05b6ab | 2017-03-30 17:22:57 +0200 | [diff] [blame] | 2485 | void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2486 | { |
| 2487 | struct sdhci_host *host = mmc_priv(mmc); |
| 2488 | unsigned long flags; |
| 2489 | |
Hans de Goede | 923713b | 2017-03-26 13:14:45 +0200 | [diff] [blame] | 2490 | if (enable) |
| 2491 | pm_runtime_get_noresume(host->mmc->parent); |
| 2492 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2493 | spin_lock_irqsave(&host->lock, flags); |
| 2494 | sdhci_enable_sdio_irq_nolock(host, enable); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2495 | spin_unlock_irqrestore(&host->lock, flags); |
Hans de Goede | 923713b | 2017-03-26 13:14:45 +0200 | [diff] [blame] | 2496 | |
| 2497 | if (!enable) |
| 2498 | pm_runtime_put_noidle(host->mmc->parent); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2499 | } |
Hu Ziji | 2f05b6ab | 2017-03-30 17:22:57 +0200 | [diff] [blame] | 2500 | EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2501 | |
Adrian Hunter | 89f3c36 | 2019-05-27 14:45:55 +0300 | [diff] [blame] | 2502 | static void sdhci_ack_sdio_irq(struct mmc_host *mmc) |
| 2503 | { |
| 2504 | struct sdhci_host *host = mmc_priv(mmc); |
| 2505 | unsigned long flags; |
| 2506 | |
| 2507 | spin_lock_irqsave(&host->lock, flags); |
Ulf Hansson | a84ad32 | 2019-09-08 12:12:34 +0200 | [diff] [blame] | 2508 | sdhci_enable_sdio_irq_nolock(host, true); |
Adrian Hunter | 89f3c36 | 2019-05-27 14:45:55 +0300 | [diff] [blame] | 2509 | spin_unlock_irqrestore(&host->lock, flags); |
| 2510 | } |
| 2511 | |
Hu Ziji | c376ea9 | 2017-03-30 17:22:56 +0200 | [diff] [blame] | 2512 | int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
| 2513 | struct mmc_ios *ios) |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 2514 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 2515 | struct sdhci_host *host = mmc_priv(mmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 2516 | u16 ctrl; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2517 | int ret; |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 2518 | |
| 2519 | /* |
| 2520 | * Signal Voltage Switching is only applicable for Host Controllers |
| 2521 | * v3.00 and above. |
| 2522 | */ |
| 2523 | if (host->version < SDHCI_SPEC_300) |
| 2524 | return 0; |
| 2525 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 2526 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2527 | |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 2528 | switch (ios->signal_voltage) { |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2529 | case MMC_SIGNAL_VOLTAGE_330: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 2530 | if (!(host->flags & SDHCI_SIGNALING_330)) |
| 2531 | return -EINVAL; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2532 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ |
| 2533 | ctrl &= ~SDHCI_CTRL_VDD_180; |
| 2534 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2535 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 2536 | if (!IS_ERR(mmc->supply.vqmmc)) { |
Dong Aisheng | 761daa3 | 2016-07-12 15:46:10 +0800 | [diff] [blame] | 2537 | ret = mmc_regulator_set_vqmmc(mmc, ios); |
Marek Vasut | 9cbe0fc | 2020-04-16 18:36:47 +0200 | [diff] [blame] | 2538 | if (ret < 0) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2539 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
| 2540 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2541 | return -EIO; |
| 2542 | } |
| 2543 | } |
| 2544 | /* Wait for 5ms */ |
| 2545 | usleep_range(5000, 5500); |
| 2546 | |
| 2547 | /* 3.3V regulator output should be stable within 5 ms */ |
| 2548 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2549 | if (!(ctrl & SDHCI_CTRL_VDD_180)) |
| 2550 | return 0; |
| 2551 | |
Fabio Estevam | b0b19ce | 2019-11-19 12:55:03 -0300 | [diff] [blame] | 2552 | pr_warn("%s: 3.3V regulator output did not become stable\n", |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2553 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2554 | |
| 2555 | return -EAGAIN; |
| 2556 | case MMC_SIGNAL_VOLTAGE_180: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 2557 | if (!(host->flags & SDHCI_SIGNALING_180)) |
| 2558 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 2559 | if (!IS_ERR(mmc->supply.vqmmc)) { |
Dong Aisheng | 761daa3 | 2016-07-12 15:46:10 +0800 | [diff] [blame] | 2560 | ret = mmc_regulator_set_vqmmc(mmc, ios); |
Marek Vasut | 9cbe0fc | 2020-04-16 18:36:47 +0200 | [diff] [blame] | 2561 | if (ret < 0) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2562 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
| 2563 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2564 | return -EIO; |
| 2565 | } |
| 2566 | } |
| 2567 | |
| 2568 | /* |
| 2569 | * Enable 1.8V Signal Enable in the Host Control2 |
| 2570 | * register |
| 2571 | */ |
| 2572 | ctrl |= SDHCI_CTRL_VDD_180; |
| 2573 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2574 | |
Vincent Yang | 9d967a6 | 2015-01-20 16:05:15 +0800 | [diff] [blame] | 2575 | /* Some controller need to do more when switching */ |
| 2576 | if (host->ops->voltage_switch) |
| 2577 | host->ops->voltage_switch(host); |
| 2578 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2579 | /* 1.8V regulator output should be stable within 5 ms */ |
| 2580 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2581 | if (ctrl & SDHCI_CTRL_VDD_180) |
| 2582 | return 0; |
| 2583 | |
Fabio Estevam | b0b19ce | 2019-11-19 12:55:03 -0300 | [diff] [blame] | 2584 | pr_warn("%s: 1.8V regulator output did not become stable\n", |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2585 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2586 | |
| 2587 | return -EAGAIN; |
| 2588 | case MMC_SIGNAL_VOLTAGE_120: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 2589 | if (!(host->flags & SDHCI_SIGNALING_120)) |
| 2590 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 2591 | if (!IS_ERR(mmc->supply.vqmmc)) { |
Dong Aisheng | 761daa3 | 2016-07-12 15:46:10 +0800 | [diff] [blame] | 2592 | ret = mmc_regulator_set_vqmmc(mmc, ios); |
Marek Vasut | 9cbe0fc | 2020-04-16 18:36:47 +0200 | [diff] [blame] | 2593 | if (ret < 0) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2594 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
| 2595 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2596 | return -EIO; |
| 2597 | } |
| 2598 | } |
| 2599 | return 0; |
| 2600 | default: |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2601 | /* No signal voltage switch required */ |
| 2602 | return 0; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2603 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2604 | } |
Hu Ziji | c376ea9 | 2017-03-30 17:22:56 +0200 | [diff] [blame] | 2605 | EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch); |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2606 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2607 | static int sdhci_card_busy(struct mmc_host *mmc) |
| 2608 | { |
| 2609 | struct sdhci_host *host = mmc_priv(mmc); |
| 2610 | u32 present_state; |
| 2611 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 2612 | /* Check whether DAT[0] is 0 */ |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2613 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2614 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 2615 | return !(present_state & SDHCI_DATA_0_LVL_MASK); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2616 | } |
| 2617 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2618 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
| 2619 | { |
| 2620 | struct sdhci_host *host = mmc_priv(mmc); |
| 2621 | unsigned long flags; |
| 2622 | |
| 2623 | spin_lock_irqsave(&host->lock, flags); |
| 2624 | host->flags |= SDHCI_HS400_TUNING; |
| 2625 | spin_unlock_irqrestore(&host->lock, flags); |
| 2626 | |
| 2627 | return 0; |
| 2628 | } |
| 2629 | |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2630 | void sdhci_start_tuning(struct sdhci_host *host) |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2631 | { |
| 2632 | u16 ctrl; |
| 2633 | |
| 2634 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2635 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
| 2636 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
| 2637 | ctrl |= SDHCI_CTRL_TUNED_CLK; |
| 2638 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2639 | |
| 2640 | /* |
| 2641 | * As per the Host Controller spec v3.00, tuning command |
| 2642 | * generates Buffer Read Ready interrupt, so enable that. |
| 2643 | * |
| 2644 | * Note: The spec clearly says that when tuning sequence |
| 2645 | * is being performed, the controller does not generate |
| 2646 | * interrupts other than Buffer Read Ready interrupt. But |
| 2647 | * to make sure we don't hit a controller bug, we _only_ |
| 2648 | * enable Buffer Read Ready interrupt here. |
| 2649 | */ |
| 2650 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
| 2651 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
| 2652 | } |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2653 | EXPORT_SYMBOL_GPL(sdhci_start_tuning); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2654 | |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2655 | void sdhci_end_tuning(struct sdhci_host *host) |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2656 | { |
| 2657 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2658 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
| 2659 | } |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2660 | EXPORT_SYMBOL_GPL(sdhci_end_tuning); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2661 | |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2662 | void sdhci_reset_tuning(struct sdhci_host *host) |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2663 | { |
| 2664 | u16 ctrl; |
| 2665 | |
| 2666 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2667 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2668 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 2669 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2670 | } |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2671 | EXPORT_SYMBOL_GPL(sdhci_reset_tuning); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2672 | |
Ben Chuang | 7353788 | 2019-08-27 08:33:22 +0800 | [diff] [blame] | 2673 | void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2674 | { |
| 2675 | sdhci_reset_tuning(host); |
| 2676 | |
| 2677 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2678 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
| 2679 | |
| 2680 | sdhci_end_tuning(host); |
| 2681 | |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2682 | mmc_abort_tuning(host->mmc, opcode); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2683 | } |
Ben Chuang | 7353788 | 2019-08-27 08:33:22 +0800 | [diff] [blame] | 2684 | EXPORT_SYMBOL_GPL(sdhci_abort_tuning); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2685 | |
| 2686 | /* |
| 2687 | * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI |
| 2688 | * tuning command does not have a data payload (or rather the hardware does it |
| 2689 | * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command |
| 2690 | * interrupt setup is different to other commands and there is no timeout |
| 2691 | * interrupt so special handling is needed. |
| 2692 | */ |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2693 | void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2694 | { |
| 2695 | struct mmc_host *mmc = host->mmc; |
Masahiro Yamada | c7836d1 | 2016-12-19 20:51:18 +0900 | [diff] [blame] | 2696 | struct mmc_command cmd = {}; |
| 2697 | struct mmc_request mrq = {}; |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2698 | unsigned long flags; |
Srinivas Kandagatla | c846a00 | 2017-08-03 14:46:13 +0200 | [diff] [blame] | 2699 | u32 b = host->sdma_boundary; |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2700 | |
| 2701 | spin_lock_irqsave(&host->lock, flags); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2702 | |
| 2703 | cmd.opcode = opcode; |
| 2704 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 2705 | cmd.mrq = &mrq; |
| 2706 | |
| 2707 | mrq.cmd = &cmd; |
| 2708 | /* |
| 2709 | * In response to CMD19, the card sends 64 bytes of tuning |
| 2710 | * block to the Host Controller. So we set the block size |
| 2711 | * to 64 here. |
| 2712 | */ |
Adrian Hunter | 8533610 | 2016-12-02 15:14:26 +0200 | [diff] [blame] | 2713 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && |
| 2714 | mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
Srinivas Kandagatla | c846a00 | 2017-08-03 14:46:13 +0200 | [diff] [blame] | 2715 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE); |
Adrian Hunter | 8533610 | 2016-12-02 15:14:26 +0200 | [diff] [blame] | 2716 | else |
Srinivas Kandagatla | c846a00 | 2017-08-03 14:46:13 +0200 | [diff] [blame] | 2717 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2718 | |
| 2719 | /* |
| 2720 | * The tuning block is sent by the card to the host controller. |
| 2721 | * So we set the TRNS_READ bit in the Transfer Mode register. |
| 2722 | * This also takes care of setting DMA Enable and Multi Block |
| 2723 | * Select in the same register to 0. |
| 2724 | */ |
| 2725 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 2726 | |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 2727 | if (!sdhci_send_command_retry(host, &cmd, flags)) { |
| 2728 | spin_unlock_irqrestore(&host->lock, flags); |
| 2729 | host->tuning_done = 0; |
| 2730 | return; |
| 2731 | } |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2732 | |
| 2733 | host->cmd = NULL; |
| 2734 | |
| 2735 | sdhci_del_timer(host, &mrq); |
| 2736 | |
| 2737 | host->tuning_done = 0; |
| 2738 | |
| 2739 | spin_unlock_irqrestore(&host->lock, flags); |
| 2740 | |
| 2741 | /* Wait for Buffer Read Ready interrupt */ |
| 2742 | wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), |
| 2743 | msecs_to_jiffies(50)); |
| 2744 | |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2745 | } |
ernest.zhang | 6663c41 | 2018-07-16 14:26:53 +0800 | [diff] [blame] | 2746 | EXPORT_SYMBOL_GPL(sdhci_send_tuning); |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2747 | |
Yinbo Zhu | 7d8bb1f | 2018-08-23 16:48:31 +0800 | [diff] [blame] | 2748 | static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2749 | { |
| 2750 | int i; |
| 2751 | |
| 2752 | /* |
| 2753 | * Issue opcode repeatedly till Execute Tuning is set to 0 or the number |
Sowjanya Komatineni | 1d8cd065 | 2019-03-23 21:45:19 -0700 | [diff] [blame] | 2754 | * of loops reaches tuning loop count. |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2755 | */ |
Sowjanya Komatineni | 1d8cd065 | 2019-03-23 21:45:19 -0700 | [diff] [blame] | 2756 | for (i = 0; i < host->tuning_loop_count; i++) { |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2757 | u16 ctrl; |
| 2758 | |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2759 | sdhci_send_tuning(host, opcode); |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2760 | |
| 2761 | if (!host->tuning_done) { |
Faiz Abbas | 811ba67 | 2019-12-06 17:13:26 +0530 | [diff] [blame] | 2762 | pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n", |
| 2763 | mmc_hostname(host->mmc)); |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2764 | sdhci_abort_tuning(host, opcode); |
Yinbo Zhu | 7d8bb1f | 2018-08-23 16:48:31 +0800 | [diff] [blame] | 2765 | return -ETIMEDOUT; |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2766 | } |
| 2767 | |
BOUGH CHEN | 2b06e15 | 2018-12-28 08:35:49 +0000 | [diff] [blame] | 2768 | /* Spec does not require a delay between tuning cycles */ |
| 2769 | if (host->tuning_delay > 0) |
| 2770 | mdelay(host->tuning_delay); |
| 2771 | |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2772 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2773 | if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { |
| 2774 | if (ctrl & SDHCI_CTRL_TUNED_CLK) |
Yinbo Zhu | 7d8bb1f | 2018-08-23 16:48:31 +0800 | [diff] [blame] | 2775 | return 0; /* Success! */ |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2776 | break; |
| 2777 | } |
| 2778 | |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2779 | } |
| 2780 | |
| 2781 | pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", |
| 2782 | mmc_hostname(host->mmc)); |
| 2783 | sdhci_reset_tuning(host); |
Yinbo Zhu | 7d8bb1f | 2018-08-23 16:48:31 +0800 | [diff] [blame] | 2784 | return -EAGAIN; |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2785 | } |
| 2786 | |
Masahiro Yamada | 85a882c | 2016-12-08 21:50:54 +0900 | [diff] [blame] | 2787 | int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2788 | { |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2789 | struct sdhci_host *host = mmc_priv(mmc); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2790 | int err = 0; |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 2791 | unsigned int tuning_count = 0; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2792 | bool hs400_tuning; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2793 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2794 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2795 | |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 2796 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 2797 | tuning_count = host->tuning_count; |
| 2798 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2799 | /* |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 2800 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
| 2801 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in |
| 2802 | * the Capabilities register. |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2803 | * If the Host Controller supports the HS200 mode then the |
| 2804 | * tuning function has to be executed. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2805 | */ |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2806 | switch (host->timing) { |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2807 | /* HS400 tuning is done in HS200 mode */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 2808 | case MMC_TIMING_MMC_HS400: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2809 | err = -EINVAL; |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2810 | goto out; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2811 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2812 | case MMC_TIMING_MMC_HS200: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2813 | /* |
| 2814 | * Periodic re-tuning for HS400 is not expected to be needed, so |
| 2815 | * disable it here. |
| 2816 | */ |
| 2817 | if (hs400_tuning) |
| 2818 | tuning_count = 0; |
| 2819 | break; |
| 2820 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2821 | case MMC_TIMING_UHS_SDR104: |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 2822 | case MMC_TIMING_UHS_DDR50: |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2823 | break; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2824 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2825 | case MMC_TIMING_UHS_SDR50: |
Adrian Hunter | 4228b21 | 2016-04-20 09:24:03 +0300 | [diff] [blame] | 2826 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING) |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2827 | break; |
Gustavo A. R. Silva | df561f66 | 2020-08-23 17:36:59 -0500 | [diff] [blame] | 2828 | fallthrough; |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 2829 | |
| 2830 | default: |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2831 | goto out; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2832 | } |
| 2833 | |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 2834 | if (host->ops->platform_execute_tuning) { |
Ritesh Harjani | 8a8fa87 | 2017-01-10 12:30:50 +0530 | [diff] [blame] | 2835 | err = host->ops->platform_execute_tuning(host, opcode); |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2836 | goto out; |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 2837 | } |
| 2838 | |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2839 | host->mmc->retune_period = tuning_count; |
| 2840 | |
Adrian Hunter | 83b600b | 2017-04-20 16:14:43 +0800 | [diff] [blame] | 2841 | if (host->tuning_delay < 0) |
| 2842 | host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK; |
| 2843 | |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2844 | sdhci_start_tuning(host); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2845 | |
Yinbo Zhu | 7d8bb1f | 2018-08-23 16:48:31 +0800 | [diff] [blame] | 2846 | host->tuning_err = __sdhci_execute_tuning(host, opcode); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2847 | |
Adrian Hunter | da4bc4f | 2016-12-02 15:59:23 +0200 | [diff] [blame] | 2848 | sdhci_end_tuning(host); |
Adrian Hunter | 2a85ef2 | 2017-03-20 19:50:38 +0200 | [diff] [blame] | 2849 | out: |
Ritesh Harjani | 8a8fa87 | 2017-01-10 12:30:50 +0530 | [diff] [blame] | 2850 | host->flags &= ~SDHCI_HS400_TUNING; |
Adrian Hunter | 6b11e70 | 2016-12-02 15:14:27 +0200 | [diff] [blame] | 2851 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2852 | return err; |
| 2853 | } |
Masahiro Yamada | 85a882c | 2016-12-08 21:50:54 +0900 | [diff] [blame] | 2854 | EXPORT_SYMBOL_GPL(sdhci_execute_tuning); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2855 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2856 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2857 | { |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2858 | /* Host Controller v3.00 defines preset value registers */ |
| 2859 | if (host->version < SDHCI_SPEC_300) |
| 2860 | return; |
| 2861 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2862 | /* |
| 2863 | * We only enable or disable Preset Value if they are not already |
| 2864 | * enabled or disabled respectively. Otherwise, we bail out. |
| 2865 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2866 | if (host->preset_enabled != enable) { |
| 2867 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2868 | |
| 2869 | if (enable) |
| 2870 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2871 | else |
| 2872 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2873 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2874 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2875 | |
| 2876 | if (enable) |
| 2877 | host->flags |= SDHCI_PV_ENABLED; |
| 2878 | else |
| 2879 | host->flags &= ~SDHCI_PV_ENABLED; |
| 2880 | |
| 2881 | host->preset_enabled = enable; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2882 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2883 | } |
| 2884 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2885 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2886 | int err) |
| 2887 | { |
| 2888 | struct sdhci_host *host = mmc_priv(mmc); |
| 2889 | struct mmc_data *data = mrq->data; |
| 2890 | |
Russell King | f48f039 | 2016-01-26 13:40:32 +0000 | [diff] [blame] | 2891 | if (data->host_cookie != COOKIE_UNMAPPED) |
Russell King | 771a3dc | 2016-01-26 13:40:53 +0000 | [diff] [blame] | 2892 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 2893 | mmc_get_dma_dir(data)); |
Russell King | 771a3dc | 2016-01-26 13:40:53 +0000 | [diff] [blame] | 2894 | |
| 2895 | data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2896 | } |
| 2897 | |
Linus Walleij | d3c6aac | 2016-11-23 11:02:24 +0100 | [diff] [blame] | 2898 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2899 | { |
| 2900 | struct sdhci_host *host = mmc_priv(mmc); |
| 2901 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2902 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2903 | |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 2904 | /* |
| 2905 | * No pre-mapping in the pre hook if we're using the bounce buffer, |
| 2906 | * for that we would need two bounce buffers since one buffer is |
| 2907 | * in flight when this is getting called. |
| 2908 | */ |
| 2909 | if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer) |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 2910 | sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2911 | } |
| 2912 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2913 | static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) |
| 2914 | { |
| 2915 | if (host->data_cmd) { |
| 2916 | host->data_cmd->error = err; |
| 2917 | sdhci_finish_mrq(host, host->data_cmd->mrq); |
| 2918 | } |
| 2919 | |
| 2920 | if (host->cmd) { |
| 2921 | host->cmd->error = err; |
| 2922 | sdhci_finish_mrq(host, host->cmd->mrq); |
| 2923 | } |
| 2924 | } |
| 2925 | |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2926 | static void sdhci_card_event(struct mmc_host *mmc) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2927 | { |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2928 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2929 | unsigned long flags; |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2930 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2931 | |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 2932 | /* First check if client has provided their own card event */ |
| 2933 | if (host->ops->card_event) |
| 2934 | host->ops->card_event(host); |
| 2935 | |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2936 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2937 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2938 | spin_lock_irqsave(&host->lock, flags); |
| 2939 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2940 | /* Check sdhci_has_requests() first in case we are runtime suspended */ |
| 2941 | if (sdhci_has_requests(host) && !present) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2942 | pr_err("%s: Card removed during transfer!\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2943 | mmc_hostname(host->mmc)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2944 | pr_err("%s: Resetting controller.\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2945 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2946 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2947 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2948 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2949 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2950 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2951 | } |
| 2952 | |
| 2953 | spin_unlock_irqrestore(&host->lock, flags); |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2954 | } |
| 2955 | |
| 2956 | static const struct mmc_host_ops sdhci_ops = { |
| 2957 | .request = sdhci_request, |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2958 | .post_req = sdhci_post_req, |
| 2959 | .pre_req = sdhci_pre_req, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2960 | .set_ios = sdhci_set_ios, |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2961 | .get_cd = sdhci_get_cd, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2962 | .get_ro = sdhci_get_ro, |
| 2963 | .hw_reset = sdhci_hw_reset, |
| 2964 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
Adrian Hunter | 89f3c36 | 2019-05-27 14:45:55 +0300 | [diff] [blame] | 2965 | .ack_sdio_irq = sdhci_ack_sdio_irq, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2966 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2967 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2968 | .execute_tuning = sdhci_execute_tuning, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2969 | .card_event = sdhci_card_event, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2970 | .card_busy = sdhci_card_busy, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2971 | }; |
| 2972 | |
| 2973 | /*****************************************************************************\ |
| 2974 | * * |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 2975 | * Request done * |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2976 | * * |
| 2977 | \*****************************************************************************/ |
| 2978 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2979 | static bool sdhci_request_done(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2980 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2981 | unsigned long flags; |
| 2982 | struct mmc_request *mrq; |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2983 | int i; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2984 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2985 | spin_lock_irqsave(&host->lock, flags); |
| 2986 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2987 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 2988 | mrq = host->mrqs_done[i]; |
Adrian Hunter | 6ebebea | 2016-11-02 15:49:08 +0200 | [diff] [blame] | 2989 | if (mrq) |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2990 | break; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2991 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2992 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2993 | if (!mrq) { |
| 2994 | spin_unlock_irqrestore(&host->lock, flags); |
| 2995 | return true; |
| 2996 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2997 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2998 | /* |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 2999 | * Always unmap the data buffers if they were mapped by |
| 3000 | * sdhci_prepare_data() whenever we finish with a request. |
| 3001 | * This avoids leaking DMA mappings on error. |
| 3002 | */ |
| 3003 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 3004 | struct mmc_data *data = mrq->data; |
| 3005 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 3006 | if (host->use_external_dma && data && |
| 3007 | (mrq->cmd->error || data->error)) { |
| 3008 | struct dma_chan *chan = sdhci_external_dma_channel(host, data); |
| 3009 | |
| 3010 | host->mrqs_done[i] = NULL; |
| 3011 | spin_unlock_irqrestore(&host->lock, flags); |
| 3012 | dmaengine_terminate_sync(chan); |
| 3013 | spin_lock_irqsave(&host->lock, flags); |
| 3014 | sdhci_set_mrq_done(host, mrq); |
| 3015 | } |
| 3016 | |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 3017 | if (data && data->host_cookie == COOKIE_MAPPED) { |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 3018 | if (host->bounce_buffer) { |
| 3019 | /* |
| 3020 | * On reads, copy the bounced data into the |
| 3021 | * sglist |
| 3022 | */ |
| 3023 | if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { |
| 3024 | unsigned int length = data->bytes_xfered; |
| 3025 | |
| 3026 | if (length > host->bounce_buffer_size) { |
| 3027 | pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", |
| 3028 | mmc_hostname(host->mmc), |
| 3029 | host->bounce_buffer_size, |
| 3030 | data->bytes_xfered); |
| 3031 | /* Cap it down and continue */ |
| 3032 | length = host->bounce_buffer_size; |
| 3033 | } |
| 3034 | dma_sync_single_for_cpu( |
| 3035 | host->mmc->parent, |
| 3036 | host->bounce_addr, |
| 3037 | host->bounce_buffer_size, |
| 3038 | DMA_FROM_DEVICE); |
| 3039 | sg_copy_from_buffer(data->sg, |
| 3040 | data->sg_len, |
| 3041 | host->bounce_buffer, |
| 3042 | length); |
| 3043 | } else { |
| 3044 | /* No copying, just switch ownership */ |
| 3045 | dma_sync_single_for_cpu( |
| 3046 | host->mmc->parent, |
| 3047 | host->bounce_addr, |
| 3048 | host->bounce_buffer_size, |
| 3049 | mmc_get_dma_dir(data)); |
| 3050 | } |
| 3051 | } else { |
| 3052 | /* Unmap the raw data */ |
| 3053 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 3054 | data->sg_len, |
| 3055 | mmc_get_dma_dir(data)); |
| 3056 | } |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 3057 | data->host_cookie = COOKIE_UNMAPPED; |
| 3058 | } |
| 3059 | } |
| 3060 | |
| 3061 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3062 | * The controller needs a reset of internal state machines |
| 3063 | * upon error conditions. |
| 3064 | */ |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 3065 | if (sdhci_needs_reset(host, mrq)) { |
Adrian Hunter | 6ebebea | 2016-11-02 15:49:08 +0200 | [diff] [blame] | 3066 | /* |
| 3067 | * Do not finish until command and data lines are available for |
| 3068 | * reset. Note there can only be one other mrq, so it cannot |
| 3069 | * also be in mrqs_done, otherwise host->cmd and host->data_cmd |
| 3070 | * would both be null. |
| 3071 | */ |
| 3072 | if (host->cmd || host->data_cmd) { |
| 3073 | spin_unlock_irqrestore(&host->lock, flags); |
| 3074 | return true; |
| 3075 | } |
| 3076 | |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 3077 | /* Some controllers need this kick or reset won't work here */ |
Andy Shevchenko | 8213af3 | 2013-01-07 16:31:08 +0200 | [diff] [blame] | 3078 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 3079 | /* This is to force an update */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 3080 | host->ops->set_clock(host, host->clock); |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 3081 | |
| 3082 | /* Spec says we should do both at the same time, but Ricoh |
| 3083 | controllers do not like that. */ |
Adrian Hunter | 6ebebea | 2016-11-02 15:49:08 +0200 | [diff] [blame] | 3084 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 3085 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 3086 | |
| 3087 | host->pending_reset = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3088 | } |
| 3089 | |
Adrian Hunter | 6ebebea | 2016-11-02 15:49:08 +0200 | [diff] [blame] | 3090 | host->mrqs_done[i] = NULL; |
| 3091 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3092 | spin_unlock_irqrestore(&host->lock, flags); |
| 3093 | |
Baolin Wang | 1774b00 | 2020-02-12 12:12:58 +0800 | [diff] [blame] | 3094 | if (host->ops->request_done) |
| 3095 | host->ops->request_done(host, mrq); |
| 3096 | else |
| 3097 | mmc_request_done(host->mmc, mrq); |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 3098 | |
| 3099 | return false; |
| 3100 | } |
| 3101 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3102 | static void sdhci_complete_work(struct work_struct *work) |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 3103 | { |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3104 | struct sdhci_host *host = container_of(work, struct sdhci_host, |
| 3105 | complete_work); |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 3106 | |
| 3107 | while (!sdhci_request_done(host)) |
| 3108 | ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3109 | } |
| 3110 | |
Kees Cook | 2ee4f62 | 2017-10-24 08:03:45 -0700 | [diff] [blame] | 3111 | static void sdhci_timeout_timer(struct timer_list *t) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3112 | { |
| 3113 | struct sdhci_host *host; |
| 3114 | unsigned long flags; |
| 3115 | |
Kees Cook | 2ee4f62 | 2017-10-24 08:03:45 -0700 | [diff] [blame] | 3116 | host = from_timer(host, t, timer); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3117 | |
| 3118 | spin_lock_irqsave(&host->lock, flags); |
| 3119 | |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3120 | if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { |
| 3121 | pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", |
| 3122 | mmc_hostname(host->mmc)); |
| 3123 | sdhci_dumpregs(host); |
| 3124 | |
| 3125 | host->cmd->error = -ETIMEDOUT; |
| 3126 | sdhci_finish_mrq(host, host->cmd->mrq); |
| 3127 | } |
| 3128 | |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3129 | spin_unlock_irqrestore(&host->lock, flags); |
| 3130 | } |
| 3131 | |
Kees Cook | 2ee4f62 | 2017-10-24 08:03:45 -0700 | [diff] [blame] | 3132 | static void sdhci_timeout_data_timer(struct timer_list *t) |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3133 | { |
| 3134 | struct sdhci_host *host; |
| 3135 | unsigned long flags; |
| 3136 | |
Kees Cook | 2ee4f62 | 2017-10-24 08:03:45 -0700 | [diff] [blame] | 3137 | host = from_timer(host, t, data_timer); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3138 | |
| 3139 | spin_lock_irqsave(&host->lock, flags); |
| 3140 | |
| 3141 | if (host->data || host->data_cmd || |
| 3142 | (host->cmd && sdhci_data_line_cmd(host->cmd))) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3143 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
| 3144 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3145 | sdhci_dumpregs(host); |
| 3146 | |
| 3147 | if (host->data) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 3148 | host->data->error = -ETIMEDOUT; |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 3149 | __sdhci_finish_data(host, true); |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3150 | queue_work(host->complete_wq, &host->complete_work); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3151 | } else if (host->data_cmd) { |
| 3152 | host->data_cmd->error = -ETIMEDOUT; |
| 3153 | sdhci_finish_mrq(host, host->data_cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3154 | } else { |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3155 | host->cmd->error = -ETIMEDOUT; |
| 3156 | sdhci_finish_mrq(host, host->cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3157 | } |
| 3158 | } |
| 3159 | |
| 3160 | spin_unlock_irqrestore(&host->lock, flags); |
| 3161 | } |
| 3162 | |
| 3163 | /*****************************************************************************\ |
| 3164 | * * |
| 3165 | * Interrupt handling * |
| 3166 | * * |
| 3167 | \*****************************************************************************/ |
| 3168 | |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 3169 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3170 | { |
Adrian Hunter | af849c8 | 2018-11-15 15:53:43 +0200 | [diff] [blame] | 3171 | /* Handle auto-CMD12 error */ |
| 3172 | if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) { |
| 3173 | struct mmc_request *mrq = host->data_cmd->mrq; |
| 3174 | u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); |
| 3175 | int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? |
| 3176 | SDHCI_INT_DATA_TIMEOUT : |
| 3177 | SDHCI_INT_DATA_CRC; |
| 3178 | |
| 3179 | /* Treat auto-CMD12 error the same as data error */ |
| 3180 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { |
| 3181 | *intmask_p |= data_err_bit; |
| 3182 | return; |
| 3183 | } |
| 3184 | } |
| 3185 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3186 | if (!host->cmd) { |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 3187 | /* |
| 3188 | * SDHCI recovers from errors by resetting the cmd and data |
| 3189 | * circuits. Until that is done, there very well might be more |
| 3190 | * interrupts, so ignore them in that case. |
| 3191 | */ |
| 3192 | if (host->pending_reset) |
| 3193 | return; |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3194 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
| 3195 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3196 | sdhci_dumpregs(host); |
| 3197 | return; |
| 3198 | } |
| 3199 | |
Russell King | ec014cb | 2016-01-26 13:39:39 +0000 | [diff] [blame] | 3200 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
| 3201 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { |
| 3202 | if (intmask & SDHCI_INT_TIMEOUT) |
| 3203 | host->cmd->error = -ETIMEDOUT; |
| 3204 | else |
| 3205 | host->cmd->error = -EILSEQ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3206 | |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 3207 | /* Treat data command CRC error the same as data CRC error */ |
Russell King | 71fcbda | 2016-01-26 13:39:45 +0000 | [diff] [blame] | 3208 | if (host->cmd->data && |
| 3209 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == |
| 3210 | SDHCI_INT_CRC) { |
| 3211 | host->cmd = NULL; |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 3212 | *intmask_p |= SDHCI_INT_DATA_CRC; |
Russell King | 71fcbda | 2016-01-26 13:39:45 +0000 | [diff] [blame] | 3213 | return; |
| 3214 | } |
| 3215 | |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3216 | __sdhci_finish_mrq(host, host->cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 3217 | return; |
| 3218 | } |
| 3219 | |
Adrian Hunter | af849c8 | 2018-11-15 15:53:43 +0200 | [diff] [blame] | 3220 | /* Handle auto-CMD23 error */ |
| 3221 | if (intmask & SDHCI_INT_AUTO_CMD_ERR) { |
| 3222 | struct mmc_request *mrq = host->cmd->mrq; |
| 3223 | u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); |
| 3224 | int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? |
| 3225 | -ETIMEDOUT : |
| 3226 | -EILSEQ; |
| 3227 | |
| 3228 | if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
| 3229 | mrq->sbc->error = err; |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3230 | __sdhci_finish_mrq(host, mrq); |
Adrian Hunter | af849c8 | 2018-11-15 15:53:43 +0200 | [diff] [blame] | 3231 | return; |
| 3232 | } |
| 3233 | } |
| 3234 | |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 3235 | if (intmask & SDHCI_INT_RESPONSE) |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 3236 | sdhci_finish_command(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3237 | } |
| 3238 | |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 3239 | static void sdhci_adma_show_error(struct sdhci_host *host) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3240 | { |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 3241 | void *desc = host->adma_table; |
Russell King | d1c536e | 2019-09-22 11:26:53 +0100 | [diff] [blame] | 3242 | dma_addr_t dma = host->adma_addr; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3243 | |
| 3244 | sdhci_dumpregs(host); |
| 3245 | |
| 3246 | while (true) { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3247 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3248 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3249 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
Russell King | d1c536e | 2019-09-22 11:26:53 +0100 | [diff] [blame] | 3250 | SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 3251 | (unsigned long long)dma, |
| 3252 | le32_to_cpu(dma_desc->addr_hi), |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3253 | le32_to_cpu(dma_desc->addr_lo), |
| 3254 | le16_to_cpu(dma_desc->len), |
| 3255 | le16_to_cpu(dma_desc->cmd)); |
| 3256 | else |
Russell King | d1c536e | 2019-09-22 11:26:53 +0100 | [diff] [blame] | 3257 | SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 3258 | (unsigned long long)dma, |
| 3259 | le32_to_cpu(dma_desc->addr_lo), |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3260 | le16_to_cpu(dma_desc->len), |
| 3261 | le16_to_cpu(dma_desc->cmd)); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3262 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 3263 | desc += host->desc_sz; |
Russell King | d1c536e | 2019-09-22 11:26:53 +0100 | [diff] [blame] | 3264 | dma += host->desc_sz; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3265 | |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 3266 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3267 | break; |
| 3268 | } |
| 3269 | } |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3270 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3271 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
| 3272 | { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3273 | u32 command; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3274 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3275 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
| 3276 | if (intmask & SDHCI_INT_DATA_AVAIL) { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3277 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
| 3278 | if (command == MMC_SEND_TUNING_BLOCK || |
| 3279 | command == MMC_SEND_TUNING_BLOCK_HS200) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3280 | host->tuning_done = 1; |
| 3281 | wake_up(&host->buf_ready_int); |
| 3282 | return; |
| 3283 | } |
| 3284 | } |
| 3285 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3286 | if (!host->data) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 3287 | struct mmc_command *data_cmd = host->data_cmd; |
| 3288 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3289 | /* |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 3290 | * The "data complete" interrupt is also used to |
| 3291 | * indicate that a busy state has ended. See comment |
| 3292 | * above in sdhci_cmd_irq(). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3293 | */ |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 3294 | if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 3295 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
Adrian Hunter | 69b962a | 2016-11-02 15:49:09 +0200 | [diff] [blame] | 3296 | host->data_cmd = NULL; |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 3297 | data_cmd->error = -ETIMEDOUT; |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3298 | __sdhci_finish_mrq(host, data_cmd->mrq); |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 3299 | return; |
| 3300 | } |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 3301 | if (intmask & SDHCI_INT_DATA_END) { |
Adrian Hunter | 69b962a | 2016-11-02 15:49:09 +0200 | [diff] [blame] | 3302 | host->data_cmd = NULL; |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 3303 | /* |
| 3304 | * Some cards handle busy-end interrupt |
| 3305 | * before the command completed, so make |
| 3306 | * sure we do things in the proper order. |
| 3307 | */ |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 3308 | if (host->cmd == data_cmd) |
| 3309 | return; |
| 3310 | |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3311 | __sdhci_finish_mrq(host, data_cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 3312 | return; |
| 3313 | } |
| 3314 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3315 | |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 3316 | /* |
| 3317 | * SDHCI recovers from errors by resetting the cmd and data |
| 3318 | * circuits. Until that is done, there very well might be more |
| 3319 | * interrupts, so ignore them in that case. |
| 3320 | */ |
| 3321 | if (host->pending_reset) |
| 3322 | return; |
| 3323 | |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3324 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
| 3325 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3326 | sdhci_dumpregs(host); |
| 3327 | |
| 3328 | return; |
| 3329 | } |
| 3330 | |
| 3331 | if (intmask & SDHCI_INT_DATA_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 3332 | host->data->error = -ETIMEDOUT; |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 3333 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
| 3334 | host->data->error = -EILSEQ; |
| 3335 | else if ((intmask & SDHCI_INT_DATA_CRC) && |
| 3336 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) |
| 3337 | != MMC_BUS_TEST_R) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 3338 | host->data->error = -EILSEQ; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3339 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
Russell King | d1c536e | 2019-09-22 11:26:53 +0100 | [diff] [blame] | 3340 | pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc), |
| 3341 | intmask); |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 3342 | sdhci_adma_show_error(host); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3343 | host->data->error = -EIO; |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 3344 | if (host->ops->adma_workaround) |
| 3345 | host->ops->adma_workaround(host, intmask); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 3346 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3347 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 3348 | if (host->data->error) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3349 | sdhci_finish_data(host); |
| 3350 | else { |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 3351 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3352 | sdhci_transfer_pio(host); |
| 3353 | |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 3354 | /* |
| 3355 | * We currently don't do anything fancy with DMA |
| 3356 | * boundaries, but as we can't disable the feature |
| 3357 | * we need to at least restart the transfer. |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 3358 | * |
| 3359 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) |
| 3360 | * should return a valid address to continue from, but as |
| 3361 | * some controllers are faulty, don't trust them. |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 3362 | */ |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 3363 | if (intmask & SDHCI_INT_DMA_END) { |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 3364 | dma_addr_t dmastart, dmanow; |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 3365 | |
| 3366 | dmastart = sdhci_sdma_address(host); |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 3367 | dmanow = dmastart + host->data->bytes_xfered; |
| 3368 | /* |
| 3369 | * Force update to the next DMA block boundary. |
| 3370 | */ |
| 3371 | dmanow = (dmanow & |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 3372 | ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 3373 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 3374 | host->data->bytes_xfered = dmanow - dmastart; |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 3375 | DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", |
| 3376 | &dmastart, host->data->bytes_xfered, &dmanow); |
| 3377 | sdhci_set_sdma_addr(host, dmanow); |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 3378 | } |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 3379 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 3380 | if (intmask & SDHCI_INT_DATA_END) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 3381 | if (host->cmd == host->data_cmd) { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 3382 | /* |
| 3383 | * Data managed to finish before the |
| 3384 | * command completed. Make sure we do |
| 3385 | * things in the proper order. |
| 3386 | */ |
| 3387 | host->data_early = 1; |
| 3388 | } else { |
| 3389 | sdhci_finish_data(host); |
| 3390 | } |
| 3391 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3392 | } |
| 3393 | } |
| 3394 | |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3395 | static inline bool sdhci_defer_done(struct sdhci_host *host, |
| 3396 | struct mmc_request *mrq) |
| 3397 | { |
| 3398 | struct mmc_data *data = mrq->data; |
| 3399 | |
Baolin Wang | 4730831 | 2020-02-12 12:12:59 +0800 | [diff] [blame] | 3400 | return host->pending_reset || host->always_defer_done || |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3401 | ((host->flags & SDHCI_REQ_USE_DMA) && data && |
| 3402 | data->host_cookie == COOKIE_MAPPED); |
| 3403 | } |
| 3404 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 3405 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3406 | { |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3407 | struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0}; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3408 | irqreturn_t result = IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3409 | struct sdhci_host *host = dev_id; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3410 | u32 intmask, mask, unexpected = 0; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3411 | int max_loops = 16; |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3412 | int i; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3413 | |
| 3414 | spin_lock(&host->lock); |
| 3415 | |
Ulf Hansson | af5d2b7 | 2019-09-08 12:12:35 +0200 | [diff] [blame] | 3416 | if (host->runtime_suspended) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3417 | spin_unlock(&host->lock); |
Adrian Hunter | 655bca7 | 2014-03-11 10:09:36 +0200 | [diff] [blame] | 3418 | return IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3419 | } |
| 3420 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 3421 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Mark Lord | 62df67a5 | 2007-03-06 13:30:13 +0100 | [diff] [blame] | 3422 | if (!intmask || intmask == 0xffffffff) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3423 | result = IRQ_NONE; |
| 3424 | goto out; |
| 3425 | } |
| 3426 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3427 | do { |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3428 | DBG("IRQ status 0x%08x\n", intmask); |
| 3429 | |
| 3430 | if (host->ops->irq) { |
| 3431 | intmask = host->ops->irq(host, intmask); |
| 3432 | if (!intmask) |
| 3433 | goto cont; |
| 3434 | } |
| 3435 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3436 | /* Clear selected interrupts. */ |
| 3437 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 3438 | SDHCI_INT_BUS_POWER); |
| 3439 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3440 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3441 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
| 3442 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 3443 | SDHCI_CARD_PRESENT; |
| 3444 | |
| 3445 | /* |
| 3446 | * There is a observation on i.mx esdhc. INSERT |
| 3447 | * bit will be immediately set again when it gets |
| 3448 | * cleared, if a card is inserted. We have to mask |
| 3449 | * the irq to prevent interrupt storm which will |
| 3450 | * freeze the system. And the REMOVE gets the |
| 3451 | * same situation. |
| 3452 | * |
| 3453 | * More testing are needed here to ensure it works |
| 3454 | * for other platforms though. |
| 3455 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3456 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
| 3457 | SDHCI_INT_CARD_REMOVE); |
| 3458 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 3459 | SDHCI_INT_CARD_INSERT; |
| 3460 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 3461 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3462 | |
| 3463 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
| 3464 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 3465 | |
| 3466 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | |
| 3467 | SDHCI_INT_CARD_REMOVE); |
| 3468 | result = IRQ_WAKE_THREAD; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3469 | } |
| 3470 | |
| 3471 | if (intmask & SDHCI_INT_CMD_MASK) |
Adrian Hunter | 4bf7809 | 2018-11-15 15:53:41 +0200 | [diff] [blame] | 3472 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3473 | |
| 3474 | if (intmask & SDHCI_INT_DATA_MASK) |
| 3475 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
| 3476 | |
| 3477 | if (intmask & SDHCI_INT_BUS_POWER) |
| 3478 | pr_err("%s: Card is consuming too much power!\n", |
| 3479 | mmc_hostname(host->mmc)); |
| 3480 | |
Dong Aisheng | f37b20e | 2016-07-12 15:46:17 +0800 | [diff] [blame] | 3481 | if (intmask & SDHCI_INT_RETUNE) |
| 3482 | mmc_retune_needed(host->mmc); |
| 3483 | |
Gabriel Krisman Bertazi | 161e6d4 | 2017-01-16 12:23:42 -0200 | [diff] [blame] | 3484 | if ((intmask & SDHCI_INT_CARD_INT) && |
| 3485 | (host->ier & SDHCI_INT_CARD_INT)) { |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3486 | sdhci_enable_sdio_irq_nolock(host, false); |
Adrian Hunter | 89f3c36 | 2019-05-27 14:45:55 +0300 | [diff] [blame] | 3487 | sdio_signal_irq(host->mmc); |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3488 | } |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3489 | |
| 3490 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 3491 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 3492 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | |
Dong Aisheng | f37b20e | 2016-07-12 15:46:17 +0800 | [diff] [blame] | 3493 | SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3494 | |
| 3495 | if (intmask) { |
| 3496 | unexpected |= intmask; |
| 3497 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
| 3498 | } |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3499 | cont: |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3500 | if (result == IRQ_NONE) |
| 3501 | result = IRQ_HANDLED; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3502 | |
| 3503 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 3504 | } while (intmask && --max_loops); |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3505 | |
| 3506 | /* Determine if mrqs can be completed immediately */ |
| 3507 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 3508 | struct mmc_request *mrq = host->mrqs_done[i]; |
| 3509 | |
| 3510 | if (!mrq) |
| 3511 | continue; |
| 3512 | |
| 3513 | if (sdhci_defer_done(host, mrq)) { |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3514 | result = IRQ_WAKE_THREAD; |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3515 | } else { |
| 3516 | mrqs_done[i] = mrq; |
| 3517 | host->mrqs_done[i] = NULL; |
| 3518 | } |
| 3519 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3520 | out: |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 3521 | if (host->deferred_cmd) |
| 3522 | result = IRQ_WAKE_THREAD; |
| 3523 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3524 | spin_unlock(&host->lock); |
| 3525 | |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3526 | /* Process mrqs ready for immediate completion */ |
| 3527 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
Baolin Wang | 1774b00 | 2020-02-12 12:12:58 +0800 | [diff] [blame] | 3528 | if (!mrqs_done[i]) |
| 3529 | continue; |
| 3530 | |
| 3531 | if (host->ops->request_done) |
| 3532 | host->ops->request_done(host, mrqs_done[i]); |
| 3533 | else |
Adrian Hunter | 19d2f69 | 2019-04-05 15:40:19 +0300 | [diff] [blame] | 3534 | mmc_request_done(host->mmc, mrqs_done[i]); |
| 3535 | } |
| 3536 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 3537 | if (unexpected) { |
| 3538 | pr_err("%s: Unexpected interrupt 0x%08x.\n", |
| 3539 | mmc_hostname(host->mmc), unexpected); |
| 3540 | sdhci_dumpregs(host); |
| 3541 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 3542 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3543 | return result; |
| 3544 | } |
| 3545 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3546 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
| 3547 | { |
| 3548 | struct sdhci_host *host = dev_id; |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 3549 | struct mmc_command *cmd; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3550 | unsigned long flags; |
| 3551 | u32 isr; |
| 3552 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3553 | while (!sdhci_request_done(host)) |
| 3554 | ; |
| 3555 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3556 | spin_lock_irqsave(&host->lock, flags); |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 3557 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3558 | isr = host->thread_isr; |
| 3559 | host->thread_isr = 0; |
Adrian Hunter | 845c939 | 2020-04-12 12:03:49 +0300 | [diff] [blame] | 3560 | |
| 3561 | cmd = host->deferred_cmd; |
| 3562 | if (cmd && !sdhci_send_command_retry(host, cmd, flags)) |
| 3563 | sdhci_finish_mrq(host, cmd->mrq); |
| 3564 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3565 | spin_unlock_irqrestore(&host->lock, flags); |
| 3566 | |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 3567 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 3568 | struct mmc_host *mmc = host->mmc; |
| 3569 | |
| 3570 | mmc->ops->card_event(mmc); |
| 3571 | mmc_detect_change(mmc, msecs_to_jiffies(200)); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 3572 | } |
| 3573 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 3574 | return IRQ_HANDLED; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3575 | } |
| 3576 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3577 | /*****************************************************************************\ |
| 3578 | * * |
| 3579 | * Suspend/resume * |
| 3580 | * * |
| 3581 | \*****************************************************************************/ |
| 3582 | |
| 3583 | #ifdef CONFIG_PM |
Adrian Hunter | 9c316b3 | 2018-02-27 14:51:23 +0200 | [diff] [blame] | 3584 | |
| 3585 | static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host) |
| 3586 | { |
| 3587 | return mmc_card_is_removable(host->mmc) && |
| 3588 | !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
| 3589 | !mmc_can_gpio_cd(host->mmc); |
| 3590 | } |
| 3591 | |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 3592 | /* |
| 3593 | * To enable wakeup events, the corresponding events have to be enabled in |
| 3594 | * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal |
| 3595 | * Table' in the SD Host Controller Standard Specification. |
| 3596 | * It is useless to restore SDHCI_INT_ENABLE state in |
| 3597 | * sdhci_disable_irq_wakeups() since it will be set by |
| 3598 | * sdhci_enable_card_detection() or sdhci_init(). |
| 3599 | */ |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3600 | static bool sdhci_enable_irq_wakeups(struct sdhci_host *host) |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3601 | { |
Adrian Hunter | 81b1454 | 2018-01-09 09:52:22 +0200 | [diff] [blame] | 3602 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
| 3603 | SDHCI_WAKE_ON_INT; |
| 3604 | u32 irq_val = 0; |
| 3605 | u8 wake_val = 0; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3606 | u8 val; |
Adrian Hunter | 81b1454 | 2018-01-09 09:52:22 +0200 | [diff] [blame] | 3607 | |
Adrian Hunter | 9c316b3 | 2018-02-27 14:51:23 +0200 | [diff] [blame] | 3608 | if (sdhci_cd_irq_can_wakeup(host)) { |
Adrian Hunter | 81b1454 | 2018-01-09 09:52:22 +0200 | [diff] [blame] | 3609 | wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE; |
| 3610 | irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE; |
| 3611 | } |
| 3612 | |
Adrian Hunter | d5d568f | 2018-02-27 14:51:24 +0200 | [diff] [blame] | 3613 | if (mmc_card_wake_sdio_irq(host->mmc)) { |
| 3614 | wake_val |= SDHCI_WAKE_ON_INT; |
| 3615 | irq_val |= SDHCI_INT_CARD_INT; |
| 3616 | } |
| 3617 | |
| 3618 | if (!irq_val) |
| 3619 | return false; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3620 | |
| 3621 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
Adrian Hunter | 81b1454 | 2018-01-09 09:52:22 +0200 | [diff] [blame] | 3622 | val &= ~mask; |
| 3623 | val |= wake_val; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3624 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
Adrian Hunter | 81b1454 | 2018-01-09 09:52:22 +0200 | [diff] [blame] | 3625 | |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 3626 | sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3627 | |
| 3628 | host->irq_wake_enabled = !enable_irq_wake(host->irq); |
| 3629 | |
| 3630 | return host->irq_wake_enabled; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3631 | } |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3632 | |
Fabio Estevam | 0b10f47 | 2014-08-30 14:53:13 -0300 | [diff] [blame] | 3633 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3634 | { |
| 3635 | u8 val; |
| 3636 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 3637 | | SDHCI_WAKE_ON_INT; |
| 3638 | |
| 3639 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 3640 | val &= ~mask; |
| 3641 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3642 | |
| 3643 | disable_irq_wake(host->irq); |
| 3644 | |
| 3645 | host->irq_wake_enabled = false; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3646 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3647 | |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 3648 | int sdhci_suspend_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3649 | { |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3650 | sdhci_disable_card_detection(host); |
| 3651 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 3652 | mmc_retune_timer_stop(host->mmc); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3653 | |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3654 | if (!device_may_wakeup(mmc_dev(host->mmc)) || |
| 3655 | !sdhci_enable_irq_wakeups(host)) { |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3656 | host->ier = 0; |
| 3657 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3658 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3659 | free_irq(host->irq, host); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 3660 | } |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3661 | |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 3662 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3663 | } |
| 3664 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3665 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3666 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3667 | int sdhci_resume_host(struct sdhci_host *host) |
| 3668 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 3669 | struct mmc_host *mmc = host->mmc; |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 3670 | int ret = 0; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3671 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3672 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3673 | if (host->ops->enable_dma) |
| 3674 | host->ops->enable_dma(host); |
| 3675 | } |
| 3676 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 3677 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
| 3678 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { |
| 3679 | /* Card keeps power but host controller does not */ |
| 3680 | sdhci_init(host, 0); |
| 3681 | host->pwr = 0; |
| 3682 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 3683 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 3684 | } else { |
| 3685 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 3686 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3687 | |
Adrian Hunter | 58e79b6 | 2018-01-09 09:52:21 +0200 | [diff] [blame] | 3688 | if (host->irq_wake_enabled) { |
| 3689 | sdhci_disable_irq_wakeups(host); |
| 3690 | } else { |
Haibo Chen | 14a7b4164 | 2015-09-15 18:32:58 +0800 | [diff] [blame] | 3691 | ret = request_threaded_irq(host->irq, sdhci_irq, |
| 3692 | sdhci_thread_irq, IRQF_SHARED, |
| 3693 | mmc_hostname(host->mmc), host); |
| 3694 | if (ret) |
| 3695 | return ret; |
Haibo Chen | 14a7b4164 | 2015-09-15 18:32:58 +0800 | [diff] [blame] | 3696 | } |
| 3697 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3698 | sdhci_enable_card_detection(host); |
| 3699 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 3700 | return ret; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3701 | } |
| 3702 | |
| 3703 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3704 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3705 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
| 3706 | { |
| 3707 | unsigned long flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3708 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 3709 | mmc_retune_timer_stop(host->mmc); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3710 | |
| 3711 | spin_lock_irqsave(&host->lock, flags); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3712 | host->ier &= SDHCI_INT_CARD_INT; |
| 3713 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 3714 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3715 | spin_unlock_irqrestore(&host->lock, flags); |
| 3716 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3717 | synchronize_hardirq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3718 | |
| 3719 | spin_lock_irqsave(&host->lock, flags); |
| 3720 | host->runtime_suspended = true; |
| 3721 | spin_unlock_irqrestore(&host->lock, flags); |
| 3722 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 3723 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3724 | } |
| 3725 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); |
| 3726 | |
Baolin Wang | c6303c5 | 2019-07-25 11:14:22 +0800 | [diff] [blame] | 3727 | int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3728 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 3729 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3730 | unsigned long flags; |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 3731 | int host_flags = host->flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3732 | |
| 3733 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 3734 | if (host->ops->enable_dma) |
| 3735 | host->ops->enable_dma(host); |
| 3736 | } |
| 3737 | |
Baolin Wang | c6303c5 | 2019-07-25 11:14:22 +0800 | [diff] [blame] | 3738 | sdhci_init(host, soft_reset); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3739 | |
Zhoujie Wu | 70bc85a | 2017-08-03 12:28:40 -0700 | [diff] [blame] | 3740 | if (mmc->ios.power_mode != MMC_POWER_UNDEFINED && |
| 3741 | mmc->ios.power_mode != MMC_POWER_OFF) { |
Adrian Hunter | 84ec048 | 2016-12-19 15:33:11 +0200 | [diff] [blame] | 3742 | /* Force clock and power re-program */ |
| 3743 | host->pwr = 0; |
| 3744 | host->clock = 0; |
| 3745 | mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); |
| 3746 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3747 | |
Adrian Hunter | 84ec048 | 2016-12-19 15:33:11 +0200 | [diff] [blame] | 3748 | if ((host_flags & SDHCI_PV_ENABLED) && |
| 3749 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { |
| 3750 | spin_lock_irqsave(&host->lock, flags); |
| 3751 | sdhci_enable_preset_value(host, true); |
| 3752 | spin_unlock_irqrestore(&host->lock, flags); |
| 3753 | } |
| 3754 | |
| 3755 | if ((mmc->caps2 & MMC_CAP2_HS400_ES) && |
| 3756 | mmc->ops->hs400_enhanced_strobe) |
| 3757 | mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 3758 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3759 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3760 | spin_lock_irqsave(&host->lock, flags); |
| 3761 | |
| 3762 | host->runtime_suspended = false; |
| 3763 | |
| 3764 | /* Enable SDIO IRQ */ |
Ulf Hansson | 0e62614 | 2019-09-08 12:12:36 +0200 | [diff] [blame] | 3765 | if (sdio_irq_claimed(mmc)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3766 | sdhci_enable_sdio_irq_nolock(host, true); |
| 3767 | |
| 3768 | /* Enable Card Detection */ |
| 3769 | sdhci_enable_card_detection(host); |
| 3770 | |
| 3771 | spin_unlock_irqrestore(&host->lock, flags); |
| 3772 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 3773 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3774 | } |
| 3775 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); |
| 3776 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 3777 | #endif /* CONFIG_PM */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3778 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3779 | /*****************************************************************************\ |
| 3780 | * * |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3781 | * Command Queue Engine (CQE) helpers * |
| 3782 | * * |
| 3783 | \*****************************************************************************/ |
| 3784 | |
| 3785 | void sdhci_cqe_enable(struct mmc_host *mmc) |
| 3786 | { |
| 3787 | struct sdhci_host *host = mmc_priv(mmc); |
| 3788 | unsigned long flags; |
| 3789 | u8 ctrl; |
| 3790 | |
| 3791 | spin_lock_irqsave(&host->lock, flags); |
| 3792 | |
| 3793 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 3794 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
Sowjanya Komatineni | 4c4faff | 2019-01-23 11:30:53 -0800 | [diff] [blame] | 3795 | /* |
| 3796 | * Host from V4.10 supports ADMA3 DMA type. |
| 3797 | * ADMA3 performs integrated descriptor which is more suitable |
| 3798 | * for cmd queuing to fetch both command and transfer descriptors. |
| 3799 | */ |
| 3800 | if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3)) |
| 3801 | ctrl |= SDHCI_CTRL_ADMA3; |
| 3802 | else if (host->flags & SDHCI_USE_64_BIT_DMA) |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3803 | ctrl |= SDHCI_CTRL_ADMA64; |
| 3804 | else |
| 3805 | ctrl |= SDHCI_CTRL_ADMA32; |
| 3806 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 3807 | |
Srinivas Kandagatla | c846a00 | 2017-08-03 14:46:13 +0200 | [diff] [blame] | 3808 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512), |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3809 | SDHCI_BLOCK_SIZE); |
| 3810 | |
| 3811 | /* Set maximum timeout */ |
BOUGH CHEN | 401059d | 2019-01-07 10:11:36 +0000 | [diff] [blame] | 3812 | sdhci_set_timeout(host, NULL); |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3813 | |
| 3814 | host->ier = host->cqe_ier; |
| 3815 | |
| 3816 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 3817 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
| 3818 | |
| 3819 | host->cqe_on = true; |
| 3820 | |
| 3821 | pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n", |
| 3822 | mmc_hostname(mmc), host->ier, |
| 3823 | sdhci_readl(host, SDHCI_INT_STATUS)); |
| 3824 | |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3825 | spin_unlock_irqrestore(&host->lock, flags); |
| 3826 | } |
| 3827 | EXPORT_SYMBOL_GPL(sdhci_cqe_enable); |
| 3828 | |
| 3829 | void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery) |
| 3830 | { |
| 3831 | struct sdhci_host *host = mmc_priv(mmc); |
| 3832 | unsigned long flags; |
| 3833 | |
| 3834 | spin_lock_irqsave(&host->lock, flags); |
| 3835 | |
| 3836 | sdhci_set_default_irqs(host); |
| 3837 | |
| 3838 | host->cqe_on = false; |
| 3839 | |
| 3840 | if (recovery) { |
| 3841 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 3842 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
| 3843 | } |
| 3844 | |
| 3845 | pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n", |
| 3846 | mmc_hostname(mmc), host->ier, |
| 3847 | sdhci_readl(host, SDHCI_INT_STATUS)); |
| 3848 | |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3849 | spin_unlock_irqrestore(&host->lock, flags); |
| 3850 | } |
| 3851 | EXPORT_SYMBOL_GPL(sdhci_cqe_disable); |
| 3852 | |
| 3853 | bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, |
| 3854 | int *data_error) |
| 3855 | { |
| 3856 | u32 mask; |
| 3857 | |
| 3858 | if (!host->cqe_on) |
| 3859 | return false; |
| 3860 | |
| 3861 | if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) |
| 3862 | *cmd_error = -EILSEQ; |
| 3863 | else if (intmask & SDHCI_INT_TIMEOUT) |
| 3864 | *cmd_error = -ETIMEDOUT; |
| 3865 | else |
| 3866 | *cmd_error = 0; |
| 3867 | |
| 3868 | if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) |
| 3869 | *data_error = -EILSEQ; |
| 3870 | else if (intmask & SDHCI_INT_DATA_TIMEOUT) |
| 3871 | *data_error = -ETIMEDOUT; |
| 3872 | else if (intmask & SDHCI_INT_ADMA_ERROR) |
| 3873 | *data_error = -EIO; |
| 3874 | else |
| 3875 | *data_error = 0; |
| 3876 | |
| 3877 | /* Clear selected interrupts. */ |
| 3878 | mask = intmask & host->cqe_ier; |
| 3879 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
| 3880 | |
| 3881 | if (intmask & SDHCI_INT_BUS_POWER) |
| 3882 | pr_err("%s: Card is consuming too much power!\n", |
| 3883 | mmc_hostname(host->mmc)); |
| 3884 | |
| 3885 | intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR); |
| 3886 | if (intmask) { |
| 3887 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
| 3888 | pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n", |
| 3889 | mmc_hostname(host->mmc), intmask); |
| 3890 | sdhci_dumpregs(host); |
| 3891 | } |
| 3892 | |
| 3893 | return true; |
| 3894 | } |
| 3895 | EXPORT_SYMBOL_GPL(sdhci_cqe_irq); |
| 3896 | |
| 3897 | /*****************************************************************************\ |
| 3898 | * * |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3899 | * Device allocation/registration * |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3900 | * * |
| 3901 | \*****************************************************************************/ |
| 3902 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3903 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 3904 | size_t priv_size) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3905 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3906 | struct mmc_host *mmc; |
| 3907 | struct sdhci_host *host; |
| 3908 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3909 | WARN_ON(dev == NULL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3910 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3911 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3912 | if (!mmc) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3913 | return ERR_PTR(-ENOMEM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3914 | |
| 3915 | host = mmc_priv(mmc); |
| 3916 | host->mmc = mmc; |
Adrian Hunter | bf60e59 | 2016-02-09 16:12:35 +0200 | [diff] [blame] | 3917 | host->mmc_host_ops = sdhci_ops; |
| 3918 | mmc->ops = &host->mmc_host_ops; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3919 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 3920 | host->flags = SDHCI_SIGNALING_330; |
| 3921 | |
Adrian Hunter | f12e39d | 2017-03-20 19:50:47 +0200 | [diff] [blame] | 3922 | host->cqe_ier = SDHCI_CQE_INT_MASK; |
| 3923 | host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK; |
| 3924 | |
Adrian Hunter | 83b600b | 2017-04-20 16:14:43 +0800 | [diff] [blame] | 3925 | host->tuning_delay = -1; |
Sowjanya Komatineni | 1d8cd065 | 2019-03-23 21:45:19 -0700 | [diff] [blame] | 3926 | host->tuning_loop_count = MAX_TUNING_LOOP; |
Adrian Hunter | 83b600b | 2017-04-20 16:14:43 +0800 | [diff] [blame] | 3927 | |
Srinivas Kandagatla | c846a00 | 2017-08-03 14:46:13 +0200 | [diff] [blame] | 3928 | host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; |
| 3929 | |
Jisheng Zhang | e93be38 | 2018-08-28 17:46:35 +0800 | [diff] [blame] | 3930 | /* |
| 3931 | * The DMA table descriptor count is calculated as the maximum |
| 3932 | * number of segments times 2, to allow for an alignment |
| 3933 | * descriptor for each segment, plus 1 for a nop end descriptor. |
| 3934 | */ |
| 3935 | host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; |
| 3936 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3937 | return host; |
| 3938 | } |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 3939 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3940 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3941 | |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 3942 | static int sdhci_set_dma_mask(struct sdhci_host *host) |
| 3943 | { |
| 3944 | struct mmc_host *mmc = host->mmc; |
| 3945 | struct device *dev = mmc_dev(mmc); |
| 3946 | int ret = -EINVAL; |
| 3947 | |
| 3948 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) |
| 3949 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 3950 | |
| 3951 | /* Try 64-bit mask if hardware is capable of it */ |
| 3952 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 3953 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
| 3954 | if (ret) { |
| 3955 | pr_warn("%s: Failed to set 64-bit DMA mask.\n", |
| 3956 | mmc_hostname(mmc)); |
| 3957 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 3958 | } |
| 3959 | } |
| 3960 | |
| 3961 | /* 32-bit mask as default & fallback */ |
| 3962 | if (ret) { |
| 3963 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| 3964 | if (ret) |
| 3965 | pr_warn("%s: Failed to set 32-bit DMA mask.\n", |
| 3966 | mmc_hostname(mmc)); |
| 3967 | } |
| 3968 | |
| 3969 | return ret; |
| 3970 | } |
| 3971 | |
Masahiro Yamada | 8784edc | 2019-08-29 19:49:27 +0900 | [diff] [blame] | 3972 | void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, |
| 3973 | const u32 *caps, const u32 *caps1) |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 3974 | { |
| 3975 | u16 v; |
Zach Brown | 92e0c44 | 2016-11-02 10:26:16 -0500 | [diff] [blame] | 3976 | u64 dt_caps_mask = 0; |
| 3977 | u64 dt_caps = 0; |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 3978 | |
| 3979 | if (host->read_caps) |
| 3980 | return; |
| 3981 | |
| 3982 | host->read_caps = true; |
| 3983 | |
| 3984 | if (debug_quirks) |
| 3985 | host->quirks = debug_quirks; |
| 3986 | |
| 3987 | if (debug_quirks2) |
| 3988 | host->quirks2 = debug_quirks2; |
| 3989 | |
| 3990 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
| 3991 | |
Chunyan Zhang | b3f80b4 | 2018-08-30 16:21:38 +0800 | [diff] [blame] | 3992 | if (host->v4_mode) |
| 3993 | sdhci_do_enable_v4_mode(host); |
| 3994 | |
Zach Brown | 92e0c44 | 2016-11-02 10:26:16 -0500 | [diff] [blame] | 3995 | of_property_read_u64(mmc_dev(host->mmc)->of_node, |
| 3996 | "sdhci-caps-mask", &dt_caps_mask); |
| 3997 | of_property_read_u64(mmc_dev(host->mmc)->of_node, |
| 3998 | "sdhci-caps", &dt_caps); |
| 3999 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 4000 | v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); |
| 4001 | host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; |
| 4002 | |
| 4003 | if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) |
| 4004 | return; |
| 4005 | |
Zach Brown | 92e0c44 | 2016-11-02 10:26:16 -0500 | [diff] [blame] | 4006 | if (caps) { |
| 4007 | host->caps = *caps; |
| 4008 | } else { |
| 4009 | host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); |
| 4010 | host->caps &= ~lower_32_bits(dt_caps_mask); |
| 4011 | host->caps |= lower_32_bits(dt_caps); |
| 4012 | } |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 4013 | |
| 4014 | if (host->version < SDHCI_SPEC_300) |
| 4015 | return; |
| 4016 | |
Zach Brown | 92e0c44 | 2016-11-02 10:26:16 -0500 | [diff] [blame] | 4017 | if (caps1) { |
| 4018 | host->caps1 = *caps1; |
| 4019 | } else { |
| 4020 | host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); |
| 4021 | host->caps1 &= ~upper_32_bits(dt_caps_mask); |
| 4022 | host->caps1 |= upper_32_bits(dt_caps); |
| 4023 | } |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 4024 | } |
| 4025 | EXPORT_SYMBOL_GPL(__sdhci_read_caps); |
| 4026 | |
Chunyan Zhang | a68dd9a | 2018-10-25 10:12:36 +0800 | [diff] [blame] | 4027 | static void sdhci_allocate_bounce_buffer(struct sdhci_host *host) |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4028 | { |
| 4029 | struct mmc_host *mmc = host->mmc; |
| 4030 | unsigned int max_blocks; |
| 4031 | unsigned int bounce_size; |
| 4032 | int ret; |
| 4033 | |
| 4034 | /* |
| 4035 | * Cap the bounce buffer at 64KB. Using a bigger bounce buffer |
| 4036 | * has diminishing returns, this is probably because SD/MMC |
| 4037 | * cards are usually optimized to handle this size of requests. |
| 4038 | */ |
| 4039 | bounce_size = SZ_64K; |
| 4040 | /* |
| 4041 | * Adjust downwards to maximum request size if this is less |
| 4042 | * than our segment size, else hammer down the maximum |
| 4043 | * request size to the maximum buffer size. |
| 4044 | */ |
| 4045 | if (mmc->max_req_size < bounce_size) |
| 4046 | bounce_size = mmc->max_req_size; |
| 4047 | max_blocks = bounce_size / 512; |
| 4048 | |
| 4049 | /* |
| 4050 | * When we just support one segment, we can get significant |
| 4051 | * speedups by the help of a bounce buffer to group scattered |
| 4052 | * reads/writes together. |
| 4053 | */ |
| 4054 | host->bounce_buffer = devm_kmalloc(mmc->parent, |
| 4055 | bounce_size, |
| 4056 | GFP_KERNEL); |
| 4057 | if (!host->bounce_buffer) { |
| 4058 | pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n", |
| 4059 | mmc_hostname(mmc), |
| 4060 | bounce_size); |
| 4061 | /* |
| 4062 | * Exiting with zero here makes sure we proceed with |
| 4063 | * mmc->max_segs == 1. |
| 4064 | */ |
Chunyan Zhang | a68dd9a | 2018-10-25 10:12:36 +0800 | [diff] [blame] | 4065 | return; |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4066 | } |
| 4067 | |
| 4068 | host->bounce_addr = dma_map_single(mmc->parent, |
| 4069 | host->bounce_buffer, |
| 4070 | bounce_size, |
| 4071 | DMA_BIDIRECTIONAL); |
| 4072 | ret = dma_mapping_error(mmc->parent, host->bounce_addr); |
| 4073 | if (ret) |
| 4074 | /* Again fall back to max_segs == 1 */ |
Chunyan Zhang | a68dd9a | 2018-10-25 10:12:36 +0800 | [diff] [blame] | 4075 | return; |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4076 | host->bounce_buffer_size = bounce_size; |
| 4077 | |
| 4078 | /* Lie about this since we're bouncing */ |
| 4079 | mmc->max_segs = max_blocks; |
| 4080 | mmc->max_seg_size = bounce_size; |
| 4081 | mmc->max_req_size = bounce_size; |
| 4082 | |
| 4083 | pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n", |
| 4084 | mmc_hostname(mmc), max_blocks, bounce_size); |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4085 | } |
| 4086 | |
Chunyan Zhang | 685e444 | 2018-08-30 16:21:40 +0800 | [diff] [blame] | 4087 | static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) |
| 4088 | { |
| 4089 | /* |
| 4090 | * According to SD Host Controller spec v4.10, bit[27] added from |
| 4091 | * version 4.10 in Capabilities Register is used as 64-bit System |
| 4092 | * Address support for V4 mode. |
| 4093 | */ |
| 4094 | if (host->version >= SDHCI_SPEC_410 && host->v4_mode) |
| 4095 | return host->caps & SDHCI_CAN_64BIT_V4; |
| 4096 | |
| 4097 | return host->caps & SDHCI_CAN_64BIT; |
| 4098 | } |
| 4099 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4100 | int sdhci_setup_host(struct sdhci_host *host) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4101 | { |
| 4102 | struct mmc_host *mmc; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4103 | u32 max_current_caps; |
| 4104 | unsigned int ocr_avail; |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 4105 | unsigned int override_timeout_clk; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 4106 | u32 max_clk; |
Dan Carpenter | 907be2a | 2020-07-14 17:14:10 +0300 | [diff] [blame] | 4107 | int ret = 0; |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4108 | bool enable_vqmmc = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4109 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4110 | WARN_ON(host == NULL); |
| 4111 | if (host == NULL) |
| 4112 | return -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4113 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4114 | mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4115 | |
Jon Hunter | efba142 | 2016-07-12 14:53:36 +0100 | [diff] [blame] | 4116 | /* |
| 4117 | * If there are external regulators, get them. Note this must be done |
| 4118 | * early before resetting the host and reading the capabilities so that |
| 4119 | * the host can take the appropriate action if regulators are not |
| 4120 | * available. |
| 4121 | */ |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4122 | if (!mmc->supply.vqmmc) { |
| 4123 | ret = mmc_regulator_get_supply(mmc); |
| 4124 | if (ret) |
| 4125 | return ret; |
| 4126 | enable_vqmmc = true; |
| 4127 | } |
Jon Hunter | efba142 | 2016-07-12 14:53:36 +0100 | [diff] [blame] | 4128 | |
Shawn Lin | 06ebc60 | 2017-07-19 15:55:49 +0800 | [diff] [blame] | 4129 | DBG("Version: 0x%08x | Present: 0x%08x\n", |
| 4130 | sdhci_readw(host, SDHCI_HOST_VERSION), |
| 4131 | sdhci_readl(host, SDHCI_PRESENT_STATE)); |
| 4132 | DBG("Caps: 0x%08x | Caps_1: 0x%08x\n", |
| 4133 | sdhci_readl(host, SDHCI_CAPABILITIES), |
| 4134 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
| 4135 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 4136 | sdhci_read_caps(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4137 | |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 4138 | override_timeout_clk = host->timeout_clk; |
| 4139 | |
Chunyan Zhang | 18da199 | 2018-08-30 16:21:37 +0800 | [diff] [blame] | 4140 | if (host->version > SDHCI_SPEC_420) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 4141 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
| 4142 | mmc_hostname(mmc), host->version); |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 4143 | } |
| 4144 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4145 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4146 | host->flags |= SDHCI_USE_SDMA; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4147 | else if (!(host->caps & SDHCI_CAN_DO_SDMA)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4148 | DBG("Controller doesn't have SDMA capability\n"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 4149 | else |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4150 | host->flags |= SDHCI_USE_SDMA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4151 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4152 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4153 | (host->flags & SDHCI_USE_SDMA)) { |
Rolf Eike Beer | cee687c | 2007-11-02 15:22:30 +0100 | [diff] [blame] | 4154 | DBG("Disabling DMA as it is marked broken\n"); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4155 | host->flags &= ~SDHCI_USE_SDMA; |
Feng Tang | 7c168e3 | 2007-09-30 12:44:18 +0200 | [diff] [blame] | 4156 | } |
| 4157 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4158 | if ((host->version >= SDHCI_SPEC_200) && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4159 | (host->caps & SDHCI_CAN_DO_ADMA2)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4160 | host->flags |= SDHCI_USE_ADMA; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4161 | |
| 4162 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && |
| 4163 | (host->flags & SDHCI_USE_ADMA)) { |
| 4164 | DBG("Disabling ADMA as it is marked broken\n"); |
| 4165 | host->flags &= ~SDHCI_USE_ADMA; |
| 4166 | } |
| 4167 | |
Chunyan Zhang | 685e444 | 2018-08-30 16:21:40 +0800 | [diff] [blame] | 4168 | if (sdhci_can_64bit_dma(host)) |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 4169 | host->flags |= SDHCI_USE_64_BIT_DMA; |
| 4170 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 4171 | if (host->use_external_dma) { |
| 4172 | ret = sdhci_external_dma_init(host); |
| 4173 | if (ret == -EPROBE_DEFER) |
| 4174 | goto unreg; |
| 4175 | /* |
| 4176 | * Fall back to use the DMA/PIO integrated in standard SDHCI |
| 4177 | * instead of external DMA devices. |
| 4178 | */ |
| 4179 | else if (ret) |
| 4180 | sdhci_switch_external_dma(host, false); |
| 4181 | /* Disable internal DMA sources */ |
| 4182 | else |
| 4183 | host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
| 4184 | } |
| 4185 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4186 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Adrian Hunter | 4ee7dde | 2019-09-23 12:08:09 +0200 | [diff] [blame] | 4187 | if (host->ops->set_dma_mask) |
| 4188 | ret = host->ops->set_dma_mask(host); |
| 4189 | else |
| 4190 | ret = sdhci_set_dma_mask(host); |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 4191 | |
| 4192 | if (!ret && host->ops->enable_dma) |
| 4193 | ret = host->ops->enable_dma(host); |
| 4194 | |
| 4195 | if (ret) { |
| 4196 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
| 4197 | mmc_hostname(mmc)); |
| 4198 | host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
| 4199 | |
| 4200 | ret = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4201 | } |
| 4202 | } |
| 4203 | |
Chunyan Zhang | 917a0c5 | 2018-08-30 16:21:39 +0800 | [diff] [blame] | 4204 | /* SDMA does not support 64-bit DMA if v4 mode not set */ |
| 4205 | if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 4206 | host->flags &= ~SDHCI_USE_SDMA; |
| 4207 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4208 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4209 | dma_addr_t dma; |
| 4210 | void *buf; |
| 4211 | |
Veerabhadrarao Badiganti | a663f64 | 2020-01-20 20:08:38 +0530 | [diff] [blame] | 4212 | if (!(host->flags & SDHCI_USE_64_BIT_DMA)) |
| 4213 | host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
| 4214 | else if (!host->alloc_desc_sz) |
| 4215 | host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); |
| 4216 | |
| 4217 | host->desc_sz = host->alloc_desc_sz; |
| 4218 | host->adma_table_sz = host->adma_table_cnt * host->desc_sz; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4219 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 4220 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
Chunyan Zhang | 685e444 | 2018-08-30 16:21:40 +0800 | [diff] [blame] | 4221 | /* |
| 4222 | * Use zalloc to zero the reserved high 32-bits of 128-bit |
| 4223 | * descriptors so that they never need to be written. |
| 4224 | */ |
Luis Chamberlain | 750afb0 | 2019-01-04 09:23:09 +0100 | [diff] [blame] | 4225 | buf = dma_alloc_coherent(mmc_dev(mmc), |
| 4226 | host->align_buffer_sz + host->adma_table_sz, |
| 4227 | &dma, GFP_KERNEL); |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4228 | if (!buf) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 4229 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4230 | mmc_hostname(mmc)); |
| 4231 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4232 | } else if ((dma + host->align_buffer_sz) & |
| 4233 | (SDHCI_ADMA2_DESC_ALIGN - 1)) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 4234 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
| 4235 | mmc_hostname(mmc)); |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 4236 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4237 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 4238 | host->adma_table_sz, buf, dma); |
| 4239 | } else { |
| 4240 | host->align_buffer = buf; |
| 4241 | host->align_addr = dma; |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 4242 | |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4243 | host->adma_table = buf + host->align_buffer_sz; |
| 4244 | host->adma_addr = dma + host->align_buffer_sz; |
| 4245 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4246 | } |
| 4247 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 4248 | /* |
| 4249 | * If we use DMA, then it's up to the caller to set the DMA |
| 4250 | * mask, but PIO does not need the hw shim so we set a new |
| 4251 | * mask here in that case. |
| 4252 | */ |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4253 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 4254 | host->dma_mask = DMA_BIT_MASK(64); |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 4255 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 4256 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4257 | |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 4258 | if (host->version >= SDHCI_SPEC_300) |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4259 | host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps); |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 4260 | else |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4261 | host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps); |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 4262 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4263 | host->max_clk *= 1000000; |
Anton Vorontsov | f27f47e | 2010-05-26 14:41:53 -0700 | [diff] [blame] | 4264 | if (host->max_clk == 0 || host->quirks & |
| 4265 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 4266 | if (!host->ops->get_max_clock) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 4267 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
| 4268 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4269 | ret = -ENODEV; |
| 4270 | goto undma; |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 4271 | } |
| 4272 | host->max_clk = host->ops->get_max_clock(host); |
| 4273 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4274 | |
| 4275 | /* |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 4276 | * In case of Host Controller v3.00, find out whether clock |
| 4277 | * multiplier is supported. |
| 4278 | */ |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4279 | host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 4280 | |
| 4281 | /* |
| 4282 | * In case the value in Clock Multiplier is 0, then programmable |
| 4283 | * clock mode is not supported, otherwise the actual clock |
| 4284 | * multiplier is one more than the value of Clock Multiplier |
| 4285 | * in the Capabilities Register. |
| 4286 | */ |
| 4287 | if (host->clk_mul) |
| 4288 | host->clk_mul += 1; |
| 4289 | |
| 4290 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4291 | * Set host parameters. |
| 4292 | */ |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 4293 | max_clk = host->max_clk; |
| 4294 | |
Marek Szyprowski | ce5f036 | 2010-08-10 18:01:56 -0700 | [diff] [blame] | 4295 | if (host->ops->get_min_clock) |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 4296 | mmc->f_min = host->ops->get_min_clock(host); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 4297 | else if (host->version >= SDHCI_SPEC_300) { |
Michał Mirosław | 2a187d0 | 2020-01-15 10:54:35 +0100 | [diff] [blame] | 4298 | if (host->clk_mul) |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 4299 | max_clk = host->max_clk * host->clk_mul; |
Michał Mirosław | 2a187d0 | 2020-01-15 10:54:35 +0100 | [diff] [blame] | 4300 | /* |
| 4301 | * Divided Clock Mode minimum clock rate is always less than |
| 4302 | * Programmable Clock Mode minimum clock rate. |
| 4303 | */ |
| 4304 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 4305 | } else |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 4306 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 4307 | |
Adrian Hunter | d310ae4 | 2016-04-12 14:25:07 +0300 | [diff] [blame] | 4308 | if (!mmc->f_max || mmc->f_max > max_clk) |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 4309 | mmc->f_max = max_clk; |
| 4310 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4311 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4312 | host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps); |
Shawn Lin | 8cc3528 | 2017-03-24 15:50:12 +0800 | [diff] [blame] | 4313 | |
| 4314 | if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) |
| 4315 | host->timeout_clk *= 1000; |
| 4316 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4317 | if (host->timeout_clk == 0) { |
Shawn Lin | 8cc3528 | 2017-03-24 15:50:12 +0800 | [diff] [blame] | 4318 | if (!host->ops->get_timeout_clock) { |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4319 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", |
| 4320 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4321 | ret = -ENODEV; |
| 4322 | goto undma; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4323 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 4324 | |
Shawn Lin | 8cc3528 | 2017-03-24 15:50:12 +0800 | [diff] [blame] | 4325 | host->timeout_clk = |
| 4326 | DIV_ROUND_UP(host->ops->get_timeout_clock(host), |
| 4327 | 1000); |
| 4328 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 4329 | |
Adrian Hunter | 9951362 | 2016-03-07 13:33:55 +0200 | [diff] [blame] | 4330 | if (override_timeout_clk) |
| 4331 | host->timeout_clk = override_timeout_clk; |
| 4332 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4333 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame] | 4334 | host->ops->get_max_timeout_count(host) : 1 << 27; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 4335 | mmc->max_busy_timeout /= host->timeout_clk; |
| 4336 | } |
Adrian Hunter | 58d1246 | 2011-06-28 17:16:03 +0300 | [diff] [blame] | 4337 | |
Adrian Hunter | a999fd9 | 2018-04-27 17:17:15 +0530 | [diff] [blame] | 4338 | if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && |
| 4339 | !host->ops->get_max_timeout_count) |
| 4340 | mmc->max_busy_timeout = 0; |
| 4341 | |
Ulf Hansson | 1be64c7 | 2020-05-08 13:29:02 +0200 | [diff] [blame] | 4342 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 4343 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 4344 | |
| 4345 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
| 4346 | host->flags |= SDHCI_AUTO_CMD12; |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 4347 | |
Chunyan Zhang | 7ed71a9 | 2018-08-30 16:21:43 +0800 | [diff] [blame] | 4348 | /* |
| 4349 | * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO. |
| 4350 | * For v4 mode, SDMA may use Auto-CMD23 as well. |
| 4351 | */ |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 4352 | if ((host->version >= SDHCI_SPEC_300) && |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 4353 | ((host->flags & SDHCI_USE_ADMA) || |
Chunyan Zhang | 7ed71a9 | 2018-08-30 16:21:43 +0800 | [diff] [blame] | 4354 | !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && |
Scott Branden | 3bfa6f0 | 2015-02-09 16:06:28 -0800 | [diff] [blame] | 4355 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 4356 | host->flags |= SDHCI_AUTO_CMD23; |
Adrian Hunter | f421865 | 2017-03-20 19:50:39 +0200 | [diff] [blame] | 4357 | DBG("Auto-CMD23 available\n"); |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 4358 | } else { |
Adrian Hunter | f421865 | 2017-03-20 19:50:39 +0200 | [diff] [blame] | 4359 | DBG("Auto-CMD23 unavailable\n"); |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 4360 | } |
| 4361 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 4362 | /* |
| 4363 | * A controller may support 8-bit width, but the board itself |
| 4364 | * might not have the pins brought out. Boards that support |
| 4365 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in |
| 4366 | * their platform code before calling sdhci_add_host(), and we |
| 4367 | * won't assume 8-bit width for hosts without that CAP. |
| 4368 | */ |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 4369 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 4370 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4371 | |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 4372 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
| 4373 | mmc->caps &= ~MMC_CAP_CMD23; |
| 4374 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4375 | if (host->caps & SDHCI_CAN_DO_HISPD) |
Zhangfei Gao | a29e7e1 | 2010-08-16 21:15:32 -0400 | [diff] [blame] | 4376 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 4377 | |
Jaehoon Chung | 176d1ed | 2010-09-27 09:42:20 +0100 | [diff] [blame] | 4378 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 4379 | mmc_card_is_removable(mmc) && |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 4380 | mmc_gpio_get_cd(host->mmc) < 0) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 4381 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 4382 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4383 | if (!IS_ERR(mmc->supply.vqmmc)) { |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4384 | if (enable_vqmmc) { |
| 4385 | ret = regulator_enable(mmc->supply.vqmmc); |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4386 | host->sdhci_core_to_disable_vqmmc = !ret; |
| 4387 | } |
Stefan Agner | 1b5190c | 2018-07-05 14:18:19 +0200 | [diff] [blame] | 4388 | |
| 4389 | /* If vqmmc provides no 1.8V signalling, then there's no UHS */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4390 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, |
| 4391 | 1950000)) |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4392 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | |
| 4393 | SDHCI_SUPPORT_SDR50 | |
| 4394 | SDHCI_SUPPORT_DDR50); |
Stefan Agner | 1b5190c | 2018-07-05 14:18:19 +0200 | [diff] [blame] | 4395 | |
| 4396 | /* In eMMC case vqmmc might be a fixed 1.8V regulator */ |
| 4397 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, |
| 4398 | 3600000)) |
| 4399 | host->flags &= ~SDHCI_SIGNALING_330; |
| 4400 | |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 4401 | if (ret) { |
| 4402 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", |
| 4403 | mmc_hostname(mmc), ret); |
Adrian Hunter | 4bb7431 | 2014-11-06 15:19:04 +0200 | [diff] [blame] | 4404 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 4405 | } |
Veerabhadrarao Badiganti | 3debc24 | 2020-07-09 18:43:25 +0530 | [diff] [blame] | 4406 | |
Kevin Liu | 8363c37 | 2012-11-17 17:55:51 -0500 | [diff] [blame] | 4407 | } |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 4408 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4409 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { |
| 4410 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 4411 | SDHCI_SUPPORT_DDR50); |
Kishon Vijay Abraham I | c16bc9a | 2018-04-27 17:17:14 +0530 | [diff] [blame] | 4412 | /* |
| 4413 | * The SDHCI controller in a SoC might support HS200/HS400 |
| 4414 | * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property), |
| 4415 | * but if the board is modeled such that the IO lines are not |
| 4416 | * connected to 1.8v then HS200/HS400 cannot be supported. |
| 4417 | * Disable HS200/HS400 if the board does not have 1.8v connected |
| 4418 | * to the IO lines. (Applicable for other modes in 1.8v) |
| 4419 | */ |
| 4420 | mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES); |
| 4421 | mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS); |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4422 | } |
Daniel Drake | 6a66180 | 2012-11-25 13:01:19 -0500 | [diff] [blame] | 4423 | |
Al Cooper | 4188bba | 2012-03-16 15:54:17 -0400 | [diff] [blame] | 4424 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4425 | if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 4426 | SDHCI_SUPPORT_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4427 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
| 4428 | |
| 4429 | /* SDR104 supports also implies SDR50 support */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4430 | if (host->caps1 & SDHCI_SUPPORT_SDR104) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4431 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 4432 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
| 4433 | * field can be promoted to support HS200. |
| 4434 | */ |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 4435 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
David Cohen | 13868bf | 2013-10-29 10:58:26 -0700 | [diff] [blame] | 4436 | mmc->caps2 |= MMC_CAP2_HS200; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4437 | } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4438 | mmc->caps |= MMC_CAP_UHS_SDR50; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4439 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4440 | |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 4441 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4442 | (host->caps1 & SDHCI_SUPPORT_HS400)) |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 4443 | mmc->caps2 |= MMC_CAP2_HS400; |
| 4444 | |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 4445 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
| 4446 | (IS_ERR(mmc->supply.vqmmc) || |
| 4447 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, |
| 4448 | 1300000))) |
| 4449 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; |
| 4450 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4451 | if ((host->caps1 & SDHCI_SUPPORT_DDR50) && |
| 4452 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4453 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 4454 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 4455 | /* Does the host need tuning for SDR50? */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4456 | if (host->caps1 & SDHCI_USE_SDR50_TUNING) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 4457 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; |
| 4458 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 4459 | /* Driver Type(s) (A, C, D) supported by the host */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4460 | if (host->caps1 & SDHCI_DRIVER_TYPE_A) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 4461 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4462 | if (host->caps1 & SDHCI_DRIVER_TYPE_C) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 4463 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4464 | if (host->caps1 & SDHCI_DRIVER_TYPE_D) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 4465 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; |
| 4466 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 4467 | /* Initial value for re-tuning timer count */ |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4468 | host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK, |
| 4469 | host->caps1); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 4470 | |
| 4471 | /* |
| 4472 | * In case Re-tuning Timer is not disabled, the actual value of |
| 4473 | * re-tuning timer will be 2 ^ (n - 1). |
| 4474 | */ |
| 4475 | if (host->tuning_count) |
| 4476 | host->tuning_count = 1 << (host->tuning_count - 1); |
| 4477 | |
| 4478 | /* Re-tuning mode supported by the Host Controller */ |
Masahiro Yamada | a8e809e | 2020-04-08 16:21:05 +0900 | [diff] [blame] | 4479 | host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 4480 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 4481 | ocr_avail = 0; |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 4482 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4483 | /* |
| 4484 | * According to SD Host Controller spec v3.00, if the Host System |
| 4485 | * can afford more than 150mA, Host Driver should set XPC to 1. Also |
| 4486 | * the value is meaningful only if Voltage Support in the Capabilities |
| 4487 | * register is set. The actual current value is 4 times the register |
| 4488 | * value. |
| 4489 | */ |
| 4490 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4491 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
Chuanxiao.Dong | ae90603 | 2014-08-01 14:00:13 +0800 | [diff] [blame] | 4492 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 4493 | if (curr > 0) { |
| 4494 | |
| 4495 | /* convert to SDHCI_MAX_CURRENT format */ |
| 4496 | curr = curr/1000; /* convert to mA */ |
| 4497 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; |
| 4498 | |
| 4499 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); |
| 4500 | max_current_caps = |
Masahiro Yamada | 804a65b | 2020-05-11 15:28:27 +0900 | [diff] [blame] | 4501 | FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) | |
| 4502 | FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) | |
| 4503 | FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 4504 | } |
| 4505 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4506 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4507 | if (host->caps & SDHCI_CAN_VDD_330) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 4508 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4509 | |
Masahiro Yamada | 804a65b | 2020-05-11 15:28:27 +0900 | [diff] [blame] | 4510 | mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK, |
| 4511 | max_current_caps) * |
| 4512 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4513 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4514 | if (host->caps & SDHCI_CAN_VDD_300) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 4515 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4516 | |
Masahiro Yamada | 804a65b | 2020-05-11 15:28:27 +0900 | [diff] [blame] | 4517 | mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK, |
| 4518 | max_current_caps) * |
| 4519 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4520 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4521 | if (host->caps & SDHCI_CAN_VDD_180) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 4522 | ocr_avail |= MMC_VDD_165_195; |
| 4523 | |
Masahiro Yamada | 804a65b | 2020-05-11 15:28:27 +0900 | [diff] [blame] | 4524 | mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK, |
| 4525 | max_current_caps) * |
| 4526 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 4527 | } |
| 4528 | |
Ulf Hansson | 5fd26c7 | 2015-06-05 11:40:08 +0200 | [diff] [blame] | 4529 | /* If OCR set by host, use it instead. */ |
| 4530 | if (host->ocr_mask) |
| 4531 | ocr_avail = host->ocr_mask; |
| 4532 | |
| 4533 | /* If OCR set by external regulators, give it highest prio. */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4534 | if (mmc->ocr_avail) |
Tim Kryger | 5222161 | 2014-06-25 00:25:34 -0700 | [diff] [blame] | 4535 | ocr_avail = mmc->ocr_avail; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4536 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 4537 | mmc->ocr_avail = ocr_avail; |
| 4538 | mmc->ocr_avail_sdio = ocr_avail; |
| 4539 | if (host->ocr_avail_sdio) |
| 4540 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; |
| 4541 | mmc->ocr_avail_sd = ocr_avail; |
| 4542 | if (host->ocr_avail_sd) |
| 4543 | mmc->ocr_avail_sd &= host->ocr_avail_sd; |
| 4544 | else /* normal SD controllers don't support 1.8V */ |
| 4545 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; |
| 4546 | mmc->ocr_avail_mmc = ocr_avail; |
| 4547 | if (host->ocr_avail_mmc) |
| 4548 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 4549 | |
| 4550 | if (mmc->ocr_avail == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 4551 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
| 4552 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4553 | ret = -ENODEV; |
| 4554 | goto unreg; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 4555 | } |
| 4556 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 4557 | if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | |
| 4558 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | |
| 4559 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || |
| 4560 | (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) |
| 4561 | host->flags |= SDHCI_SIGNALING_180; |
| 4562 | |
| 4563 | if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) |
| 4564 | host->flags |= SDHCI_SIGNALING_120; |
| 4565 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4566 | spin_lock_init(&host->lock); |
| 4567 | |
| 4568 | /* |
Adrian Hunter | ac00531 | 2014-12-05 19:25:28 +0200 | [diff] [blame] | 4569 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
| 4570 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this |
| 4571 | * is less anyway. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4572 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 4573 | mmc->max_req_size = 524288; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4574 | |
| 4575 | /* |
Ulf Hansson | 250dcd1 | 2017-11-27 11:28:50 +0100 | [diff] [blame] | 4576 | * Maximum number of segments. Depends on if the hardware |
| 4577 | * can do scatter/gather or not. |
| 4578 | */ |
| 4579 | if (host->flags & SDHCI_USE_ADMA) { |
| 4580 | mmc->max_segs = SDHCI_MAX_SEGS; |
| 4581 | } else if (host->flags & SDHCI_USE_SDMA) { |
| 4582 | mmc->max_segs = 1; |
| 4583 | if (swiotlb_max_segment()) { |
| 4584 | unsigned int max_req_size = (1 << IO_TLB_SHIFT) * |
| 4585 | IO_TLB_SEGSIZE; |
| 4586 | mmc->max_req_size = min(mmc->max_req_size, |
| 4587 | max_req_size); |
| 4588 | } |
| 4589 | } else { /* PIO */ |
| 4590 | mmc->max_segs = SDHCI_MAX_SEGS; |
| 4591 | } |
| 4592 | |
| 4593 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4594 | * Maximum segment size. Could be one segment with the maximum number |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4595 | * of bytes. When doing hardware scatter/gather, each entry cannot |
| 4596 | * be larger than 64 KiB though. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4597 | */ |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 4598 | if (host->flags & SDHCI_USE_ADMA) { |
| 4599 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) |
| 4600 | mmc->max_seg_size = 65535; |
| 4601 | else |
| 4602 | mmc->max_seg_size = 65536; |
| 4603 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4604 | mmc->max_seg_size = mmc->max_req_size; |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 4605 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4606 | |
| 4607 | /* |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 4608 | * Maximum block size. This varies from controller to controller and |
| 4609 | * is specified in the capabilities register. |
| 4610 | */ |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 4611 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
| 4612 | mmc->max_blk_size = 2; |
| 4613 | } else { |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 4614 | mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 4615 | SDHCI_MAX_BLOCK_SHIFT; |
| 4616 | if (mmc->max_blk_size >= 3) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 4617 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
| 4618 | mmc_hostname(mmc)); |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 4619 | mmc->max_blk_size = 0; |
| 4620 | } |
| 4621 | } |
| 4622 | |
| 4623 | mmc->max_blk_size = 512 << mmc->max_blk_size; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 4624 | |
| 4625 | /* |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 4626 | * Maximum block count. |
| 4627 | */ |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 4628 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 4629 | |
Chunyan Zhang | a68dd9a | 2018-10-25 10:12:36 +0800 | [diff] [blame] | 4630 | if (mmc->max_segs == 1) |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4631 | /* This may alter mmc->*_blk_* parameters */ |
Chunyan Zhang | a68dd9a | 2018-10-25 10:12:36 +0800 | [diff] [blame] | 4632 | sdhci_allocate_bounce_buffer(host); |
Linus Walleij | bd9b902 | 2018-01-29 00:44:53 +0100 | [diff] [blame] | 4633 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4634 | return 0; |
| 4635 | |
| 4636 | unreg: |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4637 | if (host->sdhci_core_to_disable_vqmmc) |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4638 | regulator_disable(mmc->supply.vqmmc); |
| 4639 | undma: |
| 4640 | if (host->align_buffer) |
| 4641 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 4642 | host->adma_table_sz, host->align_buffer, |
| 4643 | host->align_addr); |
| 4644 | host->adma_table = NULL; |
| 4645 | host->align_buffer = NULL; |
| 4646 | |
| 4647 | return ret; |
| 4648 | } |
| 4649 | EXPORT_SYMBOL_GPL(sdhci_setup_host); |
| 4650 | |
Adrian Hunter | 4180ffa | 2017-03-20 19:50:45 +0200 | [diff] [blame] | 4651 | void sdhci_cleanup_host(struct sdhci_host *host) |
| 4652 | { |
| 4653 | struct mmc_host *mmc = host->mmc; |
| 4654 | |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4655 | if (host->sdhci_core_to_disable_vqmmc) |
Adrian Hunter | 4180ffa | 2017-03-20 19:50:45 +0200 | [diff] [blame] | 4656 | regulator_disable(mmc->supply.vqmmc); |
| 4657 | |
| 4658 | if (host->align_buffer) |
| 4659 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 4660 | host->adma_table_sz, host->align_buffer, |
| 4661 | host->align_addr); |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 4662 | |
| 4663 | if (host->use_external_dma) |
| 4664 | sdhci_external_dma_release(host); |
| 4665 | |
Adrian Hunter | 4180ffa | 2017-03-20 19:50:45 +0200 | [diff] [blame] | 4666 | host->adma_table = NULL; |
| 4667 | host->align_buffer = NULL; |
| 4668 | } |
| 4669 | EXPORT_SYMBOL_GPL(sdhci_cleanup_host); |
| 4670 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4671 | int __sdhci_add_host(struct sdhci_host *host) |
| 4672 | { |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 4673 | unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4674 | struct mmc_host *mmc = host->mmc; |
| 4675 | int ret; |
| 4676 | |
Adrian Hunter | 2b17b8d | 2020-05-18 15:09:39 +0300 | [diff] [blame] | 4677 | if ((mmc->caps2 & MMC_CAP2_CQE) && |
| 4678 | (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) { |
| 4679 | mmc->caps2 &= ~MMC_CAP2_CQE; |
| 4680 | mmc->cqe_ops = NULL; |
| 4681 | } |
| 4682 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 4683 | host->complete_wq = alloc_workqueue("sdhci", flags, 0); |
| 4684 | if (!host->complete_wq) |
| 4685 | return -ENOMEM; |
| 4686 | |
| 4687 | INIT_WORK(&host->complete_work, sdhci_complete_work); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4688 | |
Kees Cook | 2ee4f62 | 2017-10-24 08:03:45 -0700 | [diff] [blame] | 4689 | timer_setup(&host->timer, sdhci_timeout_timer, 0); |
| 4690 | timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4691 | |
Adrian Hunter | 250fb7b4 | 2014-12-05 19:41:10 +0200 | [diff] [blame] | 4692 | init_waitqueue_head(&host->buf_ready_int); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 4693 | |
Shawn Guo | 2af502c | 2013-07-05 14:38:55 +0800 | [diff] [blame] | 4694 | sdhci_init(host, 0); |
| 4695 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 4696 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
| 4697 | IRQF_SHARED, mmc_hostname(mmc), host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 4698 | if (ret) { |
| 4699 | pr_err("%s: Failed to request IRQ %d: %d\n", |
| 4700 | mmc_hostname(mmc), host->irq, ret); |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 4701 | goto unwq; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 4702 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4703 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 4704 | ret = sdhci_led_register(host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 4705 | if (ret) { |
| 4706 | pr_err("%s: Failed to register LED device: %d\n", |
| 4707 | mmc_hostname(mmc), ret); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4708 | goto unirq; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 4709 | } |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 4710 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4711 | ret = mmc_add_host(mmc); |
| 4712 | if (ret) |
| 4713 | goto unled; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4714 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 4715 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
Kay Sievers | d1b2686 | 2008-11-08 21:37:46 +0100 | [diff] [blame] | 4716 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 4717 | host->use_external_dma ? "External DMA" : |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 4718 | (host->flags & SDHCI_USE_ADMA) ? |
| 4719 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 4720 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4721 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 4722 | sdhci_enable_card_detection(host); |
| 4723 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4724 | return 0; |
| 4725 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4726 | unled: |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 4727 | sdhci_led_unregister(host); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 4728 | unirq: |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 4729 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 4730 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 4731 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 4732 | free_irq(host->irq, host); |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 4733 | unwq: |
| 4734 | destroy_workqueue(host->complete_wq); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4735 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4736 | return ret; |
| 4737 | } |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4738 | EXPORT_SYMBOL_GPL(__sdhci_add_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4739 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4740 | int sdhci_add_host(struct sdhci_host *host) |
| 4741 | { |
| 4742 | int ret; |
| 4743 | |
| 4744 | ret = sdhci_setup_host(host); |
| 4745 | if (ret) |
| 4746 | return ret; |
| 4747 | |
Adrian Hunter | 4180ffa | 2017-03-20 19:50:45 +0200 | [diff] [blame] | 4748 | ret = __sdhci_add_host(host); |
| 4749 | if (ret) |
| 4750 | goto cleanup; |
| 4751 | |
| 4752 | return 0; |
| 4753 | |
| 4754 | cleanup: |
| 4755 | sdhci_cleanup_host(host); |
| 4756 | |
| 4757 | return ret; |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 4758 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4759 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
| 4760 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 4761 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4762 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4763 | struct mmc_host *mmc = host->mmc; |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 4764 | unsigned long flags; |
| 4765 | |
| 4766 | if (dead) { |
| 4767 | spin_lock_irqsave(&host->lock, flags); |
| 4768 | |
| 4769 | host->flags |= SDHCI_DEVICE_DEAD; |
| 4770 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 4771 | if (sdhci_has_requests(host)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 4772 | pr_err("%s: Controller removed during " |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 4773 | " transfer!\n", mmc_hostname(mmc)); |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 4774 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 4775 | } |
| 4776 | |
| 4777 | spin_unlock_irqrestore(&host->lock, flags); |
| 4778 | } |
| 4779 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 4780 | sdhci_disable_card_detection(host); |
| 4781 | |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 4782 | mmc_remove_host(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4783 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 4784 | sdhci_led_unregister(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 4785 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 4786 | if (!dead) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 4787 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4788 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 4789 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 4790 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4791 | free_irq(host->irq, host); |
| 4792 | |
| 4793 | del_timer_sync(&host->timer); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 4794 | del_timer_sync(&host->data_timer); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4795 | |
Adrian Hunter | c07a48c | 2019-04-05 15:40:20 +0300 | [diff] [blame] | 4796 | destroy_workqueue(host->complete_wq); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4797 | |
Vijay Viswanath | 0fcb031 | 2020-06-23 19:04:46 +0530 | [diff] [blame] | 4798 | if (host->sdhci_core_to_disable_vqmmc) |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 4799 | regulator_disable(mmc->supply.vqmmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 4800 | |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 4801 | if (host->align_buffer) |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 4802 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 4803 | host->adma_table_sz, host->align_buffer, |
| 4804 | host->align_addr); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4805 | |
Chunyan Zhang | 18e762e | 2020-01-16 16:21:47 +0530 | [diff] [blame] | 4806 | if (host->use_external_dma) |
| 4807 | sdhci_external_dma_release(host); |
| 4808 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 4809 | host->adma_table = NULL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 4810 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4811 | } |
| 4812 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4813 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
| 4814 | |
| 4815 | void sdhci_free_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4816 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4817 | mmc_free_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4818 | } |
| 4819 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4820 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4821 | |
| 4822 | /*****************************************************************************\ |
| 4823 | * * |
| 4824 | * Driver init/exit * |
| 4825 | * * |
| 4826 | \*****************************************************************************/ |
| 4827 | |
| 4828 | static int __init sdhci_drv_init(void) |
| 4829 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 4830 | pr_info(DRIVER_NAME |
Pierre Ossman | 52fbf9c | 2007-02-09 08:23:41 +0100 | [diff] [blame] | 4831 | ": Secure Digital Host Controller Interface driver\n"); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 4832 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4833 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4834 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4835 | } |
| 4836 | |
| 4837 | static void __exit sdhci_drv_exit(void) |
| 4838 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4839 | } |
| 4840 | |
| 4841 | module_init(sdhci_drv_init); |
| 4842 | module_exit(sdhci_drv_exit); |
| 4843 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 4844 | module_param(debug_quirks, uint, 0444); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 4845 | module_param(debug_quirks2, uint, 0444); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 4846 | |
Pierre Ossman | 32710e8 | 2009-04-08 20:14:54 +0200 | [diff] [blame] | 4847 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 4848 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 4849 | MODULE_LICENSE("GPL"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 4850 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 4851 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 4852 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |