blob: 592a55a34b58eba8163d5277faecc880460f76f7 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Pierre Ossmand129bce2006-03-24 03:18:17 -08002/*
Pierre Ossman70f10482007-07-11 20:04:50 +02003 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
Pierre Ossmand129bce2006-03-24 03:18:17 -08004 *
Pierre Ossmanb69c9052008-03-08 23:44:25 +01005 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
Pierre Ossmand129bce2006-03-24 03:18:17 -08006 *
Pierre Ossman84c46a52007-12-02 19:58:16 +01007 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
Pierre Ossmand129bce2006-03-24 03:18:17 -080010 */
11
Masahiro Yamadafa091012020-03-12 20:00:50 +090012#include <linux/bitfield.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080013#include <linux/delay.h>
Chunyan Zhang18e762e2020-01-16 16:21:47 +053014#include <linux/dmaengine.h>
Adrian Hunter5a436cc2017-03-20 19:50:31 +020015#include <linux/ktime.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080016#include <linux/highmem.h>
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +010017#include <linux/io.h>
Paul Gortmaker88b47672011-07-03 15:15:51 -040018#include <linux/module.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080019#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090020#include <linux/slab.h>
Ralf Baechle11763602007-10-23 20:42:11 +020021#include <linux/scatterlist.h>
Linus Walleijbd9b9022018-01-29 00:44:53 +010022#include <linux/sizes.h>
Ulf Hansson250dcd12017-11-27 11:28:50 +010023#include <linux/swiotlb.h>
Marek Szyprowski9bea3c82010-08-10 18:01:59 -070024#include <linux/regulator/consumer.h>
Adrian Hunter66fd8ad2011-10-03 15:33:34 +030025#include <linux/pm_runtime.h>
Zach Brown92e0c442016-11-02 10:26:16 -050026#include <linux/of.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080027
Pierre Ossman2f730fe2008-03-17 10:29:38 +010028#include <linux/leds.h>
29
Aries Lee22113ef2010-12-15 08:14:24 +010030#include <linux/mmc/mmc.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080031#include <linux/mmc/host.h>
Aaron Lu473b0952012-07-03 17:27:49 +080032#include <linux/mmc/card.h>
Corneliu Doban85cc1c32015-02-09 16:06:29 -080033#include <linux/mmc/sdio.h>
Guennadi Liakhovetskibec9d4e2012-09-17 16:45:10 +080034#include <linux/mmc/slot-gpio.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080035
Pierre Ossmand129bce2006-03-24 03:18:17 -080036#include "sdhci.h"
37
38#define DRIVER_NAME "sdhci"
Pierre Ossmand129bce2006-03-24 03:18:17 -080039
Pierre Ossmand129bce2006-03-24 03:18:17 -080040#define DBG(f, x...) \
Adrian Hunterf4218652017-03-20 19:50:39 +020041 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
Pierre Ossmand129bce2006-03-24 03:18:17 -080042
Adrian Hunter85ad90e2017-03-20 19:50:42 +020043#define SDHCI_DUMP(f, x...) \
44 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
45
Arindam Nathb513ea22011-05-05 12:19:04 +053046#define MAX_TUNING_LOOP 40
47
Pierre Ossmandf673b22006-06-30 02:22:31 -070048static unsigned int debug_quirks = 0;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +030049static unsigned int debug_quirks2;
Pierre Ossman67435272006-06-30 02:22:31 -070050
Kevin Liu52983382013-01-31 11:31:37 +080051static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
Pierre Ossmand129bce2006-03-24 03:18:17 -080052
Adrian Hunter845c9392020-04-12 12:03:49 +030053static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
Adrian Huntera374a722020-04-12 12:03:46 +030054
Adrian Hunterd2898172017-03-20 19:50:43 +020055void sdhci_dumpregs(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -080056{
Adrian Hunter85ad90e2017-03-20 19:50:42 +020057 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -080058
Adrian Hunter85ad90e2017-03-20 19:50:42 +020059 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
60 sdhci_readl(host, SDHCI_DMA_ADDRESS),
61 sdhci_readw(host, SDHCI_HOST_VERSION));
62 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
63 sdhci_readw(host, SDHCI_BLOCK_SIZE),
64 sdhci_readw(host, SDHCI_BLOCK_COUNT));
65 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
66 sdhci_readl(host, SDHCI_ARGUMENT),
67 sdhci_readw(host, SDHCI_TRANSFER_MODE));
68 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
69 sdhci_readl(host, SDHCI_PRESENT_STATE),
70 sdhci_readb(host, SDHCI_HOST_CONTROL));
71 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
72 sdhci_readb(host, SDHCI_POWER_CONTROL),
73 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
74 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
75 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
76 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
77 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
78 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
79 sdhci_readl(host, SDHCI_INT_STATUS));
80 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
81 sdhci_readl(host, SDHCI_INT_ENABLE),
82 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
Adrian Hunter869f8a62018-11-15 15:53:42 +020083 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
84 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
Adrian Hunter85ad90e2017-03-20 19:50:42 +020085 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
86 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
87 sdhci_readl(host, SDHCI_CAPABILITIES),
88 sdhci_readl(host, SDHCI_CAPABILITIES_1));
89 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
90 sdhci_readw(host, SDHCI_COMMAND),
91 sdhci_readl(host, SDHCI_MAX_CURRENT));
92 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
Adrian Hunter79623022017-03-20 19:50:40 +020093 sdhci_readl(host, SDHCI_RESPONSE),
94 sdhci_readl(host, SDHCI_RESPONSE + 4));
Adrian Hunter85ad90e2017-03-20 19:50:42 +020095 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
Adrian Hunter79623022017-03-20 19:50:40 +020096 sdhci_readl(host, SDHCI_RESPONSE + 8),
97 sdhci_readl(host, SDHCI_RESPONSE + 12));
Adrian Hunter85ad90e2017-03-20 19:50:42 +020098 SDHCI_DUMP("Host ctl2: 0x%08x\n",
99 sdhci_readw(host, SDHCI_HOST_CONTROL2));
Pierre Ossmand129bce2006-03-24 03:18:17 -0800100
Adrian Huntere57a5f62014-11-04 12:42:46 +0200101 if (host->flags & SDHCI_USE_ADMA) {
Adrian Hunter85ad90e2017-03-20 19:50:42 +0200102 if (host->flags & SDHCI_USE_64_BIT_DMA) {
103 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
104 sdhci_readl(host, SDHCI_ADMA_ERROR),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
106 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
107 } else {
108 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
109 sdhci_readl(host, SDHCI_ADMA_ERROR),
110 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
111 }
Adrian Huntere57a5f62014-11-04 12:42:46 +0200112 }
Ben Dooksbe3f4ae2009-06-08 23:33:52 +0100113
Sarthak Gargd1fe0762020-05-22 15:02:29 +0530114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
Adrian Hunter85ad90e2017-03-20 19:50:42 +0200117 SDHCI_DUMP("============================================\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800118}
Adrian Hunterd2898172017-03-20 19:50:43 +0200119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
Chunyan Zhangb3f80b42018-08-30 16:21:38 +0800127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
Sowjanya Komatineni97207c12018-12-13 12:34:06 -0800131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Chunyan Zhangb3f80b42018-08-30 16:21:38 +0800132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
Sowjanya Komatineni97207c12018-12-13 12:34:06 -0800136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
Chunyan Zhangb3f80b42018-08-30 16:21:38 +0800137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
Adrian Hunter56a590d2016-06-29 16:24:32 +0300150static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
154
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300155static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
156{
Russell King5b4f1f62014-04-25 12:57:02 +0100157 u32 present;
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300158
Adrian Hunterc79396c2011-12-27 15:48:42 +0200159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
Haibo Chene65bb382020-02-19 16:22:40 +0800160 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300161 return;
162
Russell King5b4f1f62014-04-25 12:57:02 +0100163 if (enable) {
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
Shawn Guod25928d2011-06-21 22:41:48 +0800166
Russell King5b4f1f62014-04-25 12:57:02 +0100167 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
168 SDHCI_INT_CARD_INSERT;
169 } else {
170 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
171 }
Russell Kingb537f942014-04-25 12:56:01 +0100172
173 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
174 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300175}
176
177static void sdhci_enable_card_detection(struct sdhci_host *host)
178{
179 sdhci_set_card_detection(host, true);
180}
181
182static void sdhci_disable_card_detection(struct sdhci_host *host)
183{
184 sdhci_set_card_detection(host, false);
185}
186
Ulf Hansson02d0b682016-04-11 15:32:41 +0200187static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
188{
189 if (host->bus_on)
190 return;
191 host->bus_on = true;
192 pm_runtime_get_noresume(host->mmc->parent);
193}
194
195static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
196{
197 if (!host->bus_on)
198 return;
199 host->bus_on = false;
200 pm_runtime_put_noidle(host->mmc->parent);
201}
202
Russell King03231f92014-04-25 12:57:12 +0100203void sdhci_reset(struct sdhci_host *host, u8 mask)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800204{
Adrian Hunter5a436cc2017-03-20 19:50:31 +0200205 ktime_t timeout;
Philip Rakity393c1a32011-01-21 11:26:40 -0800206
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300207 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800208
Adrian Hunterf0710a52013-05-06 12:17:32 +0300209 if (mask & SDHCI_RESET_ALL) {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800210 host->clock = 0;
Adrian Hunterf0710a52013-05-06 12:17:32 +0300211 /* Reset-all turns off SD Bus Power */
212 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
213 sdhci_runtime_pm_bus_off(host);
214 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800215
Pierre Ossmane16514d82006-06-30 02:22:24 -0700216 /* Wait max 100 ms */
Adrian Hunter5a436cc2017-03-20 19:50:31 +0200217 timeout = ktime_add_ms(ktime_get(), 100);
Pierre Ossmane16514d82006-06-30 02:22:24 -0700218
219 /* hw clears the bit when it's done */
Alek Dub7044412018-12-06 17:24:59 +0800220 while (1) {
221 bool timedout = ktime_after(ktime_get(), timeout);
222
223 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
224 break;
225 if (timedout) {
Girish K Sa3c76eb2011-10-11 11:44:09 +0530226 pr_err("%s: Reset 0x%x never completed.\n",
Pierre Ossmane16514d82006-06-30 02:22:24 -0700227 mmc_hostname(host->mmc), (int)mask);
228 sdhci_dumpregs(host);
229 return;
230 }
Adrian Hunter5a436cc2017-03-20 19:50:31 +0200231 udelay(10);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800232 }
Russell King03231f92014-04-25 12:57:12 +0100233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
Anton Vorontsov063a9db2009-03-17 00:14:02 +0300235
Russell King03231f92014-04-25 12:57:12 +0100236static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
Adrian Hunterd3940f22016-06-29 16:24:14 +0300239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
Russell King03231f92014-04-25 12:57:12 +0100242 return;
243 }
244
245 host->ops->reset(host, mask);
Philip Rakity393c1a32011-01-21 11:26:40 -0800246
Russell Kingda91a8f2014-04-25 13:00:12 +0100247 if (mask & SDHCI_RESET_ALL) {
248 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
249 if (host->ops->enable_dma)
250 host->ops->enable_dma(host);
251 }
252
253 /* Resetting the controller clears many */
254 host->preset_enabled = false;
Shaohui Xie3abc1e802011-12-29 16:33:00 +0800255 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800256}
257
Adrian Hunterf5c1ab82017-03-20 19:50:46 +0200258static void sdhci_set_default_irqs(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800259{
Russell Kingb537f942014-04-25 12:56:01 +0100260 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
261 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
262 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
263 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
264 SDHCI_INT_RESPONSE;
265
Dong Aishengf37b20e2016-07-12 15:46:17 +0800266 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
267 host->tuning_mode == SDHCI_TUNING_MODE_3)
268 host->ier |= SDHCI_INT_RETUNE;
269
Russell Kingb537f942014-04-25 12:56:01 +0100270 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
271 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Adrian Hunterf5c1ab82017-03-20 19:50:46 +0200272}
273
Chunyan Zhang685e4442018-08-30 16:21:40 +0800274static void sdhci_config_dma(struct sdhci_host *host)
275{
276 u8 ctrl;
277 u16 ctrl2;
278
279 if (host->version < SDHCI_SPEC_200)
280 return;
281
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283
284 /*
285 * Always adjust the DMA selection as some controllers
286 * (e.g. JMicron) can't do PIO properly when the selection
287 * is ADMA.
288 */
289 ctrl &= ~SDHCI_CTRL_DMA_MASK;
290 if (!(host->flags & SDHCI_REQ_USE_DMA))
291 goto out;
292
293 /* Note if DMA Select is zero then SDMA is selected */
294 if (host->flags & SDHCI_USE_ADMA)
295 ctrl |= SDHCI_CTRL_ADMA32;
296
297 if (host->flags & SDHCI_USE_64_BIT_DMA) {
298 /*
299 * If v4 mode, all supported DMA can be 64-bit addressing if
300 * controller supports 64-bit system address, otherwise only
301 * ADMA can support 64-bit addressing.
302 */
303 if (host->v4_mode) {
304 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
305 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
306 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
307 } else if (host->flags & SDHCI_USE_ADMA) {
308 /*
309 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
310 * set SDHCI_CTRL_ADMA64.
311 */
312 ctrl |= SDHCI_CTRL_ADMA64;
313 }
314 }
315
316out:
317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
318}
319
Adrian Hunterf5c1ab82017-03-20 19:50:46 +0200320static void sdhci_init(struct sdhci_host *host, int soft)
321{
322 struct mmc_host *mmc = host->mmc;
Haibo Chen49769d42020-04-15 17:00:55 +0800323 unsigned long flags;
Adrian Hunterf5c1ab82017-03-20 19:50:46 +0200324
325 if (soft)
326 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
327 else
328 sdhci_do_reset(host, SDHCI_RESET_ALL);
329
Chunyan Zhangb3f80b42018-08-30 16:21:38 +0800330 if (host->v4_mode)
331 sdhci_do_enable_v4_mode(host);
332
Haibo Chen49769d42020-04-15 17:00:55 +0800333 spin_lock_irqsave(&host->lock, flags);
Adrian Hunterf5c1ab82017-03-20 19:50:46 +0200334 sdhci_set_default_irqs(host);
Haibo Chen49769d42020-04-15 17:00:55 +0800335 spin_unlock_irqrestore(&host->lock, flags);
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800336
Adrian Hunterf12e39d2017-03-20 19:50:47 +0200337 host->cqe_on = false;
338
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800339 if (soft) {
340 /* force clock reconfiguration */
341 host->clock = 0;
Adrian Hunterd3940f22016-06-29 16:24:14 +0300342 mmc->ops->set_ios(mmc, &mmc->ios);
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800343 }
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300344}
Pierre Ossmand129bce2006-03-24 03:18:17 -0800345
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300346static void sdhci_reinit(struct sdhci_host *host)
347{
Raul E Rangeldcaac3f2019-09-04 10:46:24 -0600348 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
349
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800350 sdhci_init(host, 0);
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300351 sdhci_enable_card_detection(host);
Raul E Rangeldcaac3f2019-09-04 10:46:24 -0600352
353 /*
354 * A change to the card detect bits indicates a change in present state,
355 * refer sdhci_set_card_detection(). A card detect interrupt might have
356 * been missed while the host controller was being reset, so trigger a
357 * rescan to check.
358 */
359 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
360 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
Pierre Ossmand129bce2006-03-24 03:18:17 -0800361}
362
Adrian Hunter061d17a2016-04-12 14:25:09 +0300363static void __sdhci_led_activate(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800364{
365 u8 ctrl;
366
Adrian Hunterbd29f582018-12-11 15:10:42 +0200367 if (host->quirks & SDHCI_QUIRK_NO_LED)
368 return;
369
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800371 ctrl |= SDHCI_CTRL_LED;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300372 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800373}
374
Adrian Hunter061d17a2016-04-12 14:25:09 +0300375static void __sdhci_led_deactivate(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800376{
377 u8 ctrl;
378
Adrian Hunterbd29f582018-12-11 15:10:42 +0200379 if (host->quirks & SDHCI_QUIRK_NO_LED)
380 return;
381
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300382 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800383 ctrl &= ~SDHCI_CTRL_LED;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300384 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800385}
386
Masahiro Yamada4f782302016-04-14 13:19:39 +0900387#if IS_REACHABLE(CONFIG_LEDS_CLASS)
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100388static void sdhci_led_control(struct led_classdev *led,
Adrian Hunter061d17a2016-04-12 14:25:09 +0300389 enum led_brightness brightness)
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100390{
391 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
392 unsigned long flags;
393
394 spin_lock_irqsave(&host->lock, flags);
395
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300396 if (host->runtime_suspended)
397 goto out;
398
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100399 if (brightness == LED_OFF)
Adrian Hunter061d17a2016-04-12 14:25:09 +0300400 __sdhci_led_deactivate(host);
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100401 else
Adrian Hunter061d17a2016-04-12 14:25:09 +0300402 __sdhci_led_activate(host);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300403out:
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100404 spin_unlock_irqrestore(&host->lock, flags);
405}
Adrian Hunter061d17a2016-04-12 14:25:09 +0300406
407static int sdhci_led_register(struct sdhci_host *host)
408{
409 struct mmc_host *mmc = host->mmc;
410
Adrian Hunterbd29f582018-12-11 15:10:42 +0200411 if (host->quirks & SDHCI_QUIRK_NO_LED)
412 return 0;
413
Adrian Hunter061d17a2016-04-12 14:25:09 +0300414 snprintf(host->led_name, sizeof(host->led_name),
415 "%s::", mmc_hostname(mmc));
416
417 host->led.name = host->led_name;
418 host->led.brightness = LED_OFF;
419 host->led.default_trigger = mmc_hostname(mmc);
420 host->led.brightness_set = sdhci_led_control;
421
422 return led_classdev_register(mmc_dev(mmc), &host->led);
423}
424
425static void sdhci_led_unregister(struct sdhci_host *host)
426{
Adrian Hunterbd29f582018-12-11 15:10:42 +0200427 if (host->quirks & SDHCI_QUIRK_NO_LED)
428 return;
429
Adrian Hunter061d17a2016-04-12 14:25:09 +0300430 led_classdev_unregister(&host->led);
431}
432
433static inline void sdhci_led_activate(struct sdhci_host *host)
434{
435}
436
437static inline void sdhci_led_deactivate(struct sdhci_host *host)
438{
439}
440
441#else
442
443static inline int sdhci_led_register(struct sdhci_host *host)
444{
445 return 0;
446}
447
448static inline void sdhci_led_unregister(struct sdhci_host *host)
449{
450}
451
452static inline void sdhci_led_activate(struct sdhci_host *host)
453{
454 __sdhci_led_activate(host);
455}
456
457static inline void sdhci_led_deactivate(struct sdhci_host *host)
458{
459 __sdhci_led_deactivate(host);
460}
461
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100462#endif
463
Adrian Hunter97a1aba2019-04-05 15:40:17 +0300464static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
465 unsigned long timeout)
466{
467 if (sdhci_data_line_cmd(mrq->cmd))
468 mod_timer(&host->data_timer, timeout);
469 else
470 mod_timer(&host->timer, timeout);
471}
472
473static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
474{
475 if (sdhci_data_line_cmd(mrq->cmd))
476 del_timer(&host->data_timer);
477 else
478 del_timer(&host->timer);
479}
480
481static inline bool sdhci_has_requests(struct sdhci_host *host)
482{
483 return host->cmd || host->data_cmd;
484}
485
Pierre Ossmand129bce2006-03-24 03:18:17 -0800486/*****************************************************************************\
487 * *
488 * Core functions *
489 * *
490\*****************************************************************************/
491
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100492static void sdhci_read_block_pio(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800493{
Pierre Ossman76591502008-07-21 00:32:11 +0200494 unsigned long flags;
495 size_t blksize, len, chunk;
Kees Cook3f649ab2020-06-03 13:09:38 -0700496 u32 scratch;
Pierre Ossman76591502008-07-21 00:32:11 +0200497 u8 *buf;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800498
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100499 DBG("PIO reading\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800500
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100501 blksize = host->data->blksz;
Pierre Ossman76591502008-07-21 00:32:11 +0200502 chunk = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800503
Pierre Ossman76591502008-07-21 00:32:11 +0200504 local_irq_save(flags);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800505
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100506 while (blksize) {
Fabio Estevambf3a35a2015-05-09 18:44:51 -0300507 BUG_ON(!sg_miter_next(&host->sg_miter));
Pierre Ossmand129bce2006-03-24 03:18:17 -0800508
Pierre Ossman76591502008-07-21 00:32:11 +0200509 len = min(host->sg_miter.length, blksize);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800510
Pierre Ossman76591502008-07-21 00:32:11 +0200511 blksize -= len;
512 host->sg_miter.consumed = len;
Alex Dubov14d836e2007-04-13 19:04:38 +0200513
Pierre Ossman76591502008-07-21 00:32:11 +0200514 buf = host->sg_miter.addr;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800515
Pierre Ossman76591502008-07-21 00:32:11 +0200516 while (len) {
517 if (chunk == 0) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300518 scratch = sdhci_readl(host, SDHCI_BUFFER);
Pierre Ossman76591502008-07-21 00:32:11 +0200519 chunk = 4;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800520 }
Pierre Ossman76591502008-07-21 00:32:11 +0200521
522 *buf = scratch & 0xFF;
523
524 buf++;
525 scratch >>= 8;
526 chunk--;
527 len--;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800528 }
529 }
Pierre Ossman76591502008-07-21 00:32:11 +0200530
531 sg_miter_stop(&host->sg_miter);
532
533 local_irq_restore(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100534}
Pierre Ossmand129bce2006-03-24 03:18:17 -0800535
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100536static void sdhci_write_block_pio(struct sdhci_host *host)
537{
Pierre Ossman76591502008-07-21 00:32:11 +0200538 unsigned long flags;
539 size_t blksize, len, chunk;
540 u32 scratch;
541 u8 *buf;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100542
543 DBG("PIO writing\n");
544
545 blksize = host->data->blksz;
Pierre Ossman76591502008-07-21 00:32:11 +0200546 chunk = 0;
547 scratch = 0;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100548
Pierre Ossman76591502008-07-21 00:32:11 +0200549 local_irq_save(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100550
551 while (blksize) {
Fabio Estevambf3a35a2015-05-09 18:44:51 -0300552 BUG_ON(!sg_miter_next(&host->sg_miter));
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100553
Pierre Ossman76591502008-07-21 00:32:11 +0200554 len = min(host->sg_miter.length, blksize);
Alex Dubov14d836e2007-04-13 19:04:38 +0200555
Pierre Ossman76591502008-07-21 00:32:11 +0200556 blksize -= len;
557 host->sg_miter.consumed = len;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100558
Pierre Ossman76591502008-07-21 00:32:11 +0200559 buf = host->sg_miter.addr;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100560
Pierre Ossman76591502008-07-21 00:32:11 +0200561 while (len) {
562 scratch |= (u32)*buf << (chunk * 8);
563
564 buf++;
565 chunk++;
566 len--;
567
568 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300569 sdhci_writel(host, scratch, SDHCI_BUFFER);
Pierre Ossman76591502008-07-21 00:32:11 +0200570 chunk = 0;
571 scratch = 0;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100572 }
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100573 }
574 }
Pierre Ossman76591502008-07-21 00:32:11 +0200575
576 sg_miter_stop(&host->sg_miter);
577
578 local_irq_restore(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100579}
580
581static void sdhci_transfer_pio(struct sdhci_host *host)
582{
583 u32 mask;
584
Pierre Ossman76591502008-07-21 00:32:11 +0200585 if (host->blocks == 0)
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100586 return;
587
588 if (host->data->flags & MMC_DATA_READ)
589 mask = SDHCI_DATA_AVAILABLE;
590 else
591 mask = SDHCI_SPACE_AVAILABLE;
592
Pierre Ossman4a3cba32008-07-29 00:11:16 +0200593 /*
594 * Some controllers (JMicron JMB38x) mess up the buffer bits
595 * for transfers < 4 bytes. As long as it is just one block,
596 * we can ignore the bits.
597 */
598 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
599 (host->data->blocks == 1))
600 mask = ~0;
601
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300602 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Anton Vorontsov3e3bf202009-03-17 00:14:00 +0300603 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
604 udelay(100);
605
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100606 if (host->data->flags & MMC_DATA_READ)
607 sdhci_read_block_pio(host);
608 else
609 sdhci_write_block_pio(host);
610
Pierre Ossman76591502008-07-21 00:32:11 +0200611 host->blocks--;
612 if (host->blocks == 0)
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100613 break;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100614 }
615
616 DBG("PIO transfer complete.\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800617}
618
Russell King48857d92016-01-26 13:40:16 +0000619static int sdhci_pre_dma_transfer(struct sdhci_host *host,
Russell Kingc0999b72016-01-26 13:40:27 +0000620 struct mmc_data *data, int cookie)
Russell King48857d92016-01-26 13:40:16 +0000621{
622 int sg_count;
623
Russell King94538e52016-01-26 13:40:37 +0000624 /*
625 * If the data buffers are already mapped, return the previous
626 * dma_map_sg() result.
627 */
628 if (data->host_cookie == COOKIE_PRE_MAPPED)
Russell King48857d92016-01-26 13:40:16 +0000629 return data->sg_count;
Russell King48857d92016-01-26 13:40:16 +0000630
Linus Walleijbd9b9022018-01-29 00:44:53 +0100631 /* Bounce write requests to the bounce buffer */
632 if (host->bounce_buffer) {
633 unsigned int length = data->blksz * data->blocks;
634
635 if (length > host->bounce_buffer_size) {
636 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
637 mmc_hostname(host->mmc), length,
638 host->bounce_buffer_size);
639 return -EIO;
640 }
641 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
642 /* Copy the data to the bounce buffer */
Angelo Dureghelloe93577e2020-05-18 21:17:40 +0200643 if (host->ops->copy_to_bounce_buffer) {
644 host->ops->copy_to_bounce_buffer(host,
645 data, length);
646 } else {
647 sg_copy_to_buffer(data->sg, data->sg_len,
648 host->bounce_buffer, length);
649 }
Linus Walleijbd9b9022018-01-29 00:44:53 +0100650 }
651 /* Switch ownership to the DMA */
652 dma_sync_single_for_device(host->mmc->parent,
653 host->bounce_addr,
654 host->bounce_buffer_size,
655 mmc_get_dma_dir(data));
656 /* Just a dummy value */
657 sg_count = 1;
658 } else {
659 /* Just access the data directly from memory */
660 sg_count = dma_map_sg(mmc_dev(host->mmc),
661 data->sg, data->sg_len,
662 mmc_get_dma_dir(data));
663 }
Russell King48857d92016-01-26 13:40:16 +0000664
665 if (sg_count == 0)
666 return -ENOSPC;
667
668 data->sg_count = sg_count;
Russell Kingc0999b72016-01-26 13:40:27 +0000669 data->host_cookie = cookie;
Russell King48857d92016-01-26 13:40:16 +0000670
671 return sg_count;
672}
673
Pierre Ossman2134a922008-06-28 18:28:51 +0200674static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
675{
676 local_irq_save(*flags);
Cong Wang482fce92011-11-27 13:27:00 +0800677 return kmap_atomic(sg_page(sg)) + sg->offset;
Pierre Ossman2134a922008-06-28 18:28:51 +0200678}
679
680static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
681{
Cong Wang482fce92011-11-27 13:27:00 +0800682 kunmap_atomic(buffer);
Pierre Ossman2134a922008-06-28 18:28:51 +0200683 local_irq_restore(*flags);
684}
685
Jisheng Zhang54552e42018-08-28 17:47:23 +0800686void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
687 dma_addr_t addr, int len, unsigned int cmd)
Ben Dooks118cd172010-03-05 13:43:26 -0800688{
Jisheng Zhang54552e42018-08-28 17:47:23 +0800689 struct sdhci_adma2_64_desc *dma_desc = *desc;
Ben Dooks118cd172010-03-05 13:43:26 -0800690
Adrian Huntere57a5f62014-11-04 12:42:46 +0200691 /* 32-bit and 64-bit descriptors have these members in same position */
Adrian Hunter05452302014-11-04 12:42:45 +0200692 dma_desc->cmd = cpu_to_le16(cmd);
693 dma_desc->len = cpu_to_le16(len);
Masahiro Yamada38eee2e2019-08-29 20:22:06 +0900694 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
Adrian Huntere57a5f62014-11-04 12:42:46 +0200695
696 if (host->flags & SDHCI_USE_64_BIT_DMA)
Masahiro Yamada38eee2e2019-08-29 20:22:06 +0900697 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
Jisheng Zhang54552e42018-08-28 17:47:23 +0800698
699 *desc += host->desc_sz;
700}
701EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
702
703static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
704 void **desc, dma_addr_t addr,
705 int len, unsigned int cmd)
706{
707 if (host->ops->adma_write_desc)
708 host->ops->adma_write_desc(host, desc, addr, len, cmd);
Jisheng Zhang07be55b2018-09-17 13:30:41 +0800709 else
710 sdhci_adma_write_desc(host, desc, addr, len, cmd);
Ben Dooks118cd172010-03-05 13:43:26 -0800711}
712
Adrian Hunterb5ffa672014-11-04 12:42:40 +0200713static void sdhci_adma_mark_end(void *desc)
714{
Adrian Huntere57a5f62014-11-04 12:42:46 +0200715 struct sdhci_adma2_64_desc *dma_desc = desc;
Adrian Hunterb5ffa672014-11-04 12:42:40 +0200716
Adrian Huntere57a5f62014-11-04 12:42:46 +0200717 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
Adrian Hunter05452302014-11-04 12:42:45 +0200718 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
Adrian Hunterb5ffa672014-11-04 12:42:40 +0200719}
720
Russell King60c64762016-01-26 13:40:22 +0000721static void sdhci_adma_table_pre(struct sdhci_host *host,
722 struct mmc_data *data, int sg_count)
Pierre Ossman2134a922008-06-28 18:28:51 +0200723{
Pierre Ossman2134a922008-06-28 18:28:51 +0200724 struct scatterlist *sg;
Pierre Ossman2134a922008-06-28 18:28:51 +0200725 unsigned long flags;
Russell Kingacc3ad12016-01-26 13:40:00 +0000726 dma_addr_t addr, align_addr;
727 void *desc, *align;
728 char *buffer;
729 int len, offset, i;
Pierre Ossman2134a922008-06-28 18:28:51 +0200730
731 /*
732 * The spec does not specify endianness of descriptor table.
733 * We currently guess that it is LE.
734 */
735
Russell King60c64762016-01-26 13:40:22 +0000736 host->sg_count = sg_count;
Pierre Ossman2134a922008-06-28 18:28:51 +0200737
Adrian Hunter4efaa6f2014-11-04 12:42:39 +0200738 desc = host->adma_table;
Pierre Ossman2134a922008-06-28 18:28:51 +0200739 align = host->align_buffer;
740
741 align_addr = host->align_addr;
742
743 for_each_sg(data->sg, sg, host->sg_count, i) {
744 addr = sg_dma_address(sg);
745 len = sg_dma_len(sg);
746
747 /*
Russell Kingacc3ad12016-01-26 13:40:00 +0000748 * The SDHCI specification states that ADMA addresses must
749 * be 32-bit aligned. If they aren't, then we use a bounce
750 * buffer for the (up to three) bytes that screw up the
Pierre Ossman2134a922008-06-28 18:28:51 +0200751 * alignment.
752 */
Adrian Hunter04a5ae62015-11-26 14:00:49 +0200753 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
754 SDHCI_ADMA2_MASK;
Pierre Ossman2134a922008-06-28 18:28:51 +0200755 if (offset) {
756 if (data->flags & MMC_DATA_WRITE) {
757 buffer = sdhci_kmap_atomic(sg, &flags);
758 memcpy(align, buffer, offset);
759 sdhci_kunmap_atomic(buffer, &flags);
760 }
761
Ben Dooks118cd172010-03-05 13:43:26 -0800762 /* tran, valid */
Jisheng Zhang54552e42018-08-28 17:47:23 +0800763 __sdhci_adma_write_desc(host, &desc, align_addr,
764 offset, ADMA2_TRAN_VALID);
Pierre Ossman2134a922008-06-28 18:28:51 +0200765
766 BUG_ON(offset > 65536);
767
Adrian Hunter04a5ae62015-11-26 14:00:49 +0200768 align += SDHCI_ADMA2_ALIGN;
769 align_addr += SDHCI_ADMA2_ALIGN;
Pierre Ossman2134a922008-06-28 18:28:51 +0200770
Pierre Ossman2134a922008-06-28 18:28:51 +0200771 addr += offset;
772 len -= offset;
773 }
774
Pierre Ossman2134a922008-06-28 18:28:51 +0200775 BUG_ON(len > 65536);
776
Jisheng Zhang54552e42018-08-28 17:47:23 +0800777 /* tran, valid */
778 if (len)
779 __sdhci_adma_write_desc(host, &desc, addr, len,
780 ADMA2_TRAN_VALID);
Pierre Ossman2134a922008-06-28 18:28:51 +0200781
782 /*
783 * If this triggers then we have a calculation bug
784 * somewhere. :/
785 */
Adrian Hunter76fe3792014-11-04 12:42:42 +0200786 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
Pierre Ossman2134a922008-06-28 18:28:51 +0200787 }
788
Thomas Abraham70764a92010-05-26 14:42:04 -0700789 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
Russell Kingacc3ad12016-01-26 13:40:00 +0000790 /* Mark the last descriptor as the terminating descriptor */
Adrian Hunter4efaa6f2014-11-04 12:42:39 +0200791 if (desc != host->adma_table) {
Adrian Hunter76fe3792014-11-04 12:42:42 +0200792 desc -= host->desc_sz;
Adrian Hunterb5ffa672014-11-04 12:42:40 +0200793 sdhci_adma_mark_end(desc);
Thomas Abraham70764a92010-05-26 14:42:04 -0700794 }
795 } else {
Russell Kingacc3ad12016-01-26 13:40:00 +0000796 /* Add a terminating entry - nop, end, valid */
Jisheng Zhang54552e42018-08-28 17:47:23 +0800797 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
Thomas Abraham70764a92010-05-26 14:42:04 -0700798 }
Pierre Ossman2134a922008-06-28 18:28:51 +0200799}
800
801static void sdhci_adma_table_post(struct sdhci_host *host,
802 struct mmc_data *data)
803{
Pierre Ossman2134a922008-06-28 18:28:51 +0200804 struct scatterlist *sg;
805 int i, size;
Adrian Hunter1c3d5f62014-11-04 12:42:41 +0200806 void *align;
Pierre Ossman2134a922008-06-28 18:28:51 +0200807 char *buffer;
808 unsigned long flags;
809
Russell King47fa9612016-01-26 13:40:06 +0000810 if (data->flags & MMC_DATA_READ) {
811 bool has_unaligned = false;
Russell Kingde0b65a2014-04-25 12:58:29 +0100812
Russell King47fa9612016-01-26 13:40:06 +0000813 /* Do a quick scan of the SG list for any unaligned mappings */
814 for_each_sg(data->sg, sg, host->sg_count, i)
Adrian Hunter04a5ae62015-11-26 14:00:49 +0200815 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
Russell King47fa9612016-01-26 13:40:06 +0000816 has_unaligned = true;
817 break;
818 }
Pierre Ossman2134a922008-06-28 18:28:51 +0200819
Russell King47fa9612016-01-26 13:40:06 +0000820 if (has_unaligned) {
821 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
Russell Kingf55c98f2016-01-26 13:40:11 +0000822 data->sg_len, DMA_FROM_DEVICE);
Pierre Ossman2134a922008-06-28 18:28:51 +0200823
Russell King47fa9612016-01-26 13:40:06 +0000824 align = host->align_buffer;
825
826 for_each_sg(data->sg, sg, host->sg_count, i) {
827 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
828 size = SDHCI_ADMA2_ALIGN -
829 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
830
831 buffer = sdhci_kmap_atomic(sg, &flags);
832 memcpy(buffer, align, size);
833 sdhci_kunmap_atomic(buffer, &flags);
834
835 align += SDHCI_ADMA2_ALIGN;
836 }
Pierre Ossman2134a922008-06-28 18:28:51 +0200837 }
838 }
839 }
Pierre Ossman2134a922008-06-28 18:28:51 +0200840}
841
Masahiro Yamada38eee2e2019-08-29 20:22:06 +0900842static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
843{
844 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
845 if (host->flags & SDHCI_USE_64_BIT_DMA)
846 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
847}
848
Chunyan Zhang917a0c52018-08-30 16:21:39 +0800849static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
Linus Walleijbd9b9022018-01-29 00:44:53 +0100850{
851 if (host->bounce_buffer)
852 return host->bounce_addr;
853 else
854 return sg_dma_address(host->data->sg);
855}
856
Chunyan Zhang917a0c52018-08-30 16:21:39 +0800857static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
858{
Masahiro Yamada38eee2e2019-08-29 20:22:06 +0900859 if (host->v4_mode)
860 sdhci_set_adma_addr(host, addr);
861 else
Chunyan Zhang917a0c52018-08-30 16:21:39 +0800862 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
Chunyan Zhang917a0c52018-08-30 16:21:39 +0800863}
864
Adrian Hunter0bb28d72018-04-27 17:17:16 +0530865static unsigned int sdhci_target_timeout(struct sdhci_host *host,
866 struct mmc_command *cmd,
867 struct mmc_data *data)
868{
869 unsigned int target_timeout;
870
871 /* timeout in us */
872 if (!data) {
873 target_timeout = cmd->busy_timeout * 1000;
874 } else {
875 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
876 if (host->clock && data->timeout_clks) {
877 unsigned long long val;
878
879 /*
880 * data->timeout_clks is in units of clock cycles.
881 * host->clock is in Hz. target_timeout is in us.
882 * Hence, us = 1000000 * cycles / Hz. Round up.
883 */
884 val = 1000000ULL * data->timeout_clks;
885 if (do_div(val, host->clock))
886 target_timeout++;
887 target_timeout += val;
888 }
889 }
890
891 return target_timeout;
892}
893
Kishon Vijay Abraham Ifc1fa1b2018-04-27 17:17:17 +0530894static void sdhci_calc_sw_timeout(struct sdhci_host *host,
895 struct mmc_command *cmd)
896{
897 struct mmc_data *data = cmd->data;
898 struct mmc_host *mmc = host->mmc;
899 struct mmc_ios *ios = &mmc->ios;
900 unsigned char bus_width = 1 << ios->bus_width;
901 unsigned int blksz;
902 unsigned int freq;
903 u64 target_timeout;
904 u64 transfer_time;
905
906 target_timeout = sdhci_target_timeout(host, cmd, data);
907 target_timeout *= NSEC_PER_USEC;
908
909 if (data) {
910 blksz = data->blksz;
911 freq = host->mmc->actual_clock ? : host->clock;
912 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
913 do_div(transfer_time, freq);
914 /* multiply by '2' to account for any unknowns */
915 transfer_time = transfer_time * 2;
916 /* calculate timeout for the entire data */
917 host->data_timeout = data->blocks * target_timeout +
918 transfer_time;
919 } else {
920 host->data_timeout = target_timeout;
921 }
922
923 if (host->data_timeout)
924 host->data_timeout += MMC_CMD_TRANSFER_TIME;
925}
926
Adrian Huntera999fd92018-04-27 17:17:15 +0530927static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
928 bool *too_big)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800929{
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700930 u8 count;
BOUGH CHEN401059d2019-01-07 10:11:36 +0000931 struct mmc_data *data;
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700932 unsigned target_timeout, current_timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800933
Adrian Huntera999fd92018-04-27 17:17:15 +0530934 *too_big = true;
935
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200936 /*
937 * If the host controller provides us with an incorrect timeout
938 * value, just skip the check and use 0xE. The hardware may take
939 * longer to time out, but that's much better than having a too-short
940 * timeout value.
941 */
Pierre Ossman11a2f1b2009-06-21 20:59:33 +0200942 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200943 return 0xE;
Pierre Ossmane538fbe2007-08-12 16:46:32 +0200944
BOUGH CHEN401059d2019-01-07 10:11:36 +0000945 /* Unspecified command, asume max */
946 if (cmd == NULL)
947 return 0xE;
948
949 data = cmd->data;
Andrei Warkentina3c77782011-04-11 16:13:42 -0500950 /* Unspecified timeout, assume max */
Ulf Hansson1d4d7742014-01-08 15:06:08 +0100951 if (!data && !cmd->busy_timeout)
Andrei Warkentina3c77782011-04-11 16:13:42 -0500952 return 0xE;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800953
Andrei Warkentina3c77782011-04-11 16:13:42 -0500954 /* timeout in us */
Adrian Hunter0bb28d72018-04-27 17:17:16 +0530955 target_timeout = sdhci_target_timeout(host, cmd, data);
Anton Vorontsov81b39802009-09-22 16:45:13 -0700956
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700957 /*
958 * Figure out needed cycles.
959 * We do this in steps in order to fit inside a 32 bit int.
960 * The first step is the minimum timeout, which will have a
961 * minimum resolution of 6 bits:
962 * (1) 2^13*1000 > 2^22,
963 * (2) host->timeout_clk < 2^16
964 * =>
965 * (1) / (2) > 2^6
966 */
967 count = 0;
968 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
969 while (current_timeout < target_timeout) {
970 count++;
971 current_timeout <<= 1;
972 if (count >= 0xF)
973 break;
974 }
975
976 if (count >= 0xF) {
Adrian Huntera999fd92018-04-27 17:17:15 +0530977 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
978 DBG("Too large timeout 0x%x requested for CMD%d!\n",
979 count, cmd->opcode);
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700980 count = 0xE;
Adrian Huntera999fd92018-04-27 17:17:15 +0530981 } else {
982 *too_big = false;
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700983 }
984
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200985 return count;
986}
987
Anton Vorontsov6aa943a2009-03-17 00:13:50 +0300988static void sdhci_set_transfer_irqs(struct sdhci_host *host)
989{
990 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
991 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
992
993 if (host->flags & SDHCI_REQ_USE_DMA)
Russell Kingb537f942014-04-25 12:56:01 +0100994 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
Anton Vorontsov6aa943a2009-03-17 00:13:50 +0300995 else
Russell Kingb537f942014-04-25 12:56:01 +0100996 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
997
Adrian Hunteraf849c82018-11-15 15:53:43 +0200998 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
999 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1000 else
1001 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1002
Russell Kingb537f942014-04-25 12:56:01 +01001003 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1004 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Anton Vorontsov6aa943a2009-03-17 00:13:50 +03001005}
1006
Faiz Abbas7907ebe2020-01-16 16:21:49 +05301007void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
Adrian Huntera999fd92018-04-27 17:17:15 +05301008{
1009 if (enable)
1010 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1011 else
1012 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1013 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1014 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1015}
Faiz Abbas7907ebe2020-01-16 16:21:49 +05301016EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
Adrian Huntera999fd92018-04-27 17:17:15 +05301017
Faiz Abbas7d76ed72020-01-16 16:21:50 +05301018void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1019{
1020 bool too_big = false;
1021 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1022
1023 if (too_big &&
1024 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1025 sdhci_calc_sw_timeout(host, cmd);
1026 sdhci_set_data_timeout_irq(host, false);
1027 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1028 sdhci_set_data_timeout_irq(host, true);
1029 }
1030
1031 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1032}
1033EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1034
Aisheng Dongb45e6682014-08-27 15:26:29 +08001035static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
Pierre Ossmanee53ab52008-07-05 00:25:15 +02001036{
Faiz Abbas7d76ed72020-01-16 16:21:50 +05301037 if (host->ops->set_timeout)
Aisheng Dongb45e6682014-08-27 15:26:29 +08001038 host->ops->set_timeout(host, cmd);
Faiz Abbas7d76ed72020-01-16 16:21:50 +05301039 else
1040 __sdhci_set_timeout(host, cmd);
Aisheng Dongb45e6682014-08-27 15:26:29 +08001041}
1042
Faiz Abbas15db1832020-01-16 16:21:46 +05301043static void sdhci_initialize_data(struct sdhci_host *host,
1044 struct mmc_data *data)
Aisheng Dongb45e6682014-08-27 15:26:29 +08001045{
Adrian Hunter43dea092016-06-29 16:24:26 +03001046 WARN_ON(host->data);
1047
Pierre Ossmanee53ab52008-07-05 00:25:15 +02001048 /* Sanity checks */
1049 BUG_ON(data->blksz * data->blocks > 524288);
1050 BUG_ON(data->blksz > host->mmc->max_blk_size);
1051 BUG_ON(data->blocks > 65535);
1052
1053 host->data = data;
1054 host->data_early = 0;
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04001055 host->data->bytes_xfered = 0;
Faiz Abbas15db1832020-01-16 16:21:46 +05301056}
1057
1058static inline void sdhci_set_block_info(struct sdhci_host *host,
1059 struct mmc_data *data)
1060{
1061 /* Set the DMA boundary value and block size */
1062 sdhci_writew(host,
1063 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1064 SDHCI_BLOCK_SIZE);
1065 /*
1066 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1067 * can be supported, in that case 16-bit block count register must be 0.
1068 */
1069 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1070 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1071 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1072 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1073 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1074 } else {
1075 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1076 }
1077}
1078
1079static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1080{
1081 struct mmc_data *data = cmd->data;
1082
1083 sdhci_initialize_data(host, data);
Pierre Ossmanee53ab52008-07-05 00:25:15 +02001084
Russell Kingfce14422016-01-26 13:41:20 +00001085 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
Pierre Ossman2134a922008-06-28 18:28:51 +02001086 struct scatterlist *sg;
Russell Kingdf953922016-01-26 13:41:14 +00001087 unsigned int length_mask, offset_mask;
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001088 int i;
Pierre Ossman2134a922008-06-28 18:28:51 +02001089
Russell Kingfce14422016-01-26 13:41:20 +00001090 host->flags |= SDHCI_REQ_USE_DMA;
1091
1092 /*
1093 * FIXME: This doesn't account for merging when mapping the
1094 * scatterlist.
1095 *
1096 * The assumption here being that alignment and lengths are
1097 * the same after DMA mapping to device address space.
1098 */
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001099 length_mask = 0;
Russell Kingdf953922016-01-26 13:41:14 +00001100 offset_mask = 0;
Pierre Ossman2134a922008-06-28 18:28:51 +02001101 if (host->flags & SDHCI_USE_ADMA) {
Russell Kingdf953922016-01-26 13:41:14 +00001102 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001103 length_mask = 3;
Russell Kingdf953922016-01-26 13:41:14 +00001104 /*
1105 * As we use up to 3 byte chunks to work
1106 * around alignment problems, we need to
1107 * check the offset as well.
1108 */
1109 offset_mask = 3;
1110 }
Pierre Ossman2134a922008-06-28 18:28:51 +02001111 } else {
1112 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001113 length_mask = 3;
Russell Kingdf953922016-01-26 13:41:14 +00001114 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1115 offset_mask = 3;
Pierre Ossman2134a922008-06-28 18:28:51 +02001116 }
1117
Russell Kingdf953922016-01-26 13:41:14 +00001118 if (unlikely(length_mask | offset_mask)) {
Pierre Ossman2134a922008-06-28 18:28:51 +02001119 for_each_sg(data->sg, sg, data->sg_len, i) {
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001120 if (sg->length & length_mask) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01001121 DBG("Reverting to PIO because of transfer size (%d)\n",
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001122 sg->length);
Pierre Ossman2134a922008-06-28 18:28:51 +02001123 host->flags &= ~SDHCI_REQ_USE_DMA;
1124 break;
1125 }
Russell Kinga0eaf0f2016-01-26 13:41:09 +00001126 if (sg->offset & offset_mask) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01001127 DBG("Reverting to PIO because of bad alignment\n");
Pierre Ossman2134a922008-06-28 18:28:51 +02001128 host->flags &= ~SDHCI_REQ_USE_DMA;
1129 break;
1130 }
1131 }
1132 }
1133 }
1134
Pierre Ossman8f1934c2008-06-30 21:15:49 +02001135 if (host->flags & SDHCI_REQ_USE_DMA) {
Russell Kingc0999b72016-01-26 13:40:27 +00001136 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
Pierre Ossman8f1934c2008-06-30 21:15:49 +02001137
Russell King60c64762016-01-26 13:40:22 +00001138 if (sg_cnt <= 0) {
1139 /*
1140 * This only happens when someone fed
1141 * us an invalid request.
1142 */
1143 WARN_ON(1);
1144 host->flags &= ~SDHCI_REQ_USE_DMA;
1145 } else if (host->flags & SDHCI_USE_ADMA) {
1146 sdhci_adma_table_pre(host, data, sg_cnt);
Masahiro Yamada38eee2e2019-08-29 20:22:06 +09001147 sdhci_set_adma_addr(host, host->adma_addr);
Russell King60c64762016-01-26 13:40:22 +00001148 } else {
1149 WARN_ON(sg_cnt != 1);
Chunyan Zhang917a0c52018-08-30 16:21:39 +08001150 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
Pierre Ossman8f1934c2008-06-30 21:15:49 +02001151 }
1152 }
1153
Chunyan Zhang685e4442018-08-30 16:21:40 +08001154 sdhci_config_dma(host);
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +01001155
Pierre Ossman8f1934c2008-06-30 21:15:49 +02001156 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
Sebastian Andrzej Siewiorda60a912009-06-18 09:33:32 +02001157 int flags;
1158
1159 flags = SG_MITER_ATOMIC;
1160 if (host->data->flags & MMC_DATA_READ)
1161 flags |= SG_MITER_TO_SG;
1162 else
1163 flags |= SG_MITER_FROM_SG;
1164 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
Pierre Ossman76591502008-07-21 00:32:11 +02001165 host->blocks = data->blocks;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001166 }
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001167
Anton Vorontsov6aa943a2009-03-17 00:13:50 +03001168 sdhci_set_transfer_irqs(host);
1169
Faiz Abbas15db1832020-01-16 16:21:46 +05301170 sdhci_set_block_info(host, data);
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001171}
1172
Chunyan Zhang18e762e2020-01-16 16:21:47 +05301173#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1174
1175static int sdhci_external_dma_init(struct sdhci_host *host)
1176{
1177 int ret = 0;
1178 struct mmc_host *mmc = host->mmc;
1179
1180 host->tx_chan = dma_request_chan(mmc->parent, "tx");
1181 if (IS_ERR(host->tx_chan)) {
1182 ret = PTR_ERR(host->tx_chan);
1183 if (ret != -EPROBE_DEFER)
1184 pr_warn("Failed to request TX DMA channel.\n");
1185 host->tx_chan = NULL;
1186 return ret;
1187 }
1188
1189 host->rx_chan = dma_request_chan(mmc->parent, "rx");
1190 if (IS_ERR(host->rx_chan)) {
1191 if (host->tx_chan) {
1192 dma_release_channel(host->tx_chan);
1193 host->tx_chan = NULL;
1194 }
1195
1196 ret = PTR_ERR(host->rx_chan);
1197 if (ret != -EPROBE_DEFER)
1198 pr_warn("Failed to request RX DMA channel.\n");
1199 host->rx_chan = NULL;
1200 }
1201
1202 return ret;
1203}
1204
1205static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1206 struct mmc_data *data)
1207{
1208 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1209}
1210
1211static int sdhci_external_dma_setup(struct sdhci_host *host,
1212 struct mmc_command *cmd)
1213{
1214 int ret, i;
Chunyan Zhang1215c022020-01-20 11:32:23 +08001215 enum dma_transfer_direction dir;
Chunyan Zhang18e762e2020-01-16 16:21:47 +05301216 struct dma_async_tx_descriptor *desc;
1217 struct mmc_data *data = cmd->data;
1218 struct dma_chan *chan;
1219 struct dma_slave_config cfg;
1220 dma_cookie_t cookie;
1221 int sg_cnt;
1222
1223 if (!host->mapbase)
1224 return -EINVAL;
1225
1226 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230 cfg.src_maxburst = data->blksz / 4;
1231 cfg.dst_maxburst = data->blksz / 4;
1232
1233 /* Sanity check: all the SG entries must be aligned by block size. */
1234 for (i = 0; i < data->sg_len; i++) {
1235 if ((data->sg + i)->length % data->blksz)
1236 return -EINVAL;
1237 }
1238
1239 chan = sdhci_external_dma_channel(host, data);
1240
1241 ret = dmaengine_slave_config(chan, &cfg);
1242 if (ret)
1243 return ret;
1244
1245 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246 if (sg_cnt <= 0)
1247 return -EINVAL;
1248
Chunyan Zhang1215c022020-01-20 11:32:23 +08001249 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
Chunyan Zhang18e762e2020-01-16 16:21:47 +05301251 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252 if (!desc)
1253 return -EINVAL;
1254
1255 desc->callback = NULL;
1256 desc->callback_param = NULL;
1257
1258 cookie = dmaengine_submit(desc);
1259 if (dma_submit_error(cookie))
1260 ret = cookie;
1261
1262 return ret;
1263}
1264
1265static void sdhci_external_dma_release(struct sdhci_host *host)
1266{
1267 if (host->tx_chan) {
1268 dma_release_channel(host->tx_chan);
1269 host->tx_chan = NULL;
1270 }
1271
1272 if (host->rx_chan) {
1273 dma_release_channel(host->rx_chan);
1274 host->rx_chan = NULL;
1275 }
1276
1277 sdhci_switch_external_dma(host, false);
1278}
1279
1280static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281 struct mmc_command *cmd)
1282{
1283 struct mmc_data *data = cmd->data;
1284
1285 sdhci_initialize_data(host, data);
1286
1287 host->flags |= SDHCI_REQ_USE_DMA;
1288 sdhci_set_transfer_irqs(host);
1289
1290 sdhci_set_block_info(host, data);
1291}
1292
1293static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294 struct mmc_command *cmd)
1295{
1296 if (!sdhci_external_dma_setup(host, cmd)) {
1297 __sdhci_external_dma_prepare_data(host, cmd);
1298 } else {
1299 sdhci_external_dma_release(host);
1300 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301 mmc_hostname(host->mmc));
1302 sdhci_prepare_data(host, cmd);
1303 }
1304}
1305
1306static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307 struct mmc_command *cmd)
1308{
1309 struct dma_chan *chan;
1310
1311 if (!cmd->data)
1312 return;
1313
1314 chan = sdhci_external_dma_channel(host, cmd->data);
1315 if (chan)
1316 dma_async_issue_pending(chan);
1317}
1318
1319#else
1320
1321static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322{
1323 return -EOPNOTSUPP;
1324}
1325
1326static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327{
1328}
1329
1330static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331 struct mmc_command *cmd)
1332{
1333 /* This should never happen */
1334 WARN_ON_ONCE(1);
1335}
1336
1337static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338 struct mmc_command *cmd)
1339{
1340}
1341
1342static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343 struct mmc_data *data)
1344{
1345 return NULL;
1346}
1347
1348#endif
1349
1350void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351{
1352 host->use_external_dma = en;
1353}
1354EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
Adrian Hunter0293d502016-06-29 16:24:35 +03001356static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357 struct mmc_request *mrq)
1358{
Adrian Hunter20845be2016-08-16 13:44:13 +03001359 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360 !mrq->cap_cmd_during_tfr;
Adrian Hunter0293d502016-06-29 16:24:35 +03001361}
1362
Adrian Huntered633032020-04-12 12:03:45 +03001363static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364 struct mmc_request *mrq)
1365{
1366 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367}
1368
1369static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370 struct mmc_request *mrq)
1371{
1372 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373}
1374
Chunyan Zhang427b6512018-08-30 16:21:42 +08001375static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376 struct mmc_command *cmd,
1377 u16 *mode)
1378{
1379 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380 (cmd->opcode != SD_IO_RW_EXTENDED);
Adrian Huntered633032020-04-12 12:03:45 +03001381 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
Chunyan Zhang427b6512018-08-30 16:21:42 +08001382 u16 ctrl2;
1383
1384 /*
1385 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386 * Select' is recommended rather than use of 'Auto CMD12
1387 * Enable' or 'Auto CMD23 Enable'.
1388 */
1389 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1390 *mode |= SDHCI_TRNS_AUTO_SEL;
1391
1392 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1393 if (use_cmd23)
1394 ctrl2 |= SDHCI_CMD23_ENABLE;
1395 else
1396 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1397 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1398
1399 return;
1400 }
1401
1402 /*
1403 * If we are sending CMD23, CMD12 never gets sent
1404 * on successful completion (so no Auto-CMD12).
1405 */
1406 if (use_cmd12)
1407 *mode |= SDHCI_TRNS_AUTO_CMD12;
1408 else if (use_cmd23)
1409 *mode |= SDHCI_TRNS_AUTO_CMD23;
1410}
1411
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001412static void sdhci_set_transfer_mode(struct sdhci_host *host,
Andrei Warkentine89d4562011-05-23 15:06:37 -05001413 struct mmc_command *cmd)
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001414{
Vincent Yangd3fc5d72015-01-20 16:05:17 +08001415 u16 mode = 0;
Andrei Warkentine89d4562011-05-23 15:06:37 -05001416 struct mmc_data *data = cmd->data;
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001417
Dong Aisheng2b558c12013-10-30 22:09:48 +08001418 if (data == NULL) {
Vincent Wan9b8ffea2014-11-05 14:09:00 +08001419 if (host->quirks2 &
1420 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
ernest.zhang0086fc22018-07-16 14:26:54 +08001421 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1422 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1423 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
Vincent Wan9b8ffea2014-11-05 14:09:00 +08001424 } else {
Dong Aisheng2b558c12013-10-30 22:09:48 +08001425 /* clear Auto CMD settings for no data CMDs */
Vincent Wan9b8ffea2014-11-05 14:09:00 +08001426 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1427 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
Dong Aisheng2b558c12013-10-30 22:09:48 +08001428 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
Vincent Wan9b8ffea2014-11-05 14:09:00 +08001429 }
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001430 return;
Dong Aisheng2b558c12013-10-30 22:09:48 +08001431 }
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001432
Pierre Ossmane538fbe2007-08-12 16:46:32 +02001433 WARN_ON(!host->data);
1434
Vincent Yangd3fc5d72015-01-20 16:05:17 +08001435 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1436 mode = SDHCI_TRNS_BLK_CNT_EN;
1437
Andrei Warkentine89d4562011-05-23 15:06:37 -05001438 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
Vincent Yangd3fc5d72015-01-20 16:05:17 +08001439 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
Chunyan Zhang427b6512018-08-30 16:21:42 +08001440 sdhci_auto_cmd_select(host, cmd, &mode);
Adrian Huntered633032020-04-12 12:03:45 +03001441 if (sdhci_auto_cmd23(host, cmd->mrq))
Adrian Huntera4c73ab2016-06-29 16:24:25 +03001442 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
Jerry Huangc4512f72010-08-10 18:01:59 -07001443 }
Andrei Warkentin8edf63712011-05-23 15:06:39 -05001444
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001445 if (data->flags & MMC_DATA_READ)
1446 mode |= SDHCI_TRNS_READ;
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +01001447 if (host->flags & SDHCI_REQ_USE_DMA)
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001448 mode |= SDHCI_TRNS_DMA;
1449
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001450 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001451}
1452
Adrian Hunter0cc563c2016-06-29 16:24:28 +03001453static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1454{
1455 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1456 ((mrq->cmd && mrq->cmd->error) ||
1457 (mrq->sbc && mrq->sbc->error) ||
Adrian Hunter4bf78092018-11-15 15:53:41 +02001458 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
Adrian Hunter0cc563c2016-06-29 16:24:28 +03001459 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1460}
1461
Faiz Abbas15db1832020-01-16 16:21:46 +05301462static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03001463{
1464 int i;
1465
1466 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1467 if (host->mrqs_done[i] == mrq) {
1468 WARN_ON(1);
1469 return;
1470 }
1471 }
1472
1473 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1474 if (!host->mrqs_done[i]) {
1475 host->mrqs_done[i] = mrq;
1476 break;
1477 }
1478 }
1479
1480 WARN_ON(i >= SDHCI_MAX_MRQS);
Faiz Abbas15db1832020-01-16 16:21:46 +05301481}
1482
1483static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1484{
1485 if (host->cmd && host->cmd->mrq == mrq)
1486 host->cmd = NULL;
1487
1488 if (host->data_cmd && host->data_cmd->mrq == mrq)
1489 host->data_cmd = NULL;
1490
Adrian Hunter845c9392020-04-12 12:03:49 +03001491 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1492 host->deferred_cmd = NULL;
1493
Faiz Abbas15db1832020-01-16 16:21:46 +05301494 if (host->data && host->data->mrq == mrq)
1495 host->data = NULL;
1496
1497 if (sdhci_needs_reset(host, mrq))
1498 host->pending_reset = true;
1499
1500 sdhci_set_mrq_done(host, mrq);
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03001501
Adrian Huntere9a07292019-04-05 15:40:18 +03001502 sdhci_del_timer(host, mrq);
1503
1504 if (!sdhci_has_requests(host))
1505 sdhci_led_deactivate(host);
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03001506}
1507
Adrian Huntera6d3bdd2016-06-29 16:24:27 +03001508static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1509{
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03001510 __sdhci_finish_mrq(host, mrq);
Adrian Hunter2e72ab92019-04-05 15:40:16 +03001511
Adrian Hunterc07a48c2019-04-05 15:40:20 +03001512 queue_work(host->complete_wq, &host->complete_work);
Adrian Huntera6d3bdd2016-06-29 16:24:27 +03001513}
1514
Adrian Hunter845c9392020-04-12 12:03:49 +03001515static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001516{
Adrian Hunter33a57ad2016-06-29 16:24:36 +03001517 struct mmc_command *data_cmd = host->data_cmd;
1518 struct mmc_data *data = host->data;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001519
Pierre Ossmand129bce2006-03-24 03:18:17 -08001520 host->data = NULL;
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03001521 host->data_cmd = NULL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001522
Adrian Hunter4bf78092018-11-15 15:53:41 +02001523 /*
1524 * The controller needs a reset of internal state machines upon error
1525 * conditions.
1526 */
1527 if (data->error) {
1528 if (!host->cmd || host->cmd == data_cmd)
1529 sdhci_do_reset(host, SDHCI_RESET_CMD);
1530 sdhci_do_reset(host, SDHCI_RESET_DATA);
1531 }
1532
Russell Kingadd89132016-01-26 13:40:42 +00001533 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1534 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1535 sdhci_adma_table_post(host, data);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001536
1537 /*
Pierre Ossmanc9b74c52008-04-18 20:41:49 +02001538 * The specification states that the block count register must
1539 * be updated, but it does not specify at what point in the
1540 * data flow. That makes the register entirely useless to read
1541 * back so we have to assume that nothing made it to the card
1542 * in the event of an error.
Pierre Ossmand129bce2006-03-24 03:18:17 -08001543 */
Pierre Ossmanc9b74c52008-04-18 20:41:49 +02001544 if (data->error)
1545 data->bytes_xfered = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001546 else
Pierre Ossmanc9b74c52008-04-18 20:41:49 +02001547 data->bytes_xfered = data->blksz * data->blocks;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001548
Andrei Warkentine89d4562011-05-23 15:06:37 -05001549 /*
1550 * Need to send CMD12 if -
Yangbo Lufdbbe6c2019-11-14 19:18:14 +08001551 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
Andrei Warkentine89d4562011-05-23 15:06:37 -05001552 * b) error in multiblock transfer
1553 */
1554 if (data->stop &&
Yangbo Lufdbbe6c2019-11-14 19:18:14 +08001555 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1556 data->error)) {
Adrian Hunter20845be2016-08-16 13:44:13 +03001557 /*
1558 * 'cap_cmd_during_tfr' request must not use the command line
1559 * after mmc_command_done() has been called. It is upper layer's
1560 * responsibility to send the stop command if required.
1561 */
1562 if (data->mrq->cap_cmd_during_tfr) {
Adrian Hunter19d2f692019-04-05 15:40:19 +03001563 __sdhci_finish_mrq(host, data->mrq);
Adrian Hunter20845be2016-08-16 13:44:13 +03001564 } else {
1565 /* Avoid triggering warning in sdhci_send_command() */
1566 host->cmd = NULL;
Adrian Hunter845c9392020-04-12 12:03:49 +03001567 if (!sdhci_send_command(host, data->stop)) {
1568 if (sw_data_timeout) {
1569 /*
1570 * This is anyway a sw data timeout, so
1571 * give up now.
1572 */
1573 data->stop->error = -EIO;
1574 __sdhci_finish_mrq(host, data->mrq);
1575 } else {
1576 WARN_ON(host->deferred_cmd);
1577 host->deferred_cmd = data->stop;
1578 }
1579 }
Adrian Hunter20845be2016-08-16 13:44:13 +03001580 }
Adrian Huntera6d3bdd2016-06-29 16:24:27 +03001581 } else {
Adrian Hunter19d2f692019-04-05 15:40:19 +03001582 __sdhci_finish_mrq(host, data->mrq);
Adrian Huntera6d3bdd2016-06-29 16:24:27 +03001583 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001584}
1585
Adrian Hunter845c9392020-04-12 12:03:49 +03001586static void sdhci_finish_data(struct sdhci_host *host)
1587{
1588 __sdhci_finish_data(host, false);
1589}
1590
1591static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001592{
1593 int flags;
Pierre Ossmanfd2208d2006-06-30 02:22:28 -07001594 u32 mask;
Pierre Ossman7cb2c762006-06-30 02:22:23 -07001595 unsigned long timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001596
1597 WARN_ON(host->cmd);
1598
Russell King96776202016-01-26 13:39:34 +00001599 /* Initially, a command has no error */
1600 cmd->error = 0;
1601
Adrian Hunterfc605f12016-10-05 12:11:21 +03001602 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1603 cmd->opcode == MMC_STOP_TRANSMISSION)
1604 cmd->flags |= MMC_RSP_BUSY;
1605
Pierre Ossmanfd2208d2006-06-30 02:22:28 -07001606 mask = SDHCI_CMD_INHIBIT;
Adrian Hunter56a590d2016-06-29 16:24:32 +03001607 if (sdhci_data_line_cmd(cmd))
Pierre Ossmanfd2208d2006-06-30 02:22:28 -07001608 mask |= SDHCI_DATA_INHIBIT;
1609
1610 /* We shouldn't wait for data inihibit for stop commands, even
1611 though they might use busy signaling */
Adrian Huntera4c73ab2016-06-29 16:24:25 +03001612 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
Pierre Ossmanfd2208d2006-06-30 02:22:28 -07001613 mask &= ~SDHCI_DATA_INHIBIT;
1614
Adrian Hunter845c9392020-04-12 12:03:49 +03001615 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1616 return false;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001617
Pierre Ossmand129bce2006-03-24 03:18:17 -08001618 host->cmd = cmd;
Faiz Abbas15db1832020-01-16 16:21:46 +05301619 host->data_timeout = 0;
Adrian Hunter56a590d2016-06-29 16:24:32 +03001620 if (sdhci_data_line_cmd(cmd)) {
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03001621 WARN_ON(host->data_cmd);
1622 host->data_cmd = cmd;
Faiz Abbas15db1832020-01-16 16:21:46 +05301623 sdhci_set_timeout(host, cmd);
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03001624 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001625
Chunyan Zhang18e762e2020-01-16 16:21:47 +05301626 if (cmd->data) {
1627 if (host->use_external_dma)
1628 sdhci_external_dma_prepare_data(host, cmd);
1629 else
1630 sdhci_prepare_data(host, cmd);
1631 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001632
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001633 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001634
Andrei Warkentine89d4562011-05-23 15:06:37 -05001635 sdhci_set_transfer_mode(host, cmd);
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001636
Pierre Ossmand129bce2006-03-24 03:18:17 -08001637 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
Adrian Hunter845c9392020-04-12 12:03:49 +03001638 WARN_ONCE(1, "Unsupported response type!\n");
1639 /*
1640 * This does not happen in practice because 136-bit response
1641 * commands never have busy waiting, so rather than complicate
1642 * the error path, just remove busy waiting and continue.
1643 */
1644 cmd->flags &= ~MMC_RSP_BUSY;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001645 }
1646
1647 if (!(cmd->flags & MMC_RSP_PRESENT))
1648 flags = SDHCI_CMD_RESP_NONE;
1649 else if (cmd->flags & MMC_RSP_136)
1650 flags = SDHCI_CMD_RESP_LONG;
1651 else if (cmd->flags & MMC_RSP_BUSY)
1652 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1653 else
1654 flags = SDHCI_CMD_RESP_SHORT;
1655
1656 if (cmd->flags & MMC_RSP_CRC)
1657 flags |= SDHCI_CMD_CRC;
1658 if (cmd->flags & MMC_RSP_OPCODE)
1659 flags |= SDHCI_CMD_INDEX;
Arindam Nathb513ea22011-05-05 12:19:04 +05301660
1661 /* CMD19 is special in that the Data Present Select should be set */
Girish K S069c9f12012-01-06 09:56:39 +05301662 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1663 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001664 flags |= SDHCI_CMD_DATA;
1665
Kishon Vijay Abraham Ifc1fa1b2018-04-27 17:17:17 +05301666 timeout = jiffies;
1667 if (host->data_timeout)
1668 timeout += nsecs_to_jiffies(host->data_timeout);
1669 else if (!cmd->data && cmd->busy_timeout > 9000)
1670 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1671 else
1672 timeout += 10 * HZ;
1673 sdhci_mod_timer(host, cmd->mrq, timeout);
1674
Chunyan Zhang18e762e2020-01-16 16:21:47 +05301675 if (host->use_external_dma)
1676 sdhci_external_dma_pre_transfer(host, cmd);
1677
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001678 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
Adrian Hunter845c9392020-04-12 12:03:49 +03001679
1680 return true;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001681}
1682
Adrian Huntere872f1e2020-04-12 12:03:48 +03001683static bool sdhci_present_error(struct sdhci_host *host,
1684 struct mmc_command *cmd, bool present)
1685{
1686 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1687 cmd->error = -ENOMEDIUM;
1688 return true;
1689 }
1690
1691 return false;
1692}
1693
Adrian Hunter845c9392020-04-12 12:03:49 +03001694static bool sdhci_send_command_retry(struct sdhci_host *host,
1695 struct mmc_command *cmd,
1696 unsigned long flags)
1697 __releases(host->lock)
1698 __acquires(host->lock)
1699{
1700 struct mmc_command *deferred_cmd = host->deferred_cmd;
1701 int timeout = 10; /* Approx. 10 ms */
1702 bool present;
1703
1704 while (!sdhci_send_command(host, cmd)) {
1705 if (!timeout--) {
1706 pr_err("%s: Controller never released inhibit bit(s).\n",
1707 mmc_hostname(host->mmc));
1708 sdhci_dumpregs(host);
1709 cmd->error = -EIO;
1710 return false;
1711 }
1712
1713 spin_unlock_irqrestore(&host->lock, flags);
1714
1715 usleep_range(1000, 1250);
1716
1717 present = host->mmc->ops->get_cd(host->mmc);
1718
1719 spin_lock_irqsave(&host->lock, flags);
1720
1721 /* A deferred command might disappear, handle that */
1722 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1723 return true;
1724
1725 if (sdhci_present_error(host, cmd, present))
1726 return false;
1727 }
1728
1729 if (cmd == host->deferred_cmd)
1730 host->deferred_cmd = NULL;
1731
1732 return true;
1733}
1734
Adrian Hunter4a5fc112017-08-21 13:11:28 +05301735static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1736{
1737 int i, reg;
1738
1739 for (i = 0; i < 4; i++) {
1740 reg = SDHCI_RESPONSE + (3 - i) * 4;
1741 cmd->resp[i] = sdhci_readl(host, reg);
1742 }
1743
Kishon Vijay Abraham I1284c242017-08-21 13:11:29 +05301744 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1745 return;
1746
Adrian Hunter4a5fc112017-08-21 13:11:28 +05301747 /* CRC is stripped so we need to do some shifting */
1748 for (i = 0; i < 4; i++) {
1749 cmd->resp[i] <<= 8;
1750 if (i != 3)
1751 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1752 }
1753}
1754
Pierre Ossmand129bce2006-03-24 03:18:17 -08001755static void sdhci_finish_command(struct sdhci_host *host)
1756{
Adrian Huntere0a56402016-06-29 16:24:22 +03001757 struct mmc_command *cmd = host->cmd;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001758
Adrian Huntere0a56402016-06-29 16:24:22 +03001759 host->cmd = NULL;
1760
1761 if (cmd->flags & MMC_RSP_PRESENT) {
1762 if (cmd->flags & MMC_RSP_136) {
Adrian Hunter4a5fc112017-08-21 13:11:28 +05301763 sdhci_read_rsp_136(host, cmd);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001764 } else {
Adrian Huntere0a56402016-06-29 16:24:22 +03001765 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001766 }
1767 }
1768
Adrian Hunter20845be2016-08-16 13:44:13 +03001769 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1770 mmc_command_done(host->mmc, cmd->mrq);
1771
Adrian Hunter6bde8682016-06-29 16:24:20 +03001772 /*
1773 * The host can send and interrupt when the busy state has
1774 * ended, allowing us to wait without wasting CPU cycles.
1775 * The busy signal uses DAT0 so this is similar to waiting
1776 * for data to complete.
1777 *
1778 * Note: The 1.0 specification is a bit ambiguous about this
1779 * feature so there might be some problems with older
1780 * controllers.
1781 */
Adrian Huntere0a56402016-06-29 16:24:22 +03001782 if (cmd->flags & MMC_RSP_BUSY) {
1783 if (cmd->data) {
Adrian Hunter6bde8682016-06-29 16:24:20 +03001784 DBG("Cannot wait for busy signal when also doing a data transfer");
1785 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
Adrian Hunterea968022016-06-29 16:24:24 +03001786 cmd == host->data_cmd) {
1787 /* Command complete before busy is ended */
Adrian Hunter6bde8682016-06-29 16:24:20 +03001788 return;
1789 }
1790 }
1791
Andrei Warkentine89d4562011-05-23 15:06:37 -05001792 /* Finished CMD23, now send actual command. */
Adrian Huntera4c73ab2016-06-29 16:24:25 +03001793 if (cmd == cmd->mrq->sbc) {
Adrian Hunter845c9392020-04-12 12:03:49 +03001794 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1795 WARN_ON(host->deferred_cmd);
1796 host->deferred_cmd = cmd->mrq->cmd;
1797 }
Andrei Warkentine89d4562011-05-23 15:06:37 -05001798 } else {
Pierre Ossmane538fbe2007-08-12 16:46:32 +02001799
Andrei Warkentine89d4562011-05-23 15:06:37 -05001800 /* Processed actual command. */
1801 if (host->data && host->data_early)
1802 sdhci_finish_data(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001803
Adrian Huntere0a56402016-06-29 16:24:22 +03001804 if (!cmd->data)
Adrian Hunter19d2f692019-04-05 15:40:19 +03001805 __sdhci_finish_mrq(host, cmd->mrq);
Andrei Warkentine89d4562011-05-23 15:06:37 -05001806 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001807}
1808
Kevin Liu52983382013-01-31 11:31:37 +08001809static u16 sdhci_get_preset_value(struct sdhci_host *host)
1810{
Russell Kingd975f122014-04-25 12:59:31 +01001811 u16 preset = 0;
Kevin Liu52983382013-01-31 11:31:37 +08001812
Russell Kingd975f122014-04-25 12:59:31 +01001813 switch (host->timing) {
1814 case MMC_TIMING_UHS_SDR12:
Kevin Liu52983382013-01-31 11:31:37 +08001815 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1816 break;
Russell Kingd975f122014-04-25 12:59:31 +01001817 case MMC_TIMING_UHS_SDR25:
Kevin Liu52983382013-01-31 11:31:37 +08001818 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1819 break;
Russell Kingd975f122014-04-25 12:59:31 +01001820 case MMC_TIMING_UHS_SDR50:
Kevin Liu52983382013-01-31 11:31:37 +08001821 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1822 break;
Russell Kingd975f122014-04-25 12:59:31 +01001823 case MMC_TIMING_UHS_SDR104:
1824 case MMC_TIMING_MMC_HS200:
Kevin Liu52983382013-01-31 11:31:37 +08001825 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1826 break;
Russell Kingd975f122014-04-25 12:59:31 +01001827 case MMC_TIMING_UHS_DDR50:
Jisheng Zhang0dafa602015-08-18 16:21:39 +08001828 case MMC_TIMING_MMC_DDR52:
Kevin Liu52983382013-01-31 11:31:37 +08001829 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1830 break;
Adrian Huntere9fb05d2014-11-06 15:19:06 +02001831 case MMC_TIMING_MMC_HS400:
1832 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1833 break;
Kevin Liu52983382013-01-31 11:31:37 +08001834 default:
1835 pr_warn("%s: Invalid UHS-I mode selected\n",
1836 mmc_hostname(host->mmc));
1837 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1838 break;
1839 }
1840 return preset;
1841}
1842
Ludovic Desrochesfb9ee042016-04-07 11:13:08 +02001843u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1844 unsigned int *actual_clock)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001845{
Arindam Nathc3ed3872011-05-05 12:19:06 +05301846 int div = 0; /* Initialized for compiler warning */
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001847 int real_div = div, clk_mul = 1;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301848 u16 clk = 0;
ludovic.desroches@atmel.com54971592015-07-29 16:22:46 +02001849 bool switch_base_clk = false;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001850
Zhangfei Gao85105c52010-08-06 07:10:01 +08001851 if (host->version >= SDHCI_SPEC_300) {
Russell Kingda91a8f2014-04-25 13:00:12 +01001852 if (host->preset_enabled) {
Kevin Liu52983382013-01-31 11:31:37 +08001853 u16 pre_val;
1854
1855 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1856 pre_val = sdhci_get_preset_value(host);
Masahiro Yamadafa091012020-03-12 20:00:50 +09001857 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
Kevin Liu52983382013-01-31 11:31:37 +08001858 if (host->clk_mul &&
Masahiro Yamadafa091012020-03-12 20:00:50 +09001859 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
Kevin Liu52983382013-01-31 11:31:37 +08001860 clk = SDHCI_PROG_CLOCK_MODE;
1861 real_div = div + 1;
1862 clk_mul = host->clk_mul;
1863 } else {
1864 real_div = max_t(int, 1, div << 1);
1865 }
1866 goto clock_set;
1867 }
1868
Arindam Nathc3ed3872011-05-05 12:19:06 +05301869 /*
1870 * Check if the Host Controller supports Programmable Clock
1871 * Mode.
1872 */
1873 if (host->clk_mul) {
Kevin Liu52983382013-01-31 11:31:37 +08001874 for (div = 1; div <= 1024; div++) {
1875 if ((host->max_clk * host->clk_mul / div)
1876 <= clock)
1877 break;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001878 }
ludovic.desroches@atmel.com54971592015-07-29 16:22:46 +02001879 if ((host->max_clk * host->clk_mul / div) <= clock) {
1880 /*
1881 * Set Programmable Clock Mode in the Clock
1882 * Control register.
1883 */
1884 clk = SDHCI_PROG_CLOCK_MODE;
1885 real_div = div;
1886 clk_mul = host->clk_mul;
1887 div--;
1888 } else {
1889 /*
1890 * Divisor can be too small to reach clock
1891 * speed requirement. Then use the base clock.
1892 */
1893 switch_base_clk = true;
1894 }
1895 }
1896
1897 if (!host->clk_mul || switch_base_clk) {
Arindam Nathc3ed3872011-05-05 12:19:06 +05301898 /* Version 3.00 divisors must be a multiple of 2. */
1899 if (host->max_clk <= clock)
1900 div = 1;
1901 else {
1902 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1903 div += 2) {
1904 if ((host->max_clk / div) <= clock)
1905 break;
1906 }
1907 }
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001908 real_div = div;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301909 div >>= 1;
Suneel Garapatid1955c32015-06-09 13:01:50 +05301910 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1911 && !div && host->max_clk <= 25000000)
1912 div = 1;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001913 }
1914 } else {
1915 /* Version 2.00 divisors must be a power of 2. */
Zhangfei Gao03975262010-09-20 15:15:18 -04001916 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Zhangfei Gao85105c52010-08-06 07:10:01 +08001917 if ((host->max_clk / div) <= clock)
1918 break;
1919 }
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001920 real_div = div;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301921 div >>= 1;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001922 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001923
Kevin Liu52983382013-01-31 11:31:37 +08001924clock_set:
Aisheng Dong03d6f5f2014-08-27 15:26:32 +08001925 if (real_div)
Ludovic Desrochesfb9ee042016-04-07 11:13:08 +02001926 *actual_clock = (host->max_clk * clk_mul) / real_div;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301927 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001928 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1929 << SDHCI_DIVIDER_HI_SHIFT;
Ludovic Desrochesfb9ee042016-04-07 11:13:08 +02001930
1931 return clk;
1932}
1933EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1934
Ritesh Harjanifec79672016-11-21 12:07:19 +05301935void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
Ludovic Desrochesfb9ee042016-04-07 11:13:08 +02001936{
Adrian Hunter5a436cc2017-03-20 19:50:31 +02001937 ktime_t timeout;
Ludovic Desrochesfb9ee042016-04-07 11:13:08 +02001938
Pierre Ossmand129bce2006-03-24 03:18:17 -08001939 clk |= SDHCI_CLOCK_INT_EN;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001940 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001941
Ben Chuang4a9e0d12019-08-27 08:32:42 +08001942 /* Wait max 150 ms */
1943 timeout = ktime_add_ms(ktime_get(), 150);
Alek Dub7044412018-12-06 17:24:59 +08001944 while (1) {
1945 bool timedout = ktime_after(ktime_get(), timeout);
1946
1947 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1948 if (clk & SDHCI_CLOCK_INT_STABLE)
1949 break;
1950 if (timedout) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01001951 pr_err("%s: Internal clock never stabilised.\n",
1952 mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08001953 sdhci_dumpregs(host);
1954 return;
1955 }
Adrian Hunter5a436cc2017-03-20 19:50:31 +02001956 udelay(10);
Pierre Ossman7cb2c762006-06-30 02:22:23 -07001957 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001958
Ben Chuang1beabbd2019-08-27 08:32:55 +08001959 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1960 clk |= SDHCI_CLOCK_PLL_EN;
1961 clk &= ~SDHCI_CLOCK_INT_STABLE;
1962 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1963
1964 /* Wait max 150 ms */
1965 timeout = ktime_add_ms(ktime_get(), 150);
1966 while (1) {
1967 bool timedout = ktime_after(ktime_get(), timeout);
1968
1969 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1970 if (clk & SDHCI_CLOCK_INT_STABLE)
1971 break;
1972 if (timedout) {
1973 pr_err("%s: PLL clock never stabilised.\n",
1974 mmc_hostname(host->mmc));
1975 sdhci_dumpregs(host);
1976 return;
1977 }
1978 udelay(10);
1979 }
1980 }
1981
Pierre Ossmand129bce2006-03-24 03:18:17 -08001982 clk |= SDHCI_CLOCK_CARD_EN;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001984}
Ritesh Harjanifec79672016-11-21 12:07:19 +05301985EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1986
1987void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1988{
1989 u16 clk;
1990
1991 host->mmc->actual_clock = 0;
1992
1993 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1994
1995 if (clock == 0)
1996 return;
1997
1998 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1999 sdhci_enable_clk(host, clk);
2000}
Russell King17710592014-04-25 12:58:55 +01002001EXPORT_SYMBOL_GPL(sdhci_set_clock);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002002
Adrian Hunter1dceb042016-03-29 12:45:43 +03002003static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2004 unsigned short vdd)
Pierre Ossman146ad662006-06-30 02:22:23 -07002005{
Tim Kryger3a48edc2014-06-13 10:13:56 -07002006 struct mmc_host *mmc = host->mmc;
Adrian Hunter1dceb042016-03-29 12:45:43 +03002007
Adrian Hunter1dceb042016-03-29 12:45:43 +03002008 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
Adrian Hunter1dceb042016-03-29 12:45:43 +03002009
2010 if (mode != MMC_POWER_OFF)
2011 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2012 else
2013 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2014}
2015
Adrian Hunter606d3132016-10-05 12:11:22 +03002016void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2017 unsigned short vdd)
Adrian Hunter1dceb042016-03-29 12:45:43 +03002018{
Giuseppe Cavallaro83642482010-09-28 10:41:28 +02002019 u8 pwr = 0;
Pierre Ossman146ad662006-06-30 02:22:23 -07002020
Russell King24fbb3c2014-04-25 13:00:06 +01002021 if (mode != MMC_POWER_OFF) {
2022 switch (1 << vdd) {
Pierre Ossmanae628902009-05-03 20:45:03 +02002023 case MMC_VDD_165_195:
Andy Shevchenko2a609ab2018-01-11 15:51:58 +02002024 /*
2025 * Without a regulator, SDHCI does not support 2.0v
2026 * so we only get here if the driver deliberately
2027 * added the 2.0v range to ocr_avail. Map it to 1.8v
2028 * for the purpose of turning on the power.
2029 */
2030 case MMC_VDD_20_21:
Pierre Ossmanae628902009-05-03 20:45:03 +02002031 pwr = SDHCI_POWER_180;
2032 break;
2033 case MMC_VDD_29_30:
2034 case MMC_VDD_30_31:
2035 pwr = SDHCI_POWER_300;
2036 break;
2037 case MMC_VDD_32_33:
2038 case MMC_VDD_33_34:
2039 pwr = SDHCI_POWER_330;
2040 break;
2041 default:
Adrian Hunter9d5de932015-11-26 14:00:46 +02002042 WARN(1, "%s: Invalid vdd %#x\n",
2043 mmc_hostname(host->mmc), vdd);
2044 break;
Pierre Ossmanae628902009-05-03 20:45:03 +02002045 }
2046 }
2047
2048 if (host->pwr == pwr)
Russell Kinge921a8b2014-04-25 13:00:01 +01002049 return;
Pierre Ossman146ad662006-06-30 02:22:23 -07002050
Pierre Ossmanae628902009-05-03 20:45:03 +02002051 host->pwr = pwr;
2052
2053 if (pwr == 0) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002054 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
Adrian Hunterf0710a52013-05-06 12:17:32 +03002055 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2056 sdhci_runtime_pm_bus_off(host);
Russell Kinge921a8b2014-04-25 13:00:01 +01002057 } else {
2058 /*
2059 * Spec says that we should clear the power reg before setting
2060 * a new value. Some controllers don't seem to like this though.
2061 */
2062 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2063 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
Darren Salt9e9dc5f2007-01-27 15:32:31 +01002064
Russell Kinge921a8b2014-04-25 13:00:01 +01002065 /*
2066 * At least the Marvell CaFe chip gets confused if we set the
2067 * voltage and set turn on power at the same time, so set the
2068 * voltage first.
2069 */
2070 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2071 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
Pierre Ossman146ad662006-06-30 02:22:23 -07002072
Russell Kinge921a8b2014-04-25 13:00:01 +01002073 pwr |= SDHCI_POWER_ON;
2074
Pierre Ossmanae628902009-05-03 20:45:03 +02002075 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2076
Russell Kinge921a8b2014-04-25 13:00:01 +01002077 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2078 sdhci_runtime_pm_bus_on(host);
Andres Salomone08c1692008-07-04 10:00:03 -07002079
Russell Kinge921a8b2014-04-25 13:00:01 +01002080 /*
2081 * Some controllers need an extra 10ms delay of 10ms before
2082 * they can apply clock after applying power
2083 */
2084 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2085 mdelay(10);
2086 }
Adrian Hunter1dceb042016-03-29 12:45:43 +03002087}
Adrian Hunter606d3132016-10-05 12:11:22 +03002088EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
Jisheng Zhang918f4cb2015-12-11 21:36:29 +08002089
Adrian Hunter606d3132016-10-05 12:11:22 +03002090void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2091 unsigned short vdd)
Adrian Hunter1dceb042016-03-29 12:45:43 +03002092{
Adrian Hunter606d3132016-10-05 12:11:22 +03002093 if (IS_ERR(host->mmc->supply.vmmc))
2094 sdhci_set_power_noreg(host, mode, vdd);
Adrian Hunter1dceb042016-03-29 12:45:43 +03002095 else
Adrian Hunter606d3132016-10-05 12:11:22 +03002096 sdhci_set_power_reg(host, mode, vdd);
Pierre Ossman146ad662006-06-30 02:22:23 -07002097}
Adrian Hunter606d3132016-10-05 12:11:22 +03002098EXPORT_SYMBOL_GPL(sdhci_set_power);
Pierre Ossman146ad662006-06-30 02:22:23 -07002099
Nicolas Saenz Julienne6c92ae12020-03-06 18:44:03 +01002100/*
2101 * Some controllers need to configure a valid bus voltage on their power
2102 * register regardless of whether an external regulator is taking care of power
2103 * supply. This helper function takes care of it if set as the controller's
2104 * sdhci_ops.set_power callback.
2105 */
2106void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2107 unsigned char mode,
2108 unsigned short vdd)
2109{
2110 if (!IS_ERR(host->mmc->supply.vmmc)) {
2111 struct mmc_host *mmc = host->mmc;
2112
2113 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2114 }
2115 sdhci_set_power_noreg(host, mode, vdd);
2116}
2117EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2118
Pierre Ossmand129bce2006-03-24 03:18:17 -08002119/*****************************************************************************\
2120 * *
2121 * MMC callbacks *
2122 * *
2123\*****************************************************************************/
2124
Aapo Vienamod462c1b2018-08-20 12:23:32 +03002125void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002126{
Adrian Huntere872f1e2020-04-12 12:03:48 +03002127 struct sdhci_host *host = mmc_priv(mmc);
2128 struct mmc_command *cmd;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002129 unsigned long flags;
Adrian Huntere872f1e2020-04-12 12:03:48 +03002130 bool present;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002131
Scott Branden04e079cf2015-03-10 11:35:10 -07002132 /* Firstly check card presence */
Adrian Hunter8d28b7a2016-02-09 16:12:36 +02002133 present = mmc->ops->get_cd(mmc);
Krzysztof Kozlowski28367662015-01-05 10:50:15 +01002134
Pierre Ossmand129bce2006-03-24 03:18:17 -08002135 spin_lock_irqsave(&host->lock, flags);
2136
Adrian Hunter061d17a2016-04-12 14:25:09 +03002137 sdhci_led_activate(host);
Andrei Warkentine89d4562011-05-23 15:06:37 -05002138
Adrian Huntere872f1e2020-04-12 12:03:48 +03002139 if (sdhci_present_error(host, mrq->cmd, present))
2140 goto out_finish;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002141
Adrian Huntere872f1e2020-04-12 12:03:48 +03002142 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2143
Adrian Hunter845c9392020-04-12 12:03:49 +03002144 if (!sdhci_send_command_retry(host, cmd, flags))
2145 goto out_finish;
Adrian Huntere872f1e2020-04-12 12:03:48 +03002146
2147 spin_unlock_irqrestore(&host->lock, flags);
2148
2149 return;
2150
2151out_finish:
2152 sdhci_finish_mrq(host, mrq);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002153 spin_unlock_irqrestore(&host->lock, flags);
2154}
Aapo Vienamod462c1b2018-08-20 12:23:32 +03002155EXPORT_SYMBOL_GPL(sdhci_request);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002156
Baolin Wang48ef8a22020-04-13 10:46:04 +08002157int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2158{
2159 struct sdhci_host *host = mmc_priv(mmc);
2160 struct mmc_command *cmd;
2161 unsigned long flags;
2162 int ret = 0;
2163
2164 spin_lock_irqsave(&host->lock, flags);
2165
2166 if (sdhci_present_error(host, mrq->cmd, true)) {
2167 sdhci_finish_mrq(host, mrq);
2168 goto out_finish;
2169 }
2170
2171 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2172
2173 /*
2174 * The HSQ may send a command in interrupt context without polling
2175 * the busy signaling, which means we should return BUSY if controller
2176 * has not released inhibit bits to allow HSQ trying to send request
2177 * again in non-atomic context. So we should not finish this request
2178 * here.
2179 */
2180 if (!sdhci_send_command(host, cmd))
2181 ret = -EBUSY;
2182 else
2183 sdhci_led_activate(host);
2184
2185out_finish:
2186 spin_unlock_irqrestore(&host->lock, flags);
2187 return ret;
2188}
2189EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2190
Russell King2317f562014-04-25 12:57:07 +01002191void sdhci_set_bus_width(struct sdhci_host *host, int width)
2192{
2193 u8 ctrl;
2194
2195 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2196 if (width == MMC_BUS_WIDTH_8) {
2197 ctrl &= ~SDHCI_CTRL_4BITBUS;
Michał Mirosław98f94ea2017-08-14 22:00:24 +02002198 ctrl |= SDHCI_CTRL_8BITBUS;
Russell King2317f562014-04-25 12:57:07 +01002199 } else {
Michał Mirosław98f94ea2017-08-14 22:00:24 +02002200 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
Russell King2317f562014-04-25 12:57:07 +01002201 ctrl &= ~SDHCI_CTRL_8BITBUS;
2202 if (width == MMC_BUS_WIDTH_4)
2203 ctrl |= SDHCI_CTRL_4BITBUS;
2204 else
2205 ctrl &= ~SDHCI_CTRL_4BITBUS;
2206 }
2207 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2208}
2209EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2210
Russell King96d7b782014-04-25 12:59:26 +01002211void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2212{
2213 u16 ctrl_2;
2214
2215 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2216 /* Select Bus Speed Mode for host */
2217 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2218 if ((timing == MMC_TIMING_MMC_HS200) ||
2219 (timing == MMC_TIMING_UHS_SDR104))
2220 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2221 else if (timing == MMC_TIMING_UHS_SDR12)
2222 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
Faiz Abbas07bcc412019-11-28 16:34:22 +05302223 else if (timing == MMC_TIMING_UHS_SDR25)
Russell King96d7b782014-04-25 12:59:26 +01002224 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2225 else if (timing == MMC_TIMING_UHS_SDR50)
2226 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2227 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2228 (timing == MMC_TIMING_MMC_DDR52))
2229 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
Adrian Huntere9fb05d2014-11-06 15:19:06 +02002230 else if (timing == MMC_TIMING_MMC_HS400)
2231 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
Russell King96d7b782014-04-25 12:59:26 +01002232 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2233}
2234EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2235
Hu Ziji6a6d4ce2017-03-30 17:22:55 +02002236void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002237{
Dong Aishengded97e02016-04-16 01:29:25 +08002238 struct sdhci_host *host = mmc_priv(mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002239 u8 ctrl;
2240
Adrian Hunter84ec0482016-12-19 15:33:11 +02002241 if (ios->power_mode == MMC_POWER_UNDEFINED)
2242 return;
2243
Adrian Hunterceb61432011-12-27 15:48:41 +02002244 if (host->flags & SDHCI_DEVICE_DEAD) {
Tim Kryger3a48edc2014-06-13 10:13:56 -07002245 if (!IS_ERR(mmc->supply.vmmc) &&
2246 ios->power_mode == MMC_POWER_OFF)
Markus Mayer4e743f12014-07-03 13:27:42 -07002247 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
Adrian Hunterceb61432011-12-27 15:48:41 +02002248 return;
2249 }
Pierre Ossman1e728592008-04-16 19:13:13 +02002250
Pierre Ossmand129bce2006-03-24 03:18:17 -08002251 /*
2252 * Reset the chip on each power off.
2253 * Should clear out any weird states.
2254 */
2255 if (ios->power_mode == MMC_POWER_OFF) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002256 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
Anton Vorontsov7260cf52009-03-17 00:13:48 +03002257 sdhci_reinit(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002258 }
2259
Kevin Liu52983382013-01-31 11:31:37 +08002260 if (host->version >= SDHCI_SPEC_300 &&
Dong Aisheng372c4632013-10-18 19:48:50 +08002261 (ios->power_mode == MMC_POWER_UP) &&
2262 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
Kevin Liu52983382013-01-31 11:31:37 +08002263 sdhci_enable_preset_value(host, false);
2264
Russell King373073e2014-04-25 12:58:45 +01002265 if (!ios->clock || ios->clock != host->clock) {
Russell King17710592014-04-25 12:58:55 +01002266 host->ops->set_clock(host, ios->clock);
Russell King373073e2014-04-25 12:58:45 +01002267 host->clock = ios->clock;
Aisheng Dong03d6f5f2014-08-27 15:26:32 +08002268
2269 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2270 host->clock) {
2271 host->timeout_clk = host->mmc->actual_clock ?
2272 host->mmc->actual_clock / 1000 :
2273 host->clock / 1000;
2274 host->mmc->max_busy_timeout =
2275 host->ops->get_max_timeout_count ?
2276 host->ops->get_max_timeout_count(host) :
2277 1 << 27;
2278 host->mmc->max_busy_timeout /= host->timeout_clk;
2279 }
Russell King373073e2014-04-25 12:58:45 +01002280 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002281
Adrian Hunter606d3132016-10-05 12:11:22 +03002282 if (host->ops->set_power)
2283 host->ops->set_power(host, ios->power_mode, ios->vdd);
2284 else
2285 sdhci_set_power(host, ios->power_mode, ios->vdd);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002286
Philip Rakity643a81f2010-09-23 08:24:32 -07002287 if (host->ops->platform_send_init_74_clocks)
2288 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2289
Russell King2317f562014-04-25 12:57:07 +01002290 host->ops->set_bus_width(host, ios->bus_width);
Philip Rakity15ec4462010-11-19 16:48:39 -05002291
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002292 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmancd9277c2007-02-18 12:07:47 +01002293
yangbo lu501639b2017-08-15 10:16:47 +08002294 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2295 if (ios->timing == MMC_TIMING_SD_HS ||
2296 ios->timing == MMC_TIMING_MMC_HS ||
2297 ios->timing == MMC_TIMING_MMC_HS400 ||
2298 ios->timing == MMC_TIMING_MMC_HS200 ||
2299 ios->timing == MMC_TIMING_MMC_DDR52 ||
2300 ios->timing == MMC_TIMING_UHS_SDR50 ||
2301 ios->timing == MMC_TIMING_UHS_SDR104 ||
2302 ios->timing == MMC_TIMING_UHS_DDR50 ||
2303 ios->timing == MMC_TIMING_UHS_SDR25)
2304 ctrl |= SDHCI_CTRL_HISPD;
2305 else
2306 ctrl &= ~SDHCI_CTRL_HISPD;
2307 }
Pierre Ossmancd9277c2007-02-18 12:07:47 +01002308
Arindam Nathd6d50a12011-05-05 12:18:59 +05302309 if (host->version >= SDHCI_SPEC_300) {
Arindam Nath49c468f2011-05-05 12:19:01 +05302310 u16 clk, ctrl_2;
Arindam Nath49c468f2011-05-05 12:19:01 +05302311
Russell Kingda91a8f2014-04-25 13:00:12 +01002312 if (!host->preset_enabled) {
Arindam Nath758535c2011-05-05 12:19:00 +05302313 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Arindam Nathd6d50a12011-05-05 12:18:59 +05302314 /*
2315 * We only need to set Driver Strength if the
2316 * preset value enable is not set.
2317 */
Russell Kingda91a8f2014-04-25 13:00:12 +01002318 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Arindam Nathd6d50a12011-05-05 12:18:59 +05302319 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2320 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2321 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
Petri Gynther43e943a2015-05-20 14:35:00 -07002322 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2323 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
Arindam Nathd6d50a12011-05-05 12:18:59 +05302324 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2325 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
Petri Gynther43e943a2015-05-20 14:35:00 -07002326 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2327 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2328 else {
Marek Vasut2e4456f2015-11-18 10:47:02 +01002329 pr_warn("%s: invalid driver type, default to driver type B\n",
2330 mmc_hostname(mmc));
Petri Gynther43e943a2015-05-20 14:35:00 -07002331 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2332 }
Arindam Nathd6d50a12011-05-05 12:18:59 +05302333
2334 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
Arindam Nath758535c2011-05-05 12:19:00 +05302335 } else {
2336 /*
2337 * According to SDHC Spec v3.00, if the Preset Value
2338 * Enable in the Host Control 2 register is set, we
2339 * need to reset SD Clock Enable before changing High
2340 * Speed Enable to avoid generating clock gliches.
2341 */
Arindam Nath758535c2011-05-05 12:19:00 +05302342
2343 /* Reset SD Clock Enable */
2344 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2345 clk &= ~SDHCI_CLOCK_CARD_EN;
2346 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2347
2348 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2349
2350 /* Re-enable SD Clock */
Russell King17710592014-04-25 12:58:55 +01002351 host->ops->set_clock(host, host->clock);
Arindam Nathd6d50a12011-05-05 12:18:59 +05302352 }
Arindam Nath49c468f2011-05-05 12:19:01 +05302353
Arindam Nath49c468f2011-05-05 12:19:01 +05302354 /* Reset SD Clock Enable */
2355 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2356 clk &= ~SDHCI_CLOCK_CARD_EN;
2357 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2358
Russell King96d7b782014-04-25 12:59:26 +01002359 host->ops->set_uhs_signaling(host, ios->timing);
Russell Kingd975f122014-04-25 12:59:31 +01002360 host->timing = ios->timing;
Arindam Nath49c468f2011-05-05 12:19:01 +05302361
Kevin Liu52983382013-01-31 11:31:37 +08002362 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2363 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2364 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2365 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2366 (ios->timing == MMC_TIMING_UHS_SDR104) ||
Jisheng Zhang0dafa602015-08-18 16:21:39 +08002367 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2368 (ios->timing == MMC_TIMING_MMC_DDR52))) {
Kevin Liu52983382013-01-31 11:31:37 +08002369 u16 preset;
2370
2371 sdhci_enable_preset_value(host, true);
2372 preset = sdhci_get_preset_value(host);
Masahiro Yamadafa091012020-03-12 20:00:50 +09002373 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2374 preset);
Kevin Liu52983382013-01-31 11:31:37 +08002375 }
2376
Arindam Nath49c468f2011-05-05 12:19:01 +05302377 /* Re-enable SD Clock */
Russell King17710592014-04-25 12:58:55 +01002378 host->ops->set_clock(host, host->clock);
Arindam Nath758535c2011-05-05 12:19:00 +05302379 } else
2380 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Arindam Nathd6d50a12011-05-05 12:18:59 +05302381
Leandro Dorileob8352262007-07-25 23:47:04 +02002382 /*
2383 * Some (ENE) controllers go apeshit on some ios operation,
2384 * signalling timeout and CRC errors even on CMD0. Resetting
2385 * it on each ios seems to solve the problem.
2386 */
Mohammad Jamalc63705e2015-01-13 20:47:24 +05302387 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
Russell King03231f92014-04-25 12:57:12 +01002388 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002389}
Hu Ziji6a6d4ce2017-03-30 17:22:55 +02002390EXPORT_SYMBOL_GPL(sdhci_set_ios);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002391
Dong Aishengded97e02016-04-16 01:29:25 +08002392static int sdhci_get_cd(struct mmc_host *mmc)
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002393{
2394 struct sdhci_host *host = mmc_priv(mmc);
Dong Aishengded97e02016-04-16 01:29:25 +08002395 int gpio_cd = mmc_gpio_get_cd(mmc);
Kevin Liu94144a42013-02-28 17:35:53 +08002396
2397 if (host->flags & SDHCI_DEVICE_DEAD)
2398 return 0;
2399
Ivan T. Ivanov88af5652015-07-06 15:16:19 +03002400 /* If nonremovable, assume that the card is always present. */
Jaehoon Chung860951c2016-06-21 10:13:26 +09002401 if (!mmc_card_is_removable(host->mmc))
Kevin Liu94144a42013-02-28 17:35:53 +08002402 return 1;
2403
Ivan T. Ivanov88af5652015-07-06 15:16:19 +03002404 /*
2405 * Try slot gpio detect, if defined it take precedence
2406 * over build in controller functionality
2407 */
Arnd Bergmann287980e2016-05-27 23:23:25 +02002408 if (gpio_cd >= 0)
Kevin Liu94144a42013-02-28 17:35:53 +08002409 return !!gpio_cd;
2410
Ivan T. Ivanov88af5652015-07-06 15:16:19 +03002411 /* If polling, assume that the card is always present. */
2412 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2413 return 1;
2414
Kevin Liu94144a42013-02-28 17:35:53 +08002415 /* Host native card detect */
2416 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2417}
2418
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002419static int sdhci_check_ro(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002420{
Pierre Ossmand129bce2006-03-24 03:18:17 -08002421 unsigned long flags;
Wolfram Sang2dfb5792010-10-15 12:21:01 +02002422 int is_readonly;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002423
Pierre Ossmand129bce2006-03-24 03:18:17 -08002424 spin_lock_irqsave(&host->lock, flags);
2425
Pierre Ossman1e728592008-04-16 19:13:13 +02002426 if (host->flags & SDHCI_DEVICE_DEAD)
Wolfram Sang2dfb5792010-10-15 12:21:01 +02002427 is_readonly = 0;
2428 else if (host->ops->get_ro)
2429 is_readonly = host->ops->get_ro(host);
Thomas Petazzoni6d5cd062019-02-12 15:07:35 +01002430 else if (mmc_can_gpio_ro(host->mmc))
2431 is_readonly = mmc_gpio_get_ro(host->mmc);
Pierre Ossman1e728592008-04-16 19:13:13 +02002432 else
Wolfram Sang2dfb5792010-10-15 12:21:01 +02002433 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2434 & SDHCI_WRITE_PROTECT);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002435
2436 spin_unlock_irqrestore(&host->lock, flags);
2437
Wolfram Sang2dfb5792010-10-15 12:21:01 +02002438 /* This quirk needs to be replaced by a callback-function later */
2439 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2440 !is_readonly : is_readonly;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002441}
2442
Takashi Iwai82b0e232011-04-21 20:26:38 +02002443#define SAMPLE_COUNT 5
2444
Dong Aishengded97e02016-04-16 01:29:25 +08002445static int sdhci_get_ro(struct mmc_host *mmc)
Takashi Iwai82b0e232011-04-21 20:26:38 +02002446{
Dong Aishengded97e02016-04-16 01:29:25 +08002447 struct sdhci_host *host = mmc_priv(mmc);
Takashi Iwai82b0e232011-04-21 20:26:38 +02002448 int i, ro_count;
2449
Takashi Iwai82b0e232011-04-21 20:26:38 +02002450 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002451 return sdhci_check_ro(host);
Takashi Iwai82b0e232011-04-21 20:26:38 +02002452
2453 ro_count = 0;
2454 for (i = 0; i < SAMPLE_COUNT; i++) {
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002455 if (sdhci_check_ro(host)) {
Takashi Iwai82b0e232011-04-21 20:26:38 +02002456 if (++ro_count > SAMPLE_COUNT / 2)
2457 return 1;
2458 }
2459 msleep(30);
2460 }
2461 return 0;
2462}
2463
Adrian Hunter20758b62011-08-29 16:42:12 +03002464static void sdhci_hw_reset(struct mmc_host *mmc)
2465{
2466 struct sdhci_host *host = mmc_priv(mmc);
2467
2468 if (host->ops && host->ops->hw_reset)
2469 host->ops->hw_reset(host);
2470}
2471
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002472static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2473{
Russell Kingbe138552014-04-25 12:55:56 +01002474 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
Russell Kingef104332014-04-25 12:55:41 +01002475 if (enable)
Russell Kingb537f942014-04-25 12:56:01 +01002476 host->ier |= SDHCI_INT_CARD_INT;
Russell Kingef104332014-04-25 12:55:41 +01002477 else
Russell Kingb537f942014-04-25 12:56:01 +01002478 host->ier &= ~SDHCI_INT_CARD_INT;
2479
2480 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2481 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Russell Kingef104332014-04-25 12:55:41 +01002482 }
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002483}
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002484
Hu Ziji2f05b6ab2017-03-30 17:22:57 +02002485void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002486{
2487 struct sdhci_host *host = mmc_priv(mmc);
2488 unsigned long flags;
2489
Hans de Goede923713b2017-03-26 13:14:45 +02002490 if (enable)
2491 pm_runtime_get_noresume(host->mmc->parent);
2492
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002493 spin_lock_irqsave(&host->lock, flags);
2494 sdhci_enable_sdio_irq_nolock(host, enable);
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002495 spin_unlock_irqrestore(&host->lock, flags);
Hans de Goede923713b2017-03-26 13:14:45 +02002496
2497 if (!enable)
2498 pm_runtime_put_noidle(host->mmc->parent);
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002499}
Hu Ziji2f05b6ab2017-03-30 17:22:57 +02002500EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002501
Adrian Hunter89f3c362019-05-27 14:45:55 +03002502static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2503{
2504 struct sdhci_host *host = mmc_priv(mmc);
2505 unsigned long flags;
2506
2507 spin_lock_irqsave(&host->lock, flags);
Ulf Hanssona84ad322019-09-08 12:12:34 +02002508 sdhci_enable_sdio_irq_nolock(host, true);
Adrian Hunter89f3c362019-05-27 14:45:55 +03002509 spin_unlock_irqrestore(&host->lock, flags);
2510}
2511
Hu Zijic376ea92017-03-30 17:22:56 +02002512int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2513 struct mmc_ios *ios)
Philip Rakity6231f3d2012-07-23 15:56:23 -07002514{
Dong Aishengded97e02016-04-16 01:29:25 +08002515 struct sdhci_host *host = mmc_priv(mmc);
Philip Rakity6231f3d2012-07-23 15:56:23 -07002516 u16 ctrl;
Kevin Liu20b92a32012-12-17 19:29:26 +08002517 int ret;
Philip Rakity6231f3d2012-07-23 15:56:23 -07002518
2519 /*
2520 * Signal Voltage Switching is only applicable for Host Controllers
2521 * v3.00 and above.
2522 */
2523 if (host->version < SDHCI_SPEC_300)
2524 return 0;
2525
Philip Rakity6231f3d2012-07-23 15:56:23 -07002526 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Kevin Liu20b92a32012-12-17 19:29:26 +08002527
Fabio Estevam21f59982013-02-14 10:35:03 -02002528 switch (ios->signal_voltage) {
Kevin Liu20b92a32012-12-17 19:29:26 +08002529 case MMC_SIGNAL_VOLTAGE_330:
Adrian Hunter8cb851a2016-06-29 16:24:16 +03002530 if (!(host->flags & SDHCI_SIGNALING_330))
2531 return -EINVAL;
Kevin Liu20b92a32012-12-17 19:29:26 +08002532 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2533 ctrl &= ~SDHCI_CTRL_VDD_180;
2534 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2535
Tim Kryger3a48edc2014-06-13 10:13:56 -07002536 if (!IS_ERR(mmc->supply.vqmmc)) {
Dong Aisheng761daa32016-07-12 15:46:10 +08002537 ret = mmc_regulator_set_vqmmc(mmc, ios);
Marek Vasut9cbe0fc2020-04-16 18:36:47 +02002538 if (ret < 0) {
Joe Perches66061102014-09-12 14:56:56 -07002539 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2540 mmc_hostname(mmc));
Kevin Liu20b92a32012-12-17 19:29:26 +08002541 return -EIO;
2542 }
2543 }
2544 /* Wait for 5ms */
2545 usleep_range(5000, 5500);
2546
2547 /* 3.3V regulator output should be stable within 5 ms */
2548 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2549 if (!(ctrl & SDHCI_CTRL_VDD_180))
2550 return 0;
2551
Fabio Estevamb0b19ce2019-11-19 12:55:03 -03002552 pr_warn("%s: 3.3V regulator output did not become stable\n",
Joe Perches66061102014-09-12 14:56:56 -07002553 mmc_hostname(mmc));
Kevin Liu20b92a32012-12-17 19:29:26 +08002554
2555 return -EAGAIN;
2556 case MMC_SIGNAL_VOLTAGE_180:
Adrian Hunter8cb851a2016-06-29 16:24:16 +03002557 if (!(host->flags & SDHCI_SIGNALING_180))
2558 return -EINVAL;
Tim Kryger3a48edc2014-06-13 10:13:56 -07002559 if (!IS_ERR(mmc->supply.vqmmc)) {
Dong Aisheng761daa32016-07-12 15:46:10 +08002560 ret = mmc_regulator_set_vqmmc(mmc, ios);
Marek Vasut9cbe0fc2020-04-16 18:36:47 +02002561 if (ret < 0) {
Joe Perches66061102014-09-12 14:56:56 -07002562 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2563 mmc_hostname(mmc));
Kevin Liu20b92a32012-12-17 19:29:26 +08002564 return -EIO;
2565 }
2566 }
2567
2568 /*
2569 * Enable 1.8V Signal Enable in the Host Control2
2570 * register
2571 */
2572 ctrl |= SDHCI_CTRL_VDD_180;
2573 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2574
Vincent Yang9d967a62015-01-20 16:05:15 +08002575 /* Some controller need to do more when switching */
2576 if (host->ops->voltage_switch)
2577 host->ops->voltage_switch(host);
2578
Kevin Liu20b92a32012-12-17 19:29:26 +08002579 /* 1.8V regulator output should be stable within 5 ms */
2580 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2581 if (ctrl & SDHCI_CTRL_VDD_180)
2582 return 0;
2583
Fabio Estevamb0b19ce2019-11-19 12:55:03 -03002584 pr_warn("%s: 1.8V regulator output did not become stable\n",
Joe Perches66061102014-09-12 14:56:56 -07002585 mmc_hostname(mmc));
Kevin Liu20b92a32012-12-17 19:29:26 +08002586
2587 return -EAGAIN;
2588 case MMC_SIGNAL_VOLTAGE_120:
Adrian Hunter8cb851a2016-06-29 16:24:16 +03002589 if (!(host->flags & SDHCI_SIGNALING_120))
2590 return -EINVAL;
Tim Kryger3a48edc2014-06-13 10:13:56 -07002591 if (!IS_ERR(mmc->supply.vqmmc)) {
Dong Aisheng761daa32016-07-12 15:46:10 +08002592 ret = mmc_regulator_set_vqmmc(mmc, ios);
Marek Vasut9cbe0fc2020-04-16 18:36:47 +02002593 if (ret < 0) {
Joe Perches66061102014-09-12 14:56:56 -07002594 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2595 mmc_hostname(mmc));
Kevin Liu20b92a32012-12-17 19:29:26 +08002596 return -EIO;
2597 }
2598 }
2599 return 0;
2600 default:
Arindam Nathf2119df2011-05-05 12:18:57 +05302601 /* No signal voltage switch required */
2602 return 0;
Kevin Liu20b92a32012-12-17 19:29:26 +08002603 }
Arindam Nathf2119df2011-05-05 12:18:57 +05302604}
Hu Zijic376ea92017-03-30 17:22:56 +02002605EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
Arindam Nathf2119df2011-05-05 12:18:57 +05302606
Kevin Liu20b92a32012-12-17 19:29:26 +08002607static int sdhci_card_busy(struct mmc_host *mmc)
2608{
2609 struct sdhci_host *host = mmc_priv(mmc);
2610 u32 present_state;
2611
Adrian Huntere613cc42016-06-23 14:00:58 +03002612 /* Check whether DAT[0] is 0 */
Kevin Liu20b92a32012-12-17 19:29:26 +08002613 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
Kevin Liu20b92a32012-12-17 19:29:26 +08002614
Adrian Huntere613cc42016-06-23 14:00:58 +03002615 return !(present_state & SDHCI_DATA_0_LVL_MASK);
Kevin Liu20b92a32012-12-17 19:29:26 +08002616}
2617
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002618static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2619{
2620 struct sdhci_host *host = mmc_priv(mmc);
2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&host->lock, flags);
2624 host->flags |= SDHCI_HS400_TUNING;
2625 spin_unlock_irqrestore(&host->lock, flags);
2626
2627 return 0;
2628}
2629
ernest.zhang6663c412018-07-16 14:26:53 +08002630void sdhci_start_tuning(struct sdhci_host *host)
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002631{
2632 u16 ctrl;
2633
2634 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2635 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2636 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2637 ctrl |= SDHCI_CTRL_TUNED_CLK;
2638 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2639
2640 /*
2641 * As per the Host Controller spec v3.00, tuning command
2642 * generates Buffer Read Ready interrupt, so enable that.
2643 *
2644 * Note: The spec clearly says that when tuning sequence
2645 * is being performed, the controller does not generate
2646 * interrupts other than Buffer Read Ready interrupt. But
2647 * to make sure we don't hit a controller bug, we _only_
2648 * enable Buffer Read Ready interrupt here.
2649 */
2650 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2651 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2652}
ernest.zhang6663c412018-07-16 14:26:53 +08002653EXPORT_SYMBOL_GPL(sdhci_start_tuning);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002654
ernest.zhang6663c412018-07-16 14:26:53 +08002655void sdhci_end_tuning(struct sdhci_host *host)
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002656{
2657 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2658 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2659}
ernest.zhang6663c412018-07-16 14:26:53 +08002660EXPORT_SYMBOL_GPL(sdhci_end_tuning);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002661
ernest.zhang6663c412018-07-16 14:26:53 +08002662void sdhci_reset_tuning(struct sdhci_host *host)
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002663{
2664 u16 ctrl;
2665
2666 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2667 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2668 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2669 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2670}
ernest.zhang6663c412018-07-16 14:26:53 +08002671EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002672
Ben Chuang73537882019-08-27 08:33:22 +08002673void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002674{
2675 sdhci_reset_tuning(host);
2676
2677 sdhci_do_reset(host, SDHCI_RESET_CMD);
2678 sdhci_do_reset(host, SDHCI_RESET_DATA);
2679
2680 sdhci_end_tuning(host);
2681
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002682 mmc_abort_tuning(host->mmc, opcode);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002683}
Ben Chuang73537882019-08-27 08:33:22 +08002684EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002685
2686/*
2687 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2688 * tuning command does not have a data payload (or rather the hardware does it
2689 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2690 * interrupt setup is different to other commands and there is no timeout
2691 * interrupt so special handling is needed.
2692 */
ernest.zhang6663c412018-07-16 14:26:53 +08002693void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002694{
2695 struct mmc_host *mmc = host->mmc;
Masahiro Yamadac7836d12016-12-19 20:51:18 +09002696 struct mmc_command cmd = {};
2697 struct mmc_request mrq = {};
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002698 unsigned long flags;
Srinivas Kandagatlac846a002017-08-03 14:46:13 +02002699 u32 b = host->sdma_boundary;
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002700
2701 spin_lock_irqsave(&host->lock, flags);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002702
2703 cmd.opcode = opcode;
2704 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2705 cmd.mrq = &mrq;
2706
2707 mrq.cmd = &cmd;
2708 /*
2709 * In response to CMD19, the card sends 64 bytes of tuning
2710 * block to the Host Controller. So we set the block size
2711 * to 64 here.
2712 */
Adrian Hunter85336102016-12-02 15:14:26 +02002713 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2714 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
Srinivas Kandagatlac846a002017-08-03 14:46:13 +02002715 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
Adrian Hunter85336102016-12-02 15:14:26 +02002716 else
Srinivas Kandagatlac846a002017-08-03 14:46:13 +02002717 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002718
2719 /*
2720 * The tuning block is sent by the card to the host controller.
2721 * So we set the TRNS_READ bit in the Transfer Mode register.
2722 * This also takes care of setting DMA Enable and Multi Block
2723 * Select in the same register to 0.
2724 */
2725 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2726
Adrian Hunter845c9392020-04-12 12:03:49 +03002727 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2728 spin_unlock_irqrestore(&host->lock, flags);
2729 host->tuning_done = 0;
2730 return;
2731 }
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002732
2733 host->cmd = NULL;
2734
2735 sdhci_del_timer(host, &mrq);
2736
2737 host->tuning_done = 0;
2738
2739 spin_unlock_irqrestore(&host->lock, flags);
2740
2741 /* Wait for Buffer Read Ready interrupt */
2742 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2743 msecs_to_jiffies(50));
2744
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002745}
ernest.zhang6663c412018-07-16 14:26:53 +08002746EXPORT_SYMBOL_GPL(sdhci_send_tuning);
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002747
Yinbo Zhu7d8bb1f2018-08-23 16:48:31 +08002748static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
Adrian Hunter6b11e702016-12-02 15:14:27 +02002749{
2750 int i;
2751
2752 /*
2753 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
Sowjanya Komatineni1d8cd0652019-03-23 21:45:19 -07002754 * of loops reaches tuning loop count.
Adrian Hunter6b11e702016-12-02 15:14:27 +02002755 */
Sowjanya Komatineni1d8cd0652019-03-23 21:45:19 -07002756 for (i = 0; i < host->tuning_loop_count; i++) {
Adrian Hunter6b11e702016-12-02 15:14:27 +02002757 u16 ctrl;
2758
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002759 sdhci_send_tuning(host, opcode);
Adrian Hunter6b11e702016-12-02 15:14:27 +02002760
2761 if (!host->tuning_done) {
Faiz Abbas811ba672019-12-06 17:13:26 +05302762 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2763 mmc_hostname(host->mmc));
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002764 sdhci_abort_tuning(host, opcode);
Yinbo Zhu7d8bb1f2018-08-23 16:48:31 +08002765 return -ETIMEDOUT;
Adrian Hunter6b11e702016-12-02 15:14:27 +02002766 }
2767
BOUGH CHEN2b06e152018-12-28 08:35:49 +00002768 /* Spec does not require a delay between tuning cycles */
2769 if (host->tuning_delay > 0)
2770 mdelay(host->tuning_delay);
2771
Adrian Hunter6b11e702016-12-02 15:14:27 +02002772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2773 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2774 if (ctrl & SDHCI_CTRL_TUNED_CLK)
Yinbo Zhu7d8bb1f2018-08-23 16:48:31 +08002775 return 0; /* Success! */
Adrian Hunter6b11e702016-12-02 15:14:27 +02002776 break;
2777 }
2778
Adrian Hunter6b11e702016-12-02 15:14:27 +02002779 }
2780
2781 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2782 mmc_hostname(host->mmc));
2783 sdhci_reset_tuning(host);
Yinbo Zhu7d8bb1f2018-08-23 16:48:31 +08002784 return -EAGAIN;
Adrian Hunter6b11e702016-12-02 15:14:27 +02002785}
2786
Masahiro Yamada85a882c2016-12-08 21:50:54 +09002787int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
Arindam Nathb513ea22011-05-05 12:19:04 +05302788{
Russell King4b6f37d2014-04-25 12:59:36 +01002789 struct sdhci_host *host = mmc_priv(mmc);
Arindam Nathb513ea22011-05-05 12:19:04 +05302790 int err = 0;
Adrian Hunter38e40bf2014-12-05 19:25:30 +02002791 unsigned int tuning_count = 0;
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002792 bool hs400_tuning;
Arindam Nathb513ea22011-05-05 12:19:04 +05302793
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002794 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002795
Adrian Hunter38e40bf2014-12-05 19:25:30 +02002796 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2797 tuning_count = host->tuning_count;
2798
Arindam Nathb513ea22011-05-05 12:19:04 +05302799 /*
Weijun Yang9faac7b2015-10-04 12:04:12 +00002800 * The Host Controller needs tuning in case of SDR104 and DDR50
2801 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2802 * the Capabilities register.
Girish K S069c9f12012-01-06 09:56:39 +05302803 * If the Host Controller supports the HS200 mode then the
2804 * tuning function has to be executed.
Arindam Nathb513ea22011-05-05 12:19:04 +05302805 */
Russell King4b6f37d2014-04-25 12:59:36 +01002806 switch (host->timing) {
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002807 /* HS400 tuning is done in HS200 mode */
Adrian Huntere9fb05d2014-11-06 15:19:06 +02002808 case MMC_TIMING_MMC_HS400:
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002809 err = -EINVAL;
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002810 goto out;
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002811
Russell King4b6f37d2014-04-25 12:59:36 +01002812 case MMC_TIMING_MMC_HS200:
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002813 /*
2814 * Periodic re-tuning for HS400 is not expected to be needed, so
2815 * disable it here.
2816 */
2817 if (hs400_tuning)
2818 tuning_count = 0;
2819 break;
2820
Russell King4b6f37d2014-04-25 12:59:36 +01002821 case MMC_TIMING_UHS_SDR104:
Weijun Yang9faac7b2015-10-04 12:04:12 +00002822 case MMC_TIMING_UHS_DDR50:
Russell King4b6f37d2014-04-25 12:59:36 +01002823 break;
Girish K S069c9f12012-01-06 09:56:39 +05302824
Russell King4b6f37d2014-04-25 12:59:36 +01002825 case MMC_TIMING_UHS_SDR50:
Adrian Hunter4228b212016-04-20 09:24:03 +03002826 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
Russell King4b6f37d2014-04-25 12:59:36 +01002827 break;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -05002828 fallthrough;
Russell King4b6f37d2014-04-25 12:59:36 +01002829
2830 default:
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002831 goto out;
Arindam Nathb513ea22011-05-05 12:19:04 +05302832 }
2833
Dong Aisheng45251812013-09-13 19:11:30 +08002834 if (host->ops->platform_execute_tuning) {
Ritesh Harjani8a8fa872017-01-10 12:30:50 +05302835 err = host->ops->platform_execute_tuning(host, opcode);
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002836 goto out;
Dong Aisheng45251812013-09-13 19:11:30 +08002837 }
2838
Adrian Hunter6b11e702016-12-02 15:14:27 +02002839 host->mmc->retune_period = tuning_count;
2840
Adrian Hunter83b600b2017-04-20 16:14:43 +08002841 if (host->tuning_delay < 0)
2842 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2843
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002844 sdhci_start_tuning(host);
Arindam Nathb513ea22011-05-05 12:19:04 +05302845
Yinbo Zhu7d8bb1f2018-08-23 16:48:31 +08002846 host->tuning_err = __sdhci_execute_tuning(host, opcode);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302847
Adrian Hunterda4bc4f2016-12-02 15:59:23 +02002848 sdhci_end_tuning(host);
Adrian Hunter2a85ef22017-03-20 19:50:38 +02002849out:
Ritesh Harjani8a8fa872017-01-10 12:30:50 +05302850 host->flags &= ~SDHCI_HS400_TUNING;
Adrian Hunter6b11e702016-12-02 15:14:27 +02002851
Arindam Nathb513ea22011-05-05 12:19:04 +05302852 return err;
2853}
Masahiro Yamada85a882c2016-12-08 21:50:54 +09002854EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
Arindam Nathb513ea22011-05-05 12:19:04 +05302855
Kevin Liu52983382013-01-31 11:31:37 +08002856static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
Arindam Nath4d55c5a2011-05-05 12:19:05 +05302857{
Arindam Nath4d55c5a2011-05-05 12:19:05 +05302858 /* Host Controller v3.00 defines preset value registers */
2859 if (host->version < SDHCI_SPEC_300)
2860 return;
2861
Arindam Nath4d55c5a2011-05-05 12:19:05 +05302862 /*
2863 * We only enable or disable Preset Value if they are not already
2864 * enabled or disabled respectively. Otherwise, we bail out.
2865 */
Russell Kingda91a8f2014-04-25 13:00:12 +01002866 if (host->preset_enabled != enable) {
2867 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2868
2869 if (enable)
2870 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2871 else
2872 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2873
Arindam Nath4d55c5a2011-05-05 12:19:05 +05302874 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Russell Kingda91a8f2014-04-25 13:00:12 +01002875
2876 if (enable)
2877 host->flags |= SDHCI_PV_ENABLED;
2878 else
2879 host->flags &= ~SDHCI_PV_ENABLED;
2880
2881 host->preset_enabled = enable;
Arindam Nath4d55c5a2011-05-05 12:19:05 +05302882 }
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002883}
2884
Haibo Chen348487c2014-12-09 17:04:05 +08002885static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2886 int err)
2887{
2888 struct sdhci_host *host = mmc_priv(mmc);
2889 struct mmc_data *data = mrq->data;
2890
Russell Kingf48f0392016-01-26 13:40:32 +00002891 if (data->host_cookie != COOKIE_UNMAPPED)
Russell King771a3dc2016-01-26 13:40:53 +00002892 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
Heiner Kallweitfeeef092017-03-26 20:45:56 +02002893 mmc_get_dma_dir(data));
Russell King771a3dc2016-01-26 13:40:53 +00002894
2895 data->host_cookie = COOKIE_UNMAPPED;
Haibo Chen348487c2014-12-09 17:04:05 +08002896}
2897
Linus Walleijd3c6aac2016-11-23 11:02:24 +01002898static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
Haibo Chen348487c2014-12-09 17:04:05 +08002899{
2900 struct sdhci_host *host = mmc_priv(mmc);
2901
Haibo Chend31911b2015-08-25 10:02:11 +08002902 mrq->data->host_cookie = COOKIE_UNMAPPED;
Haibo Chen348487c2014-12-09 17:04:05 +08002903
Linus Walleijbd9b9022018-01-29 00:44:53 +01002904 /*
2905 * No pre-mapping in the pre hook if we're using the bounce buffer,
2906 * for that we would need two bounce buffers since one buffer is
2907 * in flight when this is getting called.
2908 */
2909 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
Russell King94538e52016-01-26 13:40:37 +00002910 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
Haibo Chen348487c2014-12-09 17:04:05 +08002911}
2912
Adrian Hunter5d0d11c2016-06-29 16:24:31 +03002913static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2914{
2915 if (host->data_cmd) {
2916 host->data_cmd->error = err;
2917 sdhci_finish_mrq(host, host->data_cmd->mrq);
2918 }
2919
2920 if (host->cmd) {
2921 host->cmd->error = err;
2922 sdhci_finish_mrq(host, host->cmd->mrq);
2923 }
2924}
2925
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002926static void sdhci_card_event(struct mmc_host *mmc)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002927{
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002928 struct sdhci_host *host = mmc_priv(mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002929 unsigned long flags;
Krzysztof Kozlowski28367662015-01-05 10:50:15 +01002930 int present;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002931
Christian Daudt722e1282013-06-20 14:26:36 -07002932 /* First check if client has provided their own card event */
2933 if (host->ops->card_event)
2934 host->ops->card_event(host);
2935
Adrian Hunterd3940f22016-06-29 16:24:14 +03002936 present = mmc->ops->get_cd(mmc);
Krzysztof Kozlowski28367662015-01-05 10:50:15 +01002937
Pierre Ossmand129bce2006-03-24 03:18:17 -08002938 spin_lock_irqsave(&host->lock, flags);
2939
Adrian Hunter5d0d11c2016-06-29 16:24:31 +03002940 /* Check sdhci_has_requests() first in case we are runtime suspended */
2941 if (sdhci_has_requests(host) && !present) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302942 pr_err("%s: Card removed during transfer!\n",
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002943 mmc_hostname(host->mmc));
Girish K Sa3c76eb2011-10-11 11:44:09 +05302944 pr_err("%s: Resetting controller.\n",
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002945 mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08002946
Russell King03231f92014-04-25 12:57:12 +01002947 sdhci_do_reset(host, SDHCI_RESET_CMD);
2948 sdhci_do_reset(host, SDHCI_RESET_DATA);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002949
Adrian Hunter5d0d11c2016-06-29 16:24:31 +03002950 sdhci_error_out_mrqs(host, -ENOMEDIUM);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002951 }
2952
2953 spin_unlock_irqrestore(&host->lock, flags);
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002954}
2955
2956static const struct mmc_host_ops sdhci_ops = {
2957 .request = sdhci_request,
Haibo Chen348487c2014-12-09 17:04:05 +08002958 .post_req = sdhci_post_req,
2959 .pre_req = sdhci_pre_req,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002960 .set_ios = sdhci_set_ios,
Kevin Liu94144a42013-02-28 17:35:53 +08002961 .get_cd = sdhci_get_cd,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002962 .get_ro = sdhci_get_ro,
2963 .hw_reset = sdhci_hw_reset,
2964 .enable_sdio_irq = sdhci_enable_sdio_irq,
Adrian Hunter89f3c362019-05-27 14:45:55 +03002965 .ack_sdio_irq = sdhci_ack_sdio_irq,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002966 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
Adrian Hunterb5540ce2014-12-05 19:25:31 +02002967 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002968 .execute_tuning = sdhci_execute_tuning,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002969 .card_event = sdhci_card_event,
Kevin Liu20b92a32012-12-17 19:29:26 +08002970 .card_busy = sdhci_card_busy,
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002971};
2972
2973/*****************************************************************************\
2974 * *
Adrian Hunterc07a48c2019-04-05 15:40:20 +03002975 * Request done *
Guennadi Liakhovetski71e69212012-12-04 16:51:40 +01002976 * *
2977\*****************************************************************************/
2978
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03002979static bool sdhci_request_done(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002980{
Pierre Ossmand129bce2006-03-24 03:18:17 -08002981 unsigned long flags;
2982 struct mmc_request *mrq;
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03002983 int i;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002984
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002985 spin_lock_irqsave(&host->lock, flags);
2986
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03002987 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2988 mrq = host->mrqs_done[i];
Adrian Hunter6ebebea2016-11-02 15:49:08 +02002989 if (mrq)
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03002990 break;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002991 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002992
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03002993 if (!mrq) {
2994 spin_unlock_irqrestore(&host->lock, flags);
2995 return true;
2996 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002997
Pierre Ossmand129bce2006-03-24 03:18:17 -08002998 /*
Russell King054cedf2016-01-26 13:40:42 +00002999 * Always unmap the data buffers if they were mapped by
3000 * sdhci_prepare_data() whenever we finish with a request.
3001 * This avoids leaking DMA mappings on error.
3002 */
3003 if (host->flags & SDHCI_REQ_USE_DMA) {
3004 struct mmc_data *data = mrq->data;
3005
Chunyan Zhang18e762e2020-01-16 16:21:47 +05303006 if (host->use_external_dma && data &&
3007 (mrq->cmd->error || data->error)) {
3008 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3009
3010 host->mrqs_done[i] = NULL;
3011 spin_unlock_irqrestore(&host->lock, flags);
3012 dmaengine_terminate_sync(chan);
3013 spin_lock_irqsave(&host->lock, flags);
3014 sdhci_set_mrq_done(host, mrq);
3015 }
3016
Russell King054cedf2016-01-26 13:40:42 +00003017 if (data && data->host_cookie == COOKIE_MAPPED) {
Linus Walleijbd9b9022018-01-29 00:44:53 +01003018 if (host->bounce_buffer) {
3019 /*
3020 * On reads, copy the bounced data into the
3021 * sglist
3022 */
3023 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3024 unsigned int length = data->bytes_xfered;
3025
3026 if (length > host->bounce_buffer_size) {
3027 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3028 mmc_hostname(host->mmc),
3029 host->bounce_buffer_size,
3030 data->bytes_xfered);
3031 /* Cap it down and continue */
3032 length = host->bounce_buffer_size;
3033 }
3034 dma_sync_single_for_cpu(
3035 host->mmc->parent,
3036 host->bounce_addr,
3037 host->bounce_buffer_size,
3038 DMA_FROM_DEVICE);
3039 sg_copy_from_buffer(data->sg,
3040 data->sg_len,
3041 host->bounce_buffer,
3042 length);
3043 } else {
3044 /* No copying, just switch ownership */
3045 dma_sync_single_for_cpu(
3046 host->mmc->parent,
3047 host->bounce_addr,
3048 host->bounce_buffer_size,
3049 mmc_get_dma_dir(data));
3050 }
3051 } else {
3052 /* Unmap the raw data */
3053 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3054 data->sg_len,
3055 mmc_get_dma_dir(data));
3056 }
Russell King054cedf2016-01-26 13:40:42 +00003057 data->host_cookie = COOKIE_UNMAPPED;
3058 }
3059 }
3060
3061 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08003062 * The controller needs a reset of internal state machines
3063 * upon error conditions.
3064 */
Adrian Hunter0cc563c2016-06-29 16:24:28 +03003065 if (sdhci_needs_reset(host, mrq)) {
Adrian Hunter6ebebea2016-11-02 15:49:08 +02003066 /*
3067 * Do not finish until command and data lines are available for
3068 * reset. Note there can only be one other mrq, so it cannot
3069 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3070 * would both be null.
3071 */
3072 if (host->cmd || host->data_cmd) {
3073 spin_unlock_irqrestore(&host->lock, flags);
3074 return true;
3075 }
3076
Pierre Ossman645289d2006-06-30 02:22:33 -07003077 /* Some controllers need this kick or reset won't work here */
Andy Shevchenko8213af32013-01-07 16:31:08 +02003078 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
Pierre Ossman645289d2006-06-30 02:22:33 -07003079 /* This is to force an update */
Russell King17710592014-04-25 12:58:55 +01003080 host->ops->set_clock(host, host->clock);
Pierre Ossman645289d2006-06-30 02:22:33 -07003081
3082 /* Spec says we should do both at the same time, but Ricoh
3083 controllers do not like that. */
Adrian Hunter6ebebea2016-11-02 15:49:08 +02003084 sdhci_do_reset(host, SDHCI_RESET_CMD);
3085 sdhci_do_reset(host, SDHCI_RESET_DATA);
Adrian Huntered1563d2016-06-29 16:24:29 +03003086
3087 host->pending_reset = false;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003088 }
3089
Adrian Hunter6ebebea2016-11-02 15:49:08 +02003090 host->mrqs_done[i] = NULL;
3091
Pierre Ossmand129bce2006-03-24 03:18:17 -08003092 spin_unlock_irqrestore(&host->lock, flags);
3093
Baolin Wang1774b002020-02-12 12:12:58 +08003094 if (host->ops->request_done)
3095 host->ops->request_done(host, mrq);
3096 else
3097 mmc_request_done(host->mmc, mrq);
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03003098
3099 return false;
3100}
3101
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003102static void sdhci_complete_work(struct work_struct *work)
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03003103{
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003104 struct sdhci_host *host = container_of(work, struct sdhci_host,
3105 complete_work);
Adrian Hunter4e9f8fe2016-06-29 16:24:34 +03003106
3107 while (!sdhci_request_done(host))
3108 ;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003109}
3110
Kees Cook2ee4f622017-10-24 08:03:45 -07003111static void sdhci_timeout_timer(struct timer_list *t)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003112{
3113 struct sdhci_host *host;
3114 unsigned long flags;
3115
Kees Cook2ee4f622017-10-24 08:03:45 -07003116 host = from_timer(host, t, timer);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003117
3118 spin_lock_irqsave(&host->lock, flags);
3119
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003120 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3121 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3122 mmc_hostname(host->mmc));
3123 sdhci_dumpregs(host);
3124
3125 host->cmd->error = -ETIMEDOUT;
3126 sdhci_finish_mrq(host, host->cmd->mrq);
3127 }
3128
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003129 spin_unlock_irqrestore(&host->lock, flags);
3130}
3131
Kees Cook2ee4f622017-10-24 08:03:45 -07003132static void sdhci_timeout_data_timer(struct timer_list *t)
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003133{
3134 struct sdhci_host *host;
3135 unsigned long flags;
3136
Kees Cook2ee4f622017-10-24 08:03:45 -07003137 host = from_timer(host, t, data_timer);
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003138
3139 spin_lock_irqsave(&host->lock, flags);
3140
3141 if (host->data || host->data_cmd ||
3142 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01003143 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3144 mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08003145 sdhci_dumpregs(host);
3146
3147 if (host->data) {
Pierre Ossman17b04292007-07-22 22:18:46 +02003148 host->data->error = -ETIMEDOUT;
Adrian Hunter845c9392020-04-12 12:03:49 +03003149 __sdhci_finish_data(host, true);
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003150 queue_work(host->complete_wq, &host->complete_work);
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003151 } else if (host->data_cmd) {
3152 host->data_cmd->error = -ETIMEDOUT;
3153 sdhci_finish_mrq(host, host->data_cmd->mrq);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003154 } else {
Adrian Hunterd7422fb2016-06-29 16:24:33 +03003155 host->cmd->error = -ETIMEDOUT;
3156 sdhci_finish_mrq(host, host->cmd->mrq);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003157 }
3158 }
3159
3160 spin_unlock_irqrestore(&host->lock, flags);
3161}
3162
3163/*****************************************************************************\
3164 * *
3165 * Interrupt handling *
3166 * *
3167\*****************************************************************************/
3168
Adrian Hunter4bf78092018-11-15 15:53:41 +02003169static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003170{
Adrian Hunteraf849c82018-11-15 15:53:43 +02003171 /* Handle auto-CMD12 error */
3172 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3173 struct mmc_request *mrq = host->data_cmd->mrq;
3174 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3175 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3176 SDHCI_INT_DATA_TIMEOUT :
3177 SDHCI_INT_DATA_CRC;
3178
3179 /* Treat auto-CMD12 error the same as data error */
3180 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3181 *intmask_p |= data_err_bit;
3182 return;
3183 }
3184 }
3185
Pierre Ossmand129bce2006-03-24 03:18:17 -08003186 if (!host->cmd) {
Adrian Huntered1563d2016-06-29 16:24:29 +03003187 /*
3188 * SDHCI recovers from errors by resetting the cmd and data
3189 * circuits. Until that is done, there very well might be more
3190 * interrupts, so ignore them in that case.
3191 */
3192 if (host->pending_reset)
3193 return;
Marek Vasut2e4456f2015-11-18 10:47:02 +01003194 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3195 mmc_hostname(host->mmc), (unsigned)intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003196 sdhci_dumpregs(host);
3197 return;
3198 }
3199
Russell Kingec014cb2016-01-26 13:39:39 +00003200 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3201 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3202 if (intmask & SDHCI_INT_TIMEOUT)
3203 host->cmd->error = -ETIMEDOUT;
3204 else
3205 host->cmd->error = -EILSEQ;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003206
Adrian Hunter4bf78092018-11-15 15:53:41 +02003207 /* Treat data command CRC error the same as data CRC error */
Russell King71fcbda2016-01-26 13:39:45 +00003208 if (host->cmd->data &&
3209 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3210 SDHCI_INT_CRC) {
3211 host->cmd = NULL;
Adrian Hunter4bf78092018-11-15 15:53:41 +02003212 *intmask_p |= SDHCI_INT_DATA_CRC;
Russell King71fcbda2016-01-26 13:39:45 +00003213 return;
3214 }
3215
Adrian Hunter19d2f692019-04-05 15:40:19 +03003216 __sdhci_finish_mrq(host, host->cmd->mrq);
Pierre Ossmane8095172008-07-25 01:09:08 +02003217 return;
3218 }
3219
Adrian Hunteraf849c82018-11-15 15:53:43 +02003220 /* Handle auto-CMD23 error */
3221 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3222 struct mmc_request *mrq = host->cmd->mrq;
3223 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3224 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3225 -ETIMEDOUT :
3226 -EILSEQ;
3227
3228 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3229 mrq->sbc->error = err;
Adrian Hunter19d2f692019-04-05 15:40:19 +03003230 __sdhci_finish_mrq(host, mrq);
Adrian Hunteraf849c82018-11-15 15:53:43 +02003231 return;
3232 }
3233 }
3234
Pierre Ossmane8095172008-07-25 01:09:08 +02003235 if (intmask & SDHCI_INT_RESPONSE)
Pierre Ossman43b58b32007-07-25 23:15:27 +02003236 sdhci_finish_command(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003237}
3238
Adrian Hunter08621b12014-11-04 12:42:38 +02003239static void sdhci_adma_show_error(struct sdhci_host *host)
Ben Dooks6882a8c2009-06-14 13:52:38 +01003240{
Adrian Hunter1c3d5f62014-11-04 12:42:41 +02003241 void *desc = host->adma_table;
Russell Kingd1c536e2019-09-22 11:26:53 +01003242 dma_addr_t dma = host->adma_addr;
Ben Dooks6882a8c2009-06-14 13:52:38 +01003243
3244 sdhci_dumpregs(host);
3245
3246 while (true) {
Adrian Huntere57a5f62014-11-04 12:42:46 +02003247 struct sdhci_adma2_64_desc *dma_desc = desc;
Ben Dooks6882a8c2009-06-14 13:52:38 +01003248
Adrian Huntere57a5f62014-11-04 12:42:46 +02003249 if (host->flags & SDHCI_USE_64_BIT_DMA)
Russell Kingd1c536e2019-09-22 11:26:53 +01003250 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3251 (unsigned long long)dma,
3252 le32_to_cpu(dma_desc->addr_hi),
Adrian Huntere57a5f62014-11-04 12:42:46 +02003253 le32_to_cpu(dma_desc->addr_lo),
3254 le16_to_cpu(dma_desc->len),
3255 le16_to_cpu(dma_desc->cmd));
3256 else
Russell Kingd1c536e2019-09-22 11:26:53 +01003257 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3258 (unsigned long long)dma,
3259 le32_to_cpu(dma_desc->addr_lo),
Adrian Huntere57a5f62014-11-04 12:42:46 +02003260 le16_to_cpu(dma_desc->len),
3261 le16_to_cpu(dma_desc->cmd));
Ben Dooks6882a8c2009-06-14 13:52:38 +01003262
Adrian Hunter76fe3792014-11-04 12:42:42 +02003263 desc += host->desc_sz;
Russell Kingd1c536e2019-09-22 11:26:53 +01003264 dma += host->desc_sz;
Ben Dooks6882a8c2009-06-14 13:52:38 +01003265
Adrian Hunter05452302014-11-04 12:42:45 +02003266 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
Ben Dooks6882a8c2009-06-14 13:52:38 +01003267 break;
3268 }
3269}
Ben Dooks6882a8c2009-06-14 13:52:38 +01003270
Pierre Ossmand129bce2006-03-24 03:18:17 -08003271static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3272{
Girish K S069c9f12012-01-06 09:56:39 +05303273 u32 command;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003274
Arindam Nathb513ea22011-05-05 12:19:04 +05303275 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3276 if (intmask & SDHCI_INT_DATA_AVAIL) {
Girish K S069c9f12012-01-06 09:56:39 +05303277 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3278 if (command == MMC_SEND_TUNING_BLOCK ||
3279 command == MMC_SEND_TUNING_BLOCK_HS200) {
Arindam Nathb513ea22011-05-05 12:19:04 +05303280 host->tuning_done = 1;
3281 wake_up(&host->buf_ready_int);
3282 return;
3283 }
3284 }
3285
Pierre Ossmand129bce2006-03-24 03:18:17 -08003286 if (!host->data) {
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03003287 struct mmc_command *data_cmd = host->data_cmd;
3288
Pierre Ossmand129bce2006-03-24 03:18:17 -08003289 /*
Pierre Ossmane8095172008-07-25 01:09:08 +02003290 * The "data complete" interrupt is also used to
3291 * indicate that a busy state has ended. See comment
3292 * above in sdhci_cmd_irq().
Pierre Ossmand129bce2006-03-24 03:18:17 -08003293 */
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03003294 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
Matthieu CASTETc5abd5e2014-08-14 16:03:17 +02003295 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
Adrian Hunter69b962a2016-11-02 15:49:09 +02003296 host->data_cmd = NULL;
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03003297 data_cmd->error = -ETIMEDOUT;
Adrian Hunter19d2f692019-04-05 15:40:19 +03003298 __sdhci_finish_mrq(host, data_cmd->mrq);
Matthieu CASTETc5abd5e2014-08-14 16:03:17 +02003299 return;
3300 }
Pierre Ossmane8095172008-07-25 01:09:08 +02003301 if (intmask & SDHCI_INT_DATA_END) {
Adrian Hunter69b962a2016-11-02 15:49:09 +02003302 host->data_cmd = NULL;
Chanho Mine99783a2014-08-30 12:40:40 +09003303 /*
3304 * Some cards handle busy-end interrupt
3305 * before the command completed, so make
3306 * sure we do things in the proper order.
3307 */
Adrian Hunterea968022016-06-29 16:24:24 +03003308 if (host->cmd == data_cmd)
3309 return;
3310
Adrian Hunter19d2f692019-04-05 15:40:19 +03003311 __sdhci_finish_mrq(host, data_cmd->mrq);
Pierre Ossmane8095172008-07-25 01:09:08 +02003312 return;
3313 }
3314 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003315
Adrian Huntered1563d2016-06-29 16:24:29 +03003316 /*
3317 * SDHCI recovers from errors by resetting the cmd and data
3318 * circuits. Until that is done, there very well might be more
3319 * interrupts, so ignore them in that case.
3320 */
3321 if (host->pending_reset)
3322 return;
3323
Marek Vasut2e4456f2015-11-18 10:47:02 +01003324 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3325 mmc_hostname(host->mmc), (unsigned)intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003326 sdhci_dumpregs(host);
3327
3328 return;
3329 }
3330
3331 if (intmask & SDHCI_INT_DATA_TIMEOUT)
Pierre Ossman17b04292007-07-22 22:18:46 +02003332 host->data->error = -ETIMEDOUT;
Aries Lee22113ef2010-12-15 08:14:24 +01003333 else if (intmask & SDHCI_INT_DATA_END_BIT)
3334 host->data->error = -EILSEQ;
3335 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3336 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3337 != MMC_BUS_TEST_R)
Pierre Ossman17b04292007-07-22 22:18:46 +02003338 host->data->error = -EILSEQ;
Ben Dooks6882a8c2009-06-14 13:52:38 +01003339 else if (intmask & SDHCI_INT_ADMA_ERROR) {
Russell Kingd1c536e2019-09-22 11:26:53 +01003340 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3341 intmask);
Adrian Hunter08621b12014-11-04 12:42:38 +02003342 sdhci_adma_show_error(host);
Pierre Ossman2134a922008-06-28 18:28:51 +02003343 host->data->error = -EIO;
Haijun Zhanga4071fb2012-12-04 10:41:28 +08003344 if (host->ops->adma_workaround)
3345 host->ops->adma_workaround(host, intmask);
Ben Dooks6882a8c2009-06-14 13:52:38 +01003346 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003347
Pierre Ossman17b04292007-07-22 22:18:46 +02003348 if (host->data->error)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003349 sdhci_finish_data(host);
3350 else {
Pierre Ossmana406f5a2006-07-02 16:50:59 +01003351 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
Pierre Ossmand129bce2006-03-24 03:18:17 -08003352 sdhci_transfer_pio(host);
3353
Pierre Ossman6ba736a2007-05-13 22:39:23 +02003354 /*
3355 * We currently don't do anything fancy with DMA
3356 * boundaries, but as we can't disable the feature
3357 * we need to at least restart the transfer.
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04003358 *
3359 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3360 * should return a valid address to continue from, but as
3361 * some controllers are faulty, don't trust them.
Pierre Ossman6ba736a2007-05-13 22:39:23 +02003362 */
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04003363 if (intmask & SDHCI_INT_DMA_END) {
Chunyan Zhang917a0c52018-08-30 16:21:39 +08003364 dma_addr_t dmastart, dmanow;
Linus Walleijbd9b9022018-01-29 00:44:53 +01003365
3366 dmastart = sdhci_sdma_address(host);
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04003367 dmanow = dmastart + host->data->bytes_xfered;
3368 /*
3369 * Force update to the next DMA block boundary.
3370 */
3371 dmanow = (dmanow &
Chunyan Zhang917a0c52018-08-30 16:21:39 +08003372 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04003373 SDHCI_DEFAULT_BOUNDARY_SIZE;
3374 host->data->bytes_xfered = dmanow - dmastart;
Chunyan Zhang917a0c52018-08-30 16:21:39 +08003375 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3376 &dmastart, host->data->bytes_xfered, &dmanow);
3377 sdhci_set_sdma_addr(host, dmanow);
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04003378 }
Pierre Ossman6ba736a2007-05-13 22:39:23 +02003379
Pierre Ossmane538fbe2007-08-12 16:46:32 +02003380 if (intmask & SDHCI_INT_DATA_END) {
Adrian Hunter7c89a3d2016-06-29 16:24:23 +03003381 if (host->cmd == host->data_cmd) {
Pierre Ossmane538fbe2007-08-12 16:46:32 +02003382 /*
3383 * Data managed to finish before the
3384 * command completed. Make sure we do
3385 * things in the proper order.
3386 */
3387 host->data_early = 1;
3388 } else {
3389 sdhci_finish_data(host);
3390 }
3391 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003392 }
3393}
3394
Adrian Hunter19d2f692019-04-05 15:40:19 +03003395static inline bool sdhci_defer_done(struct sdhci_host *host,
3396 struct mmc_request *mrq)
3397{
3398 struct mmc_data *data = mrq->data;
3399
Baolin Wang47308312020-02-12 12:12:59 +08003400 return host->pending_reset || host->always_defer_done ||
Adrian Hunter19d2f692019-04-05 15:40:19 +03003401 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3402 data->host_cookie == COOKIE_MAPPED);
3403}
3404
David Howells7d12e782006-10-05 14:55:46 +01003405static irqreturn_t sdhci_irq(int irq, void *dev_id)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003406{
Adrian Hunter19d2f692019-04-05 15:40:19 +03003407 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
Russell King781e9892014-04-25 12:55:46 +01003408 irqreturn_t result = IRQ_NONE;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003409 struct sdhci_host *host = dev_id;
Russell King41005002014-04-25 12:55:36 +01003410 u32 intmask, mask, unexpected = 0;
Russell King781e9892014-04-25 12:55:46 +01003411 int max_loops = 16;
Adrian Hunter19d2f692019-04-05 15:40:19 +03003412 int i;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003413
3414 spin_lock(&host->lock);
3415
Ulf Hanssonaf5d2b72019-09-08 12:12:35 +02003416 if (host->runtime_suspended) {
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003417 spin_unlock(&host->lock);
Adrian Hunter655bca72014-03-11 10:09:36 +02003418 return IRQ_NONE;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003419 }
3420
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03003421 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
Mark Lord62df67a52007-03-06 13:30:13 +01003422 if (!intmask || intmask == 0xffffffff) {
Pierre Ossmand129bce2006-03-24 03:18:17 -08003423 result = IRQ_NONE;
3424 goto out;
3425 }
3426
Russell King41005002014-04-25 12:55:36 +01003427 do {
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003428 DBG("IRQ status 0x%08x\n", intmask);
3429
3430 if (host->ops->irq) {
3431 intmask = host->ops->irq(host, intmask);
3432 if (!intmask)
3433 goto cont;
3434 }
3435
Russell King41005002014-04-25 12:55:36 +01003436 /* Clear selected interrupts. */
3437 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3438 SDHCI_INT_BUS_POWER);
3439 sdhci_writel(host, mask, SDHCI_INT_STATUS);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003440
Russell King41005002014-04-25 12:55:36 +01003441 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3442 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3443 SDHCI_CARD_PRESENT;
3444
3445 /*
3446 * There is a observation on i.mx esdhc. INSERT
3447 * bit will be immediately set again when it gets
3448 * cleared, if a card is inserted. We have to mask
3449 * the irq to prevent interrupt storm which will
3450 * freeze the system. And the REMOVE gets the
3451 * same situation.
3452 *
3453 * More testing are needed here to ensure it works
3454 * for other platforms though.
3455 */
Russell Kingb537f942014-04-25 12:56:01 +01003456 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3457 SDHCI_INT_CARD_REMOVE);
3458 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3459 SDHCI_INT_CARD_INSERT;
3460 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3461 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Russell King41005002014-04-25 12:55:36 +01003462
3463 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3464 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
Russell King3560db82014-04-25 12:55:51 +01003465
3466 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3467 SDHCI_INT_CARD_REMOVE);
3468 result = IRQ_WAKE_THREAD;
Russell King41005002014-04-25 12:55:36 +01003469 }
3470
3471 if (intmask & SDHCI_INT_CMD_MASK)
Adrian Hunter4bf78092018-11-15 15:53:41 +02003472 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
Russell King41005002014-04-25 12:55:36 +01003473
3474 if (intmask & SDHCI_INT_DATA_MASK)
3475 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3476
3477 if (intmask & SDHCI_INT_BUS_POWER)
3478 pr_err("%s: Card is consuming too much power!\n",
3479 mmc_hostname(host->mmc));
3480
Dong Aishengf37b20e2016-07-12 15:46:17 +08003481 if (intmask & SDHCI_INT_RETUNE)
3482 mmc_retune_needed(host->mmc);
3483
Gabriel Krisman Bertazi161e6d42017-01-16 12:23:42 -02003484 if ((intmask & SDHCI_INT_CARD_INT) &&
3485 (host->ier & SDHCI_INT_CARD_INT)) {
Russell King781e9892014-04-25 12:55:46 +01003486 sdhci_enable_sdio_irq_nolock(host, false);
Adrian Hunter89f3c362019-05-27 14:45:55 +03003487 sdio_signal_irq(host->mmc);
Russell King781e9892014-04-25 12:55:46 +01003488 }
Russell King41005002014-04-25 12:55:36 +01003489
3490 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3491 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3492 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
Dong Aishengf37b20e2016-07-12 15:46:17 +08003493 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
Russell King41005002014-04-25 12:55:36 +01003494
3495 if (intmask) {
3496 unexpected |= intmask;
3497 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3498 }
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003499cont:
Russell King781e9892014-04-25 12:55:46 +01003500 if (result == IRQ_NONE)
3501 result = IRQ_HANDLED;
Russell King41005002014-04-25 12:55:36 +01003502
3503 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
Russell King41005002014-04-25 12:55:36 +01003504 } while (intmask && --max_loops);
Adrian Hunter19d2f692019-04-05 15:40:19 +03003505
3506 /* Determine if mrqs can be completed immediately */
3507 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3508 struct mmc_request *mrq = host->mrqs_done[i];
3509
3510 if (!mrq)
3511 continue;
3512
3513 if (sdhci_defer_done(host, mrq)) {
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003514 result = IRQ_WAKE_THREAD;
Adrian Hunter19d2f692019-04-05 15:40:19 +03003515 } else {
3516 mrqs_done[i] = mrq;
3517 host->mrqs_done[i] = NULL;
3518 }
3519 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003520out:
Adrian Hunter845c9392020-04-12 12:03:49 +03003521 if (host->deferred_cmd)
3522 result = IRQ_WAKE_THREAD;
3523
Pierre Ossmand129bce2006-03-24 03:18:17 -08003524 spin_unlock(&host->lock);
3525
Adrian Hunter19d2f692019-04-05 15:40:19 +03003526 /* Process mrqs ready for immediate completion */
3527 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
Baolin Wang1774b002020-02-12 12:12:58 +08003528 if (!mrqs_done[i])
3529 continue;
3530
3531 if (host->ops->request_done)
3532 host->ops->request_done(host, mrqs_done[i]);
3533 else
Adrian Hunter19d2f692019-04-05 15:40:19 +03003534 mmc_request_done(host->mmc, mrqs_done[i]);
3535 }
3536
Alexander Stein6379b232012-03-14 09:52:10 +01003537 if (unexpected) {
3538 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3539 mmc_hostname(host->mmc), unexpected);
3540 sdhci_dumpregs(host);
3541 }
Pierre Ossmanf75979b2007-09-04 07:59:18 +02003542
Pierre Ossmand129bce2006-03-24 03:18:17 -08003543 return result;
3544}
3545
Russell King781e9892014-04-25 12:55:46 +01003546static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3547{
3548 struct sdhci_host *host = dev_id;
Adrian Hunter845c9392020-04-12 12:03:49 +03003549 struct mmc_command *cmd;
Russell King781e9892014-04-25 12:55:46 +01003550 unsigned long flags;
3551 u32 isr;
3552
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003553 while (!sdhci_request_done(host))
3554 ;
3555
Russell King781e9892014-04-25 12:55:46 +01003556 spin_lock_irqsave(&host->lock, flags);
Adrian Hunter845c9392020-04-12 12:03:49 +03003557
Russell King781e9892014-04-25 12:55:46 +01003558 isr = host->thread_isr;
3559 host->thread_isr = 0;
Adrian Hunter845c9392020-04-12 12:03:49 +03003560
3561 cmd = host->deferred_cmd;
3562 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3563 sdhci_finish_mrq(host, cmd->mrq);
3564
Russell King781e9892014-04-25 12:55:46 +01003565 spin_unlock_irqrestore(&host->lock, flags);
3566
Russell King3560db82014-04-25 12:55:51 +01003567 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
Adrian Hunterd3940f22016-06-29 16:24:14 +03003568 struct mmc_host *mmc = host->mmc;
3569
3570 mmc->ops->card_event(mmc);
3571 mmc_detect_change(mmc, msecs_to_jiffies(200));
Russell King3560db82014-04-25 12:55:51 +01003572 }
3573
Adrian Hunterc07a48c2019-04-05 15:40:20 +03003574 return IRQ_HANDLED;
Russell King781e9892014-04-25 12:55:46 +01003575}
3576
Pierre Ossmand129bce2006-03-24 03:18:17 -08003577/*****************************************************************************\
3578 * *
3579 * Suspend/resume *
3580 * *
3581\*****************************************************************************/
3582
3583#ifdef CONFIG_PM
Adrian Hunter9c316b32018-02-27 14:51:23 +02003584
3585static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3586{
3587 return mmc_card_is_removable(host->mmc) &&
3588 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3589 !mmc_can_gpio_cd(host->mmc);
3590}
3591
Ludovic Desroches84d62602016-05-13 15:16:02 +02003592/*
3593 * To enable wakeup events, the corresponding events have to be enabled in
3594 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3595 * Table' in the SD Host Controller Standard Specification.
3596 * It is useless to restore SDHCI_INT_ENABLE state in
3597 * sdhci_disable_irq_wakeups() since it will be set by
3598 * sdhci_enable_card_detection() or sdhci_init().
3599 */
Adrian Hunter58e79b62018-01-09 09:52:21 +02003600static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
Kevin Liuad080d72013-01-05 17:21:33 +08003601{
Adrian Hunter81b14542018-01-09 09:52:22 +02003602 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3603 SDHCI_WAKE_ON_INT;
3604 u32 irq_val = 0;
3605 u8 wake_val = 0;
Kevin Liuad080d72013-01-05 17:21:33 +08003606 u8 val;
Adrian Hunter81b14542018-01-09 09:52:22 +02003607
Adrian Hunter9c316b32018-02-27 14:51:23 +02003608 if (sdhci_cd_irq_can_wakeup(host)) {
Adrian Hunter81b14542018-01-09 09:52:22 +02003609 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3610 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3611 }
3612
Adrian Hunterd5d568f2018-02-27 14:51:24 +02003613 if (mmc_card_wake_sdio_irq(host->mmc)) {
3614 wake_val |= SDHCI_WAKE_ON_INT;
3615 irq_val |= SDHCI_INT_CARD_INT;
3616 }
3617
3618 if (!irq_val)
3619 return false;
Kevin Liuad080d72013-01-05 17:21:33 +08003620
3621 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
Adrian Hunter81b14542018-01-09 09:52:22 +02003622 val &= ~mask;
3623 val |= wake_val;
Kevin Liuad080d72013-01-05 17:21:33 +08003624 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
Adrian Hunter81b14542018-01-09 09:52:22 +02003625
Ludovic Desroches84d62602016-05-13 15:16:02 +02003626 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
Adrian Hunter58e79b62018-01-09 09:52:21 +02003627
3628 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3629
3630 return host->irq_wake_enabled;
Kevin Liuad080d72013-01-05 17:21:33 +08003631}
Kevin Liuad080d72013-01-05 17:21:33 +08003632
Fabio Estevam0b10f472014-08-30 14:53:13 -03003633static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
Kevin Liuad080d72013-01-05 17:21:33 +08003634{
3635 u8 val;
3636 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3637 | SDHCI_WAKE_ON_INT;
3638
3639 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3640 val &= ~mask;
3641 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
Adrian Hunter58e79b62018-01-09 09:52:21 +02003642
3643 disable_irq_wake(host->irq);
3644
3645 host->irq_wake_enabled = false;
Kevin Liuad080d72013-01-05 17:21:33 +08003646}
Pierre Ossmand129bce2006-03-24 03:18:17 -08003647
Manuel Lauss29495aa2011-11-03 11:09:45 +01003648int sdhci_suspend_host(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003649{
Anton Vorontsov7260cf52009-03-17 00:13:48 +03003650 sdhci_disable_card_detection(host);
3651
Adrian Hunter66c39dfc2015-05-07 13:10:21 +03003652 mmc_retune_timer_stop(host->mmc);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05303653
Adrian Hunter58e79b62018-01-09 09:52:21 +02003654 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3655 !sdhci_enable_irq_wakeups(host)) {
Russell Kingb537f942014-04-25 12:56:01 +01003656 host->ier = 0;
3657 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3658 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
Kevin Liuad080d72013-01-05 17:21:33 +08003659 free_irq(host->irq, host);
Kevin Liuad080d72013-01-05 17:21:33 +08003660 }
Adrian Hunter58e79b62018-01-09 09:52:21 +02003661
Ulf Hansson4ee14ec2013-09-25 14:15:24 +02003662 return 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003663}
3664
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003665EXPORT_SYMBOL_GPL(sdhci_suspend_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003666
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003667int sdhci_resume_host(struct sdhci_host *host)
3668{
Adrian Hunterd3940f22016-06-29 16:24:14 +03003669 struct mmc_host *mmc = host->mmc;
Ulf Hansson4ee14ec2013-09-25 14:15:24 +02003670 int ret = 0;
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003671
Richard Röjforsa13abc72009-09-22 16:45:30 -07003672 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003673 if (host->ops->enable_dma)
3674 host->ops->enable_dma(host);
3675 }
3676
Adrian Hunter6308d292012-02-07 14:48:54 +02003677 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3678 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3679 /* Card keeps power but host controller does not */
3680 sdhci_init(host, 0);
3681 host->pwr = 0;
3682 host->clock = 0;
Adrian Hunterd3940f22016-06-29 16:24:14 +03003683 mmc->ops->set_ios(mmc, &mmc->ios);
Adrian Hunter6308d292012-02-07 14:48:54 +02003684 } else {
3685 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
Adrian Hunter6308d292012-02-07 14:48:54 +02003686 }
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003687
Adrian Hunter58e79b62018-01-09 09:52:21 +02003688 if (host->irq_wake_enabled) {
3689 sdhci_disable_irq_wakeups(host);
3690 } else {
Haibo Chen14a7b41642015-09-15 18:32:58 +08003691 ret = request_threaded_irq(host->irq, sdhci_irq,
3692 sdhci_thread_irq, IRQF_SHARED,
3693 mmc_hostname(host->mmc), host);
3694 if (ret)
3695 return ret;
Haibo Chen14a7b41642015-09-15 18:32:58 +08003696 }
3697
Anton Vorontsov7260cf52009-03-17 00:13:48 +03003698 sdhci_enable_card_detection(host);
3699
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -08003700 return ret;
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003701}
3702
3703EXPORT_SYMBOL_GPL(sdhci_resume_host);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003704
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003705int sdhci_runtime_suspend_host(struct sdhci_host *host)
3706{
3707 unsigned long flags;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003708
Adrian Hunter66c39dfc2015-05-07 13:10:21 +03003709 mmc_retune_timer_stop(host->mmc);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003710
3711 spin_lock_irqsave(&host->lock, flags);
Russell Kingb537f942014-04-25 12:56:01 +01003712 host->ier &= SDHCI_INT_CARD_INT;
3713 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3714 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003715 spin_unlock_irqrestore(&host->lock, flags);
3716
Russell King781e9892014-04-25 12:55:46 +01003717 synchronize_hardirq(host->irq);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003718
3719 spin_lock_irqsave(&host->lock, flags);
3720 host->runtime_suspended = true;
3721 spin_unlock_irqrestore(&host->lock, flags);
3722
Markus Pargmann8a125ba2014-06-04 15:24:29 +02003723 return 0;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003724}
3725EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3726
Baolin Wangc6303c52019-07-25 11:14:22 +08003727int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003728{
Adrian Hunterd3940f22016-06-29 16:24:14 +03003729 struct mmc_host *mmc = host->mmc;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003730 unsigned long flags;
Markus Pargmann8a125ba2014-06-04 15:24:29 +02003731 int host_flags = host->flags;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003732
3733 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3734 if (host->ops->enable_dma)
3735 host->ops->enable_dma(host);
3736 }
3737
Baolin Wangc6303c52019-07-25 11:14:22 +08003738 sdhci_init(host, soft_reset);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003739
Zhoujie Wu70bc85a2017-08-03 12:28:40 -07003740 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3741 mmc->ios.power_mode != MMC_POWER_OFF) {
Adrian Hunter84ec0482016-12-19 15:33:11 +02003742 /* Force clock and power re-program */
3743 host->pwr = 0;
3744 host->clock = 0;
3745 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3746 mmc->ops->set_ios(mmc, &mmc->ios);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003747
Adrian Hunter84ec0482016-12-19 15:33:11 +02003748 if ((host_flags & SDHCI_PV_ENABLED) &&
3749 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3750 spin_lock_irqsave(&host->lock, flags);
3751 sdhci_enable_preset_value(host, true);
3752 spin_unlock_irqrestore(&host->lock, flags);
3753 }
3754
3755 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3756 mmc->ops->hs400_enhanced_strobe)
3757 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
Kevin Liu52983382013-01-31 11:31:37 +08003758 }
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003759
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003760 spin_lock_irqsave(&host->lock, flags);
3761
3762 host->runtime_suspended = false;
3763
3764 /* Enable SDIO IRQ */
Ulf Hansson0e626142019-09-08 12:12:36 +02003765 if (sdio_irq_claimed(mmc))
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003766 sdhci_enable_sdio_irq_nolock(host, true);
3767
3768 /* Enable Card Detection */
3769 sdhci_enable_card_detection(host);
3770
3771 spin_unlock_irqrestore(&host->lock, flags);
3772
Markus Pargmann8a125ba2014-06-04 15:24:29 +02003773 return 0;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003774}
3775EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3776
Rafael J. Wysocki162d6f92014-12-05 03:05:33 +01003777#endif /* CONFIG_PM */
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003778
Pierre Ossmand129bce2006-03-24 03:18:17 -08003779/*****************************************************************************\
3780 * *
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003781 * Command Queue Engine (CQE) helpers *
3782 * *
3783\*****************************************************************************/
3784
3785void sdhci_cqe_enable(struct mmc_host *mmc)
3786{
3787 struct sdhci_host *host = mmc_priv(mmc);
3788 unsigned long flags;
3789 u8 ctrl;
3790
3791 spin_lock_irqsave(&host->lock, flags);
3792
3793 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3794 ctrl &= ~SDHCI_CTRL_DMA_MASK;
Sowjanya Komatineni4c4faff2019-01-23 11:30:53 -08003795 /*
3796 * Host from V4.10 supports ADMA3 DMA type.
3797 * ADMA3 performs integrated descriptor which is more suitable
3798 * for cmd queuing to fetch both command and transfer descriptors.
3799 */
3800 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3801 ctrl |= SDHCI_CTRL_ADMA3;
3802 else if (host->flags & SDHCI_USE_64_BIT_DMA)
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003803 ctrl |= SDHCI_CTRL_ADMA64;
3804 else
3805 ctrl |= SDHCI_CTRL_ADMA32;
3806 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3807
Srinivas Kandagatlac846a002017-08-03 14:46:13 +02003808 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003809 SDHCI_BLOCK_SIZE);
3810
3811 /* Set maximum timeout */
BOUGH CHEN401059d2019-01-07 10:11:36 +00003812 sdhci_set_timeout(host, NULL);
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003813
3814 host->ier = host->cqe_ier;
3815
3816 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3817 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3818
3819 host->cqe_on = true;
3820
3821 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3822 mmc_hostname(mmc), host->ier,
3823 sdhci_readl(host, SDHCI_INT_STATUS));
3824
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003825 spin_unlock_irqrestore(&host->lock, flags);
3826}
3827EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3828
3829void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3830{
3831 struct sdhci_host *host = mmc_priv(mmc);
3832 unsigned long flags;
3833
3834 spin_lock_irqsave(&host->lock, flags);
3835
3836 sdhci_set_default_irqs(host);
3837
3838 host->cqe_on = false;
3839
3840 if (recovery) {
3841 sdhci_do_reset(host, SDHCI_RESET_CMD);
3842 sdhci_do_reset(host, SDHCI_RESET_DATA);
3843 }
3844
3845 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3846 mmc_hostname(mmc), host->ier,
3847 sdhci_readl(host, SDHCI_INT_STATUS));
3848
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003849 spin_unlock_irqrestore(&host->lock, flags);
3850}
3851EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3852
3853bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3854 int *data_error)
3855{
3856 u32 mask;
3857
3858 if (!host->cqe_on)
3859 return false;
3860
3861 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3862 *cmd_error = -EILSEQ;
3863 else if (intmask & SDHCI_INT_TIMEOUT)
3864 *cmd_error = -ETIMEDOUT;
3865 else
3866 *cmd_error = 0;
3867
3868 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3869 *data_error = -EILSEQ;
3870 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3871 *data_error = -ETIMEDOUT;
3872 else if (intmask & SDHCI_INT_ADMA_ERROR)
3873 *data_error = -EIO;
3874 else
3875 *data_error = 0;
3876
3877 /* Clear selected interrupts. */
3878 mask = intmask & host->cqe_ier;
3879 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3880
3881 if (intmask & SDHCI_INT_BUS_POWER)
3882 pr_err("%s: Card is consuming too much power!\n",
3883 mmc_hostname(host->mmc));
3884
3885 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3886 if (intmask) {
3887 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3888 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3889 mmc_hostname(host->mmc), intmask);
3890 sdhci_dumpregs(host);
3891 }
3892
3893 return true;
3894}
3895EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3896
3897/*****************************************************************************\
3898 * *
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003899 * Device allocation/registration *
Pierre Ossmand129bce2006-03-24 03:18:17 -08003900 * *
3901\*****************************************************************************/
3902
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003903struct sdhci_host *sdhci_alloc_host(struct device *dev,
3904 size_t priv_size)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003905{
Pierre Ossmand129bce2006-03-24 03:18:17 -08003906 struct mmc_host *mmc;
3907 struct sdhci_host *host;
3908
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003909 WARN_ON(dev == NULL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003910
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003911 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003912 if (!mmc)
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003913 return ERR_PTR(-ENOMEM);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003914
3915 host = mmc_priv(mmc);
3916 host->mmc = mmc;
Adrian Hunterbf60e592016-02-09 16:12:35 +02003917 host->mmc_host_ops = sdhci_ops;
3918 mmc->ops = &host->mmc_host_ops;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003919
Adrian Hunter8cb851a2016-06-29 16:24:16 +03003920 host->flags = SDHCI_SIGNALING_330;
3921
Adrian Hunterf12e39d2017-03-20 19:50:47 +02003922 host->cqe_ier = SDHCI_CQE_INT_MASK;
3923 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3924
Adrian Hunter83b600b2017-04-20 16:14:43 +08003925 host->tuning_delay = -1;
Sowjanya Komatineni1d8cd0652019-03-23 21:45:19 -07003926 host->tuning_loop_count = MAX_TUNING_LOOP;
Adrian Hunter83b600b2017-04-20 16:14:43 +08003927
Srinivas Kandagatlac846a002017-08-03 14:46:13 +02003928 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3929
Jisheng Zhange93be382018-08-28 17:46:35 +08003930 /*
3931 * The DMA table descriptor count is calculated as the maximum
3932 * number of segments times 2, to allow for an alignment
3933 * descriptor for each segment, plus 1 for a nop end descriptor.
3934 */
3935 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3936
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003937 return host;
3938}
Pierre Ossman8a4da142006-10-04 02:15:40 -07003939
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003940EXPORT_SYMBOL_GPL(sdhci_alloc_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003941
Alexandre Courbot7b913692016-03-07 11:07:55 +09003942static int sdhci_set_dma_mask(struct sdhci_host *host)
3943{
3944 struct mmc_host *mmc = host->mmc;
3945 struct device *dev = mmc_dev(mmc);
3946 int ret = -EINVAL;
3947
3948 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3949 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3950
3951 /* Try 64-bit mask if hardware is capable of it */
3952 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3953 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3954 if (ret) {
3955 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3956 mmc_hostname(mmc));
3957 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3958 }
3959 }
3960
3961 /* 32-bit mask as default & fallback */
3962 if (ret) {
3963 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3964 if (ret)
3965 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3966 mmc_hostname(mmc));
3967 }
3968
3969 return ret;
3970}
3971
Masahiro Yamada8784edc2019-08-29 19:49:27 +09003972void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3973 const u32 *caps, const u32 *caps1)
Adrian Hunter6132a3b2016-06-29 16:24:18 +03003974{
3975 u16 v;
Zach Brown92e0c442016-11-02 10:26:16 -05003976 u64 dt_caps_mask = 0;
3977 u64 dt_caps = 0;
Adrian Hunter6132a3b2016-06-29 16:24:18 +03003978
3979 if (host->read_caps)
3980 return;
3981
3982 host->read_caps = true;
3983
3984 if (debug_quirks)
3985 host->quirks = debug_quirks;
3986
3987 if (debug_quirks2)
3988 host->quirks2 = debug_quirks2;
3989
3990 sdhci_do_reset(host, SDHCI_RESET_ALL);
3991
Chunyan Zhangb3f80b42018-08-30 16:21:38 +08003992 if (host->v4_mode)
3993 sdhci_do_enable_v4_mode(host);
3994
Zach Brown92e0c442016-11-02 10:26:16 -05003995 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3996 "sdhci-caps-mask", &dt_caps_mask);
3997 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3998 "sdhci-caps", &dt_caps);
3999
Adrian Hunter6132a3b2016-06-29 16:24:18 +03004000 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4001 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4002
4003 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4004 return;
4005
Zach Brown92e0c442016-11-02 10:26:16 -05004006 if (caps) {
4007 host->caps = *caps;
4008 } else {
4009 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4010 host->caps &= ~lower_32_bits(dt_caps_mask);
4011 host->caps |= lower_32_bits(dt_caps);
4012 }
Adrian Hunter6132a3b2016-06-29 16:24:18 +03004013
4014 if (host->version < SDHCI_SPEC_300)
4015 return;
4016
Zach Brown92e0c442016-11-02 10:26:16 -05004017 if (caps1) {
4018 host->caps1 = *caps1;
4019 } else {
4020 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4021 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4022 host->caps1 |= upper_32_bits(dt_caps);
4023 }
Adrian Hunter6132a3b2016-06-29 16:24:18 +03004024}
4025EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4026
Chunyan Zhanga68dd9a2018-10-25 10:12:36 +08004027static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
Linus Walleijbd9b9022018-01-29 00:44:53 +01004028{
4029 struct mmc_host *mmc = host->mmc;
4030 unsigned int max_blocks;
4031 unsigned int bounce_size;
4032 int ret;
4033
4034 /*
4035 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4036 * has diminishing returns, this is probably because SD/MMC
4037 * cards are usually optimized to handle this size of requests.
4038 */
4039 bounce_size = SZ_64K;
4040 /*
4041 * Adjust downwards to maximum request size if this is less
4042 * than our segment size, else hammer down the maximum
4043 * request size to the maximum buffer size.
4044 */
4045 if (mmc->max_req_size < bounce_size)
4046 bounce_size = mmc->max_req_size;
4047 max_blocks = bounce_size / 512;
4048
4049 /*
4050 * When we just support one segment, we can get significant
4051 * speedups by the help of a bounce buffer to group scattered
4052 * reads/writes together.
4053 */
4054 host->bounce_buffer = devm_kmalloc(mmc->parent,
4055 bounce_size,
4056 GFP_KERNEL);
4057 if (!host->bounce_buffer) {
4058 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4059 mmc_hostname(mmc),
4060 bounce_size);
4061 /*
4062 * Exiting with zero here makes sure we proceed with
4063 * mmc->max_segs == 1.
4064 */
Chunyan Zhanga68dd9a2018-10-25 10:12:36 +08004065 return;
Linus Walleijbd9b9022018-01-29 00:44:53 +01004066 }
4067
4068 host->bounce_addr = dma_map_single(mmc->parent,
4069 host->bounce_buffer,
4070 bounce_size,
4071 DMA_BIDIRECTIONAL);
4072 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4073 if (ret)
4074 /* Again fall back to max_segs == 1 */
Chunyan Zhanga68dd9a2018-10-25 10:12:36 +08004075 return;
Linus Walleijbd9b9022018-01-29 00:44:53 +01004076 host->bounce_buffer_size = bounce_size;
4077
4078 /* Lie about this since we're bouncing */
4079 mmc->max_segs = max_blocks;
4080 mmc->max_seg_size = bounce_size;
4081 mmc->max_req_size = bounce_size;
4082
4083 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4084 mmc_hostname(mmc), max_blocks, bounce_size);
Linus Walleijbd9b9022018-01-29 00:44:53 +01004085}
4086
Chunyan Zhang685e4442018-08-30 16:21:40 +08004087static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4088{
4089 /*
4090 * According to SD Host Controller spec v4.10, bit[27] added from
4091 * version 4.10 in Capabilities Register is used as 64-bit System
4092 * Address support for V4 mode.
4093 */
4094 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4095 return host->caps & SDHCI_CAN_64BIT_V4;
4096
4097 return host->caps & SDHCI_CAN_64BIT;
4098}
4099
Adrian Hunter52f53362016-06-29 16:24:15 +03004100int sdhci_setup_host(struct sdhci_host *host)
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004101{
4102 struct mmc_host *mmc;
Arindam Nathf2119df2011-05-05 12:18:57 +05304103 u32 max_current_caps;
4104 unsigned int ocr_avail;
Adrian Hunterf5fa92e2014-09-24 10:27:32 +03004105 unsigned int override_timeout_clk;
Dong Aisheng59241752015-07-22 20:53:07 +08004106 u32 max_clk;
Dan Carpenter907be2a2020-07-14 17:14:10 +03004107 int ret = 0;
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304108 bool enable_vqmmc = false;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004109
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004110 WARN_ON(host == NULL);
4111 if (host == NULL)
4112 return -EINVAL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004113
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004114 mmc = host->mmc;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004115
Jon Hunterefba1422016-07-12 14:53:36 +01004116 /*
4117 * If there are external regulators, get them. Note this must be done
4118 * early before resetting the host and reading the capabilities so that
4119 * the host can take the appropriate action if regulators are not
4120 * available.
4121 */
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304122 if (!mmc->supply.vqmmc) {
4123 ret = mmc_regulator_get_supply(mmc);
4124 if (ret)
4125 return ret;
4126 enable_vqmmc = true;
4127 }
Jon Hunterefba1422016-07-12 14:53:36 +01004128
Shawn Lin06ebc602017-07-19 15:55:49 +08004129 DBG("Version: 0x%08x | Present: 0x%08x\n",
4130 sdhci_readw(host, SDHCI_HOST_VERSION),
4131 sdhci_readl(host, SDHCI_PRESENT_STATE));
4132 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4133 sdhci_readl(host, SDHCI_CAPABILITIES),
4134 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4135
Adrian Hunter6132a3b2016-06-29 16:24:18 +03004136 sdhci_read_caps(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004137
Adrian Hunterf5fa92e2014-09-24 10:27:32 +03004138 override_timeout_clk = host->timeout_clk;
4139
Chunyan Zhang18da1992018-08-30 16:21:37 +08004140 if (host->version > SDHCI_SPEC_420) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01004141 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4142 mmc_hostname(mmc), host->version);
Pierre Ossman4a965502006-06-30 02:22:29 -07004143 }
4144
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004145 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
Richard Röjforsa13abc72009-09-22 16:45:30 -07004146 host->flags |= SDHCI_USE_SDMA;
Adrian Hunter28da3582016-06-29 16:24:17 +03004147 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
Richard Röjforsa13abc72009-09-22 16:45:30 -07004148 DBG("Controller doesn't have SDMA capability\n");
Pierre Ossman67435272006-06-30 02:22:31 -07004149 else
Richard Röjforsa13abc72009-09-22 16:45:30 -07004150 host->flags |= SDHCI_USE_SDMA;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004151
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004152 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
Richard Röjforsa13abc72009-09-22 16:45:30 -07004153 (host->flags & SDHCI_USE_SDMA)) {
Rolf Eike Beercee687c2007-11-02 15:22:30 +01004154 DBG("Disabling DMA as it is marked broken\n");
Richard Röjforsa13abc72009-09-22 16:45:30 -07004155 host->flags &= ~SDHCI_USE_SDMA;
Feng Tang7c168e32007-09-30 12:44:18 +02004156 }
4157
Arindam Nathf2119df2011-05-05 12:18:57 +05304158 if ((host->version >= SDHCI_SPEC_200) &&
Adrian Hunter28da3582016-06-29 16:24:17 +03004159 (host->caps & SDHCI_CAN_DO_ADMA2))
Richard Röjforsa13abc72009-09-22 16:45:30 -07004160 host->flags |= SDHCI_USE_ADMA;
Pierre Ossman2134a922008-06-28 18:28:51 +02004161
4162 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4163 (host->flags & SDHCI_USE_ADMA)) {
4164 DBG("Disabling ADMA as it is marked broken\n");
4165 host->flags &= ~SDHCI_USE_ADMA;
4166 }
4167
Chunyan Zhang685e4442018-08-30 16:21:40 +08004168 if (sdhci_can_64bit_dma(host))
Adrian Huntere57a5f62014-11-04 12:42:46 +02004169 host->flags |= SDHCI_USE_64_BIT_DMA;
4170
Chunyan Zhang18e762e2020-01-16 16:21:47 +05304171 if (host->use_external_dma) {
4172 ret = sdhci_external_dma_init(host);
4173 if (ret == -EPROBE_DEFER)
4174 goto unreg;
4175 /*
4176 * Fall back to use the DMA/PIO integrated in standard SDHCI
4177 * instead of external DMA devices.
4178 */
4179 else if (ret)
4180 sdhci_switch_external_dma(host, false);
4181 /* Disable internal DMA sources */
4182 else
4183 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4184 }
4185
Richard Röjforsa13abc72009-09-22 16:45:30 -07004186 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
Adrian Hunter4ee7dde2019-09-23 12:08:09 +02004187 if (host->ops->set_dma_mask)
4188 ret = host->ops->set_dma_mask(host);
4189 else
4190 ret = sdhci_set_dma_mask(host);
Alexandre Courbot7b913692016-03-07 11:07:55 +09004191
4192 if (!ret && host->ops->enable_dma)
4193 ret = host->ops->enable_dma(host);
4194
4195 if (ret) {
4196 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4197 mmc_hostname(mmc));
4198 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4199
4200 ret = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004201 }
4202 }
4203
Chunyan Zhang917a0c52018-08-30 16:21:39 +08004204 /* SDMA does not support 64-bit DMA if v4 mode not set */
4205 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
Adrian Huntere57a5f62014-11-04 12:42:46 +02004206 host->flags &= ~SDHCI_USE_SDMA;
4207
Pierre Ossman2134a922008-06-28 18:28:51 +02004208 if (host->flags & SDHCI_USE_ADMA) {
Russell Kinge66e61c2016-01-26 13:39:55 +00004209 dma_addr_t dma;
4210 void *buf;
4211
Veerabhadrarao Badigantia663f642020-01-20 20:08:38 +05304212 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4213 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4214 else if (!host->alloc_desc_sz)
4215 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4216
4217 host->desc_sz = host->alloc_desc_sz;
4218 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
Russell Kinge66e61c2016-01-26 13:39:55 +00004219
Adrian Hunter04a5ae62015-11-26 14:00:49 +02004220 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
Chunyan Zhang685e4442018-08-30 16:21:40 +08004221 /*
4222 * Use zalloc to zero the reserved high 32-bits of 128-bit
4223 * descriptors so that they never need to be written.
4224 */
Luis Chamberlain750afb02019-01-04 09:23:09 +01004225 buf = dma_alloc_coherent(mmc_dev(mmc),
4226 host->align_buffer_sz + host->adma_table_sz,
4227 &dma, GFP_KERNEL);
Russell Kinge66e61c2016-01-26 13:39:55 +00004228 if (!buf) {
Joe Perches66061102014-09-12 14:56:56 -07004229 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
Pierre Ossman2134a922008-06-28 18:28:51 +02004230 mmc_hostname(mmc));
4231 host->flags &= ~SDHCI_USE_ADMA;
Russell Kinge66e61c2016-01-26 13:39:55 +00004232 } else if ((dma + host->align_buffer_sz) &
4233 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
Joe Perches66061102014-09-12 14:56:56 -07004234 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4235 mmc_hostname(mmc));
Russell Kingd1e49f72014-04-25 12:58:34 +01004236 host->flags &= ~SDHCI_USE_ADMA;
Russell Kinge66e61c2016-01-26 13:39:55 +00004237 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4238 host->adma_table_sz, buf, dma);
4239 } else {
4240 host->align_buffer = buf;
4241 host->align_addr = dma;
Russell Kingedd63fc2016-01-26 13:39:50 +00004242
Russell Kinge66e61c2016-01-26 13:39:55 +00004243 host->adma_table = buf + host->align_buffer_sz;
4244 host->adma_addr = dma + host->align_buffer_sz;
4245 }
Pierre Ossman2134a922008-06-28 18:28:51 +02004246 }
4247
Pierre Ossman76591502008-07-21 00:32:11 +02004248 /*
4249 * If we use DMA, then it's up to the caller to set the DMA
4250 * mask, but PIO does not need the hw shim so we set a new
4251 * mask here in that case.
4252 */
Richard Röjforsa13abc72009-09-22 16:45:30 -07004253 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
Pierre Ossman76591502008-07-21 00:32:11 +02004254 host->dma_mask = DMA_BIT_MASK(64);
Markus Mayer4e743f12014-07-03 13:27:42 -07004255 mmc_dev(mmc)->dma_mask = &host->dma_mask;
Pierre Ossman76591502008-07-21 00:32:11 +02004256 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08004257
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04004258 if (host->version >= SDHCI_SPEC_300)
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004259 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04004260 else
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004261 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04004262
Pierre Ossmand129bce2006-03-24 03:18:17 -08004263 host->max_clk *= 1000000;
Anton Vorontsovf27f47e2010-05-26 14:41:53 -07004264 if (host->max_clk == 0 || host->quirks &
4265 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
Ben Dooks4240ff02009-03-17 00:13:57 +03004266 if (!host->ops->get_max_clock) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01004267 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4268 mmc_hostname(mmc));
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004269 ret = -ENODEV;
4270 goto undma;
Ben Dooks4240ff02009-03-17 00:13:57 +03004271 }
4272 host->max_clk = host->ops->get_max_clock(host);
4273 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08004274
4275 /*
Arindam Nathc3ed3872011-05-05 12:19:06 +05304276 * In case of Host Controller v3.00, find out whether clock
4277 * multiplier is supported.
4278 */
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004279 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
Arindam Nathc3ed3872011-05-05 12:19:06 +05304280
4281 /*
4282 * In case the value in Clock Multiplier is 0, then programmable
4283 * clock mode is not supported, otherwise the actual clock
4284 * multiplier is one more than the value of Clock Multiplier
4285 * in the Capabilities Register.
4286 */
4287 if (host->clk_mul)
4288 host->clk_mul += 1;
4289
4290 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08004291 * Set host parameters.
4292 */
Dong Aisheng59241752015-07-22 20:53:07 +08004293 max_clk = host->max_clk;
4294
Marek Szyprowskice5f0362010-08-10 18:01:56 -07004295 if (host->ops->get_min_clock)
Anton Vorontsova9e58f22009-07-29 15:04:16 -07004296 mmc->f_min = host->ops->get_min_clock(host);
Arindam Nathc3ed3872011-05-05 12:19:06 +05304297 else if (host->version >= SDHCI_SPEC_300) {
Michał Mirosław2a187d02020-01-15 10:54:35 +01004298 if (host->clk_mul)
Dong Aisheng59241752015-07-22 20:53:07 +08004299 max_clk = host->max_clk * host->clk_mul;
Michał Mirosław2a187d02020-01-15 10:54:35 +01004300 /*
4301 * Divided Clock Mode minimum clock rate is always less than
4302 * Programmable Clock Mode minimum clock rate.
4303 */
4304 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
Arindam Nathc3ed3872011-05-05 12:19:06 +05304305 } else
Zhangfei Gao03975262010-09-20 15:15:18 -04004306 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
Philip Rakity15ec4462010-11-19 16:48:39 -05004307
Adrian Hunterd310ae42016-04-12 14:25:07 +03004308 if (!mmc->f_max || mmc->f_max > max_clk)
Dong Aisheng59241752015-07-22 20:53:07 +08004309 mmc->f_max = max_clk;
4310
Aisheng Dong28aab052014-08-27 15:26:31 +08004311 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004312 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
Shawn Lin8cc35282017-03-24 15:50:12 +08004313
4314 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4315 host->timeout_clk *= 1000;
4316
Aisheng Dong28aab052014-08-27 15:26:31 +08004317 if (host->timeout_clk == 0) {
Shawn Lin8cc35282017-03-24 15:50:12 +08004318 if (!host->ops->get_timeout_clock) {
Aisheng Dong28aab052014-08-27 15:26:31 +08004319 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4320 mmc_hostname(mmc));
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004321 ret = -ENODEV;
4322 goto undma;
Aisheng Dong28aab052014-08-27 15:26:31 +08004323 }
Andy Shevchenko272308c2011-08-03 18:36:00 +03004324
Shawn Lin8cc35282017-03-24 15:50:12 +08004325 host->timeout_clk =
4326 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4327 1000);
4328 }
Andy Shevchenko272308c2011-08-03 18:36:00 +03004329
Adrian Hunter99513622016-03-07 13:33:55 +02004330 if (override_timeout_clk)
4331 host->timeout_clk = override_timeout_clk;
4332
Aisheng Dong28aab052014-08-27 15:26:31 +08004333 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
Aisheng Donga6ff5ae2014-08-27 15:26:27 +08004334 host->ops->get_max_timeout_count(host) : 1 << 27;
Aisheng Dong28aab052014-08-27 15:26:31 +08004335 mmc->max_busy_timeout /= host->timeout_clk;
4336 }
Adrian Hunter58d12462011-06-28 17:16:03 +03004337
Adrian Huntera999fd92018-04-27 17:17:15 +05304338 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4339 !host->ops->get_max_timeout_count)
4340 mmc->max_busy_timeout = 0;
4341
Ulf Hansson1be64c72020-05-08 13:29:02 +02004342 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
Russell King781e9892014-04-25 12:55:46 +01004343 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
Andrei Warkentine89d4562011-05-23 15:06:37 -05004344
4345 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4346 host->flags |= SDHCI_AUTO_CMD12;
Anton Vorontsov5fe23c72009-06-18 00:14:08 +04004347
Chunyan Zhang7ed71a92018-08-30 16:21:43 +08004348 /*
4349 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4350 * For v4 mode, SDMA may use Auto-CMD23 as well.
4351 */
Andrei Warkentin4f3d3e92011-05-25 10:42:50 -04004352 if ((host->version >= SDHCI_SPEC_300) &&
Andrei Warkentin8edf63712011-05-23 15:06:39 -05004353 ((host->flags & SDHCI_USE_ADMA) ||
Chunyan Zhang7ed71a92018-08-30 16:21:43 +08004354 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
Scott Branden3bfa6f02015-02-09 16:06:28 -08004355 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
Andrei Warkentin8edf63712011-05-23 15:06:39 -05004356 host->flags |= SDHCI_AUTO_CMD23;
Adrian Hunterf4218652017-03-20 19:50:39 +02004357 DBG("Auto-CMD23 available\n");
Andrei Warkentin8edf63712011-05-23 15:06:39 -05004358 } else {
Adrian Hunterf4218652017-03-20 19:50:39 +02004359 DBG("Auto-CMD23 unavailable\n");
Andrei Warkentin8edf63712011-05-23 15:06:39 -05004360 }
4361
Philip Rakity15ec4462010-11-19 16:48:39 -05004362 /*
4363 * A controller may support 8-bit width, but the board itself
4364 * might not have the pins brought out. Boards that support
4365 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4366 * their platform code before calling sdhci_add_host(), and we
4367 * won't assume 8-bit width for hosts without that CAP.
4368 */
Anton Vorontsov5fe23c72009-06-18 00:14:08 +04004369 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
Philip Rakity15ec4462010-11-19 16:48:39 -05004370 mmc->caps |= MMC_CAP_4_BIT_DATA;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004371
Jerry Huang63ef5d82012-10-25 13:47:19 +08004372 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4373 mmc->caps &= ~MMC_CAP_CMD23;
4374
Adrian Hunter28da3582016-06-29 16:24:17 +03004375 if (host->caps & SDHCI_CAN_DO_HISPD)
Zhangfei Gaoa29e7e12010-08-16 21:15:32 -04004376 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
Pierre Ossmancd9277c2007-02-18 12:07:47 +01004377
Jaehoon Chung176d1ed2010-09-27 09:42:20 +01004378 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
Jaehoon Chung860951c2016-06-21 10:13:26 +09004379 mmc_card_is_removable(mmc) &&
Arnd Bergmann287980e2016-05-27 23:23:25 +02004380 mmc_gpio_get_cd(host->mmc) < 0)
Anton Vorontsov68d1fb72009-03-17 00:13:52 +03004381 mmc->caps |= MMC_CAP_NEEDS_POLL;
4382
Tim Kryger3a48edc2014-06-13 10:13:56 -07004383 if (!IS_ERR(mmc->supply.vqmmc)) {
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304384 if (enable_vqmmc) {
4385 ret = regulator_enable(mmc->supply.vqmmc);
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304386 host->sdhci_core_to_disable_vqmmc = !ret;
4387 }
Stefan Agner1b5190c2018-07-05 14:18:19 +02004388
4389 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
Tim Kryger3a48edc2014-06-13 10:13:56 -07004390 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4391 1950000))
Adrian Hunter28da3582016-06-29 16:24:17 +03004392 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4393 SDHCI_SUPPORT_SDR50 |
4394 SDHCI_SUPPORT_DDR50);
Stefan Agner1b5190c2018-07-05 14:18:19 +02004395
4396 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4397 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4398 3600000))
4399 host->flags &= ~SDHCI_SIGNALING_330;
4400
Chris Balla3361ab2013-03-11 17:51:53 -04004401 if (ret) {
4402 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4403 mmc_hostname(mmc), ret);
Adrian Hunter4bb74312014-11-06 15:19:04 +02004404 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
Chris Balla3361ab2013-03-11 17:51:53 -04004405 }
Veerabhadrarao Badiganti3debc242020-07-09 18:43:25 +05304406
Kevin Liu8363c372012-11-17 17:55:51 -05004407 }
Philip Rakity6231f3d2012-07-23 15:56:23 -07004408
Adrian Hunter28da3582016-06-29 16:24:17 +03004409 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4410 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4411 SDHCI_SUPPORT_DDR50);
Kishon Vijay Abraham Ic16bc9a2018-04-27 17:17:14 +05304412 /*
4413 * The SDHCI controller in a SoC might support HS200/HS400
4414 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4415 * but if the board is modeled such that the IO lines are not
4416 * connected to 1.8v then HS200/HS400 cannot be supported.
4417 * Disable HS200/HS400 if the board does not have 1.8v connected
4418 * to the IO lines. (Applicable for other modes in 1.8v)
4419 */
4420 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4421 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
Adrian Hunter28da3582016-06-29 16:24:17 +03004422 }
Daniel Drake6a661802012-11-25 13:01:19 -05004423
Al Cooper4188bba2012-03-16 15:54:17 -04004424 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
Adrian Hunter28da3582016-06-29 16:24:17 +03004425 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4426 SDHCI_SUPPORT_DDR50))
Arindam Nathf2119df2011-05-05 12:18:57 +05304427 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4428
4429 /* SDR104 supports also implies SDR50 support */
Adrian Hunter28da3582016-06-29 16:24:17 +03004430 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
Arindam Nathf2119df2011-05-05 12:18:57 +05304431 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
Giuseppe CAVALLARO156e14b2013-06-12 08:16:38 +02004432 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4433 * field can be promoted to support HS200.
4434 */
Adrian Hunter549c0b12014-11-06 15:19:05 +02004435 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
David Cohen13868bf2013-10-29 10:58:26 -07004436 mmc->caps2 |= MMC_CAP2_HS200;
Adrian Hunter28da3582016-06-29 16:24:17 +03004437 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
Arindam Nathf2119df2011-05-05 12:18:57 +05304438 mmc->caps |= MMC_CAP_UHS_SDR50;
Adrian Hunter28da3582016-06-29 16:24:17 +03004439 }
Arindam Nathf2119df2011-05-05 12:18:57 +05304440
Adrian Huntere9fb05d2014-11-06 15:19:06 +02004441 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
Adrian Hunter28da3582016-06-29 16:24:17 +03004442 (host->caps1 & SDHCI_SUPPORT_HS400))
Adrian Huntere9fb05d2014-11-06 15:19:06 +02004443 mmc->caps2 |= MMC_CAP2_HS400;
4444
Adrian Hunter549c0b12014-11-06 15:19:05 +02004445 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4446 (IS_ERR(mmc->supply.vqmmc) ||
4447 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4448 1300000)))
4449 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4450
Adrian Hunter28da3582016-06-29 16:24:17 +03004451 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4452 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
Arindam Nathf2119df2011-05-05 12:18:57 +05304453 mmc->caps |= MMC_CAP_UHS_DDR50;
4454
Girish K S069c9f12012-01-06 09:56:39 +05304455 /* Does the host need tuning for SDR50? */
Adrian Hunter28da3582016-06-29 16:24:17 +03004456 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
Arindam Nathb513ea22011-05-05 12:19:04 +05304457 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4458
Arindam Nathd6d50a12011-05-05 12:18:59 +05304459 /* Driver Type(s) (A, C, D) supported by the host */
Adrian Hunter28da3582016-06-29 16:24:17 +03004460 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
Arindam Nathd6d50a12011-05-05 12:18:59 +05304461 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
Adrian Hunter28da3582016-06-29 16:24:17 +03004462 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
Arindam Nathd6d50a12011-05-05 12:18:59 +05304463 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
Adrian Hunter28da3582016-06-29 16:24:17 +03004464 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
Arindam Nathd6d50a12011-05-05 12:18:59 +05304465 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4466
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05304467 /* Initial value for re-tuning timer count */
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004468 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4469 host->caps1);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05304470
4471 /*
4472 * In case Re-tuning Timer is not disabled, the actual value of
4473 * re-tuning timer will be 2 ^ (n - 1).
4474 */
4475 if (host->tuning_count)
4476 host->tuning_count = 1 << (host->tuning_count - 1);
4477
4478 /* Re-tuning mode supported by the Host Controller */
Masahiro Yamadaa8e809e2020-04-08 16:21:05 +09004479 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05304480
Takashi Iwai8f230f42010-12-08 10:04:30 +01004481 ocr_avail = 0;
Philip Rakitybad37e12012-05-27 18:36:44 -07004482
Arindam Nathf2119df2011-05-05 12:18:57 +05304483 /*
4484 * According to SD Host Controller spec v3.00, if the Host System
4485 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4486 * the value is meaningful only if Voltage Support in the Capabilities
4487 * register is set. The actual current value is 4 times the register
4488 * value.
4489 */
4490 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
Tim Kryger3a48edc2014-06-13 10:13:56 -07004491 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
Chuanxiao.Dongae906032014-08-01 14:00:13 +08004492 int curr = regulator_get_current_limit(mmc->supply.vmmc);
Philip Rakitybad37e12012-05-27 18:36:44 -07004493 if (curr > 0) {
4494
4495 /* convert to SDHCI_MAX_CURRENT format */
4496 curr = curr/1000; /* convert to mA */
4497 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4498
4499 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4500 max_current_caps =
Masahiro Yamada804a65b2020-05-11 15:28:27 +09004501 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4502 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4503 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
Philip Rakitybad37e12012-05-27 18:36:44 -07004504 }
4505 }
Arindam Nathf2119df2011-05-05 12:18:57 +05304506
Adrian Hunter28da3582016-06-29 16:24:17 +03004507 if (host->caps & SDHCI_CAN_VDD_330) {
Takashi Iwai8f230f42010-12-08 10:04:30 +01004508 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
Arindam Nathf2119df2011-05-05 12:18:57 +05304509
Masahiro Yamada804a65b2020-05-11 15:28:27 +09004510 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4511 max_current_caps) *
4512 SDHCI_MAX_CURRENT_MULTIPLIER;
Arindam Nathf2119df2011-05-05 12:18:57 +05304513 }
Adrian Hunter28da3582016-06-29 16:24:17 +03004514 if (host->caps & SDHCI_CAN_VDD_300) {
Takashi Iwai8f230f42010-12-08 10:04:30 +01004515 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
Arindam Nathf2119df2011-05-05 12:18:57 +05304516
Masahiro Yamada804a65b2020-05-11 15:28:27 +09004517 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4518 max_current_caps) *
4519 SDHCI_MAX_CURRENT_MULTIPLIER;
Arindam Nathf2119df2011-05-05 12:18:57 +05304520 }
Adrian Hunter28da3582016-06-29 16:24:17 +03004521 if (host->caps & SDHCI_CAN_VDD_180) {
Takashi Iwai8f230f42010-12-08 10:04:30 +01004522 ocr_avail |= MMC_VDD_165_195;
4523
Masahiro Yamada804a65b2020-05-11 15:28:27 +09004524 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4525 max_current_caps) *
4526 SDHCI_MAX_CURRENT_MULTIPLIER;
Arindam Nathf2119df2011-05-05 12:18:57 +05304527 }
4528
Ulf Hansson5fd26c72015-06-05 11:40:08 +02004529 /* If OCR set by host, use it instead. */
4530 if (host->ocr_mask)
4531 ocr_avail = host->ocr_mask;
4532
4533 /* If OCR set by external regulators, give it highest prio. */
Tim Kryger3a48edc2014-06-13 10:13:56 -07004534 if (mmc->ocr_avail)
Tim Kryger52221612014-06-25 00:25:34 -07004535 ocr_avail = mmc->ocr_avail;
Tim Kryger3a48edc2014-06-13 10:13:56 -07004536
Takashi Iwai8f230f42010-12-08 10:04:30 +01004537 mmc->ocr_avail = ocr_avail;
4538 mmc->ocr_avail_sdio = ocr_avail;
4539 if (host->ocr_avail_sdio)
4540 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4541 mmc->ocr_avail_sd = ocr_avail;
4542 if (host->ocr_avail_sd)
4543 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4544 else /* normal SD controllers don't support 1.8V */
4545 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4546 mmc->ocr_avail_mmc = ocr_avail;
4547 if (host->ocr_avail_mmc)
4548 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
Pierre Ossman146ad662006-06-30 02:22:23 -07004549
4550 if (mmc->ocr_avail == 0) {
Marek Vasut2e4456f2015-11-18 10:47:02 +01004551 pr_err("%s: Hardware doesn't report any support voltages.\n",
4552 mmc_hostname(mmc));
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004553 ret = -ENODEV;
4554 goto unreg;
Pierre Ossman146ad662006-06-30 02:22:23 -07004555 }
4556
Adrian Hunter8cb851a2016-06-29 16:24:16 +03004557 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4558 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4559 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4560 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4561 host->flags |= SDHCI_SIGNALING_180;
4562
4563 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4564 host->flags |= SDHCI_SIGNALING_120;
4565
Pierre Ossmand129bce2006-03-24 03:18:17 -08004566 spin_lock_init(&host->lock);
4567
4568 /*
Adrian Hunterac005312014-12-05 19:25:28 +02004569 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4570 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4571 * is less anyway.
Pierre Ossmand129bce2006-03-24 03:18:17 -08004572 */
Pierre Ossman55db8902006-11-21 17:55:45 +01004573 mmc->max_req_size = 524288;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004574
4575 /*
Ulf Hansson250dcd12017-11-27 11:28:50 +01004576 * Maximum number of segments. Depends on if the hardware
4577 * can do scatter/gather or not.
4578 */
4579 if (host->flags & SDHCI_USE_ADMA) {
4580 mmc->max_segs = SDHCI_MAX_SEGS;
4581 } else if (host->flags & SDHCI_USE_SDMA) {
4582 mmc->max_segs = 1;
4583 if (swiotlb_max_segment()) {
4584 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4585 IO_TLB_SEGSIZE;
4586 mmc->max_req_size = min(mmc->max_req_size,
4587 max_req_size);
4588 }
4589 } else { /* PIO */
4590 mmc->max_segs = SDHCI_MAX_SEGS;
4591 }
4592
4593 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08004594 * Maximum segment size. Could be one segment with the maximum number
Pierre Ossman2134a922008-06-28 18:28:51 +02004595 * of bytes. When doing hardware scatter/gather, each entry cannot
4596 * be larger than 64 KiB though.
Pierre Ossmand129bce2006-03-24 03:18:17 -08004597 */
Olof Johansson30652aa2011-01-01 18:37:32 -06004598 if (host->flags & SDHCI_USE_ADMA) {
4599 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4600 mmc->max_seg_size = 65535;
4601 else
4602 mmc->max_seg_size = 65536;
4603 } else {
Pierre Ossman2134a922008-06-28 18:28:51 +02004604 mmc->max_seg_size = mmc->max_req_size;
Olof Johansson30652aa2011-01-01 18:37:32 -06004605 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08004606
4607 /*
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01004608 * Maximum block size. This varies from controller to controller and
4609 * is specified in the capabilities register.
4610 */
Anton Vorontsov0633f652009-03-17 00:14:03 +03004611 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4612 mmc->max_blk_size = 2;
4613 } else {
Adrian Hunter28da3582016-06-29 16:24:17 +03004614 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
Anton Vorontsov0633f652009-03-17 00:14:03 +03004615 SDHCI_MAX_BLOCK_SHIFT;
4616 if (mmc->max_blk_size >= 3) {
Joe Perches66061102014-09-12 14:56:56 -07004617 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4618 mmc_hostname(mmc));
Anton Vorontsov0633f652009-03-17 00:14:03 +03004619 mmc->max_blk_size = 0;
4620 }
4621 }
4622
4623 mmc->max_blk_size = 512 << mmc->max_blk_size;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01004624
4625 /*
Pierre Ossman55db8902006-11-21 17:55:45 +01004626 * Maximum block count.
4627 */
Ben Dooks1388eef2009-06-14 12:40:53 +01004628 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
Pierre Ossman55db8902006-11-21 17:55:45 +01004629
Chunyan Zhanga68dd9a2018-10-25 10:12:36 +08004630 if (mmc->max_segs == 1)
Linus Walleijbd9b9022018-01-29 00:44:53 +01004631 /* This may alter mmc->*_blk_* parameters */
Chunyan Zhanga68dd9a2018-10-25 10:12:36 +08004632 sdhci_allocate_bounce_buffer(host);
Linus Walleijbd9b9022018-01-29 00:44:53 +01004633
Adrian Hunter52f53362016-06-29 16:24:15 +03004634 return 0;
4635
4636unreg:
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304637 if (host->sdhci_core_to_disable_vqmmc)
Adrian Hunter52f53362016-06-29 16:24:15 +03004638 regulator_disable(mmc->supply.vqmmc);
4639undma:
4640 if (host->align_buffer)
4641 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4642 host->adma_table_sz, host->align_buffer,
4643 host->align_addr);
4644 host->adma_table = NULL;
4645 host->align_buffer = NULL;
4646
4647 return ret;
4648}
4649EXPORT_SYMBOL_GPL(sdhci_setup_host);
4650
Adrian Hunter4180ffa2017-03-20 19:50:45 +02004651void sdhci_cleanup_host(struct sdhci_host *host)
4652{
4653 struct mmc_host *mmc = host->mmc;
4654
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304655 if (host->sdhci_core_to_disable_vqmmc)
Adrian Hunter4180ffa2017-03-20 19:50:45 +02004656 regulator_disable(mmc->supply.vqmmc);
4657
4658 if (host->align_buffer)
4659 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4660 host->adma_table_sz, host->align_buffer,
4661 host->align_addr);
Chunyan Zhang18e762e2020-01-16 16:21:47 +05304662
4663 if (host->use_external_dma)
4664 sdhci_external_dma_release(host);
4665
Adrian Hunter4180ffa2017-03-20 19:50:45 +02004666 host->adma_table = NULL;
4667 host->align_buffer = NULL;
4668}
4669EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4670
Adrian Hunter52f53362016-06-29 16:24:15 +03004671int __sdhci_add_host(struct sdhci_host *host)
4672{
Adrian Hunterc07a48c2019-04-05 15:40:20 +03004673 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
Adrian Hunter52f53362016-06-29 16:24:15 +03004674 struct mmc_host *mmc = host->mmc;
4675 int ret;
4676
Adrian Hunter2b17b8d2020-05-18 15:09:39 +03004677 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4678 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4679 mmc->caps2 &= ~MMC_CAP2_CQE;
4680 mmc->cqe_ops = NULL;
4681 }
4682
Adrian Hunterc07a48c2019-04-05 15:40:20 +03004683 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4684 if (!host->complete_wq)
4685 return -ENOMEM;
4686
4687 INIT_WORK(&host->complete_work, sdhci_complete_work);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004688
Kees Cook2ee4f622017-10-24 08:03:45 -07004689 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4690 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004691
Adrian Hunter250fb7b42014-12-05 19:41:10 +02004692 init_waitqueue_head(&host->buf_ready_int);
Arindam Nathb513ea22011-05-05 12:19:04 +05304693
Shawn Guo2af502c2013-07-05 14:38:55 +08004694 sdhci_init(host, 0);
4695
Russell King781e9892014-04-25 12:55:46 +01004696 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4697 IRQF_SHARED, mmc_hostname(mmc), host);
Mark Brown0fc81ee2012-07-02 14:26:15 +01004698 if (ret) {
4699 pr_err("%s: Failed to request IRQ %d: %d\n",
4700 mmc_hostname(mmc), host->irq, ret);
Adrian Hunterc07a48c2019-04-05 15:40:20 +03004701 goto unwq;
Mark Brown0fc81ee2012-07-02 14:26:15 +01004702 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08004703
Adrian Hunter061d17a2016-04-12 14:25:09 +03004704 ret = sdhci_led_register(host);
Mark Brown0fc81ee2012-07-02 14:26:15 +01004705 if (ret) {
4706 pr_err("%s: Failed to register LED device: %d\n",
4707 mmc_hostname(mmc), ret);
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004708 goto unirq;
Mark Brown0fc81ee2012-07-02 14:26:15 +01004709 }
Pierre Ossman2f730fe2008-03-17 10:29:38 +01004710
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004711 ret = mmc_add_host(mmc);
4712 if (ret)
4713 goto unled;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004714
Girish K Sa3c76eb2011-10-11 11:44:09 +05304715 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
Kay Sieversd1b26862008-11-08 21:37:46 +01004716 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
Chunyan Zhang18e762e2020-01-16 16:21:47 +05304717 host->use_external_dma ? "External DMA" :
Adrian Huntere57a5f62014-11-04 12:42:46 +02004718 (host->flags & SDHCI_USE_ADMA) ?
4719 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
Richard Röjforsa13abc72009-09-22 16:45:30 -07004720 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
Pierre Ossmand129bce2006-03-24 03:18:17 -08004721
Anton Vorontsov7260cf52009-03-17 00:13:48 +03004722 sdhci_enable_card_detection(host);
4723
Pierre Ossmand129bce2006-03-24 03:18:17 -08004724 return 0;
4725
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004726unled:
Adrian Hunter061d17a2016-04-12 14:25:09 +03004727 sdhci_led_unregister(host);
Adrian Huntereb5c20d2016-04-12 14:25:08 +03004728unirq:
Russell King03231f92014-04-25 12:57:12 +01004729 sdhci_do_reset(host, SDHCI_RESET_ALL);
Russell Kingb537f942014-04-25 12:56:01 +01004730 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4731 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
Pierre Ossman2f730fe2008-03-17 10:29:38 +01004732 free_irq(host->irq, host);
Adrian Hunterc07a48c2019-04-05 15:40:20 +03004733unwq:
4734 destroy_workqueue(host->complete_wq);
Adrian Hunter52f53362016-06-29 16:24:15 +03004735
Pierre Ossmand129bce2006-03-24 03:18:17 -08004736 return ret;
4737}
Adrian Hunter52f53362016-06-29 16:24:15 +03004738EXPORT_SYMBOL_GPL(__sdhci_add_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004739
Adrian Hunter52f53362016-06-29 16:24:15 +03004740int sdhci_add_host(struct sdhci_host *host)
4741{
4742 int ret;
4743
4744 ret = sdhci_setup_host(host);
4745 if (ret)
4746 return ret;
4747
Adrian Hunter4180ffa2017-03-20 19:50:45 +02004748 ret = __sdhci_add_host(host);
4749 if (ret)
4750 goto cleanup;
4751
4752 return 0;
4753
4754cleanup:
4755 sdhci_cleanup_host(host);
4756
4757 return ret;
Adrian Hunter52f53362016-06-29 16:24:15 +03004758}
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004759EXPORT_SYMBOL_GPL(sdhci_add_host);
4760
Pierre Ossman1e728592008-04-16 19:13:13 +02004761void sdhci_remove_host(struct sdhci_host *host, int dead)
Pierre Ossmand129bce2006-03-24 03:18:17 -08004762{
Tim Kryger3a48edc2014-06-13 10:13:56 -07004763 struct mmc_host *mmc = host->mmc;
Pierre Ossman1e728592008-04-16 19:13:13 +02004764 unsigned long flags;
4765
4766 if (dead) {
4767 spin_lock_irqsave(&host->lock, flags);
4768
4769 host->flags |= SDHCI_DEVICE_DEAD;
4770
Adrian Hunter5d0d11c2016-06-29 16:24:31 +03004771 if (sdhci_has_requests(host)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05304772 pr_err("%s: Controller removed during "
Markus Mayer4e743f12014-07-03 13:27:42 -07004773 " transfer!\n", mmc_hostname(mmc));
Adrian Hunter5d0d11c2016-06-29 16:24:31 +03004774 sdhci_error_out_mrqs(host, -ENOMEDIUM);
Pierre Ossman1e728592008-04-16 19:13:13 +02004775 }
4776
4777 spin_unlock_irqrestore(&host->lock, flags);
4778 }
4779
Anton Vorontsov7260cf52009-03-17 00:13:48 +03004780 sdhci_disable_card_detection(host);
4781
Markus Mayer4e743f12014-07-03 13:27:42 -07004782 mmc_remove_host(mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004783
Adrian Hunter061d17a2016-04-12 14:25:09 +03004784 sdhci_led_unregister(host);
Pierre Ossman2f730fe2008-03-17 10:29:38 +01004785
Pierre Ossman1e728592008-04-16 19:13:13 +02004786 if (!dead)
Russell King03231f92014-04-25 12:57:12 +01004787 sdhci_do_reset(host, SDHCI_RESET_ALL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004788
Russell Kingb537f942014-04-25 12:56:01 +01004789 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4790 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004791 free_irq(host->irq, host);
4792
4793 del_timer_sync(&host->timer);
Adrian Hunterd7422fb2016-06-29 16:24:33 +03004794 del_timer_sync(&host->data_timer);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004795
Adrian Hunterc07a48c2019-04-05 15:40:20 +03004796 destroy_workqueue(host->complete_wq);
Pierre Ossman2134a922008-06-28 18:28:51 +02004797
Vijay Viswanath0fcb0312020-06-23 19:04:46 +05304798 if (host->sdhci_core_to_disable_vqmmc)
Tim Kryger3a48edc2014-06-13 10:13:56 -07004799 regulator_disable(mmc->supply.vqmmc);
Philip Rakity6231f3d2012-07-23 15:56:23 -07004800
Russell Kingedd63fc2016-01-26 13:39:50 +00004801 if (host->align_buffer)
Russell Kinge66e61c2016-01-26 13:39:55 +00004802 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4803 host->adma_table_sz, host->align_buffer,
4804 host->align_addr);
Pierre Ossman2134a922008-06-28 18:28:51 +02004805
Chunyan Zhang18e762e2020-01-16 16:21:47 +05304806 if (host->use_external_dma)
4807 sdhci_external_dma_release(host);
4808
Adrian Hunter4efaa6f2014-11-04 12:42:39 +02004809 host->adma_table = NULL;
Pierre Ossman2134a922008-06-28 18:28:51 +02004810 host->align_buffer = NULL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004811}
4812
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004813EXPORT_SYMBOL_GPL(sdhci_remove_host);
4814
4815void sdhci_free_host(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08004816{
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004817 mmc_free_host(host->mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004818}
4819
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004820EXPORT_SYMBOL_GPL(sdhci_free_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08004821
4822/*****************************************************************************\
4823 * *
4824 * Driver init/exit *
4825 * *
4826\*****************************************************************************/
4827
4828static int __init sdhci_drv_init(void)
4829{
Girish K Sa3c76eb2011-10-11 11:44:09 +05304830 pr_info(DRIVER_NAME
Pierre Ossman52fbf9c2007-02-09 08:23:41 +01004831 ": Secure Digital Host Controller Interface driver\n");
Girish K Sa3c76eb2011-10-11 11:44:09 +05304832 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -08004833
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004834 return 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08004835}
4836
4837static void __exit sdhci_drv_exit(void)
4838{
Pierre Ossmand129bce2006-03-24 03:18:17 -08004839}
4840
4841module_init(sdhci_drv_init);
4842module_exit(sdhci_drv_exit);
4843
Pierre Ossmandf673b22006-06-30 02:22:31 -07004844module_param(debug_quirks, uint, 0444);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03004845module_param(debug_quirks2, uint, 0444);
Pierre Ossman67435272006-06-30 02:22:31 -07004846
Pierre Ossman32710e82009-04-08 20:14:54 +02004847MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01004848MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
Pierre Ossmand129bce2006-03-24 03:18:17 -08004849MODULE_LICENSE("GPL");
Pierre Ossman67435272006-06-30 02:22:31 -07004850
Pierre Ossmandf673b22006-06-30 02:22:31 -07004851MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03004852MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");