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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Ard Biesheuvel60c0d452015-03-06 15:49:24 +010024#include <linux/efi.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000025#include <linux/export.h>
26#include <linux/sched.h>
27#include <linux/kernel.h>
28#include <linux/mm.h>
29#include <linux/stddef.h>
30#include <linux/unistd.h>
31#include <linux/user.h>
32#include <linux/delay.h>
33#include <linux/reboot.h>
34#include <linux/interrupt.h>
35#include <linux/kallsyms.h>
36#include <linux/init.h>
37#include <linux/cpu.h>
38#include <linux/elfcore.h>
39#include <linux/pm.h>
40#include <linux/tick.h>
41#include <linux/utsname.h>
42#include <linux/uaccess.h>
43#include <linux/random.h>
44#include <linux/hw_breakpoint.h>
45#include <linux/personality.h>
46#include <linux/notifier.h>
Jisheng Zhang096b3222015-09-16 22:23:21 +080047#include <trace/events/power.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000048
James Morse57f49592016-02-05 14:58:48 +000049#include <asm/alternative.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000050#include <asm/compat.h>
51#include <asm/cacheflush.h>
James Morsed0854412016-10-18 11:27:48 +010052#include <asm/exec.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000053#include <asm/fpsimd.h>
54#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000055#include <asm/processor.h>
56#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000057
Laura Abbottc0c264a2014-06-25 23:55:03 +010058#ifdef CONFIG_CC_STACKPROTECTOR
59#include <linux/stackprotector.h>
60unsigned long __stack_chk_guard __read_mostly;
61EXPORT_SYMBOL(__stack_chk_guard);
62#endif
63
Catalin Marinasb3901d52012-03-05 11:49:28 +000064/*
65 * Function pointers to optional machine specific functions
66 */
67void (*pm_power_off)(void);
68EXPORT_SYMBOL_GPL(pm_power_off);
69
Catalin Marinasb0946fc2013-07-23 11:05:10 +010070void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +000071
Catalin Marinasb3901d52012-03-05 11:49:28 +000072/*
73 * This is our default idle handler.
74 */
Thomas Gleixner00872982013-03-21 22:49:39 +010075void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +000076{
77 /*
78 * This should do all the clock switching and wait for interrupt
79 * tricks
80 */
Jisheng Zhang096b3222015-09-16 22:23:21 +080081 trace_cpu_idle_rcuidle(1, smp_processor_id());
Nicolas Pitre69905662014-02-17 10:59:30 -050082 cpu_do_idle();
83 local_irq_enable();
Jisheng Zhang096b3222015-09-16 22:23:21 +080084 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Catalin Marinasb3901d52012-03-05 11:49:28 +000085}
86
Mark Rutland9327e2c2013-10-24 20:30:18 +010087#ifdef CONFIG_HOTPLUG_CPU
88void arch_cpu_idle_dead(void)
89{
90 cpu_die();
91}
92#endif
93
Arun KS90f51a02014-05-07 02:41:22 +010094/*
95 * Called by kexec, immediately prior to machine_kexec().
96 *
97 * This must completely disable all secondary CPUs; simply causing those CPUs
98 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
99 * kexec'd kernel to use any and all RAM as it sees fit, without having to
100 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
101 * functionality embodied in disable_nonboot_cpus() to achieve this.
102 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000103void machine_shutdown(void)
104{
Arun KS90f51a02014-05-07 02:41:22 +0100105 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000106}
107
Arun KS90f51a02014-05-07 02:41:22 +0100108/*
109 * Halting simply requires that the secondary CPUs stop performing any
110 * activity (executing tasks, handling interrupts). smp_send_stop()
111 * achieves this.
112 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000113void machine_halt(void)
114{
Arun KSb9acc492014-05-07 02:41:23 +0100115 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100116 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000117 while (1);
118}
119
Arun KS90f51a02014-05-07 02:41:22 +0100120/*
121 * Power-off simply requires that the secondary CPUs stop performing any
122 * activity (executing tasks, handling interrupts). smp_send_stop()
123 * achieves this. When the system power is turned off, it will take all CPUs
124 * with it.
125 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000126void machine_power_off(void)
127{
Arun KSb9acc492014-05-07 02:41:23 +0100128 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100129 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000130 if (pm_power_off)
131 pm_power_off();
132}
133
Arun KS90f51a02014-05-07 02:41:22 +0100134/*
135 * Restart requires that the secondary CPUs stop performing any activity
Mark Rutland68234df2015-04-20 10:24:35 +0100136 * while the primary CPU resets the system. Systems with multiple CPUs must
Arun KS90f51a02014-05-07 02:41:22 +0100137 * provide a HW restart implementation, to ensure that all CPUs reset at once.
138 * This is required so that any code running after reset on the primary CPU
139 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
140 * executing pre-reset code, and using RAM that the primary CPU's code wishes
141 * to use. Implementing such co-ordination would be essentially impossible.
142 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000143void machine_restart(char *cmd)
144{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000145 /* Disable interrupts first */
146 local_irq_disable();
Arun KSb9acc492014-05-07 02:41:23 +0100147 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000148
Ard Biesheuvel60c0d452015-03-06 15:49:24 +0100149 /*
150 * UpdateCapsule() depends on the system being reset via
151 * ResetSystem().
152 */
153 if (efi_enabled(EFI_RUNTIME_SERVICES))
154 efi_reboot(reboot_mode, NULL);
155
Catalin Marinasb3901d52012-03-05 11:49:28 +0000156 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000157 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100158 arm_pm_restart(reboot_mode, cmd);
Guenter Roeck1c7ffc32014-09-26 00:03:16 +0000159 else
160 do_kernel_restart(cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000161
162 /*
163 * Whoops - the architecture was unable to reboot.
164 */
165 printk("Reboot failed -- System halted\n");
166 while (1);
167}
168
Greg Hackmannc69559c2014-09-09 17:36:05 -0700169/*
170 * dump a block of kernel memory from around the given address
171 */
172static void show_data(unsigned long addr, int nbytes, const char *name)
173{
174 int i, j;
175 int nlines;
176 u32 *p;
177
178 /*
179 * don't attempt to dump non-kernel addresses or
180 * values that are probably just small negative numbers
181 */
182 if (addr < PAGE_OFFSET || addr > -256UL)
183 return;
184
185 printk("\n%s: %#lx:\n", name, addr);
186
187 /*
188 * round address down to a 32 bit boundary
189 * and always dump a multiple of 32 bytes
190 */
191 p = (u32 *)(addr & ~(sizeof(u32) - 1));
192 nbytes += (addr & (sizeof(u32) - 1));
193 nlines = (nbytes + 31) / 32;
194
195
196 for (i = 0; i < nlines; i++) {
197 /*
198 * just display low 16 bits of address to keep
199 * each line of the dump < 80 characters
200 */
201 printk("%04lx ", (unsigned long)p & 0xffff);
202 for (j = 0; j < 8; j++) {
203 u32 data;
204 if (probe_kernel_address(p, data)) {
205 printk(" ********");
206 } else {
207 printk(" %08x", data);
208 }
209 ++p;
210 }
211 printk("\n");
212 }
213}
214
215static void show_extra_register_data(struct pt_regs *regs, int nbytes)
216{
217 mm_segment_t fs;
218 unsigned int i;
219
220 fs = get_fs();
221 set_fs(KERNEL_DS);
222 show_data(regs->pc - nbytes, nbytes * 2, "PC");
223 show_data(regs->regs[30] - nbytes, nbytes * 2, "LR");
224 show_data(regs->sp - nbytes, nbytes * 2, "SP");
225 for (i = 0; i < 30; i++) {
226 char name[4];
227 snprintf(name, sizeof(name), "X%u", i);
228 show_data(regs->regs[i] - nbytes, nbytes * 2, name);
229 }
230 set_fs(fs);
231}
232
Catalin Marinasb3901d52012-03-05 11:49:28 +0000233void __show_regs(struct pt_regs *regs)
234{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100235 int i, top_reg;
236 u64 lr, sp;
237
238 if (compat_user_mode(regs)) {
239 lr = regs->compat_lr;
240 sp = regs->compat_sp;
241 top_reg = 12;
242 } else {
243 lr = regs->regs[30];
244 sp = regs->sp;
245 top_reg = 29;
246 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000247
Tejun Heoa43cb952013-04-30 15:27:17 -0700248 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000249 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100250 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000251 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100252 regs->pc, lr, regs->pstate);
253 printk("sp : %016llx\n", sp);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100254
255 i = top_reg;
256
257 while (i >= 0) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000258 printk("x%-2d: %016llx ", i, regs->regs[i]);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100259 i--;
260
261 if (i % 2 == 0) {
262 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
263 i--;
264 }
265
266 pr_cont("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000267 }
Greg Hackmannc69559c2014-09-09 17:36:05 -0700268 if (!user_mode(regs))
269 show_extra_register_data(regs, 128);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000270 printk("\n");
271}
272
273void show_regs(struct pt_regs * regs)
274{
275 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000276 __show_regs(regs);
277}
278
Will Deaconeb35bdd2014-09-11 14:38:16 +0100279static void tls_thread_flush(void)
280{
Mark Rutlandadf75892016-09-08 13:55:38 +0100281 write_sysreg(0, tpidr_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100282
283 if (is_compat_task()) {
284 current->thread.tp_value = 0;
285
286 /*
287 * We need to ensure ordering between the shadow state and the
288 * hardware state, so that we don't corrupt the hardware state
289 * with a stale shadow state during context switch.
290 */
291 barrier();
Mark Rutlandadf75892016-09-08 13:55:38 +0100292 write_sysreg(0, tpidrro_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100293 }
294}
295
Catalin Marinasb3901d52012-03-05 11:49:28 +0000296void flush_thread(void)
297{
298 fpsimd_flush_thread();
Will Deaconeb35bdd2014-09-11 14:38:16 +0100299 tls_thread_flush();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000300 flush_ptrace_hw_breakpoint(current);
301}
302
303void release_thread(struct task_struct *dead_task)
304{
305}
306
307int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
308{
Janet Liu6eb6c802015-06-11 12:04:32 +0800309 if (current->mm)
310 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000311 *dst = *src;
312 return 0;
313}
314
315asmlinkage void ret_from_fork(void) asm("ret_from_fork");
316
317int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400318 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000319{
320 struct pt_regs *childregs = task_pt_regs(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000321
Catalin Marinasb3901d52012-03-05 11:49:28 +0000322 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000323
Al Viro9ac08002012-10-21 15:56:52 -0400324 if (likely(!(p->flags & PF_KTHREAD))) {
325 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100326 childregs->regs[0] = 0;
Will Deacond00a3812015-05-27 15:39:40 +0100327
328 /*
329 * Read the current TLS pointer from tpidr_el0 as it may be
330 * out-of-sync with the saved value.
331 */
Mark Rutlandadf75892016-09-08 13:55:38 +0100332 *task_user_tls(p) = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100333
334 if (stack_start) {
335 if (is_compat_thread(task_thread_info(p)))
Al Viroe0fd18c2012-10-18 00:55:54 -0400336 childregs->compat_sp = stack_start;
Will Deacond00a3812015-05-27 15:39:40 +0100337 else
Al Viroe0fd18c2012-10-18 00:55:54 -0400338 childregs->sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100339 }
Will Deacond00a3812015-05-27 15:39:40 +0100340
Catalin Marinasc34501d2012-10-05 12:31:20 +0100341 /*
342 * If a TLS pointer was passed to clone (4th argument), use it
343 * for the new thread.
344 */
345 if (clone_flags & CLONE_SETTLS)
Will Deacond00a3812015-05-27 15:39:40 +0100346 p->thread.tp_value = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100347 } else {
348 memset(childregs, 0, sizeof(struct pt_regs));
349 childregs->pstate = PSR_MODE_EL1h;
James Morse57f49592016-02-05 14:58:48 +0000350 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
351 cpus_have_cap(ARM64_HAS_UAO))
352 childregs->pstate |= PSR_UAO_BIT;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100353 p->thread.cpu_context.x19 = stack_start;
354 p->thread.cpu_context.x20 = stk_sz;
355 }
356 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
357 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000358
359 ptrace_hw_copy_thread(p);
360
361 return 0;
362}
363
364static void tls_thread_switch(struct task_struct *next)
365{
366 unsigned long tpidr, tpidrro;
367
Mark Rutlandadf75892016-09-08 13:55:38 +0100368 tpidr = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100369 *task_user_tls(current) = tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000370
Will Deacond00a3812015-05-27 15:39:40 +0100371 tpidr = *task_user_tls(next);
372 tpidrro = is_compat_thread(task_thread_info(next)) ?
373 next->thread.tp_value : 0;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000374
Mark Rutlandadf75892016-09-08 13:55:38 +0100375 write_sysreg(tpidr, tpidr_el0);
376 write_sysreg(tpidrro, tpidrro_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000377}
378
James Morse57f49592016-02-05 14:58:48 +0000379/* Restore the UAO state depending on next's addr_limit */
James Morsed0854412016-10-18 11:27:48 +0100380void uao_thread_switch(struct task_struct *next)
James Morse57f49592016-02-05 14:58:48 +0000381{
Catalin Marinase9506312016-02-18 15:50:04 +0000382 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
383 if (task_thread_info(next)->addr_limit == KERNEL_DS)
384 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
385 else
386 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
387 }
James Morse57f49592016-02-05 14:58:48 +0000388}
389
Catalin Marinasb3901d52012-03-05 11:49:28 +0000390/*
391 * Thread switching.
392 */
393struct task_struct *__switch_to(struct task_struct *prev,
394 struct task_struct *next)
395{
396 struct task_struct *last;
397
398 fpsimd_thread_switch(next);
399 tls_thread_switch(next);
400 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100401 contextidr_thread_switch(next);
James Morse57f49592016-02-05 14:58:48 +0000402 uao_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000403
Catalin Marinas5108c672013-04-24 14:47:02 +0100404 /*
405 * Complete any pending TLB or cache maintenance on this CPU in case
406 * the thread migrates to a different CPU.
407 */
Will Deacon98f76852014-05-02 16:24:10 +0100408 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000409
410 /* the actual thread switch */
411 last = cpu_switch_to(prev, next);
412
413 return last;
414}
415
Catalin Marinasb3901d52012-03-05 11:49:28 +0000416unsigned long get_wchan(struct task_struct *p)
417{
418 struct stackframe frame;
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000419 unsigned long stack_page;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000420 int count = 0;
421 if (!p || p == current || p->state == TASK_RUNNING)
422 return 0;
423
424 frame.fp = thread_saved_fp(p);
425 frame.sp = thread_saved_sp(p);
426 frame.pc = thread_saved_pc(p);
AKASHI Takahiro20380bb2015-12-15 17:33:41 +0900427#ifdef CONFIG_FUNCTION_GRAPH_TRACER
428 frame.graph = p->curr_ret_stack;
429#endif
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000430 stack_page = (unsigned long)task_stack_page(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000431 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000432 if (frame.sp < stack_page ||
433 frame.sp >= stack_page + THREAD_SIZE ||
AKASHI Takahirofe13f952015-12-15 17:33:40 +0900434 unwind_frame(p, &frame))
Catalin Marinasb3901d52012-03-05 11:49:28 +0000435 return 0;
436 if (!in_sched_functions(frame.pc))
437 return frame.pc;
438 } while (count ++ < 16);
439 return 0;
440}
441
442unsigned long arch_align_stack(unsigned long sp)
443{
444 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
445 sp -= get_random_int() & ~PAGE_MASK;
446 return sp & ~0xf;
447}
448
Catalin Marinasb3901d52012-03-05 11:49:28 +0000449unsigned long arch_randomize_brk(struct mm_struct *mm)
450{
Kees Cook61462c82016-05-10 10:55:49 -0700451 if (is_compat_task())
Jason Cooperfa5114c2016-10-11 13:54:02 -0700452 return randomize_page(mm->brk, 0x02000000);
Kees Cook61462c82016-05-10 10:55:49 -0700453 else
Jason Cooperfa5114c2016-10-11 13:54:02 -0700454 return randomize_page(mm->brk, 0x40000000);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000455}