Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/process.c |
| 3 | * |
| 4 | * Original Copyright (C) 1995 Linus Torvalds |
| 5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <stdarg.h> |
| 22 | |
| 23 | #include <linux/export.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/mm.h> |
| 27 | #include <linux/stddef.h> |
| 28 | #include <linux/unistd.h> |
| 29 | #include <linux/user.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/reboot.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/kallsyms.h> |
| 34 | #include <linux/init.h> |
| 35 | #include <linux/cpu.h> |
| 36 | #include <linux/elfcore.h> |
| 37 | #include <linux/pm.h> |
| 38 | #include <linux/tick.h> |
| 39 | #include <linux/utsname.h> |
| 40 | #include <linux/uaccess.h> |
| 41 | #include <linux/random.h> |
| 42 | #include <linux/hw_breakpoint.h> |
| 43 | #include <linux/personality.h> |
| 44 | #include <linux/notifier.h> |
| 45 | |
| 46 | #include <asm/compat.h> |
| 47 | #include <asm/cacheflush.h> |
Will Deacon | ec45d1c | 2013-01-17 12:31:45 +0000 | [diff] [blame] | 48 | #include <asm/fpsimd.h> |
| 49 | #include <asm/mmu_context.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 50 | #include <asm/processor.h> |
| 51 | #include <asm/stacktrace.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 52 | |
| 53 | static void setup_restart(void) |
| 54 | { |
| 55 | /* |
| 56 | * Tell the mm system that we are going to reboot - |
| 57 | * we may need it to insert some 1:1 mappings so that |
| 58 | * soft boot works. |
| 59 | */ |
| 60 | setup_mm_for_reboot(); |
| 61 | |
| 62 | /* Clean and invalidate caches */ |
| 63 | flush_cache_all(); |
| 64 | |
| 65 | /* Turn D-cache off */ |
| 66 | cpu_cache_off(); |
| 67 | |
| 68 | /* Push out any further dirty data, and ensure cache is empty */ |
| 69 | flush_cache_all(); |
| 70 | } |
| 71 | |
| 72 | void soft_restart(unsigned long addr) |
| 73 | { |
| 74 | setup_restart(); |
| 75 | cpu_reset(addr); |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * Function pointers to optional machine specific functions |
| 80 | */ |
| 81 | void (*pm_power_off)(void); |
| 82 | EXPORT_SYMBOL_GPL(pm_power_off); |
| 83 | |
| 84 | void (*pm_restart)(const char *cmd); |
| 85 | EXPORT_SYMBOL_GPL(pm_restart); |
| 86 | |
| 87 | |
| 88 | /* |
| 89 | * This is our default idle handler. |
| 90 | */ |
| 91 | static void default_idle(void) |
| 92 | { |
| 93 | /* |
| 94 | * This should do all the clock switching and wait for interrupt |
| 95 | * tricks |
| 96 | */ |
| 97 | cpu_do_idle(); |
| 98 | local_irq_enable(); |
| 99 | } |
| 100 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 101 | /* |
Len Brown | dc883ca | 2013-02-09 23:15:13 -0500 | [diff] [blame] | 102 | * The idle thread. |
| 103 | * We always respect 'hlt_counter' to prevent low power idle. |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 104 | */ |
| 105 | void cpu_idle(void) |
| 106 | { |
| 107 | local_fiq_enable(); |
| 108 | |
| 109 | /* endless idle loop with no priority at all */ |
| 110 | while (1) { |
| 111 | tick_nohz_idle_enter(); |
| 112 | rcu_idle_enter(); |
| 113 | while (!need_resched()) { |
| 114 | /* |
| 115 | * We need to disable interrupts here to ensure |
| 116 | * we don't miss a wakeup call. |
| 117 | */ |
| 118 | local_irq_disable(); |
| 119 | if (!need_resched()) { |
| 120 | stop_critical_timings(); |
Len Brown | dc883ca | 2013-02-09 23:15:13 -0500 | [diff] [blame] | 121 | default_idle(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 122 | start_critical_timings(); |
| 123 | /* |
Len Brown | dc883ca | 2013-02-09 23:15:13 -0500 | [diff] [blame] | 124 | * default_idle functions should always return |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 125 | * with IRQs enabled. |
| 126 | */ |
| 127 | WARN_ON(irqs_disabled()); |
| 128 | } else { |
| 129 | local_irq_enable(); |
| 130 | } |
| 131 | } |
| 132 | rcu_idle_exit(); |
| 133 | tick_nohz_idle_exit(); |
| 134 | schedule_preempt_disabled(); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | void machine_shutdown(void) |
| 139 | { |
| 140 | #ifdef CONFIG_SMP |
| 141 | smp_send_stop(); |
| 142 | #endif |
| 143 | } |
| 144 | |
| 145 | void machine_halt(void) |
| 146 | { |
| 147 | machine_shutdown(); |
| 148 | while (1); |
| 149 | } |
| 150 | |
| 151 | void machine_power_off(void) |
| 152 | { |
| 153 | machine_shutdown(); |
| 154 | if (pm_power_off) |
| 155 | pm_power_off(); |
| 156 | } |
| 157 | |
| 158 | void machine_restart(char *cmd) |
| 159 | { |
| 160 | machine_shutdown(); |
| 161 | |
| 162 | /* Disable interrupts first */ |
| 163 | local_irq_disable(); |
| 164 | local_fiq_disable(); |
| 165 | |
| 166 | /* Now call the architecture specific reboot code. */ |
| 167 | if (pm_restart) |
| 168 | pm_restart(cmd); |
| 169 | |
| 170 | /* |
| 171 | * Whoops - the architecture was unable to reboot. |
| 172 | */ |
| 173 | printk("Reboot failed -- System halted\n"); |
| 174 | while (1); |
| 175 | } |
| 176 | |
| 177 | void __show_regs(struct pt_regs *regs) |
| 178 | { |
| 179 | int i; |
| 180 | |
| 181 | printk("CPU: %d %s (%s %.*s)\n", |
| 182 | raw_smp_processor_id(), print_tainted(), |
| 183 | init_utsname()->release, |
| 184 | (int)strcspn(init_utsname()->version, " "), |
| 185 | init_utsname()->version); |
| 186 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
| 187 | print_symbol("LR is at %s\n", regs->regs[30]); |
| 188 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
| 189 | regs->pc, regs->regs[30], regs->pstate); |
| 190 | printk("sp : %016llx\n", regs->sp); |
| 191 | for (i = 29; i >= 0; i--) { |
| 192 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
| 193 | if (i % 2 == 0) |
| 194 | printk("\n"); |
| 195 | } |
| 196 | printk("\n"); |
| 197 | } |
| 198 | |
| 199 | void show_regs(struct pt_regs * regs) |
| 200 | { |
| 201 | printk("\n"); |
| 202 | printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm); |
| 203 | __show_regs(regs); |
| 204 | } |
| 205 | |
| 206 | /* |
| 207 | * Free current thread data structures etc.. |
| 208 | */ |
| 209 | void exit_thread(void) |
| 210 | { |
| 211 | } |
| 212 | |
| 213 | void flush_thread(void) |
| 214 | { |
| 215 | fpsimd_flush_thread(); |
| 216 | flush_ptrace_hw_breakpoint(current); |
| 217 | } |
| 218 | |
| 219 | void release_thread(struct task_struct *dead_task) |
| 220 | { |
| 221 | } |
| 222 | |
| 223 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 224 | { |
| 225 | fpsimd_save_state(¤t->thread.fpsimd_state); |
| 226 | *dst = *src; |
| 227 | return 0; |
| 228 | } |
| 229 | |
| 230 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); |
| 231 | |
| 232 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, |
Al Viro | afa86fc | 2012-10-22 22:51:14 -0400 | [diff] [blame] | 233 | unsigned long stk_sz, struct task_struct *p) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 234 | { |
| 235 | struct pt_regs *childregs = task_pt_regs(p); |
| 236 | unsigned long tls = p->thread.tp_value; |
| 237 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 238 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 239 | |
Al Viro | 9ac0800 | 2012-10-21 15:56:52 -0400 | [diff] [blame] | 240 | if (likely(!(p->flags & PF_KTHREAD))) { |
| 241 | *childregs = *current_pt_regs(); |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 242 | childregs->regs[0] = 0; |
| 243 | if (is_compat_thread(task_thread_info(p))) { |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 244 | if (stack_start) |
| 245 | childregs->compat_sp = stack_start; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 246 | } else { |
| 247 | /* |
| 248 | * Read the current TLS pointer from tpidr_el0 as it may be |
| 249 | * out-of-sync with the saved value. |
| 250 | */ |
| 251 | asm("mrs %0, tpidr_el0" : "=r" (tls)); |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 252 | if (stack_start) { |
| 253 | /* 16-byte aligned stack mandatory on AArch64 */ |
| 254 | if (stack_start & 15) |
| 255 | return -EINVAL; |
| 256 | childregs->sp = stack_start; |
| 257 | } |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 258 | } |
| 259 | /* |
| 260 | * If a TLS pointer was passed to clone (4th argument), use it |
| 261 | * for the new thread. |
| 262 | */ |
| 263 | if (clone_flags & CLONE_SETTLS) |
Al Viro | 9ac0800 | 2012-10-21 15:56:52 -0400 | [diff] [blame] | 264 | tls = childregs->regs[3]; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 265 | } else { |
| 266 | memset(childregs, 0, sizeof(struct pt_regs)); |
| 267 | childregs->pstate = PSR_MODE_EL1h; |
| 268 | p->thread.cpu_context.x19 = stack_start; |
| 269 | p->thread.cpu_context.x20 = stk_sz; |
| 270 | } |
| 271 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
| 272 | p->thread.cpu_context.sp = (unsigned long)childregs; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 273 | p->thread.tp_value = tls; |
| 274 | |
| 275 | ptrace_hw_copy_thread(p); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static void tls_thread_switch(struct task_struct *next) |
| 281 | { |
| 282 | unsigned long tpidr, tpidrro; |
| 283 | |
| 284 | if (!is_compat_task()) { |
| 285 | asm("mrs %0, tpidr_el0" : "=r" (tpidr)); |
| 286 | current->thread.tp_value = tpidr; |
| 287 | } |
| 288 | |
| 289 | if (is_compat_thread(task_thread_info(next))) { |
| 290 | tpidr = 0; |
| 291 | tpidrro = next->thread.tp_value; |
| 292 | } else { |
| 293 | tpidr = next->thread.tp_value; |
| 294 | tpidrro = 0; |
| 295 | } |
| 296 | |
| 297 | asm( |
| 298 | " msr tpidr_el0, %0\n" |
| 299 | " msr tpidrro_el0, %1" |
| 300 | : : "r" (tpidr), "r" (tpidrro)); |
| 301 | } |
| 302 | |
| 303 | /* |
| 304 | * Thread switching. |
| 305 | */ |
| 306 | struct task_struct *__switch_to(struct task_struct *prev, |
| 307 | struct task_struct *next) |
| 308 | { |
| 309 | struct task_struct *last; |
| 310 | |
| 311 | fpsimd_thread_switch(next); |
| 312 | tls_thread_switch(next); |
| 313 | hw_breakpoint_thread_switch(next); |
Christopher Covington | 3325732 | 2013-04-03 19:01:01 +0100 | [diff] [blame] | 314 | contextidr_thread_switch(next); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 315 | |
Catalin Marinas | 5108c67 | 2013-04-24 14:47:02 +0100 | [diff] [blame^] | 316 | /* |
| 317 | * Complete any pending TLB or cache maintenance on this CPU in case |
| 318 | * the thread migrates to a different CPU. |
| 319 | */ |
| 320 | dsb(); |
| 321 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 322 | /* the actual thread switch */ |
| 323 | last = cpu_switch_to(prev, next); |
| 324 | |
| 325 | return last; |
| 326 | } |
| 327 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 328 | unsigned long get_wchan(struct task_struct *p) |
| 329 | { |
| 330 | struct stackframe frame; |
| 331 | int count = 0; |
| 332 | if (!p || p == current || p->state == TASK_RUNNING) |
| 333 | return 0; |
| 334 | |
| 335 | frame.fp = thread_saved_fp(p); |
| 336 | frame.sp = thread_saved_sp(p); |
| 337 | frame.pc = thread_saved_pc(p); |
| 338 | do { |
| 339 | int ret = unwind_frame(&frame); |
| 340 | if (ret < 0) |
| 341 | return 0; |
| 342 | if (!in_sched_functions(frame.pc)) |
| 343 | return frame.pc; |
| 344 | } while (count ++ < 16); |
| 345 | return 0; |
| 346 | } |
| 347 | |
| 348 | unsigned long arch_align_stack(unsigned long sp) |
| 349 | { |
| 350 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 351 | sp -= get_random_int() & ~PAGE_MASK; |
| 352 | return sp & ~0xf; |
| 353 | } |
| 354 | |
| 355 | static unsigned long randomize_base(unsigned long base) |
| 356 | { |
| 357 | unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1; |
| 358 | return randomize_range(base, range_end, 0) ? : base; |
| 359 | } |
| 360 | |
| 361 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 362 | { |
| 363 | return randomize_base(mm->brk); |
| 364 | } |
| 365 | |
| 366 | unsigned long randomize_et_dyn(unsigned long base) |
| 367 | { |
| 368 | return randomize_base(base); |
| 369 | } |