blob: 9fd2d9dc36896c5e7bef5fb224e4a88afb0ee92e [file] [log] [blame]
Krzysztof Kozlowski84b21702017-12-25 20:54:32 +01001// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2003-2004 Simtec Electronics
4// Ben Dooks <ben@simtec.co.uk>
5//
Alexander A. Klimov3ecdf2a2020-07-19 11:39:39 +02006// https://www.handhelds.org/projects/rx3715.html
Linus Torvalds1da177e2005-04-16 15:20:36 -07007
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/list.h>
Russell King8d717a52010-05-22 19:47:18 +010012#include <linux/memblock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/timer.h>
14#include <linux/init.h>
15#include <linux/tty.h>
16#include <linux/console.h>
Kay Sieversedbaa602011-12-21 16:26:03 -080017#include <linux/device.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010018#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/serial_core.h>
Tushar Behera334a1c72014-02-14 10:32:45 +090020#include <linux/serial_s3c.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/serial.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Ben Dooks272eb572006-04-02 16:16:15 +010023#include <linux/mtd/mtd.h>
Boris Brezillond4092d72017-08-04 17:29:10 +020024#include <linux/mtd/rawnand.h>
Miquel Raynale5acf9c2020-09-30 01:01:15 +020025#include <linux/mtd/nand-ecc-sw-hamming.h>
Ben Dooks272eb572006-04-02 16:16:15 +010026#include <linux/mtd/partitions.h>
27
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/mach/arch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/mach/irq.h>
Kukjin Kim232910d2013-01-02 10:18:58 -080030#include <asm/mach/map.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Kukjin Kim232910d2013-01-02 10:18:58 -080032#include <linux/platform_data/mtd-nand-s3c2410.h>
Arnd Bergmann81994e02019-09-02 22:33:24 +020033#include <linux/platform_data/fb-s3c2410.h>
Kukjin Kim232910d2013-01-02 10:18:58 -080034
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/irq.h>
36#include <asm/mach-types.h>
37
Arnd Bergmannc6ff1322019-09-02 18:37:30 +020038#include "regs-gpio.h"
39#include "gpio-samsung.h"
40#include "gpio-cfg.h"
Ben Dookse838ffc2005-11-01 19:44:28 +000041
Arnd Bergmannc6ff1322019-09-02 18:37:30 +020042#include "cpu.h"
43#include "devs.h"
44#include "pm.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Arnd Bergmann71b91142019-09-02 17:47:55 +020046#include "s3c24xx.h"
Kukjin Kim232910d2013-01-02 10:18:58 -080047#include "h1940.h"
Kukjin Kimb27b0722012-01-03 14:02:03 +010048
Linus Torvalds1da177e2005-04-16 15:20:36 -070049static struct map_desc rx3715_iodesc[] __initdata = {
50 /* dump ISA space somewhere unused */
51
Ben Dooksff6ffa82005-11-09 14:05:31 +000052 {
53 .virtual = (u32)S3C24XX_VA_ISA_WORD,
54 .pfn = __phys_to_pfn(S3C2410_CS3),
55 .length = SZ_1M,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
59 .pfn = __phys_to_pfn(S3C2410_CS3),
60 .length = SZ_1M,
61 .type = MT_DEVICE,
62 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070063};
64
Linus Torvalds1da177e2005-04-16 15:20:36 -070065static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
66 [0] = {
67 .hwport = 0,
68 .flags = 0,
69 .ucon = 0x3c5,
70 .ulcon = 0x03,
71 .ufcon = 0x51,
Thomas Abrahamafba7f92011-10-24 11:47:51 +020072 .clk_sel = S3C2410_UCON_CLKSEL3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 },
74 [1] = {
75 .hwport = 1,
76 .flags = 0,
77 .ucon = 0x3c5,
78 .ulcon = 0x03,
79 .ufcon = 0x00,
Thomas Abrahamafba7f92011-10-24 11:47:51 +020080 .clk_sel = S3C2410_UCON_CLKSEL3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 },
82 /* IR port */
83 [2] = {
84 .hwport = 2,
85 .uart_flags = UPF_CONS_FLOW,
86 .ucon = 0x3c5,
87 .ulcon = 0x43,
88 .ufcon = 0x51,
Thomas Abrahamafba7f92011-10-24 11:47:51 +020089 .clk_sel = S3C2410_UCON_CLKSEL3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 }
91};
92
Ben Dookse838ffc2005-11-01 19:44:28 +000093/* framebuffer lcd controller information */
94
Krzysztof Helt09fe75f2007-10-16 01:28:56 -070095static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
Krzysztof Heltf28ef572007-10-16 01:28:58 -070096 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
97 S3C2410_LCDCON5_FRM565 |
98 S3C2410_LCDCON5_HWSWP,
Ben Dookse838ffc2005-11-01 19:44:28 +000099
Krzysztof Helt1f411532007-10-16 01:28:57 -0700100 .type = S3C2410_LCDCON1_TFT,
101 .width = 240,
102 .height = 320,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700103
Krzysztof Helt69816692007-10-16 01:29:06 -0700104 .pixclock = 260000,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700105 .xres = 240,
106 .yres = 320,
107 .bpp = 16,
108 .left_margin = 36,
109 .right_margin = 36,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700110 .hsync_len = 8,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700111 .upper_margin = 6,
112 .lower_margin = 7,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700113 .vsync_len = 3,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700114};
115
116static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
117
118 .displays = &rx3715_lcdcfg,
119 .num_displays = 1,
120 .default_display = 0,
121
Ben Dookse838ffc2005-11-01 19:44:28 +0000122 .lpcsel = 0xf82,
123
124 .gpccon = 0xaa955699,
125 .gpccon_mask = 0xffc003cc,
Arnd Bergmann81994e02019-09-02 22:33:24 +0200126 .gpccon_reg = S3C2410_GPCCON,
Ben Dookse838ffc2005-11-01 19:44:28 +0000127 .gpcup = 0x0000ffff,
128 .gpcup_mask = 0xffffffff,
Arnd Bergmann81994e02019-09-02 22:33:24 +0200129 .gpcup_reg = S3C2410_GPCUP,
Ben Dookse838ffc2005-11-01 19:44:28 +0000130
131 .gpdcon = 0xaa95aaa1,
132 .gpdcon_mask = 0xffc0fff0,
Arnd Bergmann81994e02019-09-02 22:33:24 +0200133 .gpdcon_reg = S3C2410_GPDCON,
Ben Dookse838ffc2005-11-01 19:44:28 +0000134 .gpdup = 0x0000faff,
135 .gpdup_mask = 0xffffffff,
Arnd Bergmann81994e02019-09-02 22:33:24 +0200136 .gpdup_reg = S3C2410_GPDUP,
Ben Dookse838ffc2005-11-01 19:44:28 +0000137};
138
Ben Dooks2a3a1802009-09-28 13:59:49 +0300139static struct mtd_partition __initdata rx3715_nand_part[] = {
Ben Dooks272eb572006-04-02 16:16:15 +0100140 [0] = {
141 .name = "Whole Flash",
142 .offset = 0,
143 .size = MTDPART_SIZ_FULL,
144 .mask_flags = MTD_WRITEABLE,
145 }
146};
147
Ben Dooks2a3a1802009-09-28 13:59:49 +0300148static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
Ben Dooks272eb572006-04-02 16:16:15 +0100149 [0] = {
150 .name = "Internal",
151 .nr_chips = 1,
152 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
153 .partitions = rx3715_nand_part,
154 },
155};
156
Ben Dooks2a3a1802009-09-28 13:59:49 +0300157static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
Ben Dooks272eb572006-04-02 16:16:15 +0100158 .tacls = 25,
159 .twrph0 = 50,
160 .twrph1 = 15,
161 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
162 .sets = rx3715_nand_sets,
Miquel Raynalbace41f2020-08-27 10:51:58 +0200163 .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
Ben Dooks272eb572006-04-02 16:16:15 +0100164};
165
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166static struct platform_device *rx3715_devices[] __initdata = {
Ben Dooksb8132482009-11-23 00:13:39 +0000167 &s3c_device_ohci,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 &s3c_device_lcd,
169 &s3c_device_wdt,
Ben Dooks3e1b7762008-10-31 16:14:40 +0000170 &s3c_device_i2c0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 &s3c_device_iis,
Ben Dooks272eb572006-04-02 16:16:15 +0100172 &s3c_device_nand,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173};
174
Ben Dooks5fe10ab2005-09-20 17:24:33 +0100175static void __init rx3715_map_io(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176{
177 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
Krzysztof Kozlowskia1342f62020-08-20 22:42:03 +0200179 s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180}
181
Heiko Stuebnera28d6182014-05-09 05:49:19 +0900182static void __init rx3715_init_time(void)
183{
184 s3c2440_init_clocks(16934000);
Krzysztof Kozlowskia1342f62020-08-20 22:42:03 +0200185 s3c24xx_timer_init();
Heiko Stuebnera28d6182014-05-09 05:49:19 +0900186}
187
Russell King98c672c2010-05-22 18:18:57 +0100188/* H1940 and RX3715 need to reserve this for suspend */
189static void __init rx3715_reserve(void)
190{
Russell King8d717a52010-05-22 19:47:18 +0100191 memblock_reserve(0x30003000, 0x1000);
192 memblock_reserve(0x30081000, 0x1000);
Russell King98c672c2010-05-22 18:18:57 +0100193}
194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195static void __init rx3715_init_machine(void)
196{
Krzysztof Heltb1dfe1f2007-03-19 15:10:20 +0100197#ifdef CONFIG_PM_H1940
Ben Dooksbbf6f282006-12-07 20:47:58 +0100198 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
Krzysztof Heltb1dfe1f2007-03-19 15:10:20 +0100199#endif
Ben Dooks4e59c252008-12-12 00:24:18 +0000200 s3c_pm_init();
Ben Dooksbbf6f282006-12-07 20:47:58 +0100201
Ben Dooks2a3a1802009-09-28 13:59:49 +0300202 s3c_nand_set_platdata(&rx3715_nand_info);
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700203 s3c24xx_fb_set_platdata(&rx3715_fb_info);
Arnd Bergmann673085f2020-08-06 20:20:45 +0200204 /* Configure the I2S pins (GPE0...GPE4) in correct mode */
205 s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
206 S3C_GPIO_PULL_NONE);
Ben Dooks57e51712007-04-20 11:19:16 +0100207 platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208}
Ben Dookse838ffc2005-11-01 19:44:28 +0000209
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210MACHINE_START(RX3715, "IPAQ-RX3715")
Ben Dooksafdd2252010-05-07 09:24:05 +0900211 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
Nicolas Pitre69d50712011-07-05 22:38:17 -0400212 .atag_offset = 0x100,
Russell Kinge9dea0c2005-07-03 17:38:58 +0100213 .map_io = rx3715_map_io,
Russell King98c672c2010-05-22 18:18:57 +0100214 .reserve = rx3715_reserve,
Heiko Stuebnerce6c1642013-02-12 09:59:20 -0800215 .init_irq = s3c2440_init_irq,
Russell Kinge9dea0c2005-07-03 17:38:58 +0100216 .init_machine = rx3715_init_machine,
Heiko Stuebnera28d6182014-05-09 05:49:19 +0900217 .init_time = rx3715_init_time,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218MACHINE_END