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Catalin Marinas9703d9d2012-03-05 11:49:27 +00001/*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/linkage.h>
24#include <linux/init.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010025#include <linux/irqchip/arm-gic-v3.h>
Catalin Marinas9703d9d2012-03-05 11:49:27 +000026
27#include <asm/assembler.h>
Ard Biesheuvel08cdac62016-04-18 17:09:47 +020028#include <asm/boot.h>
Catalin Marinas9703d9d2012-03-05 11:49:27 +000029#include <asm/ptrace.h>
30#include <asm/asm-offsets.h>
Catalin Marinasc218bca2014-03-26 18:25:55 +000031#include <asm/cache.h>
Javi Merino0359b0e2012-08-29 18:32:18 +010032#include <asm/cputype.h>
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +010033#include <asm/elf.h>
AKASHI Takahirof56063c52018-11-15 14:52:46 +090034#include <asm/image.h>
Suzuki K. Poulose87d15872015-10-19 14:19:27 +010035#include <asm/kernel-pgtable.h>
Marc Zyngier1f364c82014-02-19 09:33:14 +000036#include <asm/kvm_arm.h>
Catalin Marinas9703d9d2012-03-05 11:49:27 +000037#include <asm/memory.h>
Catalin Marinas9703d9d2012-03-05 11:49:27 +000038#include <asm/pgtable-hwdef.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
Suzuki K Poulosebb905272016-02-23 10:31:42 +000041#include <asm/smp.h>
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +010042#include <asm/sysreg.h>
43#include <asm/thread_info.h>
Marc Zyngierf35a9202012-10-26 15:40:05 +010044#include <asm/virt.h>
Catalin Marinas9703d9d2012-03-05 11:49:27 +000045
Ard Biesheuvelb5f4a212017-03-23 19:00:46 +000046#include "efi-header.S"
47
Ard Biesheuvel6f4d57f2015-03-17 09:14:29 +010048#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
Catalin Marinas9703d9d2012-03-05 11:49:27 +000049
Ard Biesheuvel41903122014-08-13 18:53:03 +010050#if (TEXT_OFFSET & 0xfff) != 0
51#error TEXT_OFFSET must be at least 4KB aligned
52#elif (PAGE_OFFSET & 0x1fffff) != 0
Mark Rutlandda57a362014-06-24 16:51:37 +010053#error PAGE_OFFSET must be at least 2MB aligned
Ard Biesheuvel41903122014-08-13 18:53:03 +010054#elif TEXT_OFFSET > 0x1fffff
Mark Rutlandda57a362014-06-24 16:51:37 +010055#error TEXT_OFFSET must be less than 2MB
Catalin Marinas9703d9d2012-03-05 11:49:27 +000056#endif
57
Catalin Marinas9703d9d2012-03-05 11:49:27 +000058/*
Catalin Marinas9703d9d2012-03-05 11:49:27 +000059 * Kernel startup entry point.
60 * ---------------------------
61 *
62 * The requirements are:
63 * MMU = off, D-cache = off, I-cache = on or off,
64 * x0 = physical address to the FDT blob.
65 *
66 * This code is mostly position independent so you call this at
67 * __pa(PAGE_OFFSET + TEXT_OFFSET).
68 *
69 * Note that the callee-saved registers are used for storing variables
70 * that are useful before the MMU is enabled. The allocations are described
71 * in the entry routines.
72 */
73 __HEAD
Ard Biesheuvel2bf31a42015-12-26 12:46:40 +010074_head:
Catalin Marinas9703d9d2012-03-05 11:49:27 +000075 /*
76 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
77 */
Mark Salter3c7f2552014-04-15 22:47:52 -040078#ifdef CONFIG_EFI
Mark Salter3c7f2552014-04-15 22:47:52 -040079 /*
80 * This add instruction has no meaningful effect except that
81 * its opcode forms the magic "MZ" signature required by UEFI.
82 */
83 add x13, x18, #0x16
84 b stext
85#else
Catalin Marinas9703d9d2012-03-05 11:49:27 +000086 b stext // branch to kernel start, magic
87 .long 0 // reserved
Mark Salter3c7f2552014-04-15 22:47:52 -040088#endif
Ard Biesheuvel6ad1fe52015-12-26 13:48:02 +010089 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
90 le64sym _kernel_size_le // Effective size of kernel image, little-endian
91 le64sym _kernel_flags_le // Informative flags, little-endian
Roy Franz4370eec2013-08-15 00:10:00 +010092 .quad 0 // reserved
93 .quad 0 // reserved
94 .quad 0 // reserved
AKASHI Takahirof56063c52018-11-15 14:52:46 +090095 .ascii ARM64_IMAGE_MAGIC // Magic number
Mark Salter3c7f2552014-04-15 22:47:52 -040096#ifdef CONFIG_EFI
Ard Biesheuvel2bf31a42015-12-26 12:46:40 +010097 .long pe_header - _head // Offset to the PE header.
Mark Salter3c7f2552014-04-15 22:47:52 -040098
Mark Salter3c7f2552014-04-15 22:47:52 -040099pe_header:
Ard Biesheuvelb5f4a212017-03-23 19:00:46 +0000100 __EFI_PE_HEADER
Ard Biesheuvel99922252017-03-23 19:00:47 +0000101#else
102 .long 0 // reserved
Mark Salter3c7f2552014-04-15 22:47:52 -0400103#endif
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000104
Ard Biesheuvel546c8c42016-03-30 17:43:07 +0200105 __INIT
106
Ard Biesheuvela9be2ee2016-08-31 12:05:17 +0100107 /*
108 * The following callee saved general purpose registers are used on the
109 * primary lowlevel boot path:
110 *
111 * Register Scope Purpose
112 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
113 * x23 stext() .. start_kernel() physical misalignment/KASLR offset
114 * x28 __create_page_tables() callee preserved temp register
115 * x19/x20 __primary_switch() callee preserved temp registers
116 */
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000117ENTRY(stext)
Ard Biesheuvelda9c1772015-03-17 10:55:12 +0100118 bl preserve_boot_args
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100119 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
Ard Biesheuvelb929fe32016-08-31 12:05:15 +0100120 adrp x23, __PHYS_OFFSET
121 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
Matthew Leach828e9832013-10-11 14:52:16 +0100122 bl set_cpu_boot_mode_flag
Ard Biesheuvelaea73ab2016-08-16 21:02:32 +0200123 bl __create_page_tables
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000124 /*
Marc Zyngiera591ede2015-03-18 14:55:20 +0000125 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
126 * details.
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000127 * On return, the CPU will be ready for the MMU to be turned on and
128 * the TCR will have been set.
129 */
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200130 bl __cpu_setup // initialise processor
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100131 b __primary_switch
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000132ENDPROC(stext)
133
134/*
Ard Biesheuvelda9c1772015-03-17 10:55:12 +0100135 * Preserve the arguments passed by the bootloader in x0 .. x3
136 */
137preserve_boot_args:
138 mov x21, x0 // x21=FDT
139
140 adr_l x0, boot_args // record the contents of
141 stp x21, x1, [x0] // x0 .. x3 at kernel entry
142 stp x2, x3, [x0, #16]
143
144 dmb sy // needed before dc ivac with
145 // MMU off
146
Robin Murphyd46befe2017-07-25 11:55:39 +0100147 mov x1, #0x20 // 4 x 8 bytes
148 b __inval_dcache_area // tail call
Ard Biesheuvelda9c1772015-03-17 10:55:12 +0100149ENDPROC(preserve_boot_args)
150
151/*
Laura Abbott034edab2014-11-21 13:50:41 -0800152 * Macro to create a table entry to the next page.
153 *
154 * tbl: page table address
155 * virt: virtual address
156 * shift: #imm page table shift
157 * ptrs: #imm pointers per table page
158 *
159 * Preserves: virt
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000160 * Corrupts: ptrs, tmp1, tmp2
Laura Abbott034edab2014-11-21 13:50:41 -0800161 * Returns: tbl -> next level table page address
162 */
163 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
Kristina Martsenkoe6d588a2017-12-13 17:07:19 +0000164 add \tmp1, \tbl, #PAGE_SIZE
Will Deacon79ddab32018-01-29 11:59:59 +0000165 phys_to_pte \tmp2, \tmp1
Kristina Martsenkoe6d588a2017-12-13 17:07:19 +0000166 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
Laura Abbott034edab2014-11-21 13:50:41 -0800167 lsr \tmp1, \virt, #\shift
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000168 sub \ptrs, \ptrs, #1
169 and \tmp1, \tmp1, \ptrs // table index
Laura Abbott034edab2014-11-21 13:50:41 -0800170 str \tmp2, [\tbl, \tmp1, lsl #3]
171 add \tbl, \tbl, #PAGE_SIZE // next level table page
172 .endm
173
174/*
Steve Capper0370b312018-01-11 10:11:59 +0000175 * Macro to populate page table entries, these entries can be pointers to the next level
176 * or last level entries pointing to physical memory.
Laura Abbott034edab2014-11-21 13:50:41 -0800177 *
Steve Capper0370b312018-01-11 10:11:59 +0000178 * tbl: page table address
179 * rtbl: pointer to page table or physical memory
180 * index: start index to write
181 * eindex: end index to write - [index, eindex] written to
182 * flags: flags for pagetable entry to or in
183 * inc: increment to rtbl between each entry
184 * tmp1: temporary variable
185 *
186 * Preserves: tbl, eindex, flags, inc
187 * Corrupts: index, tmp1
188 * Returns: rtbl
Laura Abbott034edab2014-11-21 13:50:41 -0800189 */
Steve Capper0370b312018-01-11 10:11:59 +0000190 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
Will Deacon79ddab32018-01-29 11:59:59 +0000191.Lpe\@: phys_to_pte \tmp1, \rtbl
Steve Capper0370b312018-01-11 10:11:59 +0000192 orr \tmp1, \tmp1, \flags // tmp1 = table entry
193 str \tmp1, [\tbl, \index, lsl #3]
194 add \rtbl, \rtbl, \inc // rtbl = pa next level
195 add \index, \index, #1
196 cmp \index, \eindex
197 b.ls .Lpe\@
Laura Abbott034edab2014-11-21 13:50:41 -0800198 .endm
199
200/*
Steve Capper0370b312018-01-11 10:11:59 +0000201 * Compute indices of table entries from virtual address range. If multiple entries
202 * were needed in the previous page table level then the next page table level is assumed
203 * to be composed of multiple pages. (This effectively scales the end index).
Laura Abbott034edab2014-11-21 13:50:41 -0800204 *
Steve Capper0370b312018-01-11 10:11:59 +0000205 * vstart: virtual address of start of range
206 * vend: virtual address of end of range
207 * shift: shift used to transform virtual address into index
208 * ptrs: number of entries in page table
209 * istart: index in table corresponding to vstart
210 * iend: index in table corresponding to vend
211 * count: On entry: how many extra entries were required in previous level, scales
212 * our end index.
213 * On exit: returns how many extra entries required for next page table level
214 *
215 * Preserves: vstart, vend, shift, ptrs
216 * Returns: istart, iend, count
Laura Abbott034edab2014-11-21 13:50:41 -0800217 */
Steve Capper0370b312018-01-11 10:11:59 +0000218 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
219 lsr \iend, \vend, \shift
220 mov \istart, \ptrs
221 sub \istart, \istart, #1
222 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
223 mov \istart, \ptrs
224 mul \istart, \istart, \count
225 add \iend, \iend, \istart // iend += (count - 1) * ptrs
226 // our entries span multiple tables
227
228 lsr \istart, \vstart, \shift
229 mov \count, \ptrs
230 sub \count, \count, #1
231 and \istart, \istart, \count
232
233 sub \count, \iend, \istart
234 .endm
235
236/*
237 * Map memory for specified virtual address range. Each level of page table needed supports
238 * multiple entries. If a level requires n entries the next page table level is assumed to be
239 * formed from n pages.
240 *
241 * tbl: location of page table
242 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
243 * vstart: start address to map
244 * vend: end address to map - we map [vstart, vend]
245 * flags: flags to use to map last level entries
246 * phys: physical address corresponding to vstart - physical memory is contiguous
247 * pgds: the number of pgd entries
248 *
249 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
250 * Preserves: vstart, vend, flags
251 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
252 */
253 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
254 add \rtbl, \tbl, #PAGE_SIZE
255 mov \sv, \rtbl
256 mov \count, #0
257 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
258 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
259 mov \tbl, \sv
260 mov \sv, \rtbl
261
262#if SWAPPER_PGTABLE_LEVELS > 3
263 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
264 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
265 mov \tbl, \sv
266 mov \sv, \rtbl
267#endif
268
269#if SWAPPER_PGTABLE_LEVELS > 2
270 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
271 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
272 mov \tbl, \sv
273#endif
274
275 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
276 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
277 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
Laura Abbott034edab2014-11-21 13:50:41 -0800278 .endm
279
280/*
281 * Setup the initial page tables. We only setup the barest amount which is
282 * required to get the kernel running. The following sections are required:
283 * - identity mapping to enable the MMU (low address, TTBR0)
284 * - first few MB of the kernel linear mapping to jump to once the MMU has
Ard Biesheuvel61bd93c2015-06-01 13:40:32 +0200285 * been enabled
Laura Abbott034edab2014-11-21 13:50:41 -0800286 */
287__create_page_tables:
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100288 mov x28, lr
Laura Abbott034edab2014-11-21 13:50:41 -0800289
290 /*
Jun Yao8eb7e282018-09-24 17:56:18 +0100291 * Invalidate the init page tables to avoid potential dirty cache lines
292 * being evicted. Other page tables are allocated in rodata as part of
293 * the kernel image, and thus are clean to the PoC per the boot
294 * protocol.
Laura Abbott034edab2014-11-21 13:50:41 -0800295 */
Jun Yao8eb7e282018-09-24 17:56:18 +0100296 adrp x0, init_pg_dir
Jun Yao2b5548b2018-09-24 15:47:49 +0100297 adrp x1, init_pg_end
Steve Capper0370b312018-01-11 10:11:59 +0000298 sub x1, x1, x0
Robin Murphyd46befe2017-07-25 11:55:39 +0100299 bl __inval_dcache_area
Laura Abbott034edab2014-11-21 13:50:41 -0800300
301 /*
Jun Yao8eb7e282018-09-24 17:56:18 +0100302 * Clear the init page tables.
Laura Abbott034edab2014-11-21 13:50:41 -0800303 */
Jun Yao8eb7e282018-09-24 17:56:18 +0100304 adrp x0, init_pg_dir
Jun Yao2b5548b2018-09-24 15:47:49 +0100305 adrp x1, init_pg_end
Steve Capper0370b312018-01-11 10:11:59 +0000306 sub x1, x1, x0
Laura Abbott034edab2014-11-21 13:50:41 -08003071: stp xzr, xzr, [x0], #16
308 stp xzr, xzr, [x0], #16
309 stp xzr, xzr, [x0], #16
310 stp xzr, xzr, [x0], #16
Robin Murphyd46befe2017-07-25 11:55:39 +0100311 subs x1, x1, #64
312 b.ne 1b
Laura Abbott034edab2014-11-21 13:50:41 -0800313
Ard Biesheuvelb03cc882016-04-18 17:09:45 +0200314 mov x7, SWAPPER_MM_MMUFLAGS
Laura Abbott034edab2014-11-21 13:50:41 -0800315
316 /*
317 * Create the identity mapping.
318 */
Ard Biesheuvelaea73ab2016-08-16 21:02:32 +0200319 adrp x0, idmap_pg_dir
Ard Biesheuvel5dfe9d72015-06-01 13:40:33 +0200320 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000321
Will Deacon68d23da2018-12-10 14:15:15 +0000322#ifdef CONFIG_ARM64_USER_VA_BITS_52
Steve Capper67e7fdf2018-12-06 22:50:41 +0000323 mrs_s x6, SYS_ID_AA64MMFR2_EL1
324 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
325 mov x5, #52
326 cbnz x6, 1f
327#endif
328 mov x5, #VA_BITS
3291:
330 adr_l x6, vabits_user
331 str x5, [x6]
332 dmb sy
333 dc ivac, x6 // Invalidate potentially stale cache line
334
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000335 /*
336 * VA_BITS may be too small to allow for an ID mapping to be created
337 * that covers system RAM if that is located sufficiently high in the
338 * physical address space. So for the ID map, use an extended virtual
339 * range in that case, and configure an additional translation level
340 * if needed.
341 *
342 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
343 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
344 * this number conveniently equals the number of leading zeroes in
345 * the physical address of __idmap_text_end.
346 */
347 adrp x5, __idmap_text_end
348 clz x5, x5
349 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
350 b.ge 1f // .. then skip VA range extension
351
352 adr_l x6, idmap_t0sz
353 str x5, [x6]
354 dmb sy
355 dc ivac, x6 // Invalidate potentially stale cache line
356
357#if (VA_BITS < 48)
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000358#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000359#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000360
361 /*
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000362 * If VA_BITS < 48, we have to configure an additional table level.
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000363 * First, we have to verify our assumption that the current value of
364 * VA_BITS was chosen such that all translation levels are fully
365 * utilised, and that lowering T0SZ will always result in an additional
366 * translation level to be configured.
367 */
368#if VA_BITS != EXTRA_SHIFT
369#error "Mismatch between VA_BITS and page size/number of translation levels"
370#endif
371
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000372 mov x4, EXTRA_PTRS
373 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
374#else
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000375 /*
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000376 * If VA_BITS == 48, we don't have to configure an additional
377 * translation level, but the top-level table has more entries.
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000378 */
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000379 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
380 str_l x4, idmap_ptrs_per_pgd, x5
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000381#endif
Kristina Martsenkofa2a8442017-12-13 17:07:24 +00003821:
383 ldr_l x4, idmap_ptrs_per_pgd
Ard Biesheuvel5dfe9d72015-06-01 13:40:33 +0200384 mov x5, x3 // __pa(__idmap_text_start)
385 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
Steve Capper0370b312018-01-11 10:11:59 +0000386
387 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
Laura Abbott034edab2014-11-21 13:50:41 -0800388
389 /*
390 * Map the kernel image (starting with PHYS_OFFSET).
391 */
Jun Yao2b5548b2018-09-24 15:47:49 +0100392 adrp x0, init_pg_dir
Ard Biesheuvel18b9c0d2016-04-18 17:09:46 +0200393 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100394 add x5, x5, x23 // add KASLR displacement
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000395 mov x4, PTRS_PER_PGD
Ard Biesheuvel18b9c0d2016-04-18 17:09:46 +0200396 adrp x6, _end // runtime __pa(_end)
397 adrp x3, _text // runtime __pa(_text)
398 sub x6, x6, x3 // _end - _text
399 add x6, x6, x5 // runtime __va(_end)
Steve Capper0370b312018-01-11 10:11:59 +0000400
401 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
Laura Abbott034edab2014-11-21 13:50:41 -0800402
403 /*
Laura Abbott034edab2014-11-21 13:50:41 -0800404 * Since the page tables have been populated with non-cacheable
405 * accesses (MMU disabled), invalidate the idmap and swapper page
406 * tables again to remove any speculatively loaded cache lines.
407 */
Ard Biesheuvelaea73ab2016-08-16 21:02:32 +0200408 adrp x0, idmap_pg_dir
Jun Yao2b5548b2018-09-24 15:47:49 +0100409 adrp x1, init_pg_end
Steve Capper0370b312018-01-11 10:11:59 +0000410 sub x1, x1, x0
Mark Rutland91d57152015-03-24 13:50:27 +0000411 dmb sy
Robin Murphyd46befe2017-07-25 11:55:39 +0100412 bl __inval_dcache_area
Laura Abbott034edab2014-11-21 13:50:41 -0800413
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100414 ret x28
Laura Abbott034edab2014-11-21 13:50:41 -0800415ENDPROC(__create_page_tables)
416 .ltorg
417
Laura Abbott034edab2014-11-21 13:50:41 -0800418/*
Ard Biesheuvela871d352015-03-04 11:51:48 +0100419 * The following fragment of code is executed with the MMU enabled.
Ard Biesheuvelb929fe32016-08-31 12:05:15 +0100420 *
421 * x0 = __PHYS_OFFSET
Laura Abbott034edab2014-11-21 13:50:41 -0800422 */
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200423__primary_switched:
Ard Biesheuvel60699ba2016-08-31 12:05:16 +0100424 adrp x4, init_thread_union
425 add sp, x4, #THREAD_SIZE
Mark Rutlandc02433d2016-11-03 20:23:13 +0000426 adr_l x5, init_task
427 msr sp_el0, x5 // Save thread_info
Ard Biesheuvel60699ba2016-08-31 12:05:16 +0100428
Ard Biesheuvel2bf31a42015-12-26 12:46:40 +0100429 adr_l x8, vectors // load VBAR_EL1 with virtual
430 msr vbar_el1, x8 // vector table address
431 isb
432
Ard Biesheuvel60699ba2016-08-31 12:05:16 +0100433 stp xzr, x30, [sp, #-16]!
434 mov x29, sp
435
Ard Biesheuvelb929fe32016-08-31 12:05:15 +0100436 str_l x21, __fdt_pointer, x5 // Save FDT pointer
437
438 ldr_l x4, kimage_vaddr // Save the offset between
439 sub x4, x4, x0 // the kernel virtual and
440 str_l x4, kimage_voffset, x5 // physical mappings
441
Mark Rutland2a803c42016-01-06 11:05:27 +0000442 // Clear BSS
443 adr_l x0, __bss_start
444 mov x1, xzr
445 adr_l x2, __bss_stop
446 sub x2, x2, x0
447 bl __pi_memset
Mark Rutland5227cfa2016-01-25 11:44:57 +0000448 dsb ishst // Make zero page visible to PTW
Laura Abbott034edab2014-11-21 13:50:41 -0800449
Andrey Ryabinin39d114d2015-10-12 18:52:58 +0300450#ifdef CONFIG_KASAN
451 bl kasan_early_init
452#endif
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100453#ifdef CONFIG_RANDOMIZE_BASE
Ard Biesheuvel08cdac62016-04-18 17:09:47 +0200454 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
455 b.ne 0f
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100456 mov x0, x21 // pass FDT address in x0
457 bl kaslr_early_init // parse FDT for KASLR options
458 cbz x0, 0f // KASLR disabled? just proceed
Ard Biesheuvel08cdac62016-04-18 17:09:47 +0200459 orr x23, x23, x0 // record KASLR offset
Ard Biesheuvel60699ba2016-08-31 12:05:16 +0100460 ldp x29, x30, [sp], #16 // we must enable KASLR, return
461 ret // to __primary_switch()
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01004620:
463#endif
Ard Biesheuvel73267492017-07-22 18:45:33 +0100464 add sp, sp, #16
465 mov x29, #0
466 mov x30, #0
Laura Abbott034edab2014-11-21 13:50:41 -0800467 b start_kernel
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200468ENDPROC(__primary_switched)
Laura Abbott034edab2014-11-21 13:50:41 -0800469
470/*
471 * end early head section, begin head code that is also used for
472 * hotplug and needs to have the same protections as the text region
473 */
Will Deacon439e70e2018-01-29 12:00:00 +0000474 .section ".idmap.text","awx"
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100475
476ENTRY(kimage_vaddr)
477 .quad _text - TEXT_OFFSET
Will Deaconb89d82e2019-01-08 16:19:01 +0000478EXPORT_SYMBOL(kimage_vaddr)
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100479
Laura Abbott034edab2014-11-21 13:50:41 -0800480/*
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000481 * If we're fortunate enough to boot at EL2, ensure that the world is
482 * sane before dropping to EL1.
Matthew Leach828e9832013-10-11 14:52:16 +0100483 *
Mark Rutland510224c2017-01-09 14:31:55 +0000484 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
Matthew Leach828e9832013-10-11 14:52:16 +0100485 * booted in EL1 or EL2 respectively.
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000486 */
487ENTRY(el2_setup)
Marc Zyngier53715132017-09-26 15:57:16 +0100488 msr SPsel, #1 // We want to use SP_EL{1,2}
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000489 mrs x0, CurrentEL
Marc Zyngier974c8e42014-06-06 14:16:21 +0100490 cmp x0, #CurrentEL_EL2
Mark Rutland3ad47d02017-02-15 14:54:16 +0000491 b.eq 1f
James Morse7a00d682018-01-15 19:38:55 +0000492 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
Matthew Leach9cf71722013-10-11 14:52:17 +0100493 msr sctlr_el1, x0
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100494 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
Matthew Leach9cf71722013-10-11 14:52:17 +0100495 isb
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000496 ret
497
James Morse7a00d682018-01-15 19:38:55 +00004981: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
Mark Rutland3ad47d02017-02-15 14:54:16 +0000499 msr sctlr_el2, x0
500
Marc Zyngier1f364c82014-02-19 09:33:14 +0000501#ifdef CONFIG_ARM64_VHE
502 /*
503 * Check for VHE being present. For the rest of the EL2 setup,
504 * x2 being non-zero indicates that we do have VHE, and that the
505 * kernel is intended to run at EL2.
506 */
507 mrs x2, id_aa64mmfr1_el1
Alexandru Eliseif6e56432019-04-05 11:20:12 +0100508 ubfx x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
Marc Zyngier1f364c82014-02-19 09:33:14 +0000509#else
510 mov x2, xzr
511#endif
512
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000513 /* Hyp configuration. */
Mark Rutland4eaed6a2018-12-07 18:39:21 +0000514 mov_q x0, HCR_HOST_NVHE_FLAGS
Marc Zyngier1f364c82014-02-19 09:33:14 +0000515 cbz x2, set_hcr
Mark Rutland4eaed6a2018-12-07 18:39:21 +0000516 mov_q x0, HCR_HOST_VHE_FLAGS
Marc Zyngier1f364c82014-02-19 09:33:14 +0000517set_hcr:
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000518 msr hcr_el2, x0
Marc Zyngier1f364c82014-02-19 09:33:14 +0000519 isb
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000520
Jintack1650ac42016-11-28 21:13:02 -0500521 /*
522 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
523 * This is not necessary for VHE, since the host kernel runs in EL2,
524 * and EL0 accesses are configured in the later stage of boot process.
525 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
526 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
527 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
528 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
529 * EL2.
530 */
531 cbnz x2, 1f
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000532 mrs x0, cnthctl_el2
533 orr x0, x0, #3 // Enable EL1 physical timers
534 msr cnthctl_el2, x0
Jintack1650ac42016-11-28 21:13:02 -05005351:
Will Deacon1f75ff02012-11-29 22:48:31 +0000536 msr cntvoff_el2, xzr // Clear virtual offset
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000537
Marc Zyngier021f6532014-06-30 16:01:31 +0100538#ifdef CONFIG_ARM_GIC_V3
539 /* GICv3 system register access */
540 mrs x0, id_aa64pfr0_el1
Alexandru Eliseif6e56432019-04-05 11:20:12 +0100541 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
Vladimir Murzin74698f62019-02-20 11:43:05 +0000542 cbz x0, 3f
Marc Zyngier021f6532014-06-30 16:01:31 +0100543
Mark Rutland0e9884f2017-01-19 17:57:43 +0000544 mrs_s x0, SYS_ICC_SRE_EL2
Marc Zyngier021f6532014-06-30 16:01:31 +0100545 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
546 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
Mark Rutland0e9884f2017-01-19 17:57:43 +0000547 msr_s SYS_ICC_SRE_EL2, x0
Marc Zyngier021f6532014-06-30 16:01:31 +0100548 isb // Make sure SRE is now set
Mark Rutland0e9884f2017-01-19 17:57:43 +0000549 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
Marc Zyngierd2719762015-09-30 11:39:59 +0100550 tbz x0, #0, 3f // and check that it sticks
Mark Rutland0e9884f2017-01-19 17:57:43 +0000551 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
Marc Zyngier021f6532014-06-30 16:01:31 +0100552
5533:
554#endif
555
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000556 /* Populate ID registers. */
557 mrs x0, midr_el1
558 mrs x1, mpidr_el1
559 msr vpidr_el2, x0
560 msr vmpidr_el2, x1
561
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000562#ifdef CONFIG_COMPAT
563 msr hstr_el2, xzr // Disable CP15 traps to EL2
564#endif
565
Will Deacond10bcd42015-09-02 18:49:28 +0100566 /* EL2 debug */
Alexandru Eliseif6e56432019-04-05 11:20:12 +0100567 mrs x1, id_aa64dfr0_el1
568 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
Lorenzo Pieralisif436b2a2016-01-13 14:50:03 +0000569 cmp x0, #1
570 b.lt 4f // Skip if no PMU present
Will Deacond10bcd42015-09-02 18:49:28 +0100571 mrs x0, pmcr_el0 // Disable debug access traps
572 ubfx x0, x0, #11, #5 // to EL2 and allow access to
Lorenzo Pieralisif436b2a2016-01-13 14:50:03 +00005734:
Will Deacon2bf47e12016-09-22 11:25:25 +0100574 csel x3, xzr, x0, lt // all PMU counters from EL1
575
576 /* Statistical profiling */
Alexandru Eliseif6e56432019-04-05 11:20:12 +0100577 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
Will Deaconb0c57e12017-07-07 13:47:02 +0100578 cbz x0, 7f // Skip if SPE not present
579 cbnz x2, 6f // VHE?
580 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2,
581 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
582 cbnz x4, 5f // then permit sampling of physical
583 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
584 1 << SYS_PMSCR_EL2_PA_SHIFT)
585 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter
5865:
Will Deacon2bf47e12016-09-22 11:25:25 +0100587 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
588 orr x3, x3, x1 // If we don't have VHE, then
Will Deaconb0c57e12017-07-07 13:47:02 +0100589 b 7f // use EL1&0 translation.
5906: // For VHE, use EL2 translation
Will Deacon2bf47e12016-09-22 11:25:25 +0100591 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
Will Deaconb0c57e12017-07-07 13:47:02 +01005927:
Will Deacon2bf47e12016-09-22 11:25:25 +0100593 msr mdcr_el2, x3 // Configure debug traps
Will Deacond10bcd42015-09-02 18:49:28 +0100594
Mark Rutlandcc33c4e2018-02-13 13:39:23 +0000595 /* LORegions */
596 mrs x1, id_aa64mmfr1_el1
597 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
598 cbz x0, 1f
599 msr_s SYS_LORC_EL1, xzr
6001:
601
Marc Zyngier7dbfbe52012-11-06 19:27:59 +0000602 /* Stage-2 translation */
603 msr vttbr_el2, xzr
604
Marc Zyngier1f364c82014-02-19 09:33:14 +0000605 cbz x2, install_el2_stub
606
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100607 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
Marc Zyngier1f364c82014-02-19 09:33:14 +0000608 isb
609 ret
610
611install_el2_stub:
Mark Rutlandd61c97a2017-02-15 14:54:17 +0000612 /*
613 * When VHE is not in use, early init of EL2 and EL1 needs to be
614 * done here.
615 * When VHE _is_ in use, EL1 will not be used in the host and
616 * requires no configuration, and all non-hyp-specific EL2 setup
617 * will be done via the _EL1 system register aliases in __cpu_setup.
618 */
James Morse7a00d682018-01-15 19:38:55 +0000619 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
Mark Rutlandd61c97a2017-02-15 14:54:17 +0000620 msr sctlr_el1, x0
621
622 /* Coprocessor traps. */
623 mov x0, #0x33ff
624 msr cptr_el2, x0 // Disable copro. traps to EL2
625
Dave Martin22043a32017-10-31 15:51:04 +0000626 /* SVE register access */
627 mrs x1, id_aa64pfr0_el1
628 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
629 cbz x1, 7f
630
631 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
632 msr cptr_el2, x0 // Disable copro. traps to EL2
633 isb
634 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
635 msr_s SYS_ZCR_EL2, x1 // length for EL1.
636
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100637 /* Hypervisor stub */
Dave Martin22043a32017-10-31 15:51:04 +00006387: adr_l x0, __hyp_stub_vectors
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100639 msr vbar_el2, x0
640
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000641 /* spsr */
642 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
643 PSR_MODE_EL1h)
644 msr spsr_el2, x0
645 msr elr_el2, lr
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100646 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000647 eret
648ENDPROC(el2_setup)
649
Marc Zyngierf35a9202012-10-26 15:40:05 +0100650/*
Matthew Leach828e9832013-10-11 14:52:16 +0100651 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
Mark Rutland510224c2017-01-09 14:31:55 +0000652 * in w0. See arch/arm64/include/asm/virt.h for more info.
Matthew Leach828e9832013-10-11 14:52:16 +0100653 */
Ard Biesheuvel190c0562016-04-18 17:09:41 +0200654set_cpu_boot_mode_flag:
Ard Biesheuvel6f4d57f2015-03-17 09:14:29 +0100655 adr_l x1, __boot_cpu_mode
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100656 cmp w0, #BOOT_CPU_MODE_EL2
Matthew Leach828e9832013-10-11 14:52:16 +0100657 b.ne 1f
658 add x1, x1, #4
Ard Biesheuvel23c8a502016-08-31 12:05:12 +01006591: str w0, [x1] // This CPU has booted in EL1
Will Deacond0488592014-05-02 16:24:13 +0100660 dmb sy
661 dc ivac, x1 // Invalidate potentially stale cache line
Matthew Leach828e9832013-10-11 14:52:16 +0100662 ret
663ENDPROC(set_cpu_boot_mode_flag)
664
665/*
James Morseb6113032016-08-24 18:27:29 +0100666 * These values are written with the MMU off, but read with the MMU on.
667 * Writers will invalidate the corresponding address, discarding up to a
668 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
669 * sufficient alignment that the CWG doesn't overlap another section.
670 */
671 .pushsection ".mmuoff.data.write", "aw"
672/*
Marc Zyngierf35a9202012-10-26 15:40:05 +0100673 * We need to find out the CPU boot mode long after boot, so we need to
674 * store it in a writable variable.
675 *
676 * This is not in .bss, because we set it sufficiently early that the boot-time
677 * zeroing of .bss would clobber it.
678 */
Ard Biesheuvel947bb752015-03-13 16:21:18 +0100679ENTRY(__boot_cpu_mode)
Marc Zyngierf35a9202012-10-26 15:40:05 +0100680 .long BOOT_CPU_MODE_EL2
Mark Rutland424a3832015-03-13 16:14:36 +0000681 .long BOOT_CPU_MODE_EL1
James Morseb6113032016-08-24 18:27:29 +0100682/*
683 * The booting CPU updates the failed status @__early_cpu_boot_status,
684 * with MMU turned off.
685 */
686ENTRY(__early_cpu_boot_status)
687 .long 0
688
Marc Zyngierf35a9202012-10-26 15:40:05 +0100689 .popsection
690
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000691 /*
692 * This provides a "holding pen" for platforms to hold all secondary
693 * cores are held until we're ready for them to initialise.
694 */
695ENTRY(secondary_holding_pen)
Ard Biesheuvel23c8a502016-08-31 12:05:12 +0100696 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
Matthew Leach828e9832013-10-11 14:52:16 +0100697 bl set_cpu_boot_mode_flag
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000698 mrs x0, mpidr_el1
Ard Biesheuvelb03cc882016-04-18 17:09:45 +0200699 mov_q x1, MPIDR_HWID_BITMASK
Javi Merino0359b0e2012-08-29 18:32:18 +0100700 and x0, x0, x1
Ard Biesheuvelb1c98292015-03-10 15:00:03 +0100701 adr_l x3, secondary_holding_pen_release
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000702pen: ldr x4, [x3]
703 cmp x4, x0
704 b.eq secondary_startup
705 wfe
706 b pen
707ENDPROC(secondary_holding_pen)
Mark Rutland652af892013-10-24 20:30:16 +0100708
709 /*
710 * Secondary entry point that jumps straight into the kernel. Only to
711 * be used where CPUs are brought online dynamically by the kernel.
712 */
713ENTRY(secondary_entry)
Mark Rutland652af892013-10-24 20:30:16 +0100714 bl el2_setup // Drop to EL1
Lorenzo Pieralisi85cc00e2013-11-18 18:56:42 +0000715 bl set_cpu_boot_mode_flag
Mark Rutland652af892013-10-24 20:30:16 +0100716 b secondary_startup
717ENDPROC(secondary_entry)
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000718
Ard Biesheuvel190c0562016-04-18 17:09:41 +0200719secondary_startup:
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000720 /*
721 * Common entry point for secondary CPUs.
722 */
Steve Cappera96a33b2018-12-06 22:50:40 +0000723 bl __cpu_secondary_check52bitva
Marc Zyngiera591ede2015-03-18 14:55:20 +0000724 bl __cpu_setup // initialise processor
Jun Yao693d5632018-09-24 14:51:13 +0100725 adrp x1, swapper_pg_dir
Ard Biesheuvel9dcf7912016-08-31 12:05:14 +0100726 bl __enable_mmu
727 ldr x8, =__secondary_switched
728 br x8
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000729ENDPROC(secondary_startup)
730
Ard Biesheuvel190c0562016-04-18 17:09:41 +0200731__secondary_switched:
Ard Biesheuvel2bf31a42015-12-26 12:46:40 +0100732 adr_l x5, vectors
733 msr vbar_el1, x5
734 isb
735
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000736 adr_l x0, secondary_data
Mark Rutlandc02433d2016-11-03 20:23:13 +0000737 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
738 mov sp, x1
739 ldr x2, [x0, #CPU_BOOT_TASK]
740 msr sp_el0, x2
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000741 mov x29, #0
Ard Biesheuvel73267492017-07-22 18:45:33 +0100742 mov x30, #0
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000743 b secondary_start_kernel
744ENDPROC(__secondary_switched)
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000745
746/*
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000747 * The booting CPU updates the failed status @__early_cpu_boot_status,
748 * with MMU turned off.
749 *
750 * update_early_cpu_boot_status tmp, status
751 * - Corrupts tmp1, tmp2
752 * - Writes 'status' to __early_cpu_boot_status and makes sure
753 * it is committed to memory.
754 */
755
756 .macro update_early_cpu_boot_status status, tmp1, tmp2
757 mov \tmp2, #\status
Ard Biesheuveladb49072016-04-15 12:11:21 +0200758 adr_l \tmp1, __early_cpu_boot_status
759 str \tmp2, [\tmp1]
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000760 dmb sy
761 dc ivac, \tmp1 // Invalidate potentially stale cache line
762 .endm
763
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000764/*
Ard Biesheuvel8b0a9572015-03-17 08:59:53 +0100765 * Enable the MMU.
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000766 *
Ard Biesheuvel8b0a9572015-03-17 08:59:53 +0100767 * x0 = SCTLR_EL1 value for turning on the MMU.
Jun Yao693d5632018-09-24 14:51:13 +0100768 * x1 = TTBR1_EL1 value
Ard Biesheuvel8b0a9572015-03-17 08:59:53 +0100769 *
Ard Biesheuvel9dcf7912016-08-31 12:05:14 +0100770 * Returns to the caller via x30/lr. This requires the caller to be covered
771 * by the .idmap.text section.
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100772 *
773 * Checks if the selected granule size is supported by the CPU.
774 * If it isn't, park the CPU
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000775 */
James Morsecabe1c82016-04-27 17:47:07 +0100776ENTRY(__enable_mmu)
Jun Yao693d5632018-09-24 14:51:13 +0100777 mrs x2, ID_AA64MMFR0_EL1
778 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100779 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
780 b.ne __no_granule_support
Jun Yao693d5632018-09-24 14:51:13 +0100781 update_early_cpu_boot_status 0, x2, x3
782 adrp x2, idmap_pg_dir
783 phys_to_ttbr x1, x1
784 phys_to_ttbr x2, x2
785 msr ttbr0_el1, x2 // load TTBR0
Steve Cappere842dfb2018-12-06 22:50:39 +0000786 offset_ttbr1 x1
Jun Yao693d5632018-09-24 14:51:13 +0100787 msr ttbr1_el1, x1 // load TTBR1
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000788 isb
Catalin Marinas9703d9d2012-03-05 11:49:27 +0000789 msr sctlr_el1, x0
790 isb
Will Deacon8ec41982015-08-04 17:49:36 +0100791 /*
792 * Invalidate the local I-cache so that any instructions fetched
793 * speculatively from the PoC are discarded, since they may have
794 * been dynamically patched at the PoU.
795 */
796 ic iallu
797 dsb nsh
798 isb
Ard Biesheuvel9dcf7912016-08-31 12:05:14 +0100799 ret
Ard Biesheuvel8b0a9572015-03-17 08:59:53 +0100800ENDPROC(__enable_mmu)
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100801
Steve Cappera96a33b2018-12-06 22:50:40 +0000802ENTRY(__cpu_secondary_check52bitva)
Will Deacon68d23da2018-12-10 14:15:15 +0000803#ifdef CONFIG_ARM64_USER_VA_BITS_52
Steve Cappera96a33b2018-12-06 22:50:40 +0000804 ldr_l x0, vabits_user
805 cmp x0, #52
806 b.ne 2f
807
808 mrs_s x0, SYS_ID_AA64MMFR2_EL1
809 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
810 cbnz x0, 2f
811
Will Deacon66f16a22018-12-10 14:21:13 +0000812 update_early_cpu_boot_status \
813 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
Steve Cappera96a33b2018-12-06 22:50:40 +00008141: wfe
815 wfi
816 b 1b
817
818#endif
8192: ret
820ENDPROC(__cpu_secondary_check52bitva)
821
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100822__no_granule_support:
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000823 /* Indicate that this CPU can't boot and is stuck in the kernel */
Will Deacon66f16a22018-12-10 14:21:13 +0000824 update_early_cpu_boot_status \
825 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
Suzuki K Poulosebb905272016-02-23 10:31:42 +00008261:
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100827 wfe
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000828 wfi
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100829 b 1b
Suzuki K. Poulose4bf8b962015-10-19 14:19:35 +0100830ENDPROC(__no_granule_support)
Ard Biesheuvele5ebeec2016-04-18 17:09:42 +0200831
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200832#ifdef CONFIG_RELOCATABLE
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100833__relocate_kernel:
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200834 /*
835 * Iterate over each entry in the relocation table, and apply the
836 * relocations in place.
837 */
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200838 ldr w9, =__rela_offset // offset to reloc table
839 ldr w10, =__rela_size // size of reloc table
840
Ard Biesheuvelb03cc882016-04-18 17:09:45 +0200841 mov_q x11, KIMAGE_VADDR // default virtual offset
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200842 add x11, x11, x23 // actual virtual offset
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200843 add x9, x9, x11 // __va(.rela)
844 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
845
8460: cmp x9, x10
Ard Biesheuvel08cc55b2016-07-24 14:00:13 +0200847 b.hs 1f
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200848 ldp x11, x12, [x9], #24
849 ldr x13, [x9, #-8]
850 cmp w12, #R_AARCH64_RELATIVE
Ard Biesheuvel08cc55b2016-07-24 14:00:13 +0200851 b.ne 0b
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200852 add x13, x13, x23 // relocate
853 str x13, [x11, x23]
854 b 0b
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +01008551: ret
856ENDPROC(__relocate_kernel)
857#endif
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200858
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100859__primary_switch:
860#ifdef CONFIG_RANDOMIZE_BASE
861 mov x19, x0 // preserve new SCTLR_EL1 value
862 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
863#endif
864
Jun Yao2b5548b2018-09-24 15:47:49 +0100865 adrp x1, init_pg_dir
Ard Biesheuvel9dcf7912016-08-31 12:05:14 +0100866 bl __enable_mmu
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100867#ifdef CONFIG_RELOCATABLE
868 bl __relocate_kernel
869#ifdef CONFIG_RANDOMIZE_BASE
870 ldr x8, =__primary_switched
Ard Biesheuvelb929fe32016-08-31 12:05:15 +0100871 adrp x0, __PHYS_OFFSET
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100872 blr x8
873
874 /*
875 * If we return here, we have a KASLR displacement in x23 which we need
876 * to take into account by discarding the current kernel mapping and
877 * creating a new one.
878 */
Shanker Donthineni3060e9f2018-01-29 11:59:52 +0000879 pre_disable_mmu_workaround
Ard Biesheuvel3c5e9f22016-08-31 12:05:13 +0100880 msr sctlr_el1, x20 // disable the MMU
881 isb
882 bl __create_page_tables // recreate kernel mapping
883
884 tlbi vmalle1 // Remove any stale TLB entries
885 dsb nsh
886
887 msr sctlr_el1, x19 // re-enable the MMU
888 isb
889 ic iallu // flush instructions fetched
890 dsb nsh // via old mapping
891 isb
892
893 bl __relocate_kernel
894#endif
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200895#endif
896 ldr x8, =__primary_switched
Ard Biesheuvelb929fe32016-08-31 12:05:15 +0100897 adrp x0, __PHYS_OFFSET
Ard Biesheuvel0cd3def2016-04-18 17:09:43 +0200898 br x8
899ENDPROC(__primary_switch)