blob: b6ae7b62fd0379564d67092ff7b6f2fa1c8f8eda [file] [log] [blame]
Joel Stanleyd44a1132016-03-16 22:03:37 +10301#include "skeleton.dtsi"
2
3/ {
4 model = "Aspeed BMC";
5 compatible = "aspeed,ast2400";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&vic>;
9
Joel Stanleyef856372017-10-04 17:19:11 +103010 aliases {
11 i2c0 = &i2c0;
12 i2c1 = &i2c1;
13 i2c2 = &i2c2;
14 i2c3 = &i2c3;
15 i2c4 = &i2c4;
16 i2c5 = &i2c5;
17 i2c6 = &i2c6;
18 i2c7 = &i2c7;
19 i2c8 = &i2c8;
20 i2c9 = &i2c9;
21 i2c10 = &i2c10;
22 i2c11 = &i2c11;
23 i2c12 = &i2c12;
24 i2c13 = &i2c13;
25 };
26
Joel Stanleyd44a1132016-03-16 22:03:37 +103027 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 compatible = "arm,arm926ej-s";
33 device_type = "cpu";
34 reg = <0>;
35 };
36 };
37
Joel Stanleyd44a1132016-03-16 22:03:37 +103038 ahb {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges;
43
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010044 fmc: flash-controller@1e620000 {
45 reg = < 0x1e620000 0x94
Cédric Le Goaterbcbd3282017-04-19 15:43:15 +020046 0x20000000 0x10000000 >;
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010047 #address-cells = <1>;
48 #size-cells = <0>;
49 compatible = "aspeed,ast2400-fmc";
50 status = "disabled";
51 interrupts = <19>;
52 flash@0 {
53 reg = < 0 >;
54 compatible = "jedec,spi-nor";
55 status = "disabled";
56 };
57 };
58
59 spi: flash-controller@1e630000 {
60 reg = < 0x1e630000 0x18
Cédric Le Goaterbcbd3282017-04-19 15:43:15 +020061 0x30000000 0x10000000 >;
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010062 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "aspeed,ast2400-spi";
65 status = "disabled";
66 flash@0 {
67 reg = < 0 >;
68 compatible = "jedec,spi-nor";
69 status = "disabled";
70 };
71 };
72
Joel Stanleyd44a1132016-03-16 22:03:37 +103073 vic: interrupt-controller@1e6c0080 {
74 compatible = "aspeed,ast2400-vic";
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 valid-sources = <0xffffffff 0x0007ffff>;
78 reg = <0x1e6c0080 0x80>;
79 };
80
Joel Stanley34ea5c92017-01-04 16:30:34 +110081 mac0: ethernet@1e660000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +100082 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +110083 reg = <0x1e660000 0x180>;
84 interrupts = <2>;
Joel Stanley34ea5c92017-01-04 16:30:34 +110085 status = "disabled";
86 };
87
88 mac1: ethernet@1e680000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +100089 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +110090 reg = <0x1e680000 0x180>;
91 interrupts = <3>;
Joel Stanley34ea5c92017-01-04 16:30:34 +110092 status = "disabled";
93 };
94
Joel Stanleyd44a1132016-03-16 22:03:37 +103095 apb {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100
Andrew Jefferyd9072272016-12-06 14:53:43 +1100101 syscon: syscon@1e6e2000 {
102 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
103 reg = <0x1e6e2000 0x1a8>;
Joel Stanley491bdcf2017-04-06 11:11:43 +0930104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 clk_clkin: clk_clkin {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 clock-frequency = <48000000>;
111 };
112
113 clk_hpll: clk_hpll@70 {
114 #clock-cells = <0>;
115 compatible = "aspeed,g4-hpll-clock", "fixed-clock";
116 reg = <0x70>;
117 clocks = <&clk_clkin>;
118 clock-frequency = <384000000>;
119 };
120
121 clk_ahb: clk_ahb@70 {
122 #clock-cells = <0>;
123 compatible = "aspeed,g4-ahb-clock", "fixed-clock";
124 reg = <0x70>;
125 clocks = <&clk_hpll>;
126 clock-frequency = <192000000>;
127 };
128
129 clk_apb: clk_apb@08 {
130 #clock-cells = <0>;
131 compatible = "aspeed,g4-apb-clock", "fixed-clock";
132 reg = <0x08>;
133 clocks = <&clk_hpll>;
134 clock-frequency = <48000000>;
135 };
136
137 clk_uart: clk_uart@2c{
138 #clock-cells = <0>;
139 compatible = "aspeed,g4-uart-clock", "fixed-clock";
140 reg = <0x2c>;
141 clock-frequency = <24000000>;
142 };
Andrew Jefferyd9072272016-12-06 14:53:43 +1100143
144 pinctrl: pinctrl {
145 compatible = "aspeed,g4-pinctrl";
Andrew Jefferyd9072272016-12-06 14:53:43 +1100146 };
147 };
148
Joel Stanley29b24642017-10-04 17:19:10 +1030149 adc: adc@1e6e9000 {
150 compatible = "aspeed,ast2400-adc";
151 reg = <0x1e6e9000 0xb0>;
152 clocks = <&clk_apb>;
153 #io-channel-cells = <1>;
154 status = "disabled";
155 };
156
Joel Stanleyd44a1132016-03-16 22:03:37 +1030157 sram@1e720000 {
158 compatible = "mmio-sram";
159 reg = <0x1e720000 0x8000>; // 32K
160 };
161
Andrew Jeffery09955002016-12-06 14:53:44 +1100162 gpio: gpio@1e780000 {
163 #gpio-cells = <2>;
164 gpio-controller;
165 compatible = "aspeed,ast2400-gpio";
166 reg = <0x1e780000 0x1000>;
167 interrupts = <20>;
168 gpio-ranges = <&pinctrl 0 0 220>;
169 interrupt-controller;
170 };
171
Joel Stanleyd44a1132016-03-16 22:03:37 +1030172 timer: timer@1e782000 {
Linus Walleijf46b5632017-05-24 11:07:48 +0200173 /* This timer is a Faraday FTTMR010 derivative */
Joel Stanleyd44a1132016-03-16 22:03:37 +1030174 compatible = "aspeed,ast2400-timer";
175 reg = <0x1e782000 0x90>;
Linus Walleijf46b5632017-05-24 11:07:48 +0200176 interrupts = <16 17 18 35 36 37 38 39>;
Joel Stanleyd44a1132016-03-16 22:03:37 +1030177 clocks = <&clk_apb>;
Linus Walleijf46b5632017-05-24 11:07:48 +0200178 clock-names = "PCLK";
Joel Stanleyd44a1132016-03-16 22:03:37 +1030179 };
180
181 wdt1: wdt@1e785000 {
Joel Stanley23491da2017-04-07 12:14:19 +0930182 compatible = "aspeed,ast2400-wdt";
Joel Stanleyd44a1132016-03-16 22:03:37 +1030183 reg = <0x1e785000 0x1c>;
184 interrupts = <27>;
185 };
186
187 wdt2: wdt@1e785020 {
Joel Stanley23491da2017-04-07 12:14:19 +0930188 compatible = "aspeed,ast2400-wdt";
Joel Stanleyd44a1132016-03-16 22:03:37 +1030189 reg = <0x1e785020 0x1c>;
190 interrupts = <27>;
191 clocks = <&clk_apb>;
192 status = "disabled";
193 };
194
195 uart1: serial@1e783000 {
196 compatible = "ns16550a";
197 reg = <0x1e783000 0x1000>;
198 reg-shift = <2>;
199 interrupts = <9>;
200 clocks = <&clk_uart>;
201 no-loopback-test;
202 status = "disabled";
203 };
204
205 uart2: serial@1e78d000 {
206 compatible = "ns16550a";
207 reg = <0x1e78d000 0x1000>;
208 reg-shift = <2>;
209 interrupts = <32>;
210 clocks = <&clk_uart>;
211 no-loopback-test;
212 status = "disabled";
213 };
214
215 uart3: serial@1e78e000 {
216 compatible = "ns16550a";
217 reg = <0x1e78e000 0x1000>;
218 reg-shift = <2>;
219 interrupts = <33>;
220 clocks = <&clk_uart>;
221 no-loopback-test;
222 status = "disabled";
223 };
224
225 uart4: serial@1e78f000 {
226 compatible = "ns16550a";
227 reg = <0x1e78f000 0x1000>;
228 reg-shift = <2>;
229 interrupts = <34>;
230 clocks = <&clk_uart>;
231 no-loopback-test;
232 status = "disabled";
233 };
234
235 uart5: serial@1e784000 {
236 compatible = "ns16550a";
237 reg = <0x1e784000 0x1000>;
238 reg-shift = <2>;
239 interrupts = <10>;
240 clocks = <&clk_uart>;
241 current-speed = <38400>;
242 no-loopback-test;
243 status = "disabled";
244 };
245
246 uart6: serial@1e787000 {
247 compatible = "ns16550a";
248 reg = <0x1e787000 0x1000>;
249 reg-shift = <2>;
250 interrupts = <10>;
251 clocks = <&clk_uart>;
252 no-loopback-test;
253 status = "disabled";
254 };
Joel Stanleyef856372017-10-04 17:19:11 +1030255
256 i2c: i2c@1e78a000 {
257 compatible = "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0 0x1e78a000 0x1000>;
261 };
Joel Stanleyd44a1132016-03-16 22:03:37 +1030262 };
263 };
264};
Andrew Jefferycd7df3f2017-10-04 17:19:09 +1030265
Joel Stanleyef856372017-10-04 17:19:11 +1030266&i2c {
267 i2c_ic: interrupt-controller@0 {
268 #interrupt-cells = <1>;
269 compatible = "aspeed,ast2400-i2c-ic";
270 reg = <0x0 0x40>;
271 interrupts = <12>;
272 interrupt-controller;
273 };
274
275 i2c0: i2c-bus@40 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 #interrupt-cells = <1>;
279
280 reg = <0x40 0x40>;
281 compatible = "aspeed,ast2400-i2c-bus";
282 clocks = <&clk_apb>;
283 bus-frequency = <100000>;
284 interrupts = <0>;
285 interrupt-parent = <&i2c_ic>;
286 status = "disabled";
287 /* Does not need pinctrl properties */
288 };
289
290 i2c1: i2c-bus@80 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 #interrupt-cells = <1>;
294
295 reg = <0x80 0x40>;
296 compatible = "aspeed,ast2400-i2c-bus";
297 clocks = <&clk_apb>;
298 bus-frequency = <100000>;
299 interrupts = <1>;
300 interrupt-parent = <&i2c_ic>;
301 status = "disabled";
302 /* Does not need pinctrl properties */
303 };
304
305 i2c2: i2c-bus@c0 {
306 #address-cells = <1>;
307 #size-cells = <0>;
308 #interrupt-cells = <1>;
309
310 reg = <0xc0 0x40>;
311 compatible = "aspeed,ast2400-i2c-bus";
312 clocks = <&clk_apb>;
313 bus-frequency = <100000>;
314 interrupts = <2>;
315 interrupt-parent = <&i2c_ic>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_i2c3_default>;
318 status = "disabled";
319 };
320
321 i2c3: i2c-bus@100 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 #interrupt-cells = <1>;
325
326 reg = <0x100 0x40>;
327 compatible = "aspeed,ast2400-i2c-bus";
328 clocks = <&clk_apb>;
329 bus-frequency = <100000>;
330 interrupts = <3>;
331 interrupt-parent = <&i2c_ic>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_i2c4_default>;
334 status = "disabled";
335 };
336
337 i2c4: i2c-bus@140 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 #interrupt-cells = <1>;
341
342 reg = <0x140 0x40>;
343 compatible = "aspeed,ast2400-i2c-bus";
344 clocks = <&clk_apb>;
345 bus-frequency = <100000>;
346 interrupts = <4>;
347 interrupt-parent = <&i2c_ic>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_i2c5_default>;
350 status = "disabled";
351 };
352
353 i2c5: i2c-bus@180 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 #interrupt-cells = <1>;
357
358 reg = <0x180 0x40>;
359 compatible = "aspeed,ast2400-i2c-bus";
360 clocks = <&clk_apb>;
361 bus-frequency = <100000>;
362 interrupts = <5>;
363 interrupt-parent = <&i2c_ic>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_i2c6_default>;
366 status = "disabled";
367 };
368
369 i2c6: i2c-bus@1c0 {
370 #address-cells = <1>;
371 #size-cells = <0>;
372 #interrupt-cells = <1>;
373
374 reg = <0x1c0 0x40>;
375 compatible = "aspeed,ast2400-i2c-bus";
376 clocks = <&clk_apb>;
377 bus-frequency = <100000>;
378 interrupts = <6>;
379 interrupt-parent = <&i2c_ic>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_i2c7_default>;
382 status = "disabled";
383 };
384
385 i2c7: i2c-bus@300 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 #interrupt-cells = <1>;
389
390 reg = <0x300 0x40>;
391 compatible = "aspeed,ast2400-i2c-bus";
392 clocks = <&clk_apb>;
393 bus-frequency = <100000>;
394 interrupts = <7>;
395 interrupt-parent = <&i2c_ic>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_i2c8_default>;
398 status = "disabled";
399 };
400
401 i2c8: i2c-bus@340 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 #interrupt-cells = <1>;
405
406 reg = <0x340 0x40>;
407 compatible = "aspeed,ast2400-i2c-bus";
408 clocks = <&clk_apb>;
409 bus-frequency = <100000>;
410 interrupts = <8>;
411 interrupt-parent = <&i2c_ic>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_i2c9_default>;
414 status = "disabled";
415 };
416
417 i2c9: i2c-bus@380 {
418 #address-cells = <1>;
419 #size-cells = <0>;
420 #interrupt-cells = <1>;
421
422 reg = <0x380 0x40>;
423 compatible = "aspeed,ast2400-i2c-bus";
424 clocks = <&clk_apb>;
425 bus-frequency = <100000>;
426 interrupts = <9>;
427 interrupt-parent = <&i2c_ic>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_i2c10_default>;
430 status = "disabled";
431 };
432
433 i2c10: i2c-bus@3c0 {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 #interrupt-cells = <1>;
437
438 reg = <0x3c0 0x40>;
439 compatible = "aspeed,ast2400-i2c-bus";
440 clocks = <&clk_apb>;
441 bus-frequency = <100000>;
442 interrupts = <10>;
443 interrupt-parent = <&i2c_ic>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_i2c11_default>;
446 status = "disabled";
447 };
448
449 i2c11: i2c-bus@400 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 #interrupt-cells = <1>;
453
454 reg = <0x400 0x40>;
455 compatible = "aspeed,ast2400-i2c-bus";
456 clocks = <&clk_apb>;
457 bus-frequency = <100000>;
458 interrupts = <11>;
459 interrupt-parent = <&i2c_ic>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_i2c12_default>;
462 status = "disabled";
463 };
464
465 i2c12: i2c-bus@440 {
466 #address-cells = <1>;
467 #size-cells = <0>;
468 #interrupt-cells = <1>;
469
470 reg = <0x440 0x40>;
471 compatible = "aspeed,ast2400-i2c-bus";
472 clocks = <&clk_apb>;
473 bus-frequency = <100000>;
474 interrupts = <12>;
475 interrupt-parent = <&i2c_ic>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_i2c13_default>;
478 status = "disabled";
479 };
480
481 i2c13: i2c-bus@480 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 #interrupt-cells = <1>;
485
486 reg = <0x480 0x40>;
487 compatible = "aspeed,ast2400-i2c-bus";
488 clocks = <&clk_apb>;
489 bus-frequency = <100000>;
490 interrupts = <13>;
491 interrupt-parent = <&i2c_ic>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_i2c14_default>;
494 status = "disabled";
495 };
496};
497
Andrew Jefferycd7df3f2017-10-04 17:19:09 +1030498&pinctrl {
499 pinctrl_acpi_default: acpi_default {
500 function = "ACPI";
501 groups = "ACPI";
502 };
503
504 pinctrl_adc0_default: adc0_default {
505 function = "ADC0";
506 groups = "ADC0";
507 };
508
509 pinctrl_adc1_default: adc1_default {
510 function = "ADC1";
511 groups = "ADC1";
512 };
513
514 pinctrl_adc10_default: adc10_default {
515 function = "ADC10";
516 groups = "ADC10";
517 };
518
519 pinctrl_adc11_default: adc11_default {
520 function = "ADC11";
521 groups = "ADC11";
522 };
523
524 pinctrl_adc12_default: adc12_default {
525 function = "ADC12";
526 groups = "ADC12";
527 };
528
529 pinctrl_adc13_default: adc13_default {
530 function = "ADC13";
531 groups = "ADC13";
532 };
533
534 pinctrl_adc14_default: adc14_default {
535 function = "ADC14";
536 groups = "ADC14";
537 };
538
539 pinctrl_adc15_default: adc15_default {
540 function = "ADC15";
541 groups = "ADC15";
542 };
543
544 pinctrl_adc2_default: adc2_default {
545 function = "ADC2";
546 groups = "ADC2";
547 };
548
549 pinctrl_adc3_default: adc3_default {
550 function = "ADC3";
551 groups = "ADC3";
552 };
553
554 pinctrl_adc4_default: adc4_default {
555 function = "ADC4";
556 groups = "ADC4";
557 };
558
559 pinctrl_adc5_default: adc5_default {
560 function = "ADC5";
561 groups = "ADC5";
562 };
563
564 pinctrl_adc6_default: adc6_default {
565 function = "ADC6";
566 groups = "ADC6";
567 };
568
569 pinctrl_adc7_default: adc7_default {
570 function = "ADC7";
571 groups = "ADC7";
572 };
573
574 pinctrl_adc8_default: adc8_default {
575 function = "ADC8";
576 groups = "ADC8";
577 };
578
579 pinctrl_adc9_default: adc9_default {
580 function = "ADC9";
581 groups = "ADC9";
582 };
583
584 pinctrl_bmcint_default: bmcint_default {
585 function = "BMCINT";
586 groups = "BMCINT";
587 };
588
589 pinctrl_ddcclk_default: ddcclk_default {
590 function = "DDCCLK";
591 groups = "DDCCLK";
592 };
593
594 pinctrl_ddcdat_default: ddcdat_default {
595 function = "DDCDAT";
596 groups = "DDCDAT";
597 };
598
599 pinctrl_extrst_default: extrst_default {
600 function = "EXTRST";
601 groups = "EXTRST";
602 };
603
604 pinctrl_flack_default: flack_default {
605 function = "FLACK";
606 groups = "FLACK";
607 };
608
609 pinctrl_flbusy_default: flbusy_default {
610 function = "FLBUSY";
611 groups = "FLBUSY";
612 };
613
614 pinctrl_flwp_default: flwp_default {
615 function = "FLWP";
616 groups = "FLWP";
617 };
618
619 pinctrl_gpid_default: gpid_default {
620 function = "GPID";
621 groups = "GPID";
622 };
623
624 pinctrl_gpid0_default: gpid0_default {
625 function = "GPID0";
626 groups = "GPID0";
627 };
628
629 pinctrl_gpid2_default: gpid2_default {
630 function = "GPID2";
631 groups = "GPID2";
632 };
633
634 pinctrl_gpid4_default: gpid4_default {
635 function = "GPID4";
636 groups = "GPID4";
637 };
638
639 pinctrl_gpid6_default: gpid6_default {
640 function = "GPID6";
641 groups = "GPID6";
642 };
643
644 pinctrl_gpie0_default: gpie0_default {
645 function = "GPIE0";
646 groups = "GPIE0";
647 };
648
649 pinctrl_gpie2_default: gpie2_default {
650 function = "GPIE2";
651 groups = "GPIE2";
652 };
653
654 pinctrl_gpie4_default: gpie4_default {
655 function = "GPIE4";
656 groups = "GPIE4";
657 };
658
659 pinctrl_gpie6_default: gpie6_default {
660 function = "GPIE6";
661 groups = "GPIE6";
662 };
663
664 pinctrl_i2c10_default: i2c10_default {
665 function = "I2C10";
666 groups = "I2C10";
667 };
668
669 pinctrl_i2c11_default: i2c11_default {
670 function = "I2C11";
671 groups = "I2C11";
672 };
673
674 pinctrl_i2c12_default: i2c12_default {
675 function = "I2C12";
676 groups = "I2C12";
677 };
678
679 pinctrl_i2c13_default: i2c13_default {
680 function = "I2C13";
681 groups = "I2C13";
682 };
683
684 pinctrl_i2c14_default: i2c14_default {
685 function = "I2C14";
686 groups = "I2C14";
687 };
688
689 pinctrl_i2c3_default: i2c3_default {
690 function = "I2C3";
691 groups = "I2C3";
692 };
693
694 pinctrl_i2c4_default: i2c4_default {
695 function = "I2C4";
696 groups = "I2C4";
697 };
698
699 pinctrl_i2c5_default: i2c5_default {
700 function = "I2C5";
701 groups = "I2C5";
702 };
703
704 pinctrl_i2c6_default: i2c6_default {
705 function = "I2C6";
706 groups = "I2C6";
707 };
708
709 pinctrl_i2c7_default: i2c7_default {
710 function = "I2C7";
711 groups = "I2C7";
712 };
713
714 pinctrl_i2c8_default: i2c8_default {
715 function = "I2C8";
716 groups = "I2C8";
717 };
718
719 pinctrl_i2c9_default: i2c9_default {
720 function = "I2C9";
721 groups = "I2C9";
722 };
723
724 pinctrl_lpcpd_default: lpcpd_default {
725 function = "LPCPD";
726 groups = "LPCPD";
727 };
728
729 pinctrl_lpcpme_default: lpcpme_default {
730 function = "LPCPME";
731 groups = "LPCPME";
732 };
733
734 pinctrl_lpcrst_default: lpcrst_default {
735 function = "LPCRST";
736 groups = "LPCRST";
737 };
738
739 pinctrl_lpcsmi_default: lpcsmi_default {
740 function = "LPCSMI";
741 groups = "LPCSMI";
742 };
743
744 pinctrl_mac1link_default: mac1link_default {
745 function = "MAC1LINK";
746 groups = "MAC1LINK";
747 };
748
749 pinctrl_mac2link_default: mac2link_default {
750 function = "MAC2LINK";
751 groups = "MAC2LINK";
752 };
753
754 pinctrl_mdio1_default: mdio1_default {
755 function = "MDIO1";
756 groups = "MDIO1";
757 };
758
759 pinctrl_mdio2_default: mdio2_default {
760 function = "MDIO2";
761 groups = "MDIO2";
762 };
763
764 pinctrl_ncts1_default: ncts1_default {
765 function = "NCTS1";
766 groups = "NCTS1";
767 };
768
769 pinctrl_ncts2_default: ncts2_default {
770 function = "NCTS2";
771 groups = "NCTS2";
772 };
773
774 pinctrl_ncts3_default: ncts3_default {
775 function = "NCTS3";
776 groups = "NCTS3";
777 };
778
779 pinctrl_ncts4_default: ncts4_default {
780 function = "NCTS4";
781 groups = "NCTS4";
782 };
783
784 pinctrl_ndcd1_default: ndcd1_default {
785 function = "NDCD1";
786 groups = "NDCD1";
787 };
788
789 pinctrl_ndcd2_default: ndcd2_default {
790 function = "NDCD2";
791 groups = "NDCD2";
792 };
793
794 pinctrl_ndcd3_default: ndcd3_default {
795 function = "NDCD3";
796 groups = "NDCD3";
797 };
798
799 pinctrl_ndcd4_default: ndcd4_default {
800 function = "NDCD4";
801 groups = "NDCD4";
802 };
803
804 pinctrl_ndsr1_default: ndsr1_default {
805 function = "NDSR1";
806 groups = "NDSR1";
807 };
808
809 pinctrl_ndsr2_default: ndsr2_default {
810 function = "NDSR2";
811 groups = "NDSR2";
812 };
813
814 pinctrl_ndsr3_default: ndsr3_default {
815 function = "NDSR3";
816 groups = "NDSR3";
817 };
818
819 pinctrl_ndsr4_default: ndsr4_default {
820 function = "NDSR4";
821 groups = "NDSR4";
822 };
823
824 pinctrl_ndtr1_default: ndtr1_default {
825 function = "NDTR1";
826 groups = "NDTR1";
827 };
828
829 pinctrl_ndtr2_default: ndtr2_default {
830 function = "NDTR2";
831 groups = "NDTR2";
832 };
833
834 pinctrl_ndtr3_default: ndtr3_default {
835 function = "NDTR3";
836 groups = "NDTR3";
837 };
838
839 pinctrl_ndtr4_default: ndtr4_default {
840 function = "NDTR4";
841 groups = "NDTR4";
842 };
843
844 pinctrl_ndts4_default: ndts4_default {
845 function = "NDTS4";
846 groups = "NDTS4";
847 };
848
849 pinctrl_nri1_default: nri1_default {
850 function = "NRI1";
851 groups = "NRI1";
852 };
853
854 pinctrl_nri2_default: nri2_default {
855 function = "NRI2";
856 groups = "NRI2";
857 };
858
859 pinctrl_nri3_default: nri3_default {
860 function = "NRI3";
861 groups = "NRI3";
862 };
863
864 pinctrl_nri4_default: nri4_default {
865 function = "NRI4";
866 groups = "NRI4";
867 };
868
869 pinctrl_nrts1_default: nrts1_default {
870 function = "NRTS1";
871 groups = "NRTS1";
872 };
873
874 pinctrl_nrts2_default: nrts2_default {
875 function = "NRTS2";
876 groups = "NRTS2";
877 };
878
879 pinctrl_nrts3_default: nrts3_default {
880 function = "NRTS3";
881 groups = "NRTS3";
882 };
883
884 pinctrl_oscclk_default: oscclk_default {
885 function = "OSCCLK";
886 groups = "OSCCLK";
887 };
888
889 pinctrl_pwm0_default: pwm0_default {
890 function = "PWM0";
891 groups = "PWM0";
892 };
893
894 pinctrl_pwm1_default: pwm1_default {
895 function = "PWM1";
896 groups = "PWM1";
897 };
898
899 pinctrl_pwm2_default: pwm2_default {
900 function = "PWM2";
901 groups = "PWM2";
902 };
903
904 pinctrl_pwm3_default: pwm3_default {
905 function = "PWM3";
906 groups = "PWM3";
907 };
908
909 pinctrl_pwm4_default: pwm4_default {
910 function = "PWM4";
911 groups = "PWM4";
912 };
913
914 pinctrl_pwm5_default: pwm5_default {
915 function = "PWM5";
916 groups = "PWM5";
917 };
918
919 pinctrl_pwm6_default: pwm6_default {
920 function = "PWM6";
921 groups = "PWM6";
922 };
923
924 pinctrl_pwm7_default: pwm7_default {
925 function = "PWM7";
926 groups = "PWM7";
927 };
928
929 pinctrl_rgmii1_default: rgmii1_default {
930 function = "RGMII1";
931 groups = "RGMII1";
932 };
933
934 pinctrl_rgmii2_default: rgmii2_default {
935 function = "RGMII2";
936 groups = "RGMII2";
937 };
938
939 pinctrl_rmii1_default: rmii1_default {
940 function = "RMII1";
941 groups = "RMII1";
942 };
943
944 pinctrl_rmii2_default: rmii2_default {
945 function = "RMII2";
946 groups = "RMII2";
947 };
948
949 pinctrl_rom16_default: rom16_default {
950 function = "ROM16";
951 groups = "ROM16";
952 };
953
954 pinctrl_rom8_default: rom8_default {
955 function = "ROM8";
956 groups = "ROM8";
957 };
958
959 pinctrl_romcs1_default: romcs1_default {
960 function = "ROMCS1";
961 groups = "ROMCS1";
962 };
963
964 pinctrl_romcs2_default: romcs2_default {
965 function = "ROMCS2";
966 groups = "ROMCS2";
967 };
968
969 pinctrl_romcs3_default: romcs3_default {
970 function = "ROMCS3";
971 groups = "ROMCS3";
972 };
973
974 pinctrl_romcs4_default: romcs4_default {
975 function = "ROMCS4";
976 groups = "ROMCS4";
977 };
978
979 pinctrl_rxd1_default: rxd1_default {
980 function = "RXD1";
981 groups = "RXD1";
982 };
983
984 pinctrl_rxd2_default: rxd2_default {
985 function = "RXD2";
986 groups = "RXD2";
987 };
988
989 pinctrl_rxd3_default: rxd3_default {
990 function = "RXD3";
991 groups = "RXD3";
992 };
993
994 pinctrl_rxd4_default: rxd4_default {
995 function = "RXD4";
996 groups = "RXD4";
997 };
998
999 pinctrl_salt1_default: salt1_default {
1000 function = "SALT1";
1001 groups = "SALT1";
1002 };
1003
1004 pinctrl_salt2_default: salt2_default {
1005 function = "SALT2";
1006 groups = "SALT2";
1007 };
1008
1009 pinctrl_salt3_default: salt3_default {
1010 function = "SALT3";
1011 groups = "SALT3";
1012 };
1013
1014 pinctrl_salt4_default: salt4_default {
1015 function = "SALT4";
1016 groups = "SALT4";
1017 };
1018
1019 pinctrl_sd1_default: sd1_default {
1020 function = "SD1";
1021 groups = "SD1";
1022 };
1023
1024 pinctrl_sd2_default: sd2_default {
1025 function = "SD2";
1026 groups = "SD2";
1027 };
1028
1029 pinctrl_sgpmck_default: sgpmck_default {
1030 function = "SGPMCK";
1031 groups = "SGPMCK";
1032 };
1033
1034 pinctrl_sgpmi_default: sgpmi_default {
1035 function = "SGPMI";
1036 groups = "SGPMI";
1037 };
1038
1039 pinctrl_sgpmld_default: sgpmld_default {
1040 function = "SGPMLD";
1041 groups = "SGPMLD";
1042 };
1043
1044 pinctrl_sgpmo_default: sgpmo_default {
1045 function = "SGPMO";
1046 groups = "SGPMO";
1047 };
1048
1049 pinctrl_sgpsck_default: sgpsck_default {
1050 function = "SGPSCK";
1051 groups = "SGPSCK";
1052 };
1053
1054 pinctrl_sgpsi0_default: sgpsi0_default {
1055 function = "SGPSI0";
1056 groups = "SGPSI0";
1057 };
1058
1059 pinctrl_sgpsi1_default: sgpsi1_default {
1060 function = "SGPSI1";
1061 groups = "SGPSI1";
1062 };
1063
1064 pinctrl_sgpsld_default: sgpsld_default {
1065 function = "SGPSLD";
1066 groups = "SGPSLD";
1067 };
1068
1069 pinctrl_sioonctrl_default: sioonctrl_default {
1070 function = "SIOONCTRL";
1071 groups = "SIOONCTRL";
1072 };
1073
1074 pinctrl_siopbi_default: siopbi_default {
1075 function = "SIOPBI";
1076 groups = "SIOPBI";
1077 };
1078
1079 pinctrl_siopbo_default: siopbo_default {
1080 function = "SIOPBO";
1081 groups = "SIOPBO";
1082 };
1083
1084 pinctrl_siopwreq_default: siopwreq_default {
1085 function = "SIOPWREQ";
1086 groups = "SIOPWREQ";
1087 };
1088
1089 pinctrl_siopwrgd_default: siopwrgd_default {
1090 function = "SIOPWRGD";
1091 groups = "SIOPWRGD";
1092 };
1093
1094 pinctrl_sios3_default: sios3_default {
1095 function = "SIOS3";
1096 groups = "SIOS3";
1097 };
1098
1099 pinctrl_sios5_default: sios5_default {
1100 function = "SIOS5";
1101 groups = "SIOS5";
1102 };
1103
1104 pinctrl_siosci_default: siosci_default {
1105 function = "SIOSCI";
1106 groups = "SIOSCI";
1107 };
1108
1109 pinctrl_spi1_default: spi1_default {
1110 function = "SPI1";
1111 groups = "SPI1";
1112 };
1113
1114 pinctrl_spi1debug_default: spi1debug_default {
1115 function = "SPI1DEBUG";
1116 groups = "SPI1DEBUG";
1117 };
1118
1119 pinctrl_spi1passthru_default: spi1passthru_default {
1120 function = "SPI1PASSTHRU";
1121 groups = "SPI1PASSTHRU";
1122 };
1123
1124 pinctrl_spics1_default: spics1_default {
1125 function = "SPICS1";
1126 groups = "SPICS1";
1127 };
1128
1129 pinctrl_timer3_default: timer3_default {
1130 function = "TIMER3";
1131 groups = "TIMER3";
1132 };
1133
1134 pinctrl_timer4_default: timer4_default {
1135 function = "TIMER4";
1136 groups = "TIMER4";
1137 };
1138
1139 pinctrl_timer5_default: timer5_default {
1140 function = "TIMER5";
1141 groups = "TIMER5";
1142 };
1143
1144 pinctrl_timer6_default: timer6_default {
1145 function = "TIMER6";
1146 groups = "TIMER6";
1147 };
1148
1149 pinctrl_timer7_default: timer7_default {
1150 function = "TIMER7";
1151 groups = "TIMER7";
1152 };
1153
1154 pinctrl_timer8_default: timer8_default {
1155 function = "TIMER8";
1156 groups = "TIMER8";
1157 };
1158
1159 pinctrl_txd1_default: txd1_default {
1160 function = "TXD1";
1161 groups = "TXD1";
1162 };
1163
1164 pinctrl_txd2_default: txd2_default {
1165 function = "TXD2";
1166 groups = "TXD2";
1167 };
1168
1169 pinctrl_txd3_default: txd3_default {
1170 function = "TXD3";
1171 groups = "TXD3";
1172 };
1173
1174 pinctrl_txd4_default: txd4_default {
1175 function = "TXD4";
1176 groups = "TXD4";
1177 };
1178
1179 pinctrl_uart6_default: uart6_default {
1180 function = "UART6";
1181 groups = "UART6";
1182 };
1183
1184 pinctrl_usbcki_default: usbcki_default {
1185 function = "USBCKI";
1186 groups = "USBCKI";
1187 };
1188
1189 pinctrl_vgabios_rom_default: vgabios_rom_default {
1190 function = "VGABIOS_ROM";
1191 groups = "VGABIOS_ROM";
1192 };
1193
1194 pinctrl_vgahs_default: vgahs_default {
1195 function = "VGAHS";
1196 groups = "VGAHS";
1197 };
1198
1199 pinctrl_vgavs_default: vgavs_default {
1200 function = "VGAVS";
1201 groups = "VGAVS";
1202 };
1203
1204 pinctrl_vpi18_default: vpi18_default {
1205 function = "VPI18";
1206 groups = "VPI18";
1207 };
1208
1209 pinctrl_vpi24_default: vpi24_default {
1210 function = "VPI24";
1211 groups = "VPI24";
1212 };
1213
1214 pinctrl_vpi30_default: vpi30_default {
1215 function = "VPI30";
1216 groups = "VPI30";
1217 };
1218
1219 pinctrl_vpo12_default: vpo12_default {
1220 function = "VPO12";
1221 groups = "VPO12";
1222 };
1223
1224 pinctrl_vpo24_default: vpo24_default {
1225 function = "VPO24";
1226 groups = "VPO24";
1227 };
1228
1229 pinctrl_wdtrst1_default: wdtrst1_default {
1230 function = "WDTRST1";
1231 groups = "WDTRST1";
1232 };
1233
1234 pinctrl_wdtrst2_default: wdtrst2_default {
1235 function = "WDTRST2";
1236 groups = "WDTRST2";
1237 };
1238};