Joel Stanley | d44a113 | 2016-03-16 22:03:37 +1030 | [diff] [blame] | 1 | #include "skeleton.dtsi" |
| 2 | |
| 3 | / { |
| 4 | model = "Aspeed BMC"; |
| 5 | compatible = "aspeed,ast2400"; |
| 6 | #address-cells = <1>; |
| 7 | #size-cells = <1>; |
| 8 | interrupt-parent = <&vic>; |
| 9 | |
| 10 | cpus { |
| 11 | #address-cells = <1>; |
| 12 | #size-cells = <0>; |
| 13 | |
| 14 | cpu@0 { |
| 15 | compatible = "arm,arm926ej-s"; |
| 16 | device_type = "cpu"; |
| 17 | reg = <0>; |
| 18 | }; |
| 19 | }; |
| 20 | |
| 21 | clocks { |
| 22 | clk_clkin: clk_clkin { |
| 23 | #clock-cells = <0>; |
| 24 | compatible = "fixed-clock"; |
| 25 | clock-frequency = <48000000>; |
| 26 | }; |
| 27 | |
| 28 | }; |
| 29 | |
| 30 | ahb { |
| 31 | compatible = "simple-bus"; |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <1>; |
| 34 | ranges; |
| 35 | |
| 36 | vic: interrupt-controller@1e6c0080 { |
| 37 | compatible = "aspeed,ast2400-vic"; |
| 38 | interrupt-controller; |
| 39 | #interrupt-cells = <1>; |
| 40 | valid-sources = <0xffffffff 0x0007ffff>; |
| 41 | reg = <0x1e6c0080 0x80>; |
| 42 | }; |
| 43 | |
| 44 | apb { |
| 45 | compatible = "simple-bus"; |
| 46 | #address-cells = <1>; |
| 47 | #size-cells = <1>; |
| 48 | ranges; |
| 49 | |
| 50 | clk_hpll: clk_hpll@1e6e2070 { |
| 51 | #clock-cells = <0>; |
| 52 | compatible = "aspeed,g4-hpll-clock"; |
| 53 | reg = <0x1e6e2070 0x4>; |
| 54 | clocks = <&clk_clkin>; |
| 55 | }; |
| 56 | |
Andrew Jeffery | d907227 | 2016-12-06 14:53:43 +1100 | [diff] [blame] | 57 | syscon: syscon@1e6e2000 { |
| 58 | compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; |
| 59 | reg = <0x1e6e2000 0x1a8>; |
| 60 | |
| 61 | pinctrl: pinctrl { |
| 62 | compatible = "aspeed,g4-pinctrl"; |
| 63 | |
| 64 | pinctrl_acpi_default: acpi_default { |
| 65 | function = "ACPI"; |
| 66 | groups = "ACPI"; |
| 67 | }; |
| 68 | |
| 69 | pinctrl_adc0_default: adc0_default { |
| 70 | function = "ADC0"; |
| 71 | groups = "ADC0"; |
| 72 | }; |
| 73 | |
| 74 | pinctrl_adc1_default: adc1_default { |
| 75 | function = "ADC1"; |
| 76 | groups = "ADC1"; |
| 77 | }; |
| 78 | |
| 79 | pinctrl_adc10_default: adc10_default { |
| 80 | function = "ADC10"; |
| 81 | groups = "ADC10"; |
| 82 | }; |
| 83 | |
| 84 | pinctrl_adc11_default: adc11_default { |
| 85 | function = "ADC11"; |
| 86 | groups = "ADC11"; |
| 87 | }; |
| 88 | |
| 89 | pinctrl_adc12_default: adc12_default { |
| 90 | function = "ADC12"; |
| 91 | groups = "ADC12"; |
| 92 | }; |
| 93 | |
| 94 | pinctrl_adc13_default: adc13_default { |
| 95 | function = "ADC13"; |
| 96 | groups = "ADC13"; |
| 97 | }; |
| 98 | |
| 99 | pinctrl_adc14_default: adc14_default { |
| 100 | function = "ADC14"; |
| 101 | groups = "ADC14"; |
| 102 | }; |
| 103 | |
| 104 | pinctrl_adc15_default: adc15_default { |
| 105 | function = "ADC15"; |
| 106 | groups = "ADC15"; |
| 107 | }; |
| 108 | |
| 109 | pinctrl_adc2_default: adc2_default { |
| 110 | function = "ADC2"; |
| 111 | groups = "ADC2"; |
| 112 | }; |
| 113 | |
| 114 | pinctrl_adc3_default: adc3_default { |
| 115 | function = "ADC3"; |
| 116 | groups = "ADC3"; |
| 117 | }; |
| 118 | |
| 119 | pinctrl_adc4_default: adc4_default { |
| 120 | function = "ADC4"; |
| 121 | groups = "ADC4"; |
| 122 | }; |
| 123 | |
| 124 | pinctrl_adc5_default: adc5_default { |
| 125 | function = "ADC5"; |
| 126 | groups = "ADC5"; |
| 127 | }; |
| 128 | |
| 129 | pinctrl_adc6_default: adc6_default { |
| 130 | function = "ADC6"; |
| 131 | groups = "ADC6"; |
| 132 | }; |
| 133 | |
| 134 | pinctrl_adc7_default: adc7_default { |
| 135 | function = "ADC7"; |
| 136 | groups = "ADC7"; |
| 137 | }; |
| 138 | |
| 139 | pinctrl_adc8_default: adc8_default { |
| 140 | function = "ADC8"; |
| 141 | groups = "ADC8"; |
| 142 | }; |
| 143 | |
| 144 | pinctrl_adc9_default: adc9_default { |
| 145 | function = "ADC9"; |
| 146 | groups = "ADC9"; |
| 147 | }; |
| 148 | |
| 149 | pinctrl_bmcint_default: bmcint_default { |
| 150 | function = "BMCINT"; |
| 151 | groups = "BMCINT"; |
| 152 | }; |
| 153 | |
| 154 | pinctrl_ddcclk_default: ddcclk_default { |
| 155 | function = "DDCCLK"; |
| 156 | groups = "DDCCLK"; |
| 157 | }; |
| 158 | |
| 159 | pinctrl_ddcdat_default: ddcdat_default { |
| 160 | function = "DDCDAT"; |
| 161 | groups = "DDCDAT"; |
| 162 | }; |
| 163 | |
| 164 | pinctrl_extrst_default: extrst_default { |
| 165 | function = "EXTRST"; |
| 166 | groups = "EXTRST"; |
| 167 | }; |
| 168 | |
| 169 | pinctrl_flack_default: flack_default { |
| 170 | function = "FLACK"; |
| 171 | groups = "FLACK"; |
| 172 | }; |
| 173 | |
| 174 | pinctrl_flbusy_default: flbusy_default { |
| 175 | function = "FLBUSY"; |
| 176 | groups = "FLBUSY"; |
| 177 | }; |
| 178 | |
| 179 | pinctrl_flwp_default: flwp_default { |
| 180 | function = "FLWP"; |
| 181 | groups = "FLWP"; |
| 182 | }; |
| 183 | |
| 184 | pinctrl_gpid_default: gpid_default { |
| 185 | function = "GPID"; |
| 186 | groups = "GPID"; |
| 187 | }; |
| 188 | |
| 189 | pinctrl_gpid0_default: gpid0_default { |
| 190 | function = "GPID0"; |
| 191 | groups = "GPID0"; |
| 192 | }; |
| 193 | |
| 194 | pinctrl_gpid2_default: gpid2_default { |
| 195 | function = "GPID2"; |
| 196 | groups = "GPID2"; |
| 197 | }; |
| 198 | |
| 199 | pinctrl_gpid4_default: gpid4_default { |
| 200 | function = "GPID4"; |
| 201 | groups = "GPID4"; |
| 202 | }; |
| 203 | |
| 204 | pinctrl_gpid6_default: gpid6_default { |
| 205 | function = "GPID6"; |
| 206 | groups = "GPID6"; |
| 207 | }; |
| 208 | |
| 209 | pinctrl_gpie0_default: gpie0_default { |
| 210 | function = "GPIE0"; |
| 211 | groups = "GPIE0"; |
| 212 | }; |
| 213 | |
| 214 | pinctrl_gpie2_default: gpie2_default { |
| 215 | function = "GPIE2"; |
| 216 | groups = "GPIE2"; |
| 217 | }; |
| 218 | |
| 219 | pinctrl_gpie4_default: gpie4_default { |
| 220 | function = "GPIE4"; |
| 221 | groups = "GPIE4"; |
| 222 | }; |
| 223 | |
| 224 | pinctrl_gpie6_default: gpie6_default { |
| 225 | function = "GPIE6"; |
| 226 | groups = "GPIE6"; |
| 227 | }; |
| 228 | |
| 229 | pinctrl_i2c10_default: i2c10_default { |
| 230 | function = "I2C10"; |
| 231 | groups = "I2C10"; |
| 232 | }; |
| 233 | |
| 234 | pinctrl_i2c11_default: i2c11_default { |
| 235 | function = "I2C11"; |
| 236 | groups = "I2C11"; |
| 237 | }; |
| 238 | |
| 239 | pinctrl_i2c12_default: i2c12_default { |
| 240 | function = "I2C12"; |
| 241 | groups = "I2C12"; |
| 242 | }; |
| 243 | |
| 244 | pinctrl_i2c13_default: i2c13_default { |
| 245 | function = "I2C13"; |
| 246 | groups = "I2C13"; |
| 247 | }; |
| 248 | |
| 249 | pinctrl_i2c14_default: i2c14_default { |
| 250 | function = "I2C14"; |
| 251 | groups = "I2C14"; |
| 252 | }; |
| 253 | |
| 254 | pinctrl_i2c3_default: i2c3_default { |
| 255 | function = "I2C3"; |
| 256 | groups = "I2C3"; |
| 257 | }; |
| 258 | |
| 259 | pinctrl_i2c4_default: i2c4_default { |
| 260 | function = "I2C4"; |
| 261 | groups = "I2C4"; |
| 262 | }; |
| 263 | |
| 264 | pinctrl_i2c5_default: i2c5_default { |
| 265 | function = "I2C5"; |
| 266 | groups = "I2C5"; |
| 267 | }; |
| 268 | |
| 269 | pinctrl_i2c6_default: i2c6_default { |
| 270 | function = "I2C6"; |
| 271 | groups = "I2C6"; |
| 272 | }; |
| 273 | |
| 274 | pinctrl_i2c7_default: i2c7_default { |
| 275 | function = "I2C7"; |
| 276 | groups = "I2C7"; |
| 277 | }; |
| 278 | |
| 279 | pinctrl_i2c8_default: i2c8_default { |
| 280 | function = "I2C8"; |
| 281 | groups = "I2C8"; |
| 282 | }; |
| 283 | |
| 284 | pinctrl_i2c9_default: i2c9_default { |
| 285 | function = "I2C9"; |
| 286 | groups = "I2C9"; |
| 287 | }; |
| 288 | |
| 289 | pinctrl_lpcpd_default: lpcpd_default { |
| 290 | function = "LPCPD"; |
| 291 | groups = "LPCPD"; |
| 292 | }; |
| 293 | |
| 294 | pinctrl_lpcpme_default: lpcpme_default { |
| 295 | function = "LPCPME"; |
| 296 | groups = "LPCPME"; |
| 297 | }; |
| 298 | |
| 299 | pinctrl_lpcrst_default: lpcrst_default { |
| 300 | function = "LPCRST"; |
| 301 | groups = "LPCRST"; |
| 302 | }; |
| 303 | |
| 304 | pinctrl_lpcsmi_default: lpcsmi_default { |
| 305 | function = "LPCSMI"; |
| 306 | groups = "LPCSMI"; |
| 307 | }; |
| 308 | |
| 309 | pinctrl_mac1link_default: mac1link_default { |
| 310 | function = "MAC1LINK"; |
| 311 | groups = "MAC1LINK"; |
| 312 | }; |
| 313 | |
| 314 | pinctrl_mac2link_default: mac2link_default { |
| 315 | function = "MAC2LINK"; |
| 316 | groups = "MAC2LINK"; |
| 317 | }; |
| 318 | |
| 319 | pinctrl_mdio1_default: mdio1_default { |
| 320 | function = "MDIO1"; |
| 321 | groups = "MDIO1"; |
| 322 | }; |
| 323 | |
| 324 | pinctrl_mdio2_default: mdio2_default { |
| 325 | function = "MDIO2"; |
| 326 | groups = "MDIO2"; |
| 327 | }; |
| 328 | |
| 329 | pinctrl_ncts1_default: ncts1_default { |
| 330 | function = "NCTS1"; |
| 331 | groups = "NCTS1"; |
| 332 | }; |
| 333 | |
| 334 | pinctrl_ncts2_default: ncts2_default { |
| 335 | function = "NCTS2"; |
| 336 | groups = "NCTS2"; |
| 337 | }; |
| 338 | |
| 339 | pinctrl_ncts3_default: ncts3_default { |
| 340 | function = "NCTS3"; |
| 341 | groups = "NCTS3"; |
| 342 | }; |
| 343 | |
| 344 | pinctrl_ncts4_default: ncts4_default { |
| 345 | function = "NCTS4"; |
| 346 | groups = "NCTS4"; |
| 347 | }; |
| 348 | |
| 349 | pinctrl_ndcd1_default: ndcd1_default { |
| 350 | function = "NDCD1"; |
| 351 | groups = "NDCD1"; |
| 352 | }; |
| 353 | |
| 354 | pinctrl_ndcd2_default: ndcd2_default { |
| 355 | function = "NDCD2"; |
| 356 | groups = "NDCD2"; |
| 357 | }; |
| 358 | |
| 359 | pinctrl_ndcd3_default: ndcd3_default { |
| 360 | function = "NDCD3"; |
| 361 | groups = "NDCD3"; |
| 362 | }; |
| 363 | |
| 364 | pinctrl_ndcd4_default: ndcd4_default { |
| 365 | function = "NDCD4"; |
| 366 | groups = "NDCD4"; |
| 367 | }; |
| 368 | |
| 369 | pinctrl_ndsr1_default: ndsr1_default { |
| 370 | function = "NDSR1"; |
| 371 | groups = "NDSR1"; |
| 372 | }; |
| 373 | |
| 374 | pinctrl_ndsr2_default: ndsr2_default { |
| 375 | function = "NDSR2"; |
| 376 | groups = "NDSR2"; |
| 377 | }; |
| 378 | |
| 379 | pinctrl_ndsr3_default: ndsr3_default { |
| 380 | function = "NDSR3"; |
| 381 | groups = "NDSR3"; |
| 382 | }; |
| 383 | |
| 384 | pinctrl_ndsr4_default: ndsr4_default { |
| 385 | function = "NDSR4"; |
| 386 | groups = "NDSR4"; |
| 387 | }; |
| 388 | |
| 389 | pinctrl_ndtr1_default: ndtr1_default { |
| 390 | function = "NDTR1"; |
| 391 | groups = "NDTR1"; |
| 392 | }; |
| 393 | |
| 394 | pinctrl_ndtr2_default: ndtr2_default { |
| 395 | function = "NDTR2"; |
| 396 | groups = "NDTR2"; |
| 397 | }; |
| 398 | |
| 399 | pinctrl_ndtr3_default: ndtr3_default { |
| 400 | function = "NDTR3"; |
| 401 | groups = "NDTR3"; |
| 402 | }; |
| 403 | |
| 404 | pinctrl_ndtr4_default: ndtr4_default { |
| 405 | function = "NDTR4"; |
| 406 | groups = "NDTR4"; |
| 407 | }; |
| 408 | |
| 409 | pinctrl_ndts4_default: ndts4_default { |
| 410 | function = "NDTS4"; |
| 411 | groups = "NDTS4"; |
| 412 | }; |
| 413 | |
| 414 | pinctrl_nri1_default: nri1_default { |
| 415 | function = "NRI1"; |
| 416 | groups = "NRI1"; |
| 417 | }; |
| 418 | |
| 419 | pinctrl_nri2_default: nri2_default { |
| 420 | function = "NRI2"; |
| 421 | groups = "NRI2"; |
| 422 | }; |
| 423 | |
| 424 | pinctrl_nri3_default: nri3_default { |
| 425 | function = "NRI3"; |
| 426 | groups = "NRI3"; |
| 427 | }; |
| 428 | |
| 429 | pinctrl_nri4_default: nri4_default { |
| 430 | function = "NRI4"; |
| 431 | groups = "NRI4"; |
| 432 | }; |
| 433 | |
| 434 | pinctrl_nrts1_default: nrts1_default { |
| 435 | function = "NRTS1"; |
| 436 | groups = "NRTS1"; |
| 437 | }; |
| 438 | |
| 439 | pinctrl_nrts2_default: nrts2_default { |
| 440 | function = "NRTS2"; |
| 441 | groups = "NRTS2"; |
| 442 | }; |
| 443 | |
| 444 | pinctrl_nrts3_default: nrts3_default { |
| 445 | function = "NRTS3"; |
| 446 | groups = "NRTS3"; |
| 447 | }; |
| 448 | |
| 449 | pinctrl_oscclk_default: oscclk_default { |
| 450 | function = "OSCCLK"; |
| 451 | groups = "OSCCLK"; |
| 452 | }; |
| 453 | |
| 454 | pinctrl_pwm0_default: pwm0_default { |
| 455 | function = "PWM0"; |
| 456 | groups = "PWM0"; |
| 457 | }; |
| 458 | |
| 459 | pinctrl_pwm1_default: pwm1_default { |
| 460 | function = "PWM1"; |
| 461 | groups = "PWM1"; |
| 462 | }; |
| 463 | |
| 464 | pinctrl_pwm2_default: pwm2_default { |
| 465 | function = "PWM2"; |
| 466 | groups = "PWM2"; |
| 467 | }; |
| 468 | |
| 469 | pinctrl_pwm3_default: pwm3_default { |
| 470 | function = "PWM3"; |
| 471 | groups = "PWM3"; |
| 472 | }; |
| 473 | |
| 474 | pinctrl_pwm4_default: pwm4_default { |
| 475 | function = "PWM4"; |
| 476 | groups = "PWM4"; |
| 477 | }; |
| 478 | |
| 479 | pinctrl_pwm5_default: pwm5_default { |
| 480 | function = "PWM5"; |
| 481 | groups = "PWM5"; |
| 482 | }; |
| 483 | |
| 484 | pinctrl_pwm6_default: pwm6_default { |
| 485 | function = "PWM6"; |
| 486 | groups = "PWM6"; |
| 487 | }; |
| 488 | |
| 489 | pinctrl_pwm7_default: pwm7_default { |
| 490 | function = "PWM7"; |
| 491 | groups = "PWM7"; |
| 492 | }; |
| 493 | |
| 494 | pinctrl_rgmii1_default: rgmii1_default { |
| 495 | function = "RGMII1"; |
| 496 | groups = "RGMII1"; |
| 497 | }; |
| 498 | |
| 499 | pinctrl_rgmii2_default: rgmii2_default { |
| 500 | function = "RGMII2"; |
| 501 | groups = "RGMII2"; |
| 502 | }; |
| 503 | |
| 504 | pinctrl_rmii1_default: rmii1_default { |
| 505 | function = "RMII1"; |
| 506 | groups = "RMII1"; |
| 507 | }; |
| 508 | |
| 509 | pinctrl_rmii2_default: rmii2_default { |
| 510 | function = "RMII2"; |
| 511 | groups = "RMII2"; |
| 512 | }; |
| 513 | |
| 514 | pinctrl_rom16_default: rom16_default { |
| 515 | function = "ROM16"; |
| 516 | groups = "ROM16"; |
| 517 | }; |
| 518 | |
| 519 | pinctrl_rom8_default: rom8_default { |
| 520 | function = "ROM8"; |
| 521 | groups = "ROM8"; |
| 522 | }; |
| 523 | |
| 524 | pinctrl_romcs1_default: romcs1_default { |
| 525 | function = "ROMCS1"; |
| 526 | groups = "ROMCS1"; |
| 527 | }; |
| 528 | |
| 529 | pinctrl_romcs2_default: romcs2_default { |
| 530 | function = "ROMCS2"; |
| 531 | groups = "ROMCS2"; |
| 532 | }; |
| 533 | |
| 534 | pinctrl_romcs3_default: romcs3_default { |
| 535 | function = "ROMCS3"; |
| 536 | groups = "ROMCS3"; |
| 537 | }; |
| 538 | |
| 539 | pinctrl_romcs4_default: romcs4_default { |
| 540 | function = "ROMCS4"; |
| 541 | groups = "ROMCS4"; |
| 542 | }; |
| 543 | |
| 544 | pinctrl_rxd1_default: rxd1_default { |
| 545 | function = "RXD1"; |
| 546 | groups = "RXD1"; |
| 547 | }; |
| 548 | |
| 549 | pinctrl_rxd2_default: rxd2_default { |
| 550 | function = "RXD2"; |
| 551 | groups = "RXD2"; |
| 552 | }; |
| 553 | |
| 554 | pinctrl_rxd3_default: rxd3_default { |
| 555 | function = "RXD3"; |
| 556 | groups = "RXD3"; |
| 557 | }; |
| 558 | |
| 559 | pinctrl_rxd4_default: rxd4_default { |
| 560 | function = "RXD4"; |
| 561 | groups = "RXD4"; |
| 562 | }; |
| 563 | |
| 564 | pinctrl_salt1_default: salt1_default { |
| 565 | function = "SALT1"; |
| 566 | groups = "SALT1"; |
| 567 | }; |
| 568 | |
| 569 | pinctrl_salt2_default: salt2_default { |
| 570 | function = "SALT2"; |
| 571 | groups = "SALT2"; |
| 572 | }; |
| 573 | |
| 574 | pinctrl_salt3_default: salt3_default { |
| 575 | function = "SALT3"; |
| 576 | groups = "SALT3"; |
| 577 | }; |
| 578 | |
| 579 | pinctrl_salt4_default: salt4_default { |
| 580 | function = "SALT4"; |
| 581 | groups = "SALT4"; |
| 582 | }; |
| 583 | |
| 584 | pinctrl_sd1_default: sd1_default { |
| 585 | function = "SD1"; |
| 586 | groups = "SD1"; |
| 587 | }; |
| 588 | |
| 589 | pinctrl_sd2_default: sd2_default { |
| 590 | function = "SD2"; |
| 591 | groups = "SD2"; |
| 592 | }; |
| 593 | |
| 594 | pinctrl_sgpmck_default: sgpmck_default { |
| 595 | function = "SGPMCK"; |
| 596 | groups = "SGPMCK"; |
| 597 | }; |
| 598 | |
| 599 | pinctrl_sgpmi_default: sgpmi_default { |
| 600 | function = "SGPMI"; |
| 601 | groups = "SGPMI"; |
| 602 | }; |
| 603 | |
| 604 | pinctrl_sgpmld_default: sgpmld_default { |
| 605 | function = "SGPMLD"; |
| 606 | groups = "SGPMLD"; |
| 607 | }; |
| 608 | |
| 609 | pinctrl_sgpmo_default: sgpmo_default { |
| 610 | function = "SGPMO"; |
| 611 | groups = "SGPMO"; |
| 612 | }; |
| 613 | |
| 614 | pinctrl_sgpsck_default: sgpsck_default { |
| 615 | function = "SGPSCK"; |
| 616 | groups = "SGPSCK"; |
| 617 | }; |
| 618 | |
| 619 | pinctrl_sgpsi0_default: sgpsi0_default { |
| 620 | function = "SGPSI0"; |
| 621 | groups = "SGPSI0"; |
| 622 | }; |
| 623 | |
| 624 | pinctrl_sgpsi1_default: sgpsi1_default { |
| 625 | function = "SGPSI1"; |
| 626 | groups = "SGPSI1"; |
| 627 | }; |
| 628 | |
| 629 | pinctrl_sgpsld_default: sgpsld_default { |
| 630 | function = "SGPSLD"; |
| 631 | groups = "SGPSLD"; |
| 632 | }; |
| 633 | |
| 634 | pinctrl_sioonctrl_default: sioonctrl_default { |
| 635 | function = "SIOONCTRL"; |
| 636 | groups = "SIOONCTRL"; |
| 637 | }; |
| 638 | |
| 639 | pinctrl_siopbi_default: siopbi_default { |
| 640 | function = "SIOPBI"; |
| 641 | groups = "SIOPBI"; |
| 642 | }; |
| 643 | |
| 644 | pinctrl_siopbo_default: siopbo_default { |
| 645 | function = "SIOPBO"; |
| 646 | groups = "SIOPBO"; |
| 647 | }; |
| 648 | |
| 649 | pinctrl_siopwreq_default: siopwreq_default { |
| 650 | function = "SIOPWREQ"; |
| 651 | groups = "SIOPWREQ"; |
| 652 | }; |
| 653 | |
| 654 | pinctrl_siopwrgd_default: siopwrgd_default { |
| 655 | function = "SIOPWRGD"; |
| 656 | groups = "SIOPWRGD"; |
| 657 | }; |
| 658 | |
| 659 | pinctrl_sios3_default: sios3_default { |
| 660 | function = "SIOS3"; |
| 661 | groups = "SIOS3"; |
| 662 | }; |
| 663 | |
| 664 | pinctrl_sios5_default: sios5_default { |
| 665 | function = "SIOS5"; |
| 666 | groups = "SIOS5"; |
| 667 | }; |
| 668 | |
| 669 | pinctrl_siosci_default: siosci_default { |
| 670 | function = "SIOSCI"; |
| 671 | groups = "SIOSCI"; |
| 672 | }; |
| 673 | |
| 674 | pinctrl_spi1_default: spi1_default { |
| 675 | function = "SPI1"; |
| 676 | groups = "SPI1"; |
| 677 | }; |
| 678 | |
| 679 | pinctrl_spi1debug_default: spi1debug_default { |
| 680 | function = "SPI1DEBUG"; |
| 681 | groups = "SPI1DEBUG"; |
| 682 | }; |
| 683 | |
| 684 | pinctrl_spi1passthru_default: spi1passthru_default { |
| 685 | function = "SPI1PASSTHRU"; |
| 686 | groups = "SPI1PASSTHRU"; |
| 687 | }; |
| 688 | |
| 689 | pinctrl_spics1_default: spics1_default { |
| 690 | function = "SPICS1"; |
| 691 | groups = "SPICS1"; |
| 692 | }; |
| 693 | |
| 694 | pinctrl_timer3_default: timer3_default { |
| 695 | function = "TIMER3"; |
| 696 | groups = "TIMER3"; |
| 697 | }; |
| 698 | |
| 699 | pinctrl_timer4_default: timer4_default { |
| 700 | function = "TIMER4"; |
| 701 | groups = "TIMER4"; |
| 702 | }; |
| 703 | |
| 704 | pinctrl_timer5_default: timer5_default { |
| 705 | function = "TIMER5"; |
| 706 | groups = "TIMER5"; |
| 707 | }; |
| 708 | |
| 709 | pinctrl_timer6_default: timer6_default { |
| 710 | function = "TIMER6"; |
| 711 | groups = "TIMER6"; |
| 712 | }; |
| 713 | |
| 714 | pinctrl_timer7_default: timer7_default { |
| 715 | function = "TIMER7"; |
| 716 | groups = "TIMER7"; |
| 717 | }; |
| 718 | |
| 719 | pinctrl_timer8_default: timer8_default { |
| 720 | function = "TIMER8"; |
| 721 | groups = "TIMER8"; |
| 722 | }; |
| 723 | |
| 724 | pinctrl_txd1_default: txd1_default { |
| 725 | function = "TXD1"; |
| 726 | groups = "TXD1"; |
| 727 | }; |
| 728 | |
| 729 | pinctrl_txd2_default: txd2_default { |
| 730 | function = "TXD2"; |
| 731 | groups = "TXD2"; |
| 732 | }; |
| 733 | |
| 734 | pinctrl_txd3_default: txd3_default { |
| 735 | function = "TXD3"; |
| 736 | groups = "TXD3"; |
| 737 | }; |
| 738 | |
| 739 | pinctrl_txd4_default: txd4_default { |
| 740 | function = "TXD4"; |
| 741 | groups = "TXD4"; |
| 742 | }; |
| 743 | |
| 744 | pinctrl_uart6_default: uart6_default { |
| 745 | function = "UART6"; |
| 746 | groups = "UART6"; |
| 747 | }; |
| 748 | |
| 749 | pinctrl_usbcki_default: usbcki_default { |
| 750 | function = "USBCKI"; |
| 751 | groups = "USBCKI"; |
| 752 | }; |
| 753 | |
| 754 | pinctrl_vgabios_rom_default: vgabios_rom_default { |
| 755 | function = "VGABIOS_ROM"; |
| 756 | groups = "VGABIOS_ROM"; |
| 757 | }; |
| 758 | |
| 759 | pinctrl_vgahs_default: vgahs_default { |
| 760 | function = "VGAHS"; |
| 761 | groups = "VGAHS"; |
| 762 | }; |
| 763 | |
| 764 | pinctrl_vgavs_default: vgavs_default { |
| 765 | function = "VGAVS"; |
| 766 | groups = "VGAVS"; |
| 767 | }; |
| 768 | |
| 769 | pinctrl_vpi18_default: vpi18_default { |
| 770 | function = "VPI18"; |
| 771 | groups = "VPI18"; |
| 772 | }; |
| 773 | |
| 774 | pinctrl_vpi24_default: vpi24_default { |
| 775 | function = "VPI24"; |
| 776 | groups = "VPI24"; |
| 777 | }; |
| 778 | |
| 779 | pinctrl_vpi30_default: vpi30_default { |
| 780 | function = "VPI30"; |
| 781 | groups = "VPI30"; |
| 782 | }; |
| 783 | |
| 784 | pinctrl_vpo12_default: vpo12_default { |
| 785 | function = "VPO12"; |
| 786 | groups = "VPO12"; |
| 787 | }; |
| 788 | |
| 789 | pinctrl_vpo24_default: vpo24_default { |
| 790 | function = "VPO24"; |
| 791 | groups = "VPO24"; |
| 792 | }; |
| 793 | |
| 794 | pinctrl_wdtrst1_default: wdtrst1_default { |
| 795 | function = "WDTRST1"; |
| 796 | groups = "WDTRST1"; |
| 797 | }; |
| 798 | |
| 799 | pinctrl_wdtrst2_default: wdtrst2_default { |
| 800 | function = "WDTRST2"; |
| 801 | groups = "WDTRST2"; |
| 802 | }; |
| 803 | |
| 804 | }; |
| 805 | }; |
| 806 | |
Joel Stanley | d44a113 | 2016-03-16 22:03:37 +1030 | [diff] [blame] | 807 | clk_apb: clk_apb@1e6e2008 { |
| 808 | #clock-cells = <0>; |
| 809 | compatible = "aspeed,g4-apb-clock"; |
| 810 | reg = <0x1e6e2008 0x4>; |
| 811 | clocks = <&clk_hpll>; |
| 812 | }; |
| 813 | |
| 814 | clk_uart: clk_uart@1e6e2008 { |
| 815 | #clock-cells = <0>; |
| 816 | compatible = "aspeed,uart-clock"; |
| 817 | reg = <0x1e6e202c 0x4>; |
| 818 | }; |
| 819 | |
| 820 | sram@1e720000 { |
| 821 | compatible = "mmio-sram"; |
| 822 | reg = <0x1e720000 0x8000>; // 32K |
| 823 | }; |
| 824 | |
Andrew Jeffery | 0995500 | 2016-12-06 14:53:44 +1100 | [diff] [blame^] | 825 | gpio: gpio@1e780000 { |
| 826 | #gpio-cells = <2>; |
| 827 | gpio-controller; |
| 828 | compatible = "aspeed,ast2400-gpio"; |
| 829 | reg = <0x1e780000 0x1000>; |
| 830 | interrupts = <20>; |
| 831 | gpio-ranges = <&pinctrl 0 0 220>; |
| 832 | interrupt-controller; |
| 833 | }; |
| 834 | |
Joel Stanley | d44a113 | 2016-03-16 22:03:37 +1030 | [diff] [blame] | 835 | timer: timer@1e782000 { |
| 836 | compatible = "aspeed,ast2400-timer"; |
| 837 | reg = <0x1e782000 0x90>; |
| 838 | // The moxart_timer driver registers only one |
| 839 | // interrupt and assumes it's for timer 1 |
| 840 | //interrupts = <16 17 18 35 36 37 38 39>; |
| 841 | interrupts = <16>; |
| 842 | clocks = <&clk_apb>; |
| 843 | }; |
| 844 | |
| 845 | wdt1: wdt@1e785000 { |
| 846 | compatible = "aspeed,wdt"; |
| 847 | reg = <0x1e785000 0x1c>; |
| 848 | interrupts = <27>; |
| 849 | }; |
| 850 | |
| 851 | wdt2: wdt@1e785020 { |
| 852 | compatible = "aspeed,wdt"; |
| 853 | reg = <0x1e785020 0x1c>; |
| 854 | interrupts = <27>; |
| 855 | clocks = <&clk_apb>; |
| 856 | status = "disabled"; |
| 857 | }; |
| 858 | |
| 859 | uart1: serial@1e783000 { |
| 860 | compatible = "ns16550a"; |
| 861 | reg = <0x1e783000 0x1000>; |
| 862 | reg-shift = <2>; |
| 863 | interrupts = <9>; |
| 864 | clocks = <&clk_uart>; |
| 865 | no-loopback-test; |
| 866 | status = "disabled"; |
| 867 | }; |
| 868 | |
| 869 | uart2: serial@1e78d000 { |
| 870 | compatible = "ns16550a"; |
| 871 | reg = <0x1e78d000 0x1000>; |
| 872 | reg-shift = <2>; |
| 873 | interrupts = <32>; |
| 874 | clocks = <&clk_uart>; |
| 875 | no-loopback-test; |
| 876 | status = "disabled"; |
| 877 | }; |
| 878 | |
| 879 | uart3: serial@1e78e000 { |
| 880 | compatible = "ns16550a"; |
| 881 | reg = <0x1e78e000 0x1000>; |
| 882 | reg-shift = <2>; |
| 883 | interrupts = <33>; |
| 884 | clocks = <&clk_uart>; |
| 885 | no-loopback-test; |
| 886 | status = "disabled"; |
| 887 | }; |
| 888 | |
| 889 | uart4: serial@1e78f000 { |
| 890 | compatible = "ns16550a"; |
| 891 | reg = <0x1e78f000 0x1000>; |
| 892 | reg-shift = <2>; |
| 893 | interrupts = <34>; |
| 894 | clocks = <&clk_uart>; |
| 895 | no-loopback-test; |
| 896 | status = "disabled"; |
| 897 | }; |
| 898 | |
| 899 | uart5: serial@1e784000 { |
| 900 | compatible = "ns16550a"; |
| 901 | reg = <0x1e784000 0x1000>; |
| 902 | reg-shift = <2>; |
| 903 | interrupts = <10>; |
| 904 | clocks = <&clk_uart>; |
| 905 | current-speed = <38400>; |
| 906 | no-loopback-test; |
| 907 | status = "disabled"; |
| 908 | }; |
| 909 | |
| 910 | uart6: serial@1e787000 { |
| 911 | compatible = "ns16550a"; |
| 912 | reg = <0x1e787000 0x1000>; |
| 913 | reg-shift = <2>; |
| 914 | interrupts = <10>; |
| 915 | clocks = <&clk_uart>; |
| 916 | no-loopback-test; |
| 917 | status = "disabled"; |
| 918 | }; |
| 919 | }; |
| 920 | }; |
| 921 | }; |