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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / e90e236250e9edd2584a3405d0b2482ef687a637 / . / drivers / scsi / pm8001 / pm80xx_hwi.c
blob: 9d04e5cfffb4e4ea728ade82c555a478f6fb9294 [file] [log] [blame]
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]48
49
50int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51{
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67}
68
69void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72{
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index / 4);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85}
86
87ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89{
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]94 u32 accum_len , reg_val, index, *temp;
95 unsigned long start;
96 u8 *direct_data;
97 char *fatal_error_data = buf;
98
99 pm8001_ha->forensic_info.data_buf.direct_data = buf;
100 if (pm8001_ha->chip_id == chip_8001) {
101 pm8001_ha->forensic_info.data_buf.direct_data +=
102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
103 "Not supported for SPC controller");
104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
105 (char *)buf;
106 }
107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
108 PM8001_IO_DBG(pm8001_ha,
109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
110 direct_data = (u8 *)fatal_error_data;
111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]113 pm8001_ha->forensic_info.data_buf.read_len = 0;
114
115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]116
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]117 /* start to get data */
118 /* Program the MEMBASE II Shifting Register with 0x00.*/
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
120 pm8001_ha->fatal_forensic_shift_offset);
121 pm8001_ha->forensic_last_offset = 0;
122 pm8001_ha->forensic_fatal_step = 0;
123 pm8001_ha->fatal_bar_loc = 0;
124 }
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]125
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]126 /* Read until accum_len is retrived */
127 accum_len = pm8001_mr32(fatal_table_address,
128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
130 accum_len));
131 if (accum_len == 0xFFFFFFFF) {
132 PM8001_IO_DBG(pm8001_ha,
133 pm8001_printk("Possible PCI issue 0x%x not expected\n",
134 accum_len));
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]135 return -EIO;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]136 }
137 if (accum_len == 0 || accum_len >= 0x100000) {
138 pm8001_ha->forensic_info.data_buf.direct_data +=
139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
140 "%08x ", 0xFFFFFFFF);
141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
142 (char *)buf;
143 }
144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
145 if (pm8001_ha->forensic_fatal_step == 0) {
146moreData:
147 if (pm8001_ha->forensic_info.data_buf.direct_data) {
148 /* Data is in bar, copy to host memory */
149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
151 pm8001_ha->forensic_info.data_buf.direct_len ,
152 1);
153 }
154 pm8001_ha->fatal_bar_loc +=
155 pm8001_ha->forensic_info.data_buf.direct_len;
156 pm8001_ha->forensic_info.data_buf.direct_offset +=
157 pm8001_ha->forensic_info.data_buf.direct_len;
158 pm8001_ha->forensic_last_offset +=
159 pm8001_ha->forensic_info.data_buf.direct_len;
160 pm8001_ha->forensic_info.data_buf.read_len =
161 pm8001_ha->forensic_info.data_buf.direct_len;
162
163 if (pm8001_ha->forensic_last_offset >= accum_len) {
164 pm8001_ha->forensic_info.data_buf.direct_data +=
165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
166 "%08x ", 3);
167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
168 pm8001_ha->forensic_info.data_buf.direct_data +=
169 sprintf(pm8001_ha->
170 forensic_info.data_buf.direct_data,
171 "%08x ", *(temp + index));
172 }
173
174 pm8001_ha->fatal_bar_loc = 0;
175 pm8001_ha->forensic_fatal_step = 1;
176 pm8001_ha->fatal_forensic_shift_offset = 0;
177 pm8001_ha->forensic_last_offset = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]178 return (char *)pm8001_ha->
179 forensic_info.data_buf.direct_data -
180 (char *)buf;
181 }
182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->
185 forensic_info.data_buf.direct_data,
186 "%08x ", 2);
187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
188 pm8001_ha->forensic_info.data_buf.direct_data +=
189 sprintf(pm8001_ha->
190 forensic_info.data_buf.direct_data,
191 "%08x ", *(temp + index));
192 }
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]193 return (char *)pm8001_ha->
194 forensic_info.data_buf.direct_data -
195 (char *)buf;
196 }
197
198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
199 pm8001_ha->forensic_info.data_buf.direct_data +=
200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
201 "%08x ", 2);
202 for (index = 0; index < 256; index++) {
203 pm8001_ha->forensic_info.data_buf.direct_data +=
204 sprintf(pm8001_ha->
205 forensic_info.data_buf.direct_data,
206 "%08x ", *(temp + index));
207 }
208 pm8001_ha->fatal_forensic_shift_offset += 0x100;
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
210 pm8001_ha->fatal_forensic_shift_offset);
211 pm8001_ha->fatal_bar_loc = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
213 (char *)buf;
214 }
215 if (pm8001_ha->forensic_fatal_step == 1) {
216 pm8001_ha->fatal_forensic_shift_offset = 0;
217 /* Read 64K of the debug data. */
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
219 pm8001_ha->fatal_forensic_shift_offset);
220 pm8001_mw32(fatal_table_address,
221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
222 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
223
224 /* Poll FDDHSHK until clear */
225 start = jiffies + (2 * HZ); /* 2 sec */
226
227 do {
228 reg_val = pm8001_mr32(fatal_table_address,
229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
230 } while ((reg_val) && time_before(jiffies, start));
231
232 if (reg_val != 0) {
233 PM8001_FAIL_DBG(pm8001_ha,
234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
235 " = 0x%x\n", reg_val));
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]236 return -EIO;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]237 }
238
239 /* Read the next 64K of the debug data. */
240 pm8001_ha->forensic_fatal_step = 0;
241 if (pm8001_mr32(fatal_table_address,
242 MPI_FATAL_EDUMP_TABLE_STATUS) !=
243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
244 pm8001_mw32(fatal_table_address,
245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
246 goto moreData;
247 } else {
248 pm8001_ha->forensic_info.data_buf.direct_data +=
249 sprintf(pm8001_ha->
250 forensic_info.data_buf.direct_data,
251 "%08x ", 4);
252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
253 pm8001_ha->forensic_info.data_buf.direct_len = 0;
254 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
255 pm8001_ha->forensic_info.data_buf.read_len = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]256 }
257 }
258
259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
260 (char *)buf;
261}
262
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]263/**
264 * read_main_config_table - read the configure table and save it.
265 * @pm8001_ha: our hba card information
266 */
267static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
268{
269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
270
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
274 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
276 pm8001_mr32(address, MAIN_FW_REVISION);
277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
284 pm8001_mr32(address, MAIN_GST_OFFSET);
285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
286 pm8001_mr32(address, MAIN_IBQ_OFFSET);
287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
288 pm8001_mr32(address, MAIN_OBQ_OFFSET);
289
290 /* read Error Dump Offset and Length */
291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
299
300 /* read GPIO LED settings from the configuration table */
301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
303
304 /* read analog Setting offset from the configuration table */
305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
307
308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]312 /* read port recover and reset timeout */
313 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
314 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
Viswas G24fff012017-10-18 11:39:08 +0530[diff] [blame]315 /* read ILA and inactive firmware version */
316 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
317 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
318 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
319 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]320
321 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
322 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
323 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
324 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
325 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
326
327 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
328 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
329 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
330 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
331 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
332 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
333 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
334
335 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
336 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
337 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
338 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]339}
340
341/**
342 * read_general_status_table - read the general status table and save it.
343 * @pm8001_ha: our hba card information
344 */
345static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
346{
347 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
348 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
349 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
350 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
351 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
352 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
353 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
354 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
355 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
356 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
357 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
358 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
359 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
360 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
361 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
362 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
363 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
364 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
365 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
366 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
367 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
368 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
369 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
370 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
371 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
372 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
373 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
374 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
375 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
376}
377/**
378 * read_phy_attr_table - read the phy attribute table and save it.
379 * @pm8001_ha: our hba card information
380 */
381static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
382{
383 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
384 pm8001_ha->phy_attr_table.phystart1_16[0] =
385 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
386 pm8001_ha->phy_attr_table.phystart1_16[1] =
387 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
388 pm8001_ha->phy_attr_table.phystart1_16[2] =
389 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
390 pm8001_ha->phy_attr_table.phystart1_16[3] =
391 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
392 pm8001_ha->phy_attr_table.phystart1_16[4] =
393 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
394 pm8001_ha->phy_attr_table.phystart1_16[5] =
395 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
396 pm8001_ha->phy_attr_table.phystart1_16[6] =
397 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
398 pm8001_ha->phy_attr_table.phystart1_16[7] =
399 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
400 pm8001_ha->phy_attr_table.phystart1_16[8] =
401 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
402 pm8001_ha->phy_attr_table.phystart1_16[9] =
403 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
404 pm8001_ha->phy_attr_table.phystart1_16[10] =
405 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
406 pm8001_ha->phy_attr_table.phystart1_16[11] =
407 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
408 pm8001_ha->phy_attr_table.phystart1_16[12] =
409 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
410 pm8001_ha->phy_attr_table.phystart1_16[13] =
411 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
412 pm8001_ha->phy_attr_table.phystart1_16[14] =
413 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
414 pm8001_ha->phy_attr_table.phystart1_16[15] =
415 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
416
417 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
418 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
419 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
420 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
421 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
422 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
423 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
424 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
425 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
426 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
427 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
428 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
429 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
430 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
431 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
432 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
433 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
434 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
435 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
436 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
437 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
438 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
439 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
440 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
441 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
442 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
443 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
444 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
445 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
446 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
447 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
448 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
449
450}
451
452/**
453 * read_inbnd_queue_table - read the inbound queue table and save it.
454 * @pm8001_ha: our hba card information
455 */
456static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
457{
458 int i;
459 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
460 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
461 u32 offset = i * 0x20;
462 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
463 get_pci_bar_index(pm8001_mr32(address,
464 (offset + IB_PIPCI_BAR)));
465 pm8001_ha->inbnd_q_tbl[i].pi_offset =
466 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
467 }
468}
469
470/**
471 * read_outbnd_queue_table - read the outbound queue table and save it.
472 * @pm8001_ha: our hba card information
473 */
474static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
475{
476 int i;
477 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
478 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
479 u32 offset = i * 0x24;
480 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
481 get_pci_bar_index(pm8001_mr32(address,
482 (offset + OB_CIPCI_BAR)));
483 pm8001_ha->outbnd_q_tbl[i].ci_offset =
484 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
485 }
486}
487
488/**
489 * init_default_table_values - init the default table.
490 * @pm8001_ha: our hba card information
491 */
492static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
493{
494 int i;
495 u32 offsetib, offsetob;
496 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
497 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
498
499 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
500 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
501 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
502 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
503 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
504 PM8001_EVENT_LOG_SIZE;
505 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
506 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
507 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
508 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
509 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
510 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
511 PM8001_EVENT_LOG_SIZE;
512 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
513 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
514
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]515 /* Disable end to end CRC checking */
516 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
517
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]518 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
519 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]520 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]521 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
522 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
523 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
524 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
525 pm8001_ha->inbnd_q_tbl[i].base_virt =
526 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
527 pm8001_ha->inbnd_q_tbl[i].total_length =
528 pm8001_ha->memoryMap.region[IB + i].total_len;
529 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
530 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
531 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
532 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
533 pm8001_ha->inbnd_q_tbl[i].ci_virt =
534 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
535 offsetib = i * 0x20;
536 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
537 get_pci_bar_index(pm8001_mr32(addressib,
538 (offsetib + 0x14)));
539 pm8001_ha->inbnd_q_tbl[i].pi_offset =
540 pm8001_mr32(addressib, (offsetib + 0x18));
541 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
542 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]543
544 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
545 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
546 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
547 pm8001_ha->inbnd_q_tbl[i].pi_offset));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]548 }
549 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
550 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]551 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]552 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
553 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
554 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
555 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
556 pm8001_ha->outbnd_q_tbl[i].base_virt =
557 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
558 pm8001_ha->outbnd_q_tbl[i].total_length =
559 pm8001_ha->memoryMap.region[OB + i].total_len;
560 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
561 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
562 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
563 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
564 /* interrupt vector based on oq */
565 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
566 pm8001_ha->outbnd_q_tbl[i].pi_virt =
567 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
568 offsetob = i * 0x24;
569 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
570 get_pci_bar_index(pm8001_mr32(addressob,
571 offsetob + 0x14));
572 pm8001_ha->outbnd_q_tbl[i].ci_offset =
573 pm8001_mr32(addressob, (offsetob + 0x18));
574 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
575 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]576
577 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
578 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
579 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
580 pm8001_ha->outbnd_q_tbl[i].ci_offset));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]581 }
582}
583
584/**
585 * update_main_config_table - update the main default table to the HBA.
586 * @pm8001_ha: our hba card information
587 */
588static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
589{
590 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
591 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
593 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
594 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
595 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
597 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
598 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
599 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
600 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
601 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
602 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
603 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
604 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
605 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
606 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
607 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
608 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]609 /* Update Fatal error interrupt vector */
610 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
611 ((pm8001_ha->number_of_intr - 1) << 8);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]612 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
613 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]614 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
615 "Updated Fatal error interrupt vector 0x%x\n",
616 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
617
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]618 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
619 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]620
621 /* SPCv specific */
622 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
623 /* Set GPIOLED to 0x2 for LED indicator */
624 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
625 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
626 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]627 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
628 "Programming DW 0x21 in main cfg table with 0x%x\n",
629 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]630
631 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
632 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
633 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
634 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]635
636 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
637 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
638 PORT_RECOVERY_TIMEOUT;
Viswas G61daffd2017-10-18 11:39:12 +0530[diff] [blame]639 if (pm8001_ha->chip_id == chip_8006) {
640 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
641 0x0000ffff;
642 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
Deepak Ukey196ba662019-07-09 15:30:48 +0530[diff] [blame]643 CHIP_8006_PORT_RECOVERY_TIMEOUT;
Viswas G61daffd2017-10-18 11:39:12 +0530[diff] [blame]644 }
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]645 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
646 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]647}
648
649/**
650 * update_inbnd_queue_table - update the inbound queue table to the HBA.
651 * @pm8001_ha: our hba card information
652 */
653static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
654 int number)
655{
656 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
657 u16 offset = number * 0x20;
658 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
659 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
660 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
661 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
662 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
663 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
664 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
665 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
666 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
667 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]668
669 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
670 "IQ %d: Element pri size 0x%x\n",
671 number,
672 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
673
674 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
675 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
676 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
677 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
678
679 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
680 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
681 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
682 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]683}
684
685/**
686 * update_outbnd_queue_table - update the outbound queue table to the HBA.
687 * @pm8001_ha: our hba card information
688 */
689static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
690 int number)
691{
692 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
693 u16 offset = number * 0x24;
694 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
695 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
696 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
697 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
698 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
699 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
700 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
701 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
702 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
703 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
704 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
705 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]706
707 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
708 "OQ %d: Element pri size 0x%x\n",
709 number,
710 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
711
712 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
713 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
714 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
715 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
716
717 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
718 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
719 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
720 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]721}
722
723/**
724 * mpi_init_check - check firmware initialization status.
725 * @pm8001_ha: our hba card information
726 */
727static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
728{
729 u32 max_wait_count;
730 u32 value;
731 u32 gst_len_mpistate;
732
733 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
734 table is updated */
735 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
736 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]737 if (IS_SPCV_12G(pm8001_ha->pdev)) {
ianyare90e23622019-11-14 15:39:03 +0530[diff] [blame^]738 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]739 } else {
ianyare90e23622019-11-14 15:39:03 +0530[diff] [blame^]740 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]741 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]742 do {
743 udelay(1);
744 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
745 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
746 } while ((value != 0) && (--max_wait_count));
747
748 if (!max_wait_count)
749 return -1;
750 /* check the MPI-State for initialization upto 100ms*/
751 max_wait_count = 100 * 1000;/* 100 msec */
752 do {
753 udelay(1);
754 gst_len_mpistate =
755 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
756 GST_GSTLEN_MPIS_OFFSET);
757 } while ((GST_MPI_STATE_INIT !=
758 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
759 if (!max_wait_count)
760 return -1;
761
762 /* check MPI Initialization error */
763 gst_len_mpistate = gst_len_mpistate >> 16;
764 if (0x0000 != gst_len_mpistate)
765 return -1;
766
767 return 0;
768}
769
770/**
771 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
772 * @pm8001_ha: our hba card information
773 */
774static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
775{
776 u32 value;
777 u32 max_wait_count;
778 u32 max_wait_time;
779 int ret = 0;
780
781 /* reset / PCIe ready */
782 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
783 do {
784 udelay(1);
785 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
786 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
787
788 /* check ila status */
789 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
790 do {
791 udelay(1);
792 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
793 } while (((value & SCRATCH_PAD_ILA_READY) !=
794 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
795 if (!max_wait_count)
796 ret = -1;
797 else {
798 PM8001_MSG_DBG(pm8001_ha,
799 pm8001_printk(" ila ready status in %d millisec\n",
800 (max_wait_time - max_wait_count)));
801 }
802
803 /* check RAAE status */
804 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
805 do {
806 udelay(1);
807 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
808 } while (((value & SCRATCH_PAD_RAAE_READY) !=
809 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
810 if (!max_wait_count)
811 ret = -1;
812 else {
813 PM8001_MSG_DBG(pm8001_ha,
814 pm8001_printk(" raae ready status in %d millisec\n",
815 (max_wait_time - max_wait_count)));
816 }
817
818 /* check iop0 status */
819 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
820 do {
821 udelay(1);
822 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
823 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
824 (--max_wait_count));
825 if (!max_wait_count)
826 ret = -1;
827 else {
828 PM8001_MSG_DBG(pm8001_ha,
829 pm8001_printk(" iop0 ready status in %d millisec\n",
830 (max_wait_time - max_wait_count)));
831 }
832
833 /* check iop1 status only for 16 port controllers */
834 if ((pm8001_ha->chip_id != chip_8008) &&
835 (pm8001_ha->chip_id != chip_8009)) {
836 /* 200 milli sec */
837 max_wait_time = max_wait_count = 200 * 1000;
838 do {
839 udelay(1);
840 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
841 } while (((value & SCRATCH_PAD_IOP1_READY) !=
842 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
843 if (!max_wait_count)
844 ret = -1;
845 else {
846 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
847 "iop1 ready status in %d millisec\n",
848 (max_wait_time - max_wait_count)));
849 }
850 }
851
852 return ret;
853}
854
855static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
856{
857 void __iomem *base_addr;
858 u32 value;
859 u32 offset;
860 u32 pcibar;
861 u32 pcilogic;
862
863 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
864 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
865
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]866 PM8001_DEV_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]867 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
868 offset, value));
869 pcilogic = (value & 0xFC000000) >> 26;
870 pcibar = get_pci_bar_index(pcilogic);
871 PM8001_INIT_DBG(pm8001_ha,
872 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
873 pm8001_ha->main_cfg_tbl_addr = base_addr =
874 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
875 pm8001_ha->general_stat_tbl_addr =
876 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
877 0xFFFFFF);
878 pm8001_ha->inbnd_q_tbl_addr =
879 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
880 0xFFFFFF);
881 pm8001_ha->outbnd_q_tbl_addr =
882 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
883 0xFFFFFF);
884 pm8001_ha->ivt_tbl_addr =
885 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
886 0xFFFFFF);
887 pm8001_ha->pspa_q_tbl_addr =
888 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
889 0xFFFFFF);
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]890 pm8001_ha->fatal_tbl_addr =
891 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
892 0xFFFFFF);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]893
894 PM8001_INIT_DBG(pm8001_ha,
895 pm8001_printk("GST OFFSET 0x%x\n",
896 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
897 PM8001_INIT_DBG(pm8001_ha,
898 pm8001_printk("INBND OFFSET 0x%x\n",
899 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
900 PM8001_INIT_DBG(pm8001_ha,
901 pm8001_printk("OBND OFFSET 0x%x\n",
902 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
903 PM8001_INIT_DBG(pm8001_ha,
904 pm8001_printk("IVT OFFSET 0x%x\n",
905 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
906 PM8001_INIT_DBG(pm8001_ha,
907 pm8001_printk("PSPA OFFSET 0x%x\n",
908 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
909 PM8001_INIT_DBG(pm8001_ha,
910 pm8001_printk("addr - main cfg %p general status %p\n",
911 pm8001_ha->main_cfg_tbl_addr,
912 pm8001_ha->general_stat_tbl_addr));
913 PM8001_INIT_DBG(pm8001_ha,
914 pm8001_printk("addr - inbnd %p obnd %p\n",
915 pm8001_ha->inbnd_q_tbl_addr,
916 pm8001_ha->outbnd_q_tbl_addr));
917 PM8001_INIT_DBG(pm8001_ha,
918 pm8001_printk("addr - pspa %p ivt %p\n",
919 pm8001_ha->pspa_q_tbl_addr,
920 pm8001_ha->ivt_tbl_addr));
921}
922
923/**
924 * pm80xx_set_thermal_config - support the thermal configuration
925 * @pm8001_ha: our hba card information.
926 */
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]927int
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]928pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
929{
930 struct set_ctrl_cfg_req payload;
931 struct inbound_queue_table *circularQ;
932 int rc;
933 u32 tag;
934 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]935 u32 page_code;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]936
937 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
938 rc = pm8001_tag_alloc(pm8001_ha, &tag);
939 if (rc)
940 return -1;
941
942 circularQ = &pm8001_ha->inbnd_q_tbl[0];
943 payload.tag = cpu_to_le32(tag);
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]944
945 if (IS_SPCV_12G(pm8001_ha->pdev))
946 page_code = THERMAL_PAGE_CODE_7H;
947 else
948 page_code = THERMAL_PAGE_CODE_8H;
949
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]950 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]951 (THERMAL_ENABLE << 8) | page_code;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]952 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
953
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]954 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
955 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
956 payload.cfg_pg[0], payload.cfg_pg[1]));
957
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]958 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]959 if (rc)
960 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]961 return rc;
962
963}
964
965/**
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]966* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
967* Timer configuration page
968* @pm8001_ha: our hba card information.
969*/
970static int
971pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
972{
973 struct set_ctrl_cfg_req payload;
974 struct inbound_queue_table *circularQ;
975 SASProtocolTimerConfig_t SASConfigPage;
976 int rc;
977 u32 tag;
978 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
979
980 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
981 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
982
983 rc = pm8001_tag_alloc(pm8001_ha, &tag);
984
985 if (rc)
986 return -1;
987
988 circularQ = &pm8001_ha->inbnd_q_tbl[0];
989 payload.tag = cpu_to_le32(tag);
990
991 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
992 SASConfigPage.MST_MSI = 3 << 15;
993 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
994 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
995 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
996 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
997
998 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
999 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1000
1001
1002 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1003 SAS_OPNRJT_RTRY_INTVL;
1004 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1005 | SAS_COPNRJT_RTRY_TMO;
1006 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1007 | SAS_COPNRJT_RTRY_THR;
1008 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1009
1010 PM8001_INIT_DBG(pm8001_ha,
1011 pm8001_printk("SASConfigPage.pageCode "
1012 "0x%08x\n", SASConfigPage.pageCode));
1013 PM8001_INIT_DBG(pm8001_ha,
1014 pm8001_printk("SASConfigPage.MST_MSI "
1015 " 0x%08x\n", SASConfigPage.MST_MSI));
1016 PM8001_INIT_DBG(pm8001_ha,
1017 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1018 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1019 PM8001_INIT_DBG(pm8001_ha,
1020 pm8001_printk("SASConfigPage.STP_FRM_TMO "
1021 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1022 PM8001_INIT_DBG(pm8001_ha,
1023 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1024 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1025 PM8001_INIT_DBG(pm8001_ha,
1026 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1027 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1028 PM8001_INIT_DBG(pm8001_ha,
1029 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1030 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1033 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1034 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1035 " 0x%08x\n", SASConfigPage.MAX_AIP));
1036
1037 memcpy(&payload.cfg_pg, &SASConfigPage,
1038 sizeof(SASProtocolTimerConfig_t));
1039
1040 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1041 if (rc)
1042 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1043
1044 return rc;
1045}
1046
1047/**
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1048 * pm80xx_get_encrypt_info - Check for encryption
1049 * @pm8001_ha: our hba card information.
1050 */
1051static int
1052pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1053{
1054 u32 scratch3_value;
Rickard Strandqvistda225492014-07-09 17:20:10 +0530[diff] [blame]1055 int ret = -1;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1056
1057 /* Read encryption status from SCRATCH PAD 3 */
1058 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1059
1060 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1061 SCRATCH_PAD3_ENC_READY) {
1062 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1063 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1064 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1065 SCRATCH_PAD3_SMF_ENABLED)
1066 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1067 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1068 SCRATCH_PAD3_SMA_ENABLED)
1069 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1070 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1071 SCRATCH_PAD3_SMB_ENABLED)
1072 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1073 pm8001_ha->encrypt_info.status = 0;
1074 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1075 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1076 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1077 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1078 pm8001_ha->encrypt_info.sec_mode,
1079 pm8001_ha->encrypt_info.status));
1080 ret = 0;
1081 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1082 SCRATCH_PAD3_ENC_DISABLED) {
1083 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1084 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1085 scratch3_value));
1086 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1087 pm8001_ha->encrypt_info.cipher_mode = 0;
1088 pm8001_ha->encrypt_info.sec_mode = 0;
Rickard Strandqvistda225492014-07-09 17:20:10 +0530[diff] [blame]1089 ret = 0;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1090 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1091 SCRATCH_PAD3_ENC_DIS_ERR) {
1092 pm8001_ha->encrypt_info.status =
1093 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1094 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1095 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1096 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1097 SCRATCH_PAD3_SMF_ENABLED)
1098 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1099 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1100 SCRATCH_PAD3_SMA_ENABLED)
1101 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1102 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1103 SCRATCH_PAD3_SMB_ENABLED)
1104 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1105 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1106 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1107 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1108 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1109 pm8001_ha->encrypt_info.sec_mode,
1110 pm8001_ha->encrypt_info.status));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1111 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1112 SCRATCH_PAD3_ENC_ENA_ERR) {
1113
1114 pm8001_ha->encrypt_info.status =
1115 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1116 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1117 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1118 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1119 SCRATCH_PAD3_SMF_ENABLED)
1120 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1121 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1122 SCRATCH_PAD3_SMA_ENABLED)
1123 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1124 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1125 SCRATCH_PAD3_SMB_ENABLED)
1126 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1127
1128 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1129 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1130 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1131 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1132 pm8001_ha->encrypt_info.sec_mode,
1133 pm8001_ha->encrypt_info.status));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1134 }
1135 return ret;
1136}
1137
1138/**
1139 * pm80xx_encrypt_update - update flash with encryption informtion
1140 * @pm8001_ha: our hba card information.
1141 */
1142static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1143{
1144 struct kek_mgmt_req payload;
1145 struct inbound_queue_table *circularQ;
1146 int rc;
1147 u32 tag;
1148 u32 opc = OPC_INB_KEK_MANAGEMENT;
1149
1150 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1151 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1152 if (rc)
1153 return -1;
1154
1155 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1156 payload.tag = cpu_to_le32(tag);
1157 /* Currently only one key is used. New KEK index is 1.
1158 * Current KEK index is 1. Store KEK to NVRAM is 1.
1159 */
1160 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1161 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1162
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1163 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1164 "Saving Encryption info to flash. payload 0x%x\n",
1165 payload.new_curidx_ksop));
1166
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1167 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1168 if (rc)
1169 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1170
1171 return rc;
1172}
1173
1174/**
1175 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1176 * @pm8001_ha: our hba card information
1177 */
1178static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1179{
1180 int ret;
1181 u8 i = 0;
1182
1183 /* check the firmware status */
1184 if (-1 == check_fw_ready(pm8001_ha)) {
1185 PM8001_FAIL_DBG(pm8001_ha,
1186 pm8001_printk("Firmware is not ready!\n"));
1187 return -EBUSY;
1188 }
1189
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]1190 /* Initialize the controller fatal error flag */
1191 pm8001_ha->controller_fatal_error = false;
1192
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1193 /* Initialize pci space address eg: mpi offset */
1194 init_pci_device_addresses(pm8001_ha);
1195 init_default_table_values(pm8001_ha);
1196 read_main_config_table(pm8001_ha);
1197 read_general_status_table(pm8001_ha);
1198 read_inbnd_queue_table(pm8001_ha);
1199 read_outbnd_queue_table(pm8001_ha);
1200 read_phy_attr_table(pm8001_ha);
1201
1202 /* update main config table ,inbound table and outbound table */
1203 update_main_config_table(pm8001_ha);
1204 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1205 update_inbnd_queue_table(pm8001_ha, i);
1206 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1207 update_outbnd_queue_table(pm8001_ha, i);
1208
1209 /* notify firmware update finished and check initialization status */
1210 if (0 == mpi_init_check(pm8001_ha)) {
1211 PM8001_INIT_DBG(pm8001_ha,
1212 pm8001_printk("MPI initialize successful!\n"));
1213 } else
1214 return -EBUSY;
1215
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1216 /* send SAS protocol timer configuration page to FW */
1217 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1218
1219 /* Check for encryption */
1220 if (pm8001_ha->chip->encrypt) {
1221 PM8001_INIT_DBG(pm8001_ha,
1222 pm8001_printk("Checking for encryption\n"));
1223 ret = pm80xx_get_encrypt_info(pm8001_ha);
1224 if (ret == -1) {
1225 PM8001_INIT_DBG(pm8001_ha,
1226 pm8001_printk("Encryption error !!\n"));
1227 if (pm8001_ha->encrypt_info.status == 0x81) {
1228 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1229 "Encryption enabled with error."
1230 "Saving encryption key to flash\n"));
1231 pm80xx_encrypt_update(pm8001_ha);
1232 }
1233 }
1234 }
1235 return 0;
1236}
1237
1238static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1239{
1240 u32 max_wait_count;
1241 u32 value;
1242 u32 gst_len_mpistate;
1243 init_pci_device_addresses(pm8001_ha);
1244 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1245 table is stop */
1246 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1247
1248 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]1249 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1250 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1251 } else {
1252 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1253 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1254 do {
1255 udelay(1);
1256 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1257 value &= SPCv_MSGU_CFG_TABLE_RESET;
1258 } while ((value != 0) && (--max_wait_count));
1259
1260 if (!max_wait_count) {
1261 PM8001_FAIL_DBG(pm8001_ha,
1262 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1263 return -1;
1264 }
1265
1266 /* check the MPI-State for termination in progress */
1267 /* wait until Inbound DoorBell Clear Register toggled */
1268 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1269 do {
1270 udelay(1);
1271 gst_len_mpistate =
1272 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1273 GST_GSTLEN_MPIS_OFFSET);
1274 if (GST_MPI_STATE_UNINIT ==
1275 (gst_len_mpistate & GST_MPI_STATE_MASK))
1276 break;
1277 } while (--max_wait_count);
1278 if (!max_wait_count) {
1279 PM8001_FAIL_DBG(pm8001_ha,
1280 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1281 gst_len_mpistate & GST_MPI_STATE_MASK));
1282 return -1;
1283 }
1284
1285 return 0;
1286}
1287
1288/**
1289 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1290 * the FW register status to the originated status.
1291 * @pm8001_ha: our hba card information
1292 */
1293
1294static int
1295pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1296{
1297 u32 regval;
1298 u32 bootloader_state;
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1299 u32 ibutton0, ibutton1;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1300
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]1301 /* Process MPI table uninitialization only if FW is ready */
1302 if (!pm8001_ha->controller_fatal_error) {
1303 /* Check if MPI is in ready state to reset */
1304 if (mpi_uninit_check(pm8001_ha) != 0) {
1305 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1306 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1307 "MPI state is not ready scratch1 :0x%x\n",
1308 regval));
1309 return -1;
1310 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1311 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1312 /* checked for reset register normal state; 0x0 */
1313 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1314 PM8001_INIT_DBG(pm8001_ha,
1315 pm8001_printk("reset register before write : 0x%x\n", regval));
1316
1317 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
Vikram Auradkar4daf1ef2019-11-14 15:39:01 +0530[diff] [blame]1318 msleep(500);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1319
1320 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1321 PM8001_INIT_DBG(pm8001_ha,
1322 pm8001_printk("reset register after write 0x%x\n", regval));
1323
1324 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1325 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1326 PM8001_MSG_DBG(pm8001_ha,
1327 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1328 regval));
1329 } else {
1330 PM8001_MSG_DBG(pm8001_ha,
1331 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1332 regval));
1333
1334 /* check bootloader is successfully executed or in HDA mode */
1335 bootloader_state =
1336 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1337 SCRATCH_PAD1_BOOTSTATE_MASK;
1338
1339 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1340 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1341 "Bootloader state - HDA mode SEEPROM\n"));
1342 } else if (bootloader_state ==
1343 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1344 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1345 "Bootloader state - HDA mode Bootstrap Pin\n"));
1346 } else if (bootloader_state ==
1347 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1348 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1349 "Bootloader state - HDA mode soft reset\n"));
1350 } else if (bootloader_state ==
1351 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1352 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1353 "Bootloader state-HDA mode critical error\n"));
1354 }
1355 return -EBUSY;
1356 }
1357
1358 /* check the firmware status after reset */
1359 if (-1 == check_fw_ready(pm8001_ha)) {
1360 PM8001_FAIL_DBG(pm8001_ha,
1361 pm8001_printk("Firmware is not ready!\n"));
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1362 /* check iButton feature support for motherboard controller */
1363 if (pm8001_ha->pdev->subsystem_vendor !=
1364 PCI_VENDOR_ID_ADAPTEC2 &&
Benjamin Roodfaf321b2015-10-30 10:53:29 -0400[diff] [blame]1365 pm8001_ha->pdev->subsystem_vendor !=
1366 PCI_VENDOR_ID_ATTO &&
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1367 pm8001_ha->pdev->subsystem_vendor != 0) {
1368 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1369 MSGU_HOST_SCRATCH_PAD_6);
1370 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1371 MSGU_HOST_SCRATCH_PAD_7);
1372 if (!ibutton0 && !ibutton1) {
1373 PM8001_FAIL_DBG(pm8001_ha,
1374 pm8001_printk("iButton Feature is"
1375 " not Available!!!\n"));
1376 return -EBUSY;
1377 }
1378 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1379 PM8001_FAIL_DBG(pm8001_ha,
1380 pm8001_printk("CRC Check for iButton"
1381 " Feature Failed!!!\n"));
1382 return -EBUSY;
1383 }
1384 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1385 }
1386 PM8001_INIT_DBG(pm8001_ha,
1387 pm8001_printk("SPCv soft reset Complete\n"));
1388 return 0;
1389}
1390
1391static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1392{
Colin Ian King9e2a07e2019-03-17 18:15:32 +0000[diff] [blame]1393 u32 i;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1394
1395 PM8001_INIT_DBG(pm8001_ha,
1396 pm8001_printk("chip reset start\n"));
1397
1398 /* do SPCv chip reset. */
1399 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1400 PM8001_INIT_DBG(pm8001_ha,
1401 pm8001_printk("SPC soft reset Complete\n"));
1402
1403 /* Check this ..whether delay is required or no */
1404 /* delay 10 usec */
1405 udelay(10);
1406
1407 /* wait for 20 msec until the firmware gets reloaded */
1408 i = 20;
1409 do {
1410 mdelay(1);
1411 } while ((--i) != 0);
1412
1413 PM8001_INIT_DBG(pm8001_ha,
1414 pm8001_printk("chip reset finished\n"));
1415}
1416
1417/**
1418 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1419 * @pm8001_ha: our hba card information
1420 */
1421static void
1422pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1423{
1424 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1425 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1426}
1427
1428/**
1429 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1430 * @pm8001_ha: our hba card information
1431 */
1432static void
1433pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1434{
1435 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1436}
1437
1438/**
1439 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1440 * @pm8001_ha: our hba card information
1441 */
1442static void
1443pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1444{
1445#ifdef PM8001_USE_MSIX
1446 u32 mask;
1447 mask = (u32)(1 << vec);
1448
1449 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1450 return;
1451#endif
1452 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1453
1454}
1455
1456/**
1457 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1458 * @pm8001_ha: our hba card information
1459 */
1460static void
1461pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1462{
1463#ifdef PM8001_USE_MSIX
1464 u32 mask;
1465 if (vec == 0xFF)
1466 mask = 0xFFFFFFFF;
1467 else
1468 mask = (u32)(1 << vec);
1469 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1470 return;
1471#endif
1472 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1473}
1474
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1475static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1476 struct pm8001_device *pm8001_ha_dev)
1477{
1478 int res;
1479 u32 ccb_tag;
1480 struct pm8001_ccb_info *ccb;
1481 struct sas_task *task = NULL;
1482 struct task_abort_req task_abort;
1483 struct inbound_queue_table *circularQ;
1484 u32 opc = OPC_INB_SATA_ABORT;
1485 int ret;
1486
1487 if (!pm8001_ha_dev) {
1488 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1489 return;
1490 }
1491
1492 task = sas_alloc_slow_task(GFP_ATOMIC);
1493
1494 if (!task) {
1495 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1496 "allocate task\n"));
1497 return;
1498 }
1499
1500 task->task_done = pm8001_task_done;
1501
1502 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1503 if (res) {
1504 sas_free_task(task);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1505 return;
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1506 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1507
1508 ccb = &pm8001_ha->ccb_info[ccb_tag];
1509 ccb->device = pm8001_ha_dev;
1510 ccb->ccb_tag = ccb_tag;
1511 ccb->task = task;
1512
1513 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1514
1515 memset(&task_abort, 0, sizeof(task_abort));
1516 task_abort.abort_all = cpu_to_le32(1);
1517 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1518 task_abort.tag = cpu_to_le32(ccb_tag);
1519
1520 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1521 if (ret) {
1522 sas_free_task(task);
1523 pm8001_tag_free(pm8001_ha, ccb_tag);
1524 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1525}
1526
1527static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1528 struct pm8001_device *pm8001_ha_dev)
1529{
1530 struct sata_start_req sata_cmd;
1531 int res;
1532 u32 ccb_tag;
1533 struct pm8001_ccb_info *ccb;
1534 struct sas_task *task = NULL;
1535 struct host_to_dev_fis fis;
1536 struct domain_device *dev;
1537 struct inbound_queue_table *circularQ;
1538 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1539
1540 task = sas_alloc_slow_task(GFP_ATOMIC);
1541
1542 if (!task) {
1543 PM8001_FAIL_DBG(pm8001_ha,
1544 pm8001_printk("cannot allocate task !!!\n"));
1545 return;
1546 }
1547 task->task_done = pm8001_task_done;
1548
1549 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1550 if (res) {
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1551 sas_free_task(task);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1552 PM8001_FAIL_DBG(pm8001_ha,
1553 pm8001_printk("cannot allocate tag !!!\n"));
1554 return;
1555 }
1556
1557 /* allocate domain device by ourselves as libsas
1558 * is not going to provide any
1559 */
1560 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1561 if (!dev) {
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1562 sas_free_task(task);
1563 pm8001_tag_free(pm8001_ha, ccb_tag);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1564 PM8001_FAIL_DBG(pm8001_ha,
1565 pm8001_printk("Domain device cannot be allocated\n"));
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1566 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1567 }
1568
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1569 task->dev = dev;
1570 task->dev->lldd_dev = pm8001_ha_dev;
1571
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1572 ccb = &pm8001_ha->ccb_info[ccb_tag];
1573 ccb->device = pm8001_ha_dev;
1574 ccb->ccb_tag = ccb_tag;
1575 ccb->task = task;
Viswas G0b6df112017-10-18 11:39:14 +0530[diff] [blame]1576 ccb->n_elem = 0;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1577 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1578 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1579
1580 memset(&sata_cmd, 0, sizeof(sata_cmd));
1581 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1582
1583 /* construct read log FIS */
1584 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1585 fis.fis_type = 0x27;
1586 fis.flags = 0x80;
1587 fis.command = ATA_CMD_READ_LOG_EXT;
1588 fis.lbal = 0x10;
1589 fis.sector_count = 0x1;
1590
1591 sata_cmd.tag = cpu_to_le32(ccb_tag);
1592 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1593 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1594 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1595
1596 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1597 if (res) {
1598 sas_free_task(task);
1599 pm8001_tag_free(pm8001_ha, ccb_tag);
1600 kfree(dev);
1601 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1602}
1603
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1604/**
1605 * mpi_ssp_completion- process the event that FW response to the SSP request.
1606 * @pm8001_ha: our hba card information
1607 * @piomb: the message contents of this outbound message.
1608 *
1609 * When FW has completed a ssp request for example a IO request, after it has
1610 * filled the SG data with the data, it will trigger this event represent
1611 * that he has finished the job,please check the coresponding buffer.
1612 * So we will tell the caller who maybe waiting the result to tell upper layer
1613 * that the task has been finished.
1614 */
1615static void
1616mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1617{
1618 struct sas_task *t;
1619 struct pm8001_ccb_info *ccb;
1620 unsigned long flags;
1621 u32 status;
1622 u32 param;
1623 u32 tag;
1624 struct ssp_completion_resp *psspPayload;
1625 struct task_status_struct *ts;
1626 struct ssp_response_iu *iu;
1627 struct pm8001_device *pm8001_dev;
1628 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1629 status = le32_to_cpu(psspPayload->status);
1630 tag = le32_to_cpu(psspPayload->tag);
1631 ccb = &pm8001_ha->ccb_info[tag];
1632 if ((status == IO_ABORTED) && ccb->open_retry) {
1633 /* Being completed by another */
1634 ccb->open_retry = 0;
1635 return;
1636 }
1637 pm8001_dev = ccb->device;
1638 param = le32_to_cpu(psspPayload->param);
1639 t = ccb->task;
1640
1641 if (status && status != IO_UNDERFLOW)
1642 PM8001_FAIL_DBG(pm8001_ha,
1643 pm8001_printk("sas IO status 0x%x\n", status));
1644 if (unlikely(!t || !t->lldd_task || !t->dev))
1645 return;
1646 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1647
1648 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1649 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1650
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]1651 /* Print sas address of IO failed device */
1652 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1653 (status != IO_UNDERFLOW))
1654 PM8001_FAIL_DBG(pm8001_ha,
1655 pm8001_printk("SAS Address of IO Failure Drive"
1656 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1657
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1658 switch (status) {
1659 case IO_SUCCESS:
1660 PM8001_IO_DBG(pm8001_ha,
1661 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1662 param));
1663 if (param == 0) {
1664 ts->resp = SAS_TASK_COMPLETE;
1665 ts->stat = SAM_STAT_GOOD;
1666 } else {
1667 ts->resp = SAS_TASK_COMPLETE;
1668 ts->stat = SAS_PROTO_RESPONSE;
1669 ts->residual = param;
1670 iu = &psspPayload->ssp_resp_iu;
1671 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1672 }
1673 if (pm8001_dev)
1674 pm8001_dev->running_req--;
1675 break;
1676 case IO_ABORTED:
1677 PM8001_IO_DBG(pm8001_ha,
1678 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1679 ts->resp = SAS_TASK_COMPLETE;
1680 ts->stat = SAS_ABORTED_TASK;
1681 break;
1682 case IO_UNDERFLOW:
1683 /* SSP Completion with error */
1684 PM8001_IO_DBG(pm8001_ha,
1685 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1686 param));
1687 ts->resp = SAS_TASK_COMPLETE;
1688 ts->stat = SAS_DATA_UNDERRUN;
1689 ts->residual = param;
1690 if (pm8001_dev)
1691 pm8001_dev->running_req--;
1692 break;
1693 case IO_NO_DEVICE:
1694 PM8001_IO_DBG(pm8001_ha,
1695 pm8001_printk("IO_NO_DEVICE\n"));
1696 ts->resp = SAS_TASK_UNDELIVERED;
1697 ts->stat = SAS_PHY_DOWN;
1698 break;
1699 case IO_XFER_ERROR_BREAK:
1700 PM8001_IO_DBG(pm8001_ha,
1701 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1702 ts->resp = SAS_TASK_COMPLETE;
1703 ts->stat = SAS_OPEN_REJECT;
1704 /* Force the midlayer to retry */
1705 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1706 break;
1707 case IO_XFER_ERROR_PHY_NOT_READY:
1708 PM8001_IO_DBG(pm8001_ha,
1709 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1710 ts->resp = SAS_TASK_COMPLETE;
1711 ts->stat = SAS_OPEN_REJECT;
1712 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1713 break;
Viswas G27ecfa52015-08-11 15:06:31 +0530[diff] [blame]1714 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1715 PM8001_IO_DBG(pm8001_ha,
1716 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1717 ts->resp = SAS_TASK_COMPLETE;
1718 ts->stat = SAS_OPEN_REJECT;
1719 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1720 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1721 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1722 PM8001_IO_DBG(pm8001_ha,
1723 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1724 ts->resp = SAS_TASK_COMPLETE;
1725 ts->stat = SAS_OPEN_REJECT;
1726 ts->open_rej_reason = SAS_OREJ_EPROTO;
1727 break;
1728 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1729 PM8001_IO_DBG(pm8001_ha,
1730 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1731 ts->resp = SAS_TASK_COMPLETE;
1732 ts->stat = SAS_OPEN_REJECT;
1733 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1734 break;
1735 case IO_OPEN_CNX_ERROR_BREAK:
1736 PM8001_IO_DBG(pm8001_ha,
1737 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1738 ts->resp = SAS_TASK_COMPLETE;
1739 ts->stat = SAS_OPEN_REJECT;
1740 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1741 break;
1742 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1743 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1744 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1745 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1746 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1747 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1748 PM8001_IO_DBG(pm8001_ha,
1749 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1750 ts->resp = SAS_TASK_COMPLETE;
1751 ts->stat = SAS_OPEN_REJECT;
1752 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1753 if (!t->uldd_task)
1754 pm8001_handle_event(pm8001_ha,
1755 pm8001_dev,
1756 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1757 break;
1758 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1759 PM8001_IO_DBG(pm8001_ha,
1760 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1761 ts->resp = SAS_TASK_COMPLETE;
1762 ts->stat = SAS_OPEN_REJECT;
1763 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1764 break;
1765 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1766 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1767 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1768 ts->resp = SAS_TASK_COMPLETE;
1769 ts->stat = SAS_OPEN_REJECT;
1770 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1771 break;
1772 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1773 PM8001_IO_DBG(pm8001_ha,
1774 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1775 ts->resp = SAS_TASK_UNDELIVERED;
1776 ts->stat = SAS_OPEN_REJECT;
1777 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1778 break;
1779 case IO_XFER_ERROR_NAK_RECEIVED:
1780 PM8001_IO_DBG(pm8001_ha,
1781 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1782 ts->resp = SAS_TASK_COMPLETE;
1783 ts->stat = SAS_OPEN_REJECT;
1784 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1785 break;
1786 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1787 PM8001_IO_DBG(pm8001_ha,
1788 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1789 ts->resp = SAS_TASK_COMPLETE;
1790 ts->stat = SAS_NAK_R_ERR;
1791 break;
1792 case IO_XFER_ERROR_DMA:
1793 PM8001_IO_DBG(pm8001_ha,
1794 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1795 ts->resp = SAS_TASK_COMPLETE;
1796 ts->stat = SAS_OPEN_REJECT;
1797 break;
1798 case IO_XFER_OPEN_RETRY_TIMEOUT:
1799 PM8001_IO_DBG(pm8001_ha,
1800 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1801 ts->resp = SAS_TASK_COMPLETE;
1802 ts->stat = SAS_OPEN_REJECT;
1803 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1804 break;
1805 case IO_XFER_ERROR_OFFSET_MISMATCH:
1806 PM8001_IO_DBG(pm8001_ha,
1807 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1808 ts->resp = SAS_TASK_COMPLETE;
1809 ts->stat = SAS_OPEN_REJECT;
1810 break;
1811 case IO_PORT_IN_RESET:
1812 PM8001_IO_DBG(pm8001_ha,
1813 pm8001_printk("IO_PORT_IN_RESET\n"));
1814 ts->resp = SAS_TASK_COMPLETE;
1815 ts->stat = SAS_OPEN_REJECT;
1816 break;
1817 case IO_DS_NON_OPERATIONAL:
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1820 ts->resp = SAS_TASK_COMPLETE;
1821 ts->stat = SAS_OPEN_REJECT;
1822 if (!t->uldd_task)
1823 pm8001_handle_event(pm8001_ha,
1824 pm8001_dev,
1825 IO_DS_NON_OPERATIONAL);
1826 break;
1827 case IO_DS_IN_RECOVERY:
1828 PM8001_IO_DBG(pm8001_ha,
1829 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1830 ts->resp = SAS_TASK_COMPLETE;
1831 ts->stat = SAS_OPEN_REJECT;
1832 break;
1833 case IO_TM_TAG_NOT_FOUND:
1834 PM8001_IO_DBG(pm8001_ha,
1835 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_OPEN_REJECT;
1838 break;
1839 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1840 PM8001_IO_DBG(pm8001_ha,
1841 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1842 ts->resp = SAS_TASK_COMPLETE;
1843 ts->stat = SAS_OPEN_REJECT;
1844 break;
1845 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1846 PM8001_IO_DBG(pm8001_ha,
1847 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1848 ts->resp = SAS_TASK_COMPLETE;
1849 ts->stat = SAS_OPEN_REJECT;
1850 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1851 break;
1852 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1853 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1854 pm8001_printk("Unknown status 0x%x\n", status));
1855 /* not allowed case. Therefore, return failed status */
1856 ts->resp = SAS_TASK_COMPLETE;
1857 ts->stat = SAS_OPEN_REJECT;
1858 break;
1859 }
1860 PM8001_IO_DBG(pm8001_ha,
1861 pm8001_printk("scsi_status = 0x%x\n ",
1862 psspPayload->ssp_resp_iu.status));
1863 spin_lock_irqsave(&t->task_state_lock, flags);
1864 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1865 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1866 t->task_state_flags |= SAS_TASK_STATE_DONE;
1867 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1868 spin_unlock_irqrestore(&t->task_state_lock, flags);
1869 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1870 "task 0x%p done with io_status 0x%x resp 0x%x "
1871 "stat 0x%x but aborted by upper layer!\n",
1872 t, status, ts->resp, ts->stat));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]1873 if (t->slow_task)
1874 complete(&t->slow_task->completion);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1875 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1876 } else {
1877 spin_unlock_irqrestore(&t->task_state_lock, flags);
1878 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1879 mb();/* in order to force CPU ordering */
1880 t->task_done(t);
1881 }
1882}
1883
1884/*See the comments for mpi_ssp_completion */
1885static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1886{
1887 struct sas_task *t;
1888 unsigned long flags;
1889 struct task_status_struct *ts;
1890 struct pm8001_ccb_info *ccb;
1891 struct pm8001_device *pm8001_dev;
1892 struct ssp_event_resp *psspPayload =
1893 (struct ssp_event_resp *)(piomb + 4);
1894 u32 event = le32_to_cpu(psspPayload->event);
1895 u32 tag = le32_to_cpu(psspPayload->tag);
1896 u32 port_id = le32_to_cpu(psspPayload->port_id);
1897
1898 ccb = &pm8001_ha->ccb_info[tag];
1899 t = ccb->task;
1900 pm8001_dev = ccb->device;
1901 if (event)
1902 PM8001_FAIL_DBG(pm8001_ha,
1903 pm8001_printk("sas IO status 0x%x\n", event));
1904 if (unlikely(!t || !t->lldd_task || !t->dev))
1905 return;
1906 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1907 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1908 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1909 port_id, tag, event));
1910 switch (event) {
1911 case IO_OVERFLOW:
1912 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1913 ts->resp = SAS_TASK_COMPLETE;
1914 ts->stat = SAS_DATA_OVERRUN;
1915 ts->residual = 0;
1916 if (pm8001_dev)
1917 pm8001_dev->running_req--;
1918 break;
1919 case IO_XFER_ERROR_BREAK:
1920 PM8001_IO_DBG(pm8001_ha,
1921 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1922 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1923 return;
1924 case IO_XFER_ERROR_PHY_NOT_READY:
1925 PM8001_IO_DBG(pm8001_ha,
1926 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1927 ts->resp = SAS_TASK_COMPLETE;
1928 ts->stat = SAS_OPEN_REJECT;
1929 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1930 break;
1931 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1932 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1933 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1934 ts->resp = SAS_TASK_COMPLETE;
1935 ts->stat = SAS_OPEN_REJECT;
1936 ts->open_rej_reason = SAS_OREJ_EPROTO;
1937 break;
1938 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1939 PM8001_IO_DBG(pm8001_ha,
1940 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1941 ts->resp = SAS_TASK_COMPLETE;
1942 ts->stat = SAS_OPEN_REJECT;
1943 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1944 break;
1945 case IO_OPEN_CNX_ERROR_BREAK:
1946 PM8001_IO_DBG(pm8001_ha,
1947 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1948 ts->resp = SAS_TASK_COMPLETE;
1949 ts->stat = SAS_OPEN_REJECT;
1950 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1951 break;
1952 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1953 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1954 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1955 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1956 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1957 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1958 PM8001_IO_DBG(pm8001_ha,
1959 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1960 ts->resp = SAS_TASK_COMPLETE;
1961 ts->stat = SAS_OPEN_REJECT;
1962 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1963 if (!t->uldd_task)
1964 pm8001_handle_event(pm8001_ha,
1965 pm8001_dev,
1966 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1967 break;
1968 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1969 PM8001_IO_DBG(pm8001_ha,
1970 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1971 ts->resp = SAS_TASK_COMPLETE;
1972 ts->stat = SAS_OPEN_REJECT;
1973 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1974 break;
1975 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1976 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1977 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1978 ts->resp = SAS_TASK_COMPLETE;
1979 ts->stat = SAS_OPEN_REJECT;
1980 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1981 break;
1982 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1983 PM8001_IO_DBG(pm8001_ha,
1984 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1985 ts->resp = SAS_TASK_COMPLETE;
1986 ts->stat = SAS_OPEN_REJECT;
1987 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1988 break;
1989 case IO_XFER_ERROR_NAK_RECEIVED:
1990 PM8001_IO_DBG(pm8001_ha,
1991 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1992 ts->resp = SAS_TASK_COMPLETE;
1993 ts->stat = SAS_OPEN_REJECT;
1994 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1995 break;
1996 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1997 PM8001_IO_DBG(pm8001_ha,
1998 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1999 ts->resp = SAS_TASK_COMPLETE;
2000 ts->stat = SAS_NAK_R_ERR;
2001 break;
2002 case IO_XFER_OPEN_RETRY_TIMEOUT:
2003 PM8001_IO_DBG(pm8001_ha,
2004 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2005 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2006 return;
2007 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2008 PM8001_IO_DBG(pm8001_ha,
2009 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2010 ts->resp = SAS_TASK_COMPLETE;
2011 ts->stat = SAS_DATA_OVERRUN;
2012 break;
2013 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2014 PM8001_IO_DBG(pm8001_ha,
2015 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2016 ts->resp = SAS_TASK_COMPLETE;
2017 ts->stat = SAS_DATA_OVERRUN;
2018 break;
2019 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2020 PM8001_IO_DBG(pm8001_ha,
2021 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2022 ts->resp = SAS_TASK_COMPLETE;
2023 ts->stat = SAS_DATA_OVERRUN;
2024 break;
2025 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2026 PM8001_IO_DBG(pm8001_ha,
2027 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2028 ts->resp = SAS_TASK_COMPLETE;
2029 ts->stat = SAS_DATA_OVERRUN;
2030 break;
2031 case IO_XFER_ERROR_OFFSET_MISMATCH:
2032 PM8001_IO_DBG(pm8001_ha,
2033 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2034 ts->resp = SAS_TASK_COMPLETE;
2035 ts->stat = SAS_DATA_OVERRUN;
2036 break;
2037 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2038 PM8001_IO_DBG(pm8001_ha,
2039 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2040 ts->resp = SAS_TASK_COMPLETE;
2041 ts->stat = SAS_DATA_OVERRUN;
2042 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2043 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2044 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2045 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2046 /* TBC: used default set values */
2047 ts->resp = SAS_TASK_COMPLETE;
2048 ts->stat = SAS_DATA_OVERRUN;
2049 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2050 case IO_XFER_CMD_FRAME_ISSUED:
2051 PM8001_IO_DBG(pm8001_ha,
2052 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2053 return;
2054 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2055 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2056 pm8001_printk("Unknown status 0x%x\n", event));
2057 /* not allowed case. Therefore, return failed status */
2058 ts->resp = SAS_TASK_COMPLETE;
2059 ts->stat = SAS_DATA_OVERRUN;
2060 break;
2061 }
2062 spin_lock_irqsave(&t->task_state_lock, flags);
2063 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2064 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2065 t->task_state_flags |= SAS_TASK_STATE_DONE;
2066 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2067 spin_unlock_irqrestore(&t->task_state_lock, flags);
2068 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2069 "task 0x%p done with event 0x%x resp 0x%x "
2070 "stat 0x%x but aborted by upper layer!\n",
2071 t, event, ts->resp, ts->stat));
2072 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2073 } else {
2074 spin_unlock_irqrestore(&t->task_state_lock, flags);
2075 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2076 mb();/* in order to force CPU ordering */
2077 t->task_done(t);
2078 }
2079}
2080
2081/*See the comments for mpi_ssp_completion */
2082static void
2083mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2084{
2085 struct sas_task *t;
2086 struct pm8001_ccb_info *ccb;
2087 u32 param;
2088 u32 status;
2089 u32 tag;
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2090 int i, j;
2091 u8 sata_addr_low[4];
2092 u32 temp_sata_addr_low, temp_sata_addr_hi;
2093 u8 sata_addr_hi[4];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2094 struct sata_completion_resp *psataPayload;
2095 struct task_status_struct *ts;
2096 struct ata_task_resp *resp ;
2097 u32 *sata_resp;
2098 struct pm8001_device *pm8001_dev;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2099 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2100
2101 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2102 status = le32_to_cpu(psataPayload->status);
2103 tag = le32_to_cpu(psataPayload->tag);
2104
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2105 if (!tag) {
2106 PM8001_FAIL_DBG(pm8001_ha,
2107 pm8001_printk("tag null\n"));
2108 return;
2109 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2110 ccb = &pm8001_ha->ccb_info[tag];
2111 param = le32_to_cpu(psataPayload->param);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2112 if (ccb) {
2113 t = ccb->task;
2114 pm8001_dev = ccb->device;
2115 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2116 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2117 pm8001_printk("ccb null\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2118 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2119 }
2120
2121 if (t) {
2122 if (t->dev && (t->dev->lldd_dev))
2123 pm8001_dev = t->dev->lldd_dev;
2124 } else {
2125 PM8001_FAIL_DBG(pm8001_ha,
2126 pm8001_printk("task null\n"));
2127 return;
2128 }
2129
2130 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2131 && unlikely(!t || !t->lldd_task || !t->dev)) {
2132 PM8001_FAIL_DBG(pm8001_ha,
2133 pm8001_printk("task or dev null\n"));
2134 return;
2135 }
2136
2137 ts = &t->task_status;
2138 if (!ts) {
2139 PM8001_FAIL_DBG(pm8001_ha,
2140 pm8001_printk("ts null\n"));
2141 return;
2142 }
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2143
2144 if (unlikely(status))
2145 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2146 "status:0x%x, tag:0x%x, task::0x%p\n",
2147 status, tag, t));
2148
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2149 /* Print sas address of IO failed device */
2150 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2151 (status != IO_UNDERFLOW)) {
2152 if (!((t->dev->parent) &&
John Garry924a3542019-06-10 20:41:41 +0800[diff] [blame]2153 (dev_is_expander(t->dev->parent->dev_type)))) {
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2154 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2155 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2156 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2157 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2158 memcpy(&temp_sata_addr_low, sata_addr_low,
2159 sizeof(sata_addr_low));
2160 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2161 sizeof(sata_addr_hi));
2162 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2163 |((temp_sata_addr_hi << 8) &
2164 0xff0000) |
2165 ((temp_sata_addr_hi >> 8)
2166 & 0xff00) |
2167 ((temp_sata_addr_hi << 24) &
2168 0xff000000));
2169 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2170 & 0xff) |
2171 ((temp_sata_addr_low << 8)
2172 & 0xff0000) |
2173 ((temp_sata_addr_low >> 8)
2174 & 0xff00) |
2175 ((temp_sata_addr_low << 24)
2176 & 0xff000000)) +
2177 pm8001_dev->attached_phy +
2178 0x10);
2179 PM8001_FAIL_DBG(pm8001_ha,
2180 pm8001_printk("SAS Address of IO Failure Drive:"
2181 "%08x%08x", temp_sata_addr_hi,
2182 temp_sata_addr_low));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2183
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2184 } else {
2185 PM8001_FAIL_DBG(pm8001_ha,
2186 pm8001_printk("SAS Address of IO Failure Drive:"
2187 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2188 }
2189 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2190 switch (status) {
2191 case IO_SUCCESS:
2192 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2193 if (param == 0) {
2194 ts->resp = SAS_TASK_COMPLETE;
2195 ts->stat = SAM_STAT_GOOD;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2196 /* check if response is for SEND READ LOG */
2197 if (pm8001_dev &&
2198 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2199 /* set new bit for abort_all */
2200 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2201 /* clear bit for read log */
2202 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2203 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2204 /* Free the tag */
2205 pm8001_tag_free(pm8001_ha, tag);
2206 sas_free_task(t);
2207 return;
2208 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2209 } else {
2210 u8 len;
2211 ts->resp = SAS_TASK_COMPLETE;
2212 ts->stat = SAS_PROTO_RESPONSE;
2213 ts->residual = param;
2214 PM8001_IO_DBG(pm8001_ha,
2215 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2216 param));
2217 sata_resp = &psataPayload->sata_resp[0];
2218 resp = (struct ata_task_resp *)ts->buf;
2219 if (t->ata_task.dma_xfer == 0 &&
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]2220 t->data_dir == DMA_FROM_DEVICE) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2221 len = sizeof(struct pio_setup_fis);
2222 PM8001_IO_DBG(pm8001_ha,
2223 pm8001_printk("PIO read len = %d\n", len));
2224 } else if (t->ata_task.use_ncq) {
2225 len = sizeof(struct set_dev_bits_fis);
2226 PM8001_IO_DBG(pm8001_ha,
2227 pm8001_printk("FPDMA len = %d\n", len));
2228 } else {
2229 len = sizeof(struct dev_to_host_fis);
2230 PM8001_IO_DBG(pm8001_ha,
2231 pm8001_printk("other len = %d\n", len));
2232 }
2233 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2234 resp->frame_len = len;
2235 memcpy(&resp->ending_fis[0], sata_resp, len);
2236 ts->buf_valid_size = sizeof(*resp);
2237 } else
2238 PM8001_IO_DBG(pm8001_ha,
2239 pm8001_printk("response to large\n"));
2240 }
2241 if (pm8001_dev)
2242 pm8001_dev->running_req--;
2243 break;
2244 case IO_ABORTED:
2245 PM8001_IO_DBG(pm8001_ha,
2246 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2247 ts->resp = SAS_TASK_COMPLETE;
2248 ts->stat = SAS_ABORTED_TASK;
2249 if (pm8001_dev)
2250 pm8001_dev->running_req--;
2251 break;
2252 /* following cases are to do cases */
2253 case IO_UNDERFLOW:
2254 /* SATA Completion with error */
2255 PM8001_IO_DBG(pm8001_ha,
2256 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2257 ts->resp = SAS_TASK_COMPLETE;
2258 ts->stat = SAS_DATA_UNDERRUN;
2259 ts->residual = param;
2260 if (pm8001_dev)
2261 pm8001_dev->running_req--;
2262 break;
2263 case IO_NO_DEVICE:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_NO_DEVICE\n"));
2266 ts->resp = SAS_TASK_UNDELIVERED;
2267 ts->stat = SAS_PHY_DOWN;
2268 break;
2269 case IO_XFER_ERROR_BREAK:
2270 PM8001_IO_DBG(pm8001_ha,
2271 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2272 ts->resp = SAS_TASK_COMPLETE;
2273 ts->stat = SAS_INTERRUPTED;
2274 break;
2275 case IO_XFER_ERROR_PHY_NOT_READY:
2276 PM8001_IO_DBG(pm8001_ha,
2277 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2278 ts->resp = SAS_TASK_COMPLETE;
2279 ts->stat = SAS_OPEN_REJECT;
2280 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2281 break;
2282 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2283 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2284 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2285 ts->resp = SAS_TASK_COMPLETE;
2286 ts->stat = SAS_OPEN_REJECT;
2287 ts->open_rej_reason = SAS_OREJ_EPROTO;
2288 break;
2289 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2290 PM8001_IO_DBG(pm8001_ha,
2291 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2292 ts->resp = SAS_TASK_COMPLETE;
2293 ts->stat = SAS_OPEN_REJECT;
2294 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2295 break;
2296 case IO_OPEN_CNX_ERROR_BREAK:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_OPEN_REJECT;
2301 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2302 break;
2303 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2304 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2305 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2306 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2307 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2308 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2309 PM8001_IO_DBG(pm8001_ha,
2310 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2311 ts->resp = SAS_TASK_COMPLETE;
2312 ts->stat = SAS_DEV_NO_RESPONSE;
2313 if (!t->uldd_task) {
2314 pm8001_handle_event(pm8001_ha,
2315 pm8001_dev,
2316 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2317 ts->resp = SAS_TASK_UNDELIVERED;
2318 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2319 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2320 return;
2321 }
2322 break;
2323 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2324 PM8001_IO_DBG(pm8001_ha,
2325 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2326 ts->resp = SAS_TASK_UNDELIVERED;
2327 ts->stat = SAS_OPEN_REJECT;
2328 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2329 if (!t->uldd_task) {
2330 pm8001_handle_event(pm8001_ha,
2331 pm8001_dev,
2332 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2333 ts->resp = SAS_TASK_UNDELIVERED;
2334 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2335 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2336 return;
2337 }
2338 break;
2339 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2340 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2341 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2342 ts->resp = SAS_TASK_COMPLETE;
2343 ts->stat = SAS_OPEN_REJECT;
2344 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2345 break;
2346 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2347 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2348 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2349 ts->resp = SAS_TASK_COMPLETE;
2350 ts->stat = SAS_DEV_NO_RESPONSE;
2351 if (!t->uldd_task) {
2352 pm8001_handle_event(pm8001_ha,
2353 pm8001_dev,
2354 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2355 ts->resp = SAS_TASK_UNDELIVERED;
2356 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2357 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2358 return;
2359 }
2360 break;
2361 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2362 PM8001_IO_DBG(pm8001_ha,
2363 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2364 ts->resp = SAS_TASK_COMPLETE;
2365 ts->stat = SAS_OPEN_REJECT;
2366 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2367 break;
2368 case IO_XFER_ERROR_NAK_RECEIVED:
2369 PM8001_IO_DBG(pm8001_ha,
2370 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2371 ts->resp = SAS_TASK_COMPLETE;
2372 ts->stat = SAS_NAK_R_ERR;
2373 break;
2374 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2375 PM8001_IO_DBG(pm8001_ha,
2376 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2377 ts->resp = SAS_TASK_COMPLETE;
2378 ts->stat = SAS_NAK_R_ERR;
2379 break;
2380 case IO_XFER_ERROR_DMA:
2381 PM8001_IO_DBG(pm8001_ha,
2382 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2383 ts->resp = SAS_TASK_COMPLETE;
2384 ts->stat = SAS_ABORTED_TASK;
2385 break;
2386 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2387 PM8001_IO_DBG(pm8001_ha,
2388 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2389 ts->resp = SAS_TASK_UNDELIVERED;
2390 ts->stat = SAS_DEV_NO_RESPONSE;
2391 break;
2392 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2393 PM8001_IO_DBG(pm8001_ha,
2394 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2395 ts->resp = SAS_TASK_COMPLETE;
2396 ts->stat = SAS_DATA_UNDERRUN;
2397 break;
2398 case IO_XFER_OPEN_RETRY_TIMEOUT:
2399 PM8001_IO_DBG(pm8001_ha,
2400 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2401 ts->resp = SAS_TASK_COMPLETE;
2402 ts->stat = SAS_OPEN_TO;
2403 break;
2404 case IO_PORT_IN_RESET:
2405 PM8001_IO_DBG(pm8001_ha,
2406 pm8001_printk("IO_PORT_IN_RESET\n"));
2407 ts->resp = SAS_TASK_COMPLETE;
2408 ts->stat = SAS_DEV_NO_RESPONSE;
2409 break;
2410 case IO_DS_NON_OPERATIONAL:
2411 PM8001_IO_DBG(pm8001_ha,
2412 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2413 ts->resp = SAS_TASK_COMPLETE;
2414 ts->stat = SAS_DEV_NO_RESPONSE;
2415 if (!t->uldd_task) {
2416 pm8001_handle_event(pm8001_ha, pm8001_dev,
2417 IO_DS_NON_OPERATIONAL);
2418 ts->resp = SAS_TASK_UNDELIVERED;
2419 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2420 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2421 return;
2422 }
2423 break;
2424 case IO_DS_IN_RECOVERY:
2425 PM8001_IO_DBG(pm8001_ha,
2426 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2427 ts->resp = SAS_TASK_COMPLETE;
2428 ts->stat = SAS_DEV_NO_RESPONSE;
2429 break;
2430 case IO_DS_IN_ERROR:
2431 PM8001_IO_DBG(pm8001_ha,
2432 pm8001_printk("IO_DS_IN_ERROR\n"));
2433 ts->resp = SAS_TASK_COMPLETE;
2434 ts->stat = SAS_DEV_NO_RESPONSE;
2435 if (!t->uldd_task) {
2436 pm8001_handle_event(pm8001_ha, pm8001_dev,
2437 IO_DS_IN_ERROR);
2438 ts->resp = SAS_TASK_UNDELIVERED;
2439 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2440 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2441 return;
2442 }
2443 break;
2444 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2445 PM8001_IO_DBG(pm8001_ha,
2446 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2447 ts->resp = SAS_TASK_COMPLETE;
2448 ts->stat = SAS_OPEN_REJECT;
2449 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
Johannes Thumshirn50acde82015-08-17 15:52:32 +0200[diff] [blame]2450 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2451 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2452 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2453 pm8001_printk("Unknown status 0x%x\n", status));
2454 /* not allowed case. Therefore, return failed status */
2455 ts->resp = SAS_TASK_COMPLETE;
2456 ts->stat = SAS_DEV_NO_RESPONSE;
2457 break;
2458 }
2459 spin_lock_irqsave(&t->task_state_lock, flags);
2460 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2461 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2462 t->task_state_flags |= SAS_TASK_STATE_DONE;
2463 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2464 spin_unlock_irqrestore(&t->task_state_lock, flags);
2465 PM8001_FAIL_DBG(pm8001_ha,
2466 pm8001_printk("task 0x%p done with io_status 0x%x"
2467 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2468 t, status, ts->resp, ts->stat));
peter changce21c632019-11-14 15:38:58 +0530[diff] [blame]2469 if (t->slow_task)
2470 complete(&t->slow_task->completion);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2471 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2472 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2473 spin_unlock_irqrestore(&t->task_state_lock, flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2474 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2475 }
2476}
2477
2478/*See the comments for mpi_ssp_completion */
2479static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2480{
2481 struct sas_task *t;
2482 struct task_status_struct *ts;
2483 struct pm8001_ccb_info *ccb;
2484 struct pm8001_device *pm8001_dev;
2485 struct sata_event_resp *psataPayload =
2486 (struct sata_event_resp *)(piomb + 4);
2487 u32 event = le32_to_cpu(psataPayload->event);
2488 u32 tag = le32_to_cpu(psataPayload->tag);
2489 u32 port_id = le32_to_cpu(psataPayload->port_id);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2490 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2491 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2492
2493 ccb = &pm8001_ha->ccb_info[tag];
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2494
2495 if (ccb) {
2496 t = ccb->task;
2497 pm8001_dev = ccb->device;
2498 } else {
2499 PM8001_FAIL_DBG(pm8001_ha,
2500 pm8001_printk("No CCB !!!. returning\n"));
2501 return;
2502 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2503 if (event)
2504 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2505 pm8001_printk("SATA EVENT 0x%x\n", event));
2506
2507 /* Check if this is NCQ error */
2508 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2509 /* find device using device id */
2510 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2511 /* send read log extension */
2512 if (pm8001_dev)
2513 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2514 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2515 }
2516
2517 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2518 PM8001_FAIL_DBG(pm8001_ha,
2519 pm8001_printk("task or dev null\n"));
2520 return;
2521 }
2522
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2523 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2524 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2525 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2526 port_id, tag, event));
2527 switch (event) {
2528 case IO_OVERFLOW:
2529 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2530 ts->resp = SAS_TASK_COMPLETE;
2531 ts->stat = SAS_DATA_OVERRUN;
2532 ts->residual = 0;
2533 if (pm8001_dev)
2534 pm8001_dev->running_req--;
2535 break;
2536 case IO_XFER_ERROR_BREAK:
2537 PM8001_IO_DBG(pm8001_ha,
2538 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2539 ts->resp = SAS_TASK_COMPLETE;
2540 ts->stat = SAS_INTERRUPTED;
2541 break;
2542 case IO_XFER_ERROR_PHY_NOT_READY:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_OPEN_REJECT;
2547 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2548 break;
2549 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2550 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2551 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_OPEN_REJECT;
2554 ts->open_rej_reason = SAS_OREJ_EPROTO;
2555 break;
2556 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2557 PM8001_IO_DBG(pm8001_ha,
2558 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2559 ts->resp = SAS_TASK_COMPLETE;
2560 ts->stat = SAS_OPEN_REJECT;
2561 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2562 break;
2563 case IO_OPEN_CNX_ERROR_BREAK:
2564 PM8001_IO_DBG(pm8001_ha,
2565 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2566 ts->resp = SAS_TASK_COMPLETE;
2567 ts->stat = SAS_OPEN_REJECT;
2568 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2569 break;
2570 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2571 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2572 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2573 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2574 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2575 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2576 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2577 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2578 ts->resp = SAS_TASK_UNDELIVERED;
2579 ts->stat = SAS_DEV_NO_RESPONSE;
2580 if (!t->uldd_task) {
2581 pm8001_handle_event(pm8001_ha,
2582 pm8001_dev,
2583 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2586 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2587 return;
2588 }
2589 break;
2590 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2591 PM8001_IO_DBG(pm8001_ha,
2592 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2593 ts->resp = SAS_TASK_UNDELIVERED;
2594 ts->stat = SAS_OPEN_REJECT;
2595 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2596 break;
2597 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2598 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2599 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2600 ts->resp = SAS_TASK_COMPLETE;
2601 ts->stat = SAS_OPEN_REJECT;
2602 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2603 break;
2604 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2605 PM8001_IO_DBG(pm8001_ha,
2606 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2607 ts->resp = SAS_TASK_COMPLETE;
2608 ts->stat = SAS_OPEN_REJECT;
2609 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2610 break;
2611 case IO_XFER_ERROR_NAK_RECEIVED:
2612 PM8001_IO_DBG(pm8001_ha,
2613 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2614 ts->resp = SAS_TASK_COMPLETE;
2615 ts->stat = SAS_NAK_R_ERR;
2616 break;
2617 case IO_XFER_ERROR_PEER_ABORTED:
2618 PM8001_IO_DBG(pm8001_ha,
2619 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2620 ts->resp = SAS_TASK_COMPLETE;
2621 ts->stat = SAS_NAK_R_ERR;
2622 break;
2623 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2624 PM8001_IO_DBG(pm8001_ha,
2625 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2626 ts->resp = SAS_TASK_COMPLETE;
2627 ts->stat = SAS_DATA_UNDERRUN;
2628 break;
2629 case IO_XFER_OPEN_RETRY_TIMEOUT:
2630 PM8001_IO_DBG(pm8001_ha,
2631 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2632 ts->resp = SAS_TASK_COMPLETE;
2633 ts->stat = SAS_OPEN_TO;
2634 break;
2635 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2636 PM8001_IO_DBG(pm8001_ha,
2637 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2638 ts->resp = SAS_TASK_COMPLETE;
2639 ts->stat = SAS_OPEN_TO;
2640 break;
2641 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2642 PM8001_IO_DBG(pm8001_ha,
2643 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2644 ts->resp = SAS_TASK_COMPLETE;
2645 ts->stat = SAS_OPEN_TO;
2646 break;
2647 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2648 PM8001_IO_DBG(pm8001_ha,
2649 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2650 ts->resp = SAS_TASK_COMPLETE;
2651 ts->stat = SAS_OPEN_TO;
2652 break;
2653 case IO_XFER_ERROR_OFFSET_MISMATCH:
2654 PM8001_IO_DBG(pm8001_ha,
2655 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2656 ts->resp = SAS_TASK_COMPLETE;
2657 ts->stat = SAS_OPEN_TO;
2658 break;
2659 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2660 PM8001_IO_DBG(pm8001_ha,
2661 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2662 ts->resp = SAS_TASK_COMPLETE;
2663 ts->stat = SAS_OPEN_TO;
2664 break;
2665 case IO_XFER_CMD_FRAME_ISSUED:
2666 PM8001_IO_DBG(pm8001_ha,
2667 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2668 break;
2669 case IO_XFER_PIO_SETUP_ERROR:
2670 PM8001_IO_DBG(pm8001_ha,
2671 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2672 ts->resp = SAS_TASK_COMPLETE;
2673 ts->stat = SAS_OPEN_TO;
2674 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2675 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2676 PM8001_FAIL_DBG(pm8001_ha,
2677 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2678 /* TBC: used default set values */
2679 ts->resp = SAS_TASK_COMPLETE;
2680 ts->stat = SAS_OPEN_TO;
2681 break;
2682 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2683 PM8001_FAIL_DBG(pm8001_ha,
2684 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2685 /* TBC: used default set values */
2686 ts->resp = SAS_TASK_COMPLETE;
2687 ts->stat = SAS_OPEN_TO;
2688 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2689 default:
2690 PM8001_IO_DBG(pm8001_ha,
2691 pm8001_printk("Unknown status 0x%x\n", event));
2692 /* not allowed case. Therefore, return failed status */
2693 ts->resp = SAS_TASK_COMPLETE;
2694 ts->stat = SAS_OPEN_TO;
2695 break;
2696 }
2697 spin_lock_irqsave(&t->task_state_lock, flags);
2698 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2699 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2700 t->task_state_flags |= SAS_TASK_STATE_DONE;
2701 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2702 spin_unlock_irqrestore(&t->task_state_lock, flags);
2703 PM8001_FAIL_DBG(pm8001_ha,
2704 pm8001_printk("task 0x%p done with io_status 0x%x"
2705 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2706 t, event, ts->resp, ts->stat));
2707 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2708 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2709 spin_unlock_irqrestore(&t->task_state_lock, flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2710 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2711 }
2712}
2713
2714/*See the comments for mpi_ssp_completion */
2715static void
2716mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2717{
2718 u32 param, i;
2719 struct sas_task *t;
2720 struct pm8001_ccb_info *ccb;
2721 unsigned long flags;
2722 u32 status;
2723 u32 tag;
2724 struct smp_completion_resp *psmpPayload;
2725 struct task_status_struct *ts;
2726 struct pm8001_device *pm8001_dev;
2727 char *pdma_respaddr = NULL;
2728
2729 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2730 status = le32_to_cpu(psmpPayload->status);
2731 tag = le32_to_cpu(psmpPayload->tag);
2732
2733 ccb = &pm8001_ha->ccb_info[tag];
2734 param = le32_to_cpu(psmpPayload->param);
2735 t = ccb->task;
2736 ts = &t->task_status;
2737 pm8001_dev = ccb->device;
2738 if (status)
2739 PM8001_FAIL_DBG(pm8001_ha,
2740 pm8001_printk("smp IO status 0x%x\n", status));
2741 if (unlikely(!t || !t->lldd_task || !t->dev))
2742 return;
2743
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2744 PM8001_DEV_DBG(pm8001_ha,
2745 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
2746
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2747 switch (status) {
2748
2749 case IO_SUCCESS:
2750 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2751 ts->resp = SAS_TASK_COMPLETE;
2752 ts->stat = SAM_STAT_GOOD;
2753 if (pm8001_dev)
2754 pm8001_dev->running_req--;
2755 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2756 PM8001_IO_DBG(pm8001_ha,
2757 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2758 param));
2759 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2760 ((u64)sg_dma_address
2761 (&t->smp_task.smp_resp))));
2762 for (i = 0; i < param; i++) {
2763 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2764 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2765 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2766 i, *(pdma_respaddr+i),
2767 psmpPayload->_r_a[i]));
2768 }
2769 }
2770 break;
2771 case IO_ABORTED:
2772 PM8001_IO_DBG(pm8001_ha,
2773 pm8001_printk("IO_ABORTED IOMB\n"));
2774 ts->resp = SAS_TASK_COMPLETE;
2775 ts->stat = SAS_ABORTED_TASK;
2776 if (pm8001_dev)
2777 pm8001_dev->running_req--;
2778 break;
2779 case IO_OVERFLOW:
2780 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2781 ts->resp = SAS_TASK_COMPLETE;
2782 ts->stat = SAS_DATA_OVERRUN;
2783 ts->residual = 0;
2784 if (pm8001_dev)
2785 pm8001_dev->running_req--;
2786 break;
2787 case IO_NO_DEVICE:
2788 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2789 ts->resp = SAS_TASK_COMPLETE;
2790 ts->stat = SAS_PHY_DOWN;
2791 break;
2792 case IO_ERROR_HW_TIMEOUT:
2793 PM8001_IO_DBG(pm8001_ha,
2794 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2795 ts->resp = SAS_TASK_COMPLETE;
2796 ts->stat = SAM_STAT_BUSY;
2797 break;
2798 case IO_XFER_ERROR_BREAK:
2799 PM8001_IO_DBG(pm8001_ha,
2800 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2801 ts->resp = SAS_TASK_COMPLETE;
2802 ts->stat = SAM_STAT_BUSY;
2803 break;
2804 case IO_XFER_ERROR_PHY_NOT_READY:
2805 PM8001_IO_DBG(pm8001_ha,
2806 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2807 ts->resp = SAS_TASK_COMPLETE;
2808 ts->stat = SAM_STAT_BUSY;
2809 break;
2810 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2811 PM8001_IO_DBG(pm8001_ha,
2812 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2813 ts->resp = SAS_TASK_COMPLETE;
2814 ts->stat = SAS_OPEN_REJECT;
2815 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2816 break;
2817 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2818 PM8001_IO_DBG(pm8001_ha,
2819 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2820 ts->resp = SAS_TASK_COMPLETE;
2821 ts->stat = SAS_OPEN_REJECT;
2822 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2823 break;
2824 case IO_OPEN_CNX_ERROR_BREAK:
2825 PM8001_IO_DBG(pm8001_ha,
2826 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2827 ts->resp = SAS_TASK_COMPLETE;
2828 ts->stat = SAS_OPEN_REJECT;
2829 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2830 break;
2831 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2832 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2833 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2834 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2835 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2836 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2837 PM8001_IO_DBG(pm8001_ha,
2838 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2839 ts->resp = SAS_TASK_COMPLETE;
2840 ts->stat = SAS_OPEN_REJECT;
2841 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2842 pm8001_handle_event(pm8001_ha,
2843 pm8001_dev,
2844 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2845 break;
2846 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2847 PM8001_IO_DBG(pm8001_ha,
2848 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2849 ts->resp = SAS_TASK_COMPLETE;
2850 ts->stat = SAS_OPEN_REJECT;
2851 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2852 break;
2853 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2854 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2855 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2856 ts->resp = SAS_TASK_COMPLETE;
2857 ts->stat = SAS_OPEN_REJECT;
2858 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2859 break;
2860 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2861 PM8001_IO_DBG(pm8001_ha,
2862 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2863 ts->resp = SAS_TASK_COMPLETE;
2864 ts->stat = SAS_OPEN_REJECT;
2865 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2866 break;
2867 case IO_XFER_ERROR_RX_FRAME:
2868 PM8001_IO_DBG(pm8001_ha,
2869 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2870 ts->resp = SAS_TASK_COMPLETE;
2871 ts->stat = SAS_DEV_NO_RESPONSE;
2872 break;
2873 case IO_XFER_OPEN_RETRY_TIMEOUT:
2874 PM8001_IO_DBG(pm8001_ha,
2875 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2876 ts->resp = SAS_TASK_COMPLETE;
2877 ts->stat = SAS_OPEN_REJECT;
2878 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2879 break;
2880 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2881 PM8001_IO_DBG(pm8001_ha,
2882 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2883 ts->resp = SAS_TASK_COMPLETE;
2884 ts->stat = SAS_QUEUE_FULL;
2885 break;
2886 case IO_PORT_IN_RESET:
2887 PM8001_IO_DBG(pm8001_ha,
2888 pm8001_printk("IO_PORT_IN_RESET\n"));
2889 ts->resp = SAS_TASK_COMPLETE;
2890 ts->stat = SAS_OPEN_REJECT;
2891 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2892 break;
2893 case IO_DS_NON_OPERATIONAL:
2894 PM8001_IO_DBG(pm8001_ha,
2895 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2896 ts->resp = SAS_TASK_COMPLETE;
2897 ts->stat = SAS_DEV_NO_RESPONSE;
2898 break;
2899 case IO_DS_IN_RECOVERY:
2900 PM8001_IO_DBG(pm8001_ha,
2901 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2902 ts->resp = SAS_TASK_COMPLETE;
2903 ts->stat = SAS_OPEN_REJECT;
2904 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2905 break;
2906 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2907 PM8001_IO_DBG(pm8001_ha,
2908 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2909 ts->resp = SAS_TASK_COMPLETE;
2910 ts->stat = SAS_OPEN_REJECT;
2911 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2912 break;
2913 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2914 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2915 pm8001_printk("Unknown status 0x%x\n", status));
2916 ts->resp = SAS_TASK_COMPLETE;
2917 ts->stat = SAS_DEV_NO_RESPONSE;
2918 /* not allowed case. Therefore, return failed status */
2919 break;
2920 }
2921 spin_lock_irqsave(&t->task_state_lock, flags);
2922 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2923 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2924 t->task_state_flags |= SAS_TASK_STATE_DONE;
2925 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2926 spin_unlock_irqrestore(&t->task_state_lock, flags);
2927 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2928 "task 0x%p done with io_status 0x%x resp 0x%x"
2929 "stat 0x%x but aborted by upper layer!\n",
2930 t, status, ts->resp, ts->stat));
2931 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2932 } else {
2933 spin_unlock_irqrestore(&t->task_state_lock, flags);
2934 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2935 mb();/* in order to force CPU ordering */
2936 t->task_done(t);
2937 }
2938}
2939
2940/**
2941 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2942 * @pm8001_ha: our hba card information
2943 * @Qnum: the outbound queue message number.
2944 * @SEA: source of event to ack
2945 * @port_id: port id.
2946 * @phyId: phy id.
2947 * @param0: parameter 0.
2948 * @param1: parameter 1.
2949 */
2950static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2951 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2952{
2953 struct hw_event_ack_req payload;
2954 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2955
2956 struct inbound_queue_table *circularQ;
2957
2958 memset((u8 *)&payload, 0, sizeof(payload));
2959 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2960 payload.tag = cpu_to_le32(1);
2961 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2962 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2963 payload.param0 = cpu_to_le32(param0);
2964 payload.param1 = cpu_to_le32(param1);
2965 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2966}
2967
2968static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2969 u32 phyId, u32 phy_op);
2970
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]2971static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2972 void *piomb)
2973{
2974 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2975 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2976 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2977 u32 lr_status_evt_portid =
2978 le32_to_cpu(pPayload->lr_status_evt_portid);
2979 u8 deviceType = pPayload->sas_identify.dev_type;
2980 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2981 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2982 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2983 struct pm8001_port *port = &pm8001_ha->port[port_id];
2984
2985 if (deviceType == SAS_END_DEVICE) {
2986 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2987 PHY_NOTIFY_ENABLE_SPINUP);
2988 }
2989
2990 port->wide_port_phymap |= (1U << phy_id);
2991 pm8001_get_lrate_mode(phy, link_rate);
2992 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2993 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2994 phy->phy_attached = 1;
2995}
2996
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2997/**
2998 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2999 * @pm8001_ha: our hba card information
3000 * @piomb: IO message buffer
3001 */
3002static void
3003hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3004{
3005 struct hw_event_resp *pPayload =
3006 (struct hw_event_resp *)(piomb + 4);
3007 u32 lr_status_evt_portid =
3008 le32_to_cpu(pPayload->lr_status_evt_portid);
3009 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3010
3011 u8 link_rate =
3012 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3013 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3014 u8 phy_id =
3015 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3016 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3017
3018 struct pm8001_port *port = &pm8001_ha->port[port_id];
3019 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3020 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3021 unsigned long flags;
3022 u8 deviceType = pPayload->sas_identify.dev_type;
3023 port->port_state = portstate;
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3024 port->wide_port_phymap |= (1U << phy_id);
Nikith Ganigarakoppal7d029002013-10-30 16:23:47 +0530[diff] [blame]3025 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3026 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3027 "portid:%d; phyid:%d; linkrate:%d; "
3028 "portstate:%x; devicetype:%x\n",
3029 port_id, phy_id, link_rate, portstate, deviceType));
3030
3031 switch (deviceType) {
3032 case SAS_PHY_UNUSED:
3033 PM8001_MSG_DBG(pm8001_ha,
3034 pm8001_printk("device type no device.\n"));
3035 break;
3036 case SAS_END_DEVICE:
3037 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3038 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3039 PHY_NOTIFY_ENABLE_SPINUP);
3040 port->port_attached = 1;
3041 pm8001_get_lrate_mode(phy, link_rate);
3042 break;
3043 case SAS_EDGE_EXPANDER_DEVICE:
3044 PM8001_MSG_DBG(pm8001_ha,
3045 pm8001_printk("expander device.\n"));
3046 port->port_attached = 1;
3047 pm8001_get_lrate_mode(phy, link_rate);
3048 break;
3049 case SAS_FANOUT_EXPANDER_DEVICE:
3050 PM8001_MSG_DBG(pm8001_ha,
3051 pm8001_printk("fanout expander device.\n"));
3052 port->port_attached = 1;
3053 pm8001_get_lrate_mode(phy, link_rate);
3054 break;
3055 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3056 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3057 pm8001_printk("unknown device type(%x)\n", deviceType));
3058 break;
3059 }
3060 phy->phy_type |= PORT_TYPE_SAS;
3061 phy->identify.device_type = deviceType;
3062 phy->phy_attached = 1;
3063 if (phy->identify.device_type == SAS_END_DEVICE)
3064 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3065 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3066 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3067 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3068 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3069 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3070 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3071 sizeof(struct sas_identify_frame)-4);
3072 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3073 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3074 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3075 if (pm8001_ha->flags == PM8001F_RUN_TIME)
Vikram Auradkar4daf1ef2019-11-14 15:39:01 +0530[diff] [blame]3076 msleep(200);/*delay a moment to wait disk to spinup*/
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3077 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3078}
3079
3080/**
3081 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3082 * @pm8001_ha: our hba card information
3083 * @piomb: IO message buffer
3084 */
3085static void
3086hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3087{
3088 struct hw_event_resp *pPayload =
3089 (struct hw_event_resp *)(piomb + 4);
3090 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3091 u32 lr_status_evt_portid =
3092 le32_to_cpu(pPayload->lr_status_evt_portid);
3093 u8 link_rate =
3094 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3095 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3096 u8 phy_id =
3097 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3098
3099 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3100
3101 struct pm8001_port *port = &pm8001_ha->port[port_id];
3102 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3103 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3104 unsigned long flags;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3105 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3106 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3107 port_id, phy_id, link_rate, portstate));
3108
3109 port->port_state = portstate;
Nikith Ganigarakoppal7d029002013-10-30 16:23:47 +0530[diff] [blame]3110 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3111 port->port_attached = 1;
3112 pm8001_get_lrate_mode(phy, link_rate);
3113 phy->phy_type |= PORT_TYPE_SATA;
3114 phy->phy_attached = 1;
3115 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3116 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3117 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3118 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3119 sizeof(struct dev_to_host_fis));
3120 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3121 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]3122 phy->identify.device_type = SAS_SATA_DEV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3123 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3124 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3125 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3126}
3127
3128/**
3129 * hw_event_phy_down -we should notify the libsas the phy is down.
3130 * @pm8001_ha: our hba card information
3131 * @piomb: IO message buffer
3132 */
3133static void
3134hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3135{
3136 struct hw_event_resp *pPayload =
3137 (struct hw_event_resp *)(piomb + 4);
3138
3139 u32 lr_status_evt_portid =
3140 le32_to_cpu(pPayload->lr_status_evt_portid);
3141 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3142 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3143 u8 phy_id =
3144 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3145 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3146
3147 struct pm8001_port *port = &pm8001_ha->port[port_id];
3148 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3149 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3150 port->port_state = portstate;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3151 phy->identify.device_type = 0;
3152 phy->phy_attached = 0;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3153 switch (portstate) {
3154 case PORT_VALID:
3155 break;
3156 case PORT_INVALID:
3157 PM8001_MSG_DBG(pm8001_ha,
3158 pm8001_printk(" PortInvalid portID %d\n", port_id));
3159 PM8001_MSG_DBG(pm8001_ha,
3160 pm8001_printk(" Last phy Down and port invalid\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3161 if (port_sata) {
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3162 phy->phy_type = 0;
3163 port->port_attached = 0;
3164 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3165 port_id, phy_id, 0, 0);
3166 }
3167 sas_phy_disconnected(&phy->sas_phy);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3168 break;
3169 case PORT_IN_RESET:
3170 PM8001_MSG_DBG(pm8001_ha,
3171 pm8001_printk(" Port In Reset portID %d\n", port_id));
3172 break;
3173 case PORT_NOT_ESTABLISHED:
3174 PM8001_MSG_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3175 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3176 port->port_attached = 0;
3177 break;
3178 case PORT_LOSTCOMM:
3179 PM8001_MSG_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3180 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3181 PM8001_MSG_DBG(pm8001_ha,
3182 pm8001_printk(" Last phy Down and port invalid\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3183 if (port_sata) {
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3184 port->port_attached = 0;
3185 phy->phy_type = 0;
3186 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3187 port_id, phy_id, 0, 0);
3188 }
3189 sas_phy_disconnected(&phy->sas_phy);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3190 break;
3191 default:
3192 port->port_attached = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3193 PM8001_DEVIO_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3194 pm8001_printk(" Phy Down and(default) = 0x%x\n",
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3195 portstate));
3196 break;
3197
3198 }
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3199 if (port_sata && (portstate != PORT_IN_RESET)) {
3200 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3201
3202 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3203 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3204}
3205
3206static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3207{
3208 struct phy_start_resp *pPayload =
3209 (struct phy_start_resp *)(piomb + 4);
3210 u32 status =
3211 le32_to_cpu(pPayload->status);
3212 u32 phy_id =
3213 le32_to_cpu(pPayload->phyid);
3214 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3215
3216 PM8001_INIT_DBG(pm8001_ha,
3217 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3218 status, phy_id));
3219 if (status == 0) {
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3220 phy->phy_state = PHY_LINK_DOWN;
3221 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
peter change7039772019-11-14 15:38:59 +0530[diff] [blame]3222 phy->enable_completion != NULL) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3223 complete(phy->enable_completion);
peter change7039772019-11-14 15:38:59 +0530[diff] [blame]3224 phy->enable_completion = NULL;
3225 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3226 }
3227 return 0;
3228
3229}
3230
3231/**
3232 * mpi_thermal_hw_event -The hw event has come.
3233 * @pm8001_ha: our hba card information
3234 * @piomb: IO message buffer
3235 */
3236static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3237{
3238 struct thermal_hw_event *pPayload =
3239 (struct thermal_hw_event *)(piomb + 4);
3240
3241 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3242 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3243
3244 if (thermal_event & 0x40) {
3245 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3246 "Thermal Event: Local high temperature violated!\n"));
3247 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3248 "Thermal Event: Measured local high temperature %d\n",
3249 ((rht_lht & 0xFF00) >> 8)));
3250 }
3251 if (thermal_event & 0x10) {
3252 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3253 "Thermal Event: Remote high temperature violated!\n"));
3254 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3255 "Thermal Event: Measured remote high temperature %d\n",
3256 ((rht_lht & 0xFF000000) >> 24)));
3257 }
3258 return 0;
3259}
3260
3261/**
3262 * mpi_hw_event -The hw event has come.
3263 * @pm8001_ha: our hba card information
3264 * @piomb: IO message buffer
3265 */
3266static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3267{
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3268 unsigned long flags, i;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3269 struct hw_event_resp *pPayload =
3270 (struct hw_event_resp *)(piomb + 4);
3271 u32 lr_status_evt_portid =
3272 le32_to_cpu(pPayload->lr_status_evt_portid);
3273 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3274 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3275 u8 phy_id =
3276 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3277 u16 eventType =
3278 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3279 u8 status =
3280 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3281 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3282 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3283 struct pm8001_port *port = &pm8001_ha->port[port_id];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3284 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3285 PM8001_DEV_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3286 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3287 port_id, phy_id, eventType, status));
3288
3289 switch (eventType) {
3290
3291 case HW_EVENT_SAS_PHY_UP:
3292 PM8001_MSG_DBG(pm8001_ha,
3293 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3294 hw_event_sas_phy_up(pm8001_ha, piomb);
3295 break;
3296 case HW_EVENT_SATA_PHY_UP:
3297 PM8001_MSG_DBG(pm8001_ha,
3298 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3299 hw_event_sata_phy_up(pm8001_ha, piomb);
3300 break;
3301 case HW_EVENT_SATA_SPINUP_HOLD:
3302 PM8001_MSG_DBG(pm8001_ha,
3303 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3304 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3305 break;
3306 case HW_EVENT_PHY_DOWN:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3309 hw_event_phy_down(pm8001_ha, piomb);
3310 if (pm8001_ha->reset_in_progress) {
3311 PM8001_MSG_DBG(pm8001_ha,
3312 pm8001_printk("Reset in progress\n"));
3313 return 0;
3314 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3315 phy->phy_attached = 0;
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3316 phy->phy_state = PHY_LINK_DISABLE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3317 break;
3318 case HW_EVENT_PORT_INVALID:
3319 PM8001_MSG_DBG(pm8001_ha,
3320 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3321 sas_phy_disconnected(sas_phy);
3322 phy->phy_attached = 0;
3323 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3324 break;
3325 /* the broadcast change primitive received, tell the LIBSAS this event
3326 to revalidate the sas domain*/
3327 case HW_EVENT_BROADCAST_CHANGE:
3328 PM8001_MSG_DBG(pm8001_ha,
3329 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3330 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3331 port_id, phy_id, 1, 0);
3332 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3333 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3334 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3335 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3336 break;
3337 case HW_EVENT_PHY_ERROR:
3338 PM8001_MSG_DBG(pm8001_ha,
3339 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3340 sas_phy_disconnected(&phy->sas_phy);
3341 phy->phy_attached = 0;
3342 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3343 break;
3344 case HW_EVENT_BROADCAST_EXP:
3345 PM8001_MSG_DBG(pm8001_ha,
3346 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3347 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3348 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3349 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3350 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3351 break;
3352 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3353 PM8001_MSG_DBG(pm8001_ha,
3354 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3355 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3356 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3357 break;
3358 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3359 PM8001_MSG_DBG(pm8001_ha,
3360 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3361 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3362 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3363 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3364 break;
3365 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3368 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3369 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3370 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3371 break;
3372 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3373 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3374 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3375 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3376 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3377 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3378 break;
3379 case HW_EVENT_MALFUNCTION:
3380 PM8001_MSG_DBG(pm8001_ha,
3381 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3382 break;
3383 case HW_EVENT_BROADCAST_SES:
3384 PM8001_MSG_DBG(pm8001_ha,
3385 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3386 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3387 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3388 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3389 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3390 break;
3391 case HW_EVENT_INBOUND_CRC_ERROR:
3392 PM8001_MSG_DBG(pm8001_ha,
3393 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3394 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3395 HW_EVENT_INBOUND_CRC_ERROR,
3396 port_id, phy_id, 0, 0);
3397 break;
3398 case HW_EVENT_HARD_RESET_RECEIVED:
3399 PM8001_MSG_DBG(pm8001_ha,
3400 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3401 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3402 break;
3403 case HW_EVENT_ID_FRAME_TIMEOUT:
3404 PM8001_MSG_DBG(pm8001_ha,
3405 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3406 sas_phy_disconnected(sas_phy);
3407 phy->phy_attached = 0;
3408 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3409 break;
3410 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3411 PM8001_MSG_DBG(pm8001_ha,
3412 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3413 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3414 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3415 port_id, phy_id, 0, 0);
3416 sas_phy_disconnected(sas_phy);
3417 phy->phy_attached = 0;
3418 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3419 break;
3420 case HW_EVENT_PORT_RESET_TIMER_TMO:
3421 PM8001_MSG_DBG(pm8001_ha,
3422 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3423 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3424 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3425 sas_phy_disconnected(sas_phy);
3426 phy->phy_attached = 0;
3427 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3428 if (pm8001_ha->phy[phy_id].reset_completion) {
3429 pm8001_ha->phy[phy_id].port_reset_status =
3430 PORT_RESET_TMO;
3431 complete(pm8001_ha->phy[phy_id].reset_completion);
3432 pm8001_ha->phy[phy_id].reset_completion = NULL;
3433 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3434 break;
3435 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3436 PM8001_MSG_DBG(pm8001_ha,
3437 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]3438 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3439 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3440 port_id, phy_id, 0, 0);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3441 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3442 if (port->wide_port_phymap & (1 << i)) {
3443 phy = &pm8001_ha->phy[i];
3444 sas_ha->notify_phy_event(&phy->sas_phy,
3445 PHYE_LOSS_OF_SIGNAL);
3446 port->wide_port_phymap &= ~(1 << i);
3447 }
3448 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3449 break;
3450 case HW_EVENT_PORT_RECOVER:
3451 PM8001_MSG_DBG(pm8001_ha,
3452 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3453 hw_event_port_recover(pm8001_ha, piomb);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3454 break;
3455 case HW_EVENT_PORT_RESET_COMPLETE:
3456 PM8001_MSG_DBG(pm8001_ha,
3457 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3458 if (pm8001_ha->phy[phy_id].reset_completion) {
3459 pm8001_ha->phy[phy_id].port_reset_status =
3460 PORT_RESET_SUCCESS;
3461 complete(pm8001_ha->phy[phy_id].reset_completion);
3462 pm8001_ha->phy[phy_id].reset_completion = NULL;
3463 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3464 break;
3465 case EVENT_BROADCAST_ASYNCH_EVENT:
3466 PM8001_MSG_DBG(pm8001_ha,
3467 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3468 break;
3469 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3470 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3471 pm8001_printk("Unknown event type 0x%x\n", eventType));
3472 break;
3473 }
3474 return 0;
3475}
3476
3477/**
3478 * mpi_phy_stop_resp - SPCv specific
3479 * @pm8001_ha: our hba card information
3480 * @piomb: IO message buffer
3481 */
3482static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3483{
3484 struct phy_stop_resp *pPayload =
3485 (struct phy_stop_resp *)(piomb + 4);
3486 u32 status =
3487 le32_to_cpu(pPayload->status);
3488 u32 phyid =
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3489 le32_to_cpu(pPayload->phyid) & 0xFF;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3490 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3491 PM8001_MSG_DBG(pm8001_ha,
3492 pm8001_printk("phy:0x%x status:0x%x\n",
3493 phyid, status));
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3494 if (status == PHY_STOP_SUCCESS ||
3495 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3496 phy->phy_state = PHY_LINK_DISABLE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3497 return 0;
3498}
3499
3500/**
3501 * mpi_set_controller_config_resp - SPCv specific
3502 * @pm8001_ha: our hba card information
3503 * @piomb: IO message buffer
3504 */
3505static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3506 void *piomb)
3507{
3508 struct set_ctrl_cfg_resp *pPayload =
3509 (struct set_ctrl_cfg_resp *)(piomb + 4);
3510 u32 status = le32_to_cpu(pPayload->status);
3511 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3512
3513 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3514 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3515 status, err_qlfr_pgcd));
3516
3517 return 0;
3518}
3519
3520/**
3521 * mpi_get_controller_config_resp - SPCv specific
3522 * @pm8001_ha: our hba card information
3523 * @piomb: IO message buffer
3524 */
3525static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3526 void *piomb)
3527{
3528 PM8001_MSG_DBG(pm8001_ha,
3529 pm8001_printk(" pm80xx_addition_functionality\n"));
3530
3531 return 0;
3532}
3533
3534/**
3535 * mpi_get_phy_profile_resp - SPCv specific
3536 * @pm8001_ha: our hba card information
3537 * @piomb: IO message buffer
3538 */
3539static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3540 void *piomb)
3541{
3542 PM8001_MSG_DBG(pm8001_ha,
3543 pm8001_printk(" pm80xx_addition_functionality\n"));
3544
3545 return 0;
3546}
3547
3548/**
3549 * mpi_flash_op_ext_resp - SPCv specific
3550 * @pm8001_ha: our hba card information
3551 * @piomb: IO message buffer
3552 */
3553static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3554{
3555 PM8001_MSG_DBG(pm8001_ha,
3556 pm8001_printk(" pm80xx_addition_functionality\n"));
3557
3558 return 0;
3559}
3560
3561/**
3562 * mpi_set_phy_profile_resp - SPCv specific
3563 * @pm8001_ha: our hba card information
3564 * @piomb: IO message buffer
3565 */
3566static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3567 void *piomb)
3568{
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]3569 u8 page_code;
3570 struct set_phy_profile_resp *pPayload =
3571 (struct set_phy_profile_resp *)(piomb + 4);
3572 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3573 u32 status = le32_to_cpu(pPayload->status);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3574
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]3575 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3576 if (status) {
3577 /* status is FAILED */
3578 PM8001_FAIL_DBG(pm8001_ha,
3579 pm8001_printk("PhyProfile command failed with status "
3580 "0x%08X \n", status));
3581 return -1;
3582 } else {
3583 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3584 PM8001_FAIL_DBG(pm8001_ha,
3585 pm8001_printk("Invalid page code 0x%X\n",
3586 page_code));
3587 return -1;
3588 }
3589 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3590 return 0;
3591}
3592
3593/**
3594 * mpi_kek_management_resp - SPCv specific
3595 * @pm8001_ha: our hba card information
3596 * @piomb: IO message buffer
3597 */
3598static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3599 void *piomb)
3600{
3601 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3602
3603 u32 status = le32_to_cpu(pPayload->status);
3604 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3605 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3606
3607 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3608 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3609 status, kidx_new_curr_ksop, err_qlfr));
3610
3611 return 0;
3612}
3613
3614/**
3615 * mpi_dek_management_resp - SPCv specific
3616 * @pm8001_ha: our hba card information
3617 * @piomb: IO message buffer
3618 */
3619static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3620 void *piomb)
3621{
3622 PM8001_MSG_DBG(pm8001_ha,
3623 pm8001_printk(" pm80xx_addition_functionality\n"));
3624
3625 return 0;
3626}
3627
3628/**
3629 * ssp_coalesced_comp_resp - SPCv specific
3630 * @pm8001_ha: our hba card information
3631 * @piomb: IO message buffer
3632 */
3633static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3634 void *piomb)
3635{
3636 PM8001_MSG_DBG(pm8001_ha,
3637 pm8001_printk(" pm80xx_addition_functionality\n"));
3638
3639 return 0;
3640}
3641
3642/**
3643 * process_one_iomb - process one outbound Queue memory block
3644 * @pm8001_ha: our hba card information
3645 * @piomb: IO message buffer
3646 */
3647static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3648{
3649 __le32 pHeader = *(__le32 *)piomb;
3650 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3651
3652 switch (opc) {
3653 case OPC_OUB_ECHO:
3654 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3655 break;
3656 case OPC_OUB_HW_EVENT:
3657 PM8001_MSG_DBG(pm8001_ha,
3658 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3659 mpi_hw_event(pm8001_ha, piomb);
3660 break;
3661 case OPC_OUB_THERM_HW_EVENT:
3662 PM8001_MSG_DBG(pm8001_ha,
3663 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3664 mpi_thermal_hw_event(pm8001_ha, piomb);
3665 break;
3666 case OPC_OUB_SSP_COMP:
3667 PM8001_MSG_DBG(pm8001_ha,
3668 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3669 mpi_ssp_completion(pm8001_ha, piomb);
3670 break;
3671 case OPC_OUB_SMP_COMP:
3672 PM8001_MSG_DBG(pm8001_ha,
3673 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3674 mpi_smp_completion(pm8001_ha, piomb);
3675 break;
3676 case OPC_OUB_LOCAL_PHY_CNTRL:
3677 PM8001_MSG_DBG(pm8001_ha,
3678 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3679 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3680 break;
3681 case OPC_OUB_DEV_REGIST:
3682 PM8001_MSG_DBG(pm8001_ha,
3683 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3684 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3685 break;
3686 case OPC_OUB_DEREG_DEV:
3687 PM8001_MSG_DBG(pm8001_ha,
Masanari Iida8b513d02013-05-21 23:13:12 +0900[diff] [blame]3688 pm8001_printk("unregister the device\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3689 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3690 break;
3691 case OPC_OUB_GET_DEV_HANDLE:
3692 PM8001_MSG_DBG(pm8001_ha,
3693 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3694 break;
3695 case OPC_OUB_SATA_COMP:
3696 PM8001_MSG_DBG(pm8001_ha,
3697 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3698 mpi_sata_completion(pm8001_ha, piomb);
3699 break;
3700 case OPC_OUB_SATA_EVENT:
3701 PM8001_MSG_DBG(pm8001_ha,
3702 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3703 mpi_sata_event(pm8001_ha, piomb);
3704 break;
3705 case OPC_OUB_SSP_EVENT:
3706 PM8001_MSG_DBG(pm8001_ha,
3707 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3708 mpi_ssp_event(pm8001_ha, piomb);
3709 break;
3710 case OPC_OUB_DEV_HANDLE_ARRIV:
3711 PM8001_MSG_DBG(pm8001_ha,
3712 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3713 /*This is for target*/
3714 break;
3715 case OPC_OUB_SSP_RECV_EVENT:
3716 PM8001_MSG_DBG(pm8001_ha,
3717 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3718 /*This is for target*/
3719 break;
3720 case OPC_OUB_FW_FLASH_UPDATE:
3721 PM8001_MSG_DBG(pm8001_ha,
3722 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3723 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3724 break;
3725 case OPC_OUB_GPIO_RESPONSE:
3726 PM8001_MSG_DBG(pm8001_ha,
3727 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3728 break;
3729 case OPC_OUB_GPIO_EVENT:
3730 PM8001_MSG_DBG(pm8001_ha,
3731 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3732 break;
3733 case OPC_OUB_GENERAL_EVENT:
3734 PM8001_MSG_DBG(pm8001_ha,
3735 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3736 pm8001_mpi_general_event(pm8001_ha, piomb);
3737 break;
3738 case OPC_OUB_SSP_ABORT_RSP:
3739 PM8001_MSG_DBG(pm8001_ha,
3740 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3741 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3742 break;
3743 case OPC_OUB_SATA_ABORT_RSP:
3744 PM8001_MSG_DBG(pm8001_ha,
3745 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3746 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3747 break;
3748 case OPC_OUB_SAS_DIAG_MODE_START_END:
3749 PM8001_MSG_DBG(pm8001_ha,
3750 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3751 break;
3752 case OPC_OUB_SAS_DIAG_EXECUTE:
3753 PM8001_MSG_DBG(pm8001_ha,
3754 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3755 break;
3756 case OPC_OUB_GET_TIME_STAMP:
3757 PM8001_MSG_DBG(pm8001_ha,
3758 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3759 break;
3760 case OPC_OUB_SAS_HW_EVENT_ACK:
3761 PM8001_MSG_DBG(pm8001_ha,
3762 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3763 break;
3764 case OPC_OUB_PORT_CONTROL:
3765 PM8001_MSG_DBG(pm8001_ha,
3766 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3767 break;
3768 case OPC_OUB_SMP_ABORT_RSP:
3769 PM8001_MSG_DBG(pm8001_ha,
3770 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3771 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3772 break;
3773 case OPC_OUB_GET_NVMD_DATA:
3774 PM8001_MSG_DBG(pm8001_ha,
3775 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3776 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3777 break;
3778 case OPC_OUB_SET_NVMD_DATA:
3779 PM8001_MSG_DBG(pm8001_ha,
3780 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3781 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3782 break;
3783 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3784 PM8001_MSG_DBG(pm8001_ha,
3785 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3786 break;
3787 case OPC_OUB_SET_DEVICE_STATE:
3788 PM8001_MSG_DBG(pm8001_ha,
3789 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3790 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3791 break;
3792 case OPC_OUB_GET_DEVICE_STATE:
3793 PM8001_MSG_DBG(pm8001_ha,
3794 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3795 break;
3796 case OPC_OUB_SET_DEV_INFO:
3797 PM8001_MSG_DBG(pm8001_ha,
3798 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3799 break;
3800 /* spcv specifc commands */
3801 case OPC_OUB_PHY_START_RESP:
3802 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3803 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3804 mpi_phy_start_resp(pm8001_ha, piomb);
3805 break;
3806 case OPC_OUB_PHY_STOP_RESP:
3807 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3808 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3809 mpi_phy_stop_resp(pm8001_ha, piomb);
3810 break;
3811 case OPC_OUB_SET_CONTROLLER_CONFIG:
3812 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3813 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3814 mpi_set_controller_config_resp(pm8001_ha, piomb);
3815 break;
3816 case OPC_OUB_GET_CONTROLLER_CONFIG:
3817 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3818 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3819 mpi_get_controller_config_resp(pm8001_ha, piomb);
3820 break;
3821 case OPC_OUB_GET_PHY_PROFILE:
3822 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3823 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3824 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3825 break;
3826 case OPC_OUB_FLASH_OP_EXT:
3827 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3828 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3829 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3830 break;
3831 case OPC_OUB_SET_PHY_PROFILE:
3832 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3833 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3834 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3835 break;
3836 case OPC_OUB_KEK_MANAGEMENT_RESP:
3837 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3838 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3839 mpi_kek_management_resp(pm8001_ha, piomb);
3840 break;
3841 case OPC_OUB_DEK_MANAGEMENT_RESP:
3842 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3843 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3844 mpi_dek_management_resp(pm8001_ha, piomb);
3845 break;
3846 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3847 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3848 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3849 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3850 break;
3851 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3852 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3853 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3854 break;
3855 }
3856}
3857
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3858static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3859{
3860 PM8001_FAIL_DBG(pm8001_ha,
3861 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
3862 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
3863 PM8001_FAIL_DBG(pm8001_ha,
3864 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
3865 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
3866 PM8001_FAIL_DBG(pm8001_ha,
3867 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
3868 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
3869 PM8001_FAIL_DBG(pm8001_ha,
3870 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
3871 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
3872 PM8001_FAIL_DBG(pm8001_ha,
3873 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
3874 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
3875 PM8001_FAIL_DBG(pm8001_ha,
3876 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
3877 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
3878 PM8001_FAIL_DBG(pm8001_ha,
3879 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
3880 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
3881 PM8001_FAIL_DBG(pm8001_ha,
3882 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
3883 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
3884 PM8001_FAIL_DBG(pm8001_ha,
3885 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
3886 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
3887 PM8001_FAIL_DBG(pm8001_ha,
3888 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
3889 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
3890 PM8001_FAIL_DBG(pm8001_ha,
3891 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
3892 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
3893 PM8001_FAIL_DBG(pm8001_ha,
3894 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
3895 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
3896}
3897
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3898static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3899{
3900 struct outbound_queue_table *circularQ;
3901 void *pMsg1 = NULL;
3902 u8 uninitialized_var(bc);
3903 u32 ret = MPI_IO_STATUS_FAIL;
3904 unsigned long flags;
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3905 u32 regval;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3906
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3907 if (vec == (pm8001_ha->number_of_intr - 1)) {
3908 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
3909 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
3910 SCRATCH_PAD_MIPSALL_READY) {
3911 pm8001_ha->controller_fatal_error = true;
3912 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3913 "Firmware Fatal error! Regval:0x%x\n", regval));
3914 print_scratchpad_registers(pm8001_ha);
3915 return ret;
3916 }
3917 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3918 spin_lock_irqsave(&pm8001_ha->lock, flags);
3919 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3920 do {
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3921 /* spurious interrupt during setup if kexec-ing and
3922 * driver doing a doorbell access w/ the pre-kexec oq
3923 * interrupt setup.
3924 */
3925 if (!circularQ->pi_virt)
3926 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3927 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3928 if (MPI_IO_STATUS_SUCCESS == ret) {
3929 /* process the outbound message */
3930 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3931 /* free the message from the outbound circular buffer */
3932 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3933 circularQ, bc);
3934 }
3935 if (MPI_IO_STATUS_BUSY == ret) {
3936 /* Update the producer index from SPC */
3937 circularQ->producer_index =
3938 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3939 if (le32_to_cpu(circularQ->producer_index) ==
3940 circularQ->consumer_idx)
3941 /* OQ is empty */
3942 break;
3943 }
3944 } while (1);
3945 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3946 return ret;
3947}
3948
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]3949/* DMA_... to our direction translation. */
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3950static const u8 data_dir_flags[] = {
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]3951 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
3952 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
3953 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
3954 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3955};
3956
3957static void build_smp_cmd(u32 deviceID, __le32 hTag,
3958 struct smp_req *psmp_cmd, int mode, int length)
3959{
3960 psmp_cmd->tag = hTag;
3961 psmp_cmd->device_id = cpu_to_le32(deviceID);
3962 if (mode == SMP_DIRECT) {
3963 length = length - 4; /* subtract crc */
3964 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3965 } else {
3966 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3967 }
3968}
3969
3970/**
3971 * pm8001_chip_smp_req - send a SMP task to FW
3972 * @pm8001_ha: our hba card information.
3973 * @ccb: the ccb information this request used.
3974 */
3975static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3976 struct pm8001_ccb_info *ccb)
3977{
3978 int elem, rc;
3979 struct sas_task *task = ccb->task;
3980 struct domain_device *dev = task->dev;
3981 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3982 struct scatterlist *sg_req, *sg_resp;
3983 u32 req_len, resp_len;
3984 struct smp_req smp_cmd;
3985 u32 opc;
3986 struct inbound_queue_table *circularQ;
3987 char *preq_dma_addr = NULL;
3988 __le64 tmp_addr;
3989 u32 i, length;
3990
3991 memset(&smp_cmd, 0, sizeof(smp_cmd));
3992 /*
3993 * DMA-map SMP request, response buffers
3994 */
3995 sg_req = &task->smp_task.smp_req;
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]3996 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3997 if (!elem)
3998 return -ENOMEM;
3999 req_len = sg_dma_len(sg_req);
4000
4001 sg_resp = &task->smp_task.smp_resp;
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4002 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4003 if (!elem) {
4004 rc = -ENOMEM;
4005 goto err_out;
4006 }
4007 resp_len = sg_dma_len(sg_resp);
4008 /* must be in dwords */
4009 if ((req_len & 0x3) || (resp_len & 0x3)) {
4010 rc = -EINVAL;
4011 goto err_out_2;
4012 }
4013
4014 opc = OPC_INB_SMP_REQUEST;
4015 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4016 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4017
4018 length = sg_req->length;
4019 PM8001_IO_DBG(pm8001_ha,
4020 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4021 if (!(length - 8))
4022 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4023 else
4024 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4025
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4026
4027 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4028 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4029
4030 /* INDIRECT MODE command settings. Use DMA */
4031 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4032 PM8001_IO_DBG(pm8001_ha,
4033 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4034 /* for SPCv indirect mode. Place the top 4 bytes of
4035 * SMP Request header here. */
4036 for (i = 0; i < 4; i++)
4037 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4038 /* exclude top 4 bytes for SMP req header */
4039 smp_cmd.long_smp_req.long_req_addr =
4040 cpu_to_le64((u64)sg_dma_address
Anand Kumar Santhanamcb993e52013-09-17 14:37:14 +0530[diff] [blame]4041 (&task->smp_task.smp_req) + 4);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4042 /* exclude 4 bytes for SMP req header and CRC */
4043 smp_cmd.long_smp_req.long_req_size =
4044 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4045 smp_cmd.long_smp_req.long_resp_addr =
4046 cpu_to_le64((u64)sg_dma_address
4047 (&task->smp_task.smp_resp));
4048 smp_cmd.long_smp_req.long_resp_size =
4049 cpu_to_le32((u32)sg_dma_len
4050 (&task->smp_task.smp_resp)-4);
4051 } else { /* DIRECT MODE */
4052 smp_cmd.long_smp_req.long_req_addr =
4053 cpu_to_le64((u64)sg_dma_address
4054 (&task->smp_task.smp_req));
4055 smp_cmd.long_smp_req.long_req_size =
4056 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4057 smp_cmd.long_smp_req.long_resp_addr =
4058 cpu_to_le64((u64)sg_dma_address
4059 (&task->smp_task.smp_resp));
4060 smp_cmd.long_smp_req.long_resp_size =
4061 cpu_to_le32
4062 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4063 }
4064 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4065 PM8001_IO_DBG(pm8001_ha,
4066 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4067 for (i = 0; i < length; i++)
4068 if (i < 16) {
4069 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4070 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4071 "Byte[%d]:%x (DMA data:%x)\n",
4072 i, smp_cmd.smp_req16[i],
4073 *(preq_dma_addr)));
4074 } else {
4075 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4076 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4077 "Byte[%d]:%x (DMA data:%x)\n",
4078 i, smp_cmd.smp_req[i],
4079 *(preq_dma_addr)));
4080 }
4081 }
4082
4083 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4084 &smp_cmd, pm8001_ha->smp_exp_mode, length);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4085 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4086 (u32 *)&smp_cmd, 0);
4087 if (rc)
4088 goto err_out_2;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4089 return 0;
4090
4091err_out_2:
4092 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4093 DMA_FROM_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4094err_out:
4095 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4096 DMA_TO_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4097 return rc;
4098}
4099
4100static int check_enc_sas_cmd(struct sas_task *task)
4101{
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4102 u8 cmd = task->ssp_task.cmd->cmnd[0];
4103
4104 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4105 return 1;
4106 else
4107 return 0;
4108}
4109
4110static int check_enc_sat_cmd(struct sas_task *task)
4111{
4112 int ret = 0;
4113 switch (task->ata_task.fis.command) {
4114 case ATA_CMD_FPDMA_READ:
4115 case ATA_CMD_READ_EXT:
4116 case ATA_CMD_READ:
4117 case ATA_CMD_FPDMA_WRITE:
4118 case ATA_CMD_WRITE_EXT:
4119 case ATA_CMD_WRITE:
4120 case ATA_CMD_PIO_READ:
4121 case ATA_CMD_PIO_READ_EXT:
4122 case ATA_CMD_PIO_WRITE:
4123 case ATA_CMD_PIO_WRITE_EXT:
4124 ret = 1;
4125 break;
4126 default:
4127 ret = 0;
4128 break;
4129 }
4130 return ret;
4131}
4132
4133/**
4134 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4135 * @pm8001_ha: our hba card information.
4136 * @ccb: the ccb information this request used.
4137 */
4138static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4139 struct pm8001_ccb_info *ccb)
4140{
4141 struct sas_task *task = ccb->task;
4142 struct domain_device *dev = task->dev;
4143 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4144 struct ssp_ini_io_start_req ssp_cmd;
4145 u32 tag = ccb->ccb_tag;
4146 int ret;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4147 u64 phys_addr, start_addr, end_addr;
4148 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4149 struct inbound_queue_table *circularQ;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4150 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4151 u32 opc = OPC_INB_SSPINIIOSTART;
4152 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4153 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4154 /* data address domain added for spcv; set to 0 by host,
4155 * used internally by controller
4156 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4157 */
4158 ssp_cmd.dad_dir_m_tlr =
4159 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4160 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4161 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4162 ssp_cmd.tag = cpu_to_le32(tag);
4163 if (task->ssp_task.enable_first_burst)
4164 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4165 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4166 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4167 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4168 task->ssp_task.cmd->cmd_len);
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4169 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4170 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4171
4172 /* Check if encryption is set */
4173 if (pm8001_ha->chip->encrypt &&
4174 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4175 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4176 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4177 task->ssp_task.cmd->cmnd[0]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4178 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4179 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4180 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4181 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4182
4183 /* fill in PRD (scatter/gather) table, if any */
4184 if (task->num_scatter > 1) {
4185 pm8001_chip_make_sg(task->scatter,
4186 ccb->n_elem, ccb->buf_prd);
4187 phys_addr = ccb->ccb_dma_handle +
4188 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4189 ssp_cmd.enc_addr_low =
4190 cpu_to_le32(lower_32_bits(phys_addr));
4191 ssp_cmd.enc_addr_high =
4192 cpu_to_le32(upper_32_bits(phys_addr));
4193 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4194 } else if (task->num_scatter == 1) {
4195 u64 dma_addr = sg_dma_address(task->scatter);
4196 ssp_cmd.enc_addr_low =
4197 cpu_to_le32(lower_32_bits(dma_addr));
4198 ssp_cmd.enc_addr_high =
4199 cpu_to_le32(upper_32_bits(dma_addr));
4200 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4201 ssp_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4202 /* Check 4G Boundary */
4203 start_addr = cpu_to_le64(dma_addr);
4204 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4205 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4206 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4207 if (end_addr_high != ssp_cmd.enc_addr_high) {
4208 PM8001_FAIL_DBG(pm8001_ha,
4209 pm8001_printk("The sg list address "
4210 "start_addr=0x%016llx data_len=0x%x "
4211 "end_addr_high=0x%08x end_addr_low="
4212 "0x%08x has crossed 4G boundary\n",
4213 start_addr, ssp_cmd.enc_len,
4214 end_addr_high, end_addr_low));
4215 pm8001_chip_make_sg(task->scatter, 1,
4216 ccb->buf_prd);
4217 phys_addr = ccb->ccb_dma_handle +
4218 offsetof(struct pm8001_ccb_info,
4219 buf_prd[0]);
4220 ssp_cmd.enc_addr_low =
4221 cpu_to_le32(lower_32_bits(phys_addr));
4222 ssp_cmd.enc_addr_high =
4223 cpu_to_le32(upper_32_bits(phys_addr));
4224 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4225 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4226 } else if (task->num_scatter == 0) {
4227 ssp_cmd.enc_addr_low = 0;
4228 ssp_cmd.enc_addr_high = 0;
4229 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4230 ssp_cmd.enc_esgl = 0;
4231 }
4232 /* XTS mode. All other fields are 0 */
4233 ssp_cmd.key_cmode = 0x6 << 4;
4234 /* set tweak values. Should be the start lba */
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4235 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4236 (task->ssp_task.cmd->cmnd[3] << 16) |
4237 (task->ssp_task.cmd->cmnd[4] << 8) |
4238 (task->ssp_task.cmd->cmnd[5]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4239 } else {
4240 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4241 "Sending Normal SAS command 0x%x inb q %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4242 task->ssp_task.cmd->cmnd[0], q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4243 /* fill in PRD (scatter/gather) table, if any */
4244 if (task->num_scatter > 1) {
4245 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4246 ccb->buf_prd);
4247 phys_addr = ccb->ccb_dma_handle +
4248 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4249 ssp_cmd.addr_low =
4250 cpu_to_le32(lower_32_bits(phys_addr));
4251 ssp_cmd.addr_high =
4252 cpu_to_le32(upper_32_bits(phys_addr));
4253 ssp_cmd.esgl = cpu_to_le32(1<<31);
4254 } else if (task->num_scatter == 1) {
4255 u64 dma_addr = sg_dma_address(task->scatter);
4256 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4257 ssp_cmd.addr_high =
4258 cpu_to_le32(upper_32_bits(dma_addr));
4259 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4260 ssp_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4261 /* Check 4G Boundary */
4262 start_addr = cpu_to_le64(dma_addr);
4263 end_addr = (start_addr + ssp_cmd.len) - 1;
4264 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4265 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4266 if (end_addr_high != ssp_cmd.addr_high) {
4267 PM8001_FAIL_DBG(pm8001_ha,
4268 pm8001_printk("The sg list address "
4269 "start_addr=0x%016llx data_len=0x%x "
4270 "end_addr_high=0x%08x end_addr_low="
4271 "0x%08x has crossed 4G boundary\n",
4272 start_addr, ssp_cmd.len,
4273 end_addr_high, end_addr_low));
4274 pm8001_chip_make_sg(task->scatter, 1,
4275 ccb->buf_prd);
4276 phys_addr = ccb->ccb_dma_handle +
4277 offsetof(struct pm8001_ccb_info,
4278 buf_prd[0]);
4279 ssp_cmd.addr_low =
4280 cpu_to_le32(lower_32_bits(phys_addr));
4281 ssp_cmd.addr_high =
4282 cpu_to_le32(upper_32_bits(phys_addr));
4283 ssp_cmd.esgl = cpu_to_le32(1<<31);
4284 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4285 } else if (task->num_scatter == 0) {
4286 ssp_cmd.addr_low = 0;
4287 ssp_cmd.addr_high = 0;
4288 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4289 ssp_cmd.esgl = 0;
4290 }
4291 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4292 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4293 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4294 &ssp_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4295 return ret;
4296}
4297
4298static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4299 struct pm8001_ccb_info *ccb)
4300{
4301 struct sas_task *task = ccb->task;
4302 struct domain_device *dev = task->dev;
4303 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4304 u32 tag = ccb->ccb_tag;
4305 int ret;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4306 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4307 struct sata_start_req sata_cmd;
4308 u32 hdr_tag, ncg_tag = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4309 u64 phys_addr, start_addr, end_addr;
4310 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4311 u32 ATAP = 0x0;
4312 u32 dir;
4313 struct inbound_queue_table *circularQ;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4314 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4315 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4316 memset(&sata_cmd, 0, sizeof(sata_cmd));
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4317 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4318 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4319
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4320 if (task->data_dir == DMA_NONE) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4321 ATAP = 0x04; /* no data*/
4322 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4323 } else if (likely(!task->ata_task.device_control_reg_update)) {
4324 if (task->ata_task.dma_xfer) {
4325 ATAP = 0x06; /* DMA */
4326 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4327 } else {
4328 ATAP = 0x05; /* PIO*/
4329 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4330 }
4331 if (task->ata_task.use_ncq &&
Hannes Reinecke1cbd7722014-11-05 13:08:20 +0100[diff] [blame]4332 dev->sata_dev.class != ATA_DEV_ATAPI) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4333 ATAP = 0x07; /* FPDMA */
4334 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4335 }
4336 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4337 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4338 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4339 ncg_tag = hdr_tag;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4340 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4341 dir = data_dir_flags[task->data_dir] << 8;
4342 sata_cmd.tag = cpu_to_le32(tag);
4343 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4344 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4345
4346 sata_cmd.sata_fis = task->ata_task.fis;
4347 if (likely(!task->ata_task.device_control_reg_update))
4348 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4349 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4350
4351 /* Check if encryption is set */
4352 if (pm8001_ha->chip->encrypt &&
4353 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4354 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4355 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4356 sata_cmd.sata_fis.command));
4357 opc = OPC_INB_SATA_DIF_ENC_IO;
4358
4359 /* set encryption bit */
4360 sata_cmd.ncqtag_atap_dir_m_dad =
4361 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4362 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4363 /* dad (bit 0-1) is 0 */
4364 /* fill in PRD (scatter/gather) table, if any */
4365 if (task->num_scatter > 1) {
4366 pm8001_chip_make_sg(task->scatter,
4367 ccb->n_elem, ccb->buf_prd);
4368 phys_addr = ccb->ccb_dma_handle +
4369 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4370 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4371 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4372 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4373 } else if (task->num_scatter == 1) {
4374 u64 dma_addr = sg_dma_address(task->scatter);
4375 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4376 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4377 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4378 sata_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4379 /* Check 4G Boundary */
4380 start_addr = cpu_to_le64(dma_addr);
4381 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4382 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4383 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4384 if (end_addr_high != sata_cmd.enc_addr_high) {
4385 PM8001_FAIL_DBG(pm8001_ha,
4386 pm8001_printk("The sg list address "
4387 "start_addr=0x%016llx data_len=0x%x "
4388 "end_addr_high=0x%08x end_addr_low"
4389 "=0x%08x has crossed 4G boundary\n",
4390 start_addr, sata_cmd.enc_len,
4391 end_addr_high, end_addr_low));
4392 pm8001_chip_make_sg(task->scatter, 1,
4393 ccb->buf_prd);
4394 phys_addr = ccb->ccb_dma_handle +
4395 offsetof(struct pm8001_ccb_info,
4396 buf_prd[0]);
4397 sata_cmd.enc_addr_low =
4398 lower_32_bits(phys_addr);
4399 sata_cmd.enc_addr_high =
4400 upper_32_bits(phys_addr);
4401 sata_cmd.enc_esgl =
4402 cpu_to_le32(1 << 31);
4403 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4404 } else if (task->num_scatter == 0) {
4405 sata_cmd.enc_addr_low = 0;
4406 sata_cmd.enc_addr_high = 0;
4407 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4408 sata_cmd.enc_esgl = 0;
4409 }
4410 /* XTS mode. All other fields are 0 */
4411 sata_cmd.key_index_mode = 0x6 << 4;
4412 /* set tweak values. Should be the start lba */
4413 sata_cmd.twk_val0 =
4414 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4415 (sata_cmd.sata_fis.lbah << 16) |
4416 (sata_cmd.sata_fis.lbam << 8) |
4417 (sata_cmd.sata_fis.lbal));
4418 sata_cmd.twk_val1 =
4419 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4420 (sata_cmd.sata_fis.lbam_exp));
4421 } else {
4422 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4423 "Sending Normal SATA command 0x%x inb %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4424 sata_cmd.sata_fis.command, q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4425 /* dad (bit 0-1) is 0 */
4426 sata_cmd.ncqtag_atap_dir_m_dad =
4427 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4428 ((ATAP & 0x3f) << 10) | dir);
4429
4430 /* fill in PRD (scatter/gather) table, if any */
4431 if (task->num_scatter > 1) {
4432 pm8001_chip_make_sg(task->scatter,
4433 ccb->n_elem, ccb->buf_prd);
4434 phys_addr = ccb->ccb_dma_handle +
4435 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4436 sata_cmd.addr_low = lower_32_bits(phys_addr);
4437 sata_cmd.addr_high = upper_32_bits(phys_addr);
4438 sata_cmd.esgl = cpu_to_le32(1 << 31);
4439 } else if (task->num_scatter == 1) {
4440 u64 dma_addr = sg_dma_address(task->scatter);
4441 sata_cmd.addr_low = lower_32_bits(dma_addr);
4442 sata_cmd.addr_high = upper_32_bits(dma_addr);
4443 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4444 sata_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4445 /* Check 4G Boundary */
4446 start_addr = cpu_to_le64(dma_addr);
4447 end_addr = (start_addr + sata_cmd.len) - 1;
4448 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4449 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4450 if (end_addr_high != sata_cmd.addr_high) {
4451 PM8001_FAIL_DBG(pm8001_ha,
4452 pm8001_printk("The sg list address "
4453 "start_addr=0x%016llx data_len=0x%x"
4454 "end_addr_high=0x%08x end_addr_low="
4455 "0x%08x has crossed 4G boundary\n",
4456 start_addr, sata_cmd.len,
4457 end_addr_high, end_addr_low));
4458 pm8001_chip_make_sg(task->scatter, 1,
4459 ccb->buf_prd);
4460 phys_addr = ccb->ccb_dma_handle +
4461 offsetof(struct pm8001_ccb_info,
4462 buf_prd[0]);
4463 sata_cmd.addr_low =
4464 lower_32_bits(phys_addr);
4465 sata_cmd.addr_high =
4466 upper_32_bits(phys_addr);
4467 sata_cmd.esgl = cpu_to_le32(1 << 31);
4468 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4469 } else if (task->num_scatter == 0) {
4470 sata_cmd.addr_low = 0;
4471 sata_cmd.addr_high = 0;
4472 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4473 sata_cmd.esgl = 0;
4474 }
Colin Ian King9e2a07e2019-03-17 18:15:32 +0000[diff] [blame]4475 /* scsi cdb */
4476 sata_cmd.atapi_scsi_cdb[0] =
4477 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4478 (task->ata_task.atapi_packet[1] << 8) |
4479 (task->ata_task.atapi_packet[2] << 16) |
4480 (task->ata_task.atapi_packet[3] << 24)));
4481 sata_cmd.atapi_scsi_cdb[1] =
4482 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4483 (task->ata_task.atapi_packet[5] << 8) |
4484 (task->ata_task.atapi_packet[6] << 16) |
4485 (task->ata_task.atapi_packet[7] << 24)));
4486 sata_cmd.atapi_scsi_cdb[2] =
4487 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4488 (task->ata_task.atapi_packet[9] << 8) |
4489 (task->ata_task.atapi_packet[10] << 16) |
4490 (task->ata_task.atapi_packet[11] << 24)));
4491 sata_cmd.atapi_scsi_cdb[3] =
4492 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4493 (task->ata_task.atapi_packet[13] << 8) |
4494 (task->ata_task.atapi_packet[14] << 16) |
4495 (task->ata_task.atapi_packet[15] << 24)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4496 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4497
4498 /* Check for read log for failed drive and return */
4499 if (sata_cmd.sata_fis.command == 0x2f) {
4500 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4501 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4502 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4503 struct task_status_struct *ts;
4504
4505 pm8001_ha_dev->id &= 0xDFFFFFFF;
4506 ts = &task->task_status;
4507
4508 spin_lock_irqsave(&task->task_state_lock, flags);
4509 ts->resp = SAS_TASK_COMPLETE;
4510 ts->stat = SAM_STAT_GOOD;
4511 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4512 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4513 task->task_state_flags |= SAS_TASK_STATE_DONE;
4514 if (unlikely((task->task_state_flags &
4515 SAS_TASK_STATE_ABORTED))) {
4516 spin_unlock_irqrestore(&task->task_state_lock,
4517 flags);
4518 PM8001_FAIL_DBG(pm8001_ha,
4519 pm8001_printk("task 0x%p resp 0x%x "
4520 " stat 0x%x but aborted by upper layer "
4521 "\n", task, ts->resp, ts->stat));
4522 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4523 return 0;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]4524 } else {
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4525 spin_unlock_irqrestore(&task->task_state_lock,
4526 flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]4527 pm8001_ccb_task_free_done(pm8001_ha, task,
4528 ccb, tag);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4529 return 0;
4530 }
4531 }
4532 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4533 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4534 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4535 &sata_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4536 return ret;
4537}
4538
4539/**
4540 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4541 * @pm8001_ha: our hba card information.
4542 * @num: the inbound queue number
4543 * @phy_id: the phy id which we wanted to start up.
4544 */
4545static int
4546pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4547{
4548 struct phy_start_req payload;
4549 struct inbound_queue_table *circularQ;
4550 int ret;
4551 u32 tag = 0x01;
4552 u32 opcode = OPC_INB_PHYSTART;
4553 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4554 memset(&payload, 0, sizeof(payload));
4555 payload.tag = cpu_to_le32(tag);
4556
4557 PM8001_INIT_DBG(pm8001_ha,
4558 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4559 /*
4560 ** [0:7] PHY Identifier
4561 ** [8:11] link rate 1.5G, 3G, 6G
4562 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4563 ** [14] 0b disable spin up hold; 1b enable spin up hold
4564 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4565 */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]4566 if (!IS_SPCV_12G(pm8001_ha->pdev))
4567 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4568 LINKMODE_AUTO | LINKRATE_15 |
4569 LINKRATE_30 | LINKRATE_60 | phy_id);
4570 else
4571 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4572 LINKMODE_AUTO | LINKRATE_15 |
4573 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4574 phy_id);
4575
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4576 /* SSC Disable and SAS Analog ST configuration */
4577 /**
4578 payload.ase_sh_lm_slr_phyid =
4579 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4580 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4581 phy_id);
4582 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4583 **/
4584
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4585 payload.sas_identify.dev_type = SAS_END_DEVICE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4586 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4587 memcpy(payload.sas_identify.sas_addr,
Viswas G6c85e4b2017-10-18 11:39:09 +0530[diff] [blame]4588 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4589 payload.sas_identify.phy_id = phy_id;
4590 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4591 return ret;
4592}
4593
4594/**
4595 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4596 * @pm8001_ha: our hba card information.
4597 * @num: the inbound queue number
4598 * @phy_id: the phy id which we wanted to start up.
4599 */
4600static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4601 u8 phy_id)
4602{
4603 struct phy_stop_req payload;
4604 struct inbound_queue_table *circularQ;
4605 int ret;
4606 u32 tag = 0x01;
4607 u32 opcode = OPC_INB_PHYSTOP;
4608 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4609 memset(&payload, 0, sizeof(payload));
4610 payload.tag = cpu_to_le32(tag);
4611 payload.phy_id = cpu_to_le32(phy_id);
4612 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4613 return ret;
4614}
4615
4616/**
4617 * see comments on pm8001_mpi_reg_resp.
4618 */
4619static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4620 struct pm8001_device *pm8001_dev, u32 flag)
4621{
4622 struct reg_dev_req payload;
4623 u32 opc;
4624 u32 stp_sspsmp_sata = 0x4;
4625 struct inbound_queue_table *circularQ;
4626 u32 linkrate, phy_id;
4627 int rc, tag = 0xdeadbeef;
4628 struct pm8001_ccb_info *ccb;
4629 u8 retryFlag = 0x1;
4630 u16 firstBurstSize = 0;
4631 u16 ITNT = 2000;
4632 struct domain_device *dev = pm8001_dev->sas_device;
4633 struct domain_device *parent_dev = dev->parent;
4634 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4635
4636 memset(&payload, 0, sizeof(payload));
4637 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4638 if (rc)
4639 return rc;
4640 ccb = &pm8001_ha->ccb_info[tag];
4641 ccb->device = pm8001_dev;
4642 ccb->ccb_tag = tag;
4643 payload.tag = cpu_to_le32(tag);
4644
4645 if (flag == 1) {
4646 stp_sspsmp_sata = 0x02; /*direct attached sata */
4647 } else {
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4648 if (pm8001_dev->dev_type == SAS_SATA_DEV)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4649 stp_sspsmp_sata = 0x00; /* stp*/
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4650 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4651 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4652 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4653 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4654 }
John Garry924a3542019-06-10 20:41:41 +0800[diff] [blame]4655 if (parent_dev && dev_is_expander(parent_dev->dev_type))
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4656 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4657 else
4658 phy_id = pm8001_dev->attached_phy;
4659
4660 opc = OPC_INB_REG_DEV;
4661
4662 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4663 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4664
4665 payload.phyid_portid =
4666 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4667 ((phy_id & 0xFF) << 8));
4668
4669 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4670 ((linkrate & 0x0F) << 24) |
4671 ((stp_sspsmp_sata & 0x03) << 28));
4672 payload.firstburstsize_ITNexustimeout =
4673 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4674
4675 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4676 SAS_ADDR_SIZE);
4677
4678 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4679 if (rc)
4680 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4681
4682 return rc;
4683}
4684
4685/**
4686 * pm80xx_chip_phy_ctl_req - support the local phy operation
4687 * @pm8001_ha: our hba card information.
4688 * @num: the inbound queue number
4689 * @phy_id: the phy id which we wanted to operate
4690 * @phy_op:
4691 */
4692static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4693 u32 phyId, u32 phy_op)
4694{
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4695 u32 tag;
4696 int rc;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4697 struct local_phy_ctl_req payload;
4698 struct inbound_queue_table *circularQ;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4699 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4700 memset(&payload, 0, sizeof(payload));
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4701 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4702 if (rc)
4703 return rc;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4704 circularQ = &pm8001_ha->inbnd_q_tbl[0];
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4705 payload.tag = cpu_to_le32(tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4706 payload.phyop_phyid =
4707 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4708 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4709}
4710
Colin Ian Kingf310a4e2019-03-29 23:44:23 +0000[diff] [blame]4711static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4712{
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4713#ifdef PM8001_USE_MSIX
4714 return 1;
Colin Ian King292c04c2019-03-28 23:43:28 +0000[diff] [blame]4715#else
4716 u32 value;
4717
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4718 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4719 if (value)
4720 return 1;
4721 return 0;
Colin Ian King292c04c2019-03-28 23:43:28 +0000[diff] [blame]4722#endif
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4723}
4724
4725/**
4726 * pm8001_chip_isr - PM8001 isr handler.
4727 * @pm8001_ha: our hba card information.
4728 * @irq: irq number.
4729 * @stat: stat.
4730 */
4731static irqreturn_t
4732pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4733{
4734 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]4735 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4736 "irq vec %d, ODMR:0x%x\n",
4737 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4738 process_oq(pm8001_ha, vec);
4739 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4740 return IRQ_HANDLED;
4741}
4742
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4743void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4744 u32 operation, u32 phyid, u32 length, u32 *buf)
4745{
4746 u32 tag , i, j = 0;
4747 int rc;
4748 struct set_phy_profile_req payload;
4749 struct inbound_queue_table *circularQ;
4750 u32 opc = OPC_INB_SET_PHY_PROFILE;
4751
4752 memset(&payload, 0, sizeof(payload));
4753 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4754 if (rc)
4755 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4756 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4757 payload.tag = cpu_to_le32(tag);
4758 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4759 PM8001_INIT_DBG(pm8001_ha,
4760 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4761 payload.ppc_phyid, length));
4762 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4763 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4764 j++;
4765 }
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4766 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4767 if (rc)
4768 pm8001_tag_free(pm8001_ha, tag);
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4769}
4770
4771void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4772 u32 length, u8 *buf)
4773{
YueHaibingfdd0a662018-09-14 01:38:56 +0000[diff] [blame]4774 u32 i;
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4775
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4776 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4777 mpi_set_phy_profile_req(pm8001_ha,
4778 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4779 length = length + PHY_DWORD_LENGTH;
4780 }
4781 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4782}
Benjamin Roodc5614df2015-10-30 10:53:28 -0400[diff] [blame]4783
4784void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4785 u32 phy, u32 length, u32 *buf)
4786{
4787 u32 tag, opc;
4788 int rc, i;
4789 struct set_phy_profile_req payload;
4790 struct inbound_queue_table *circularQ;
4791
4792 memset(&payload, 0, sizeof(payload));
4793
4794 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4795 if (rc)
4796 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4797
4798 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4799 opc = OPC_INB_SET_PHY_PROFILE;
4800
4801 payload.tag = cpu_to_le32(tag);
4802 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4803 | (phy & 0xFF));
4804
4805 for (i = 0; i < length; i++)
4806 payload.reserved[i] = cpu_to_le32(*(buf + i));
4807
4808 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4809 if (rc)
4810 pm8001_tag_free(pm8001_ha, tag);
4811
4812 PM8001_INIT_DBG(pm8001_ha,
4813 pm8001_printk("PHY %d settings applied", phy));
4814}
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4815const struct pm8001_dispatch pm8001_80xx_dispatch = {
4816 .name = "pmc80xx",
4817 .chip_init = pm80xx_chip_init,
4818 .chip_soft_rst = pm80xx_chip_soft_rst,
4819 .chip_rst = pm80xx_hw_chip_rst,
4820 .chip_iounmap = pm8001_chip_iounmap,
4821 .isr = pm80xx_chip_isr,
Colin Ian Kingf310a4e2019-03-29 23:44:23 +0000[diff] [blame]4822 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4823 .isr_process_oq = process_oq,
4824 .interrupt_enable = pm80xx_chip_interrupt_enable,
4825 .interrupt_disable = pm80xx_chip_interrupt_disable,
4826 .make_prd = pm8001_chip_make_sg,
4827 .smp_req = pm80xx_chip_smp_req,
4828 .ssp_io_req = pm80xx_chip_ssp_io_req,
4829 .sata_req = pm80xx_chip_sata_req,
4830 .phy_start_req = pm80xx_chip_phy_start_req,
4831 .phy_stop_req = pm80xx_chip_phy_stop_req,
4832 .reg_dev_req = pm80xx_chip_reg_dev_req,
4833 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4834 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4835 .task_abort = pm8001_chip_abort_task,
4836 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4837 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4838 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4839 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4840 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4841};