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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / cb269c26ed027bea67f5961619ae43f480a4dd3d / . / drivers / scsi / pm8001 / pm80xx_hwi.c
blob: 0a2dc56ed9f6e950824133923f52b2c40ad4de83 [file] [log] [blame]
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48/**
49 * read_main_config_table - read the configure table and save it.
50 * @pm8001_ha: our hba card information
51 */
52static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53{
54 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
55
56 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
57 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
58 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
59 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
60 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
61 pm8001_mr32(address, MAIN_FW_REVISION);
62 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
63 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
64 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
65 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
67 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
68 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
69 pm8001_mr32(address, MAIN_GST_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
71 pm8001_mr32(address, MAIN_IBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
73 pm8001_mr32(address, MAIN_OBQ_OFFSET);
74
75 /* read Error Dump Offset and Length */
76 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
78 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
80 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
84
85 /* read GPIO LED settings from the configuration table */
86 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
87 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
88
89 /* read analog Setting offset from the configuration table */
90 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
91 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
92
93 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
94 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
95 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
96 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
97}
98
99/**
100 * read_general_status_table - read the general status table and save it.
101 * @pm8001_ha: our hba card information
102 */
103static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
104{
105 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
106 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
107 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
108 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
109 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
110 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
111 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
112 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
113 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
114 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
115 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
116 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
117 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
118 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
119 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
120 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
121 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
122 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
123 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
124 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
125 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
126 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
127 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
128 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
129 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
130 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
131 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
132 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
133 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
134}
135/**
136 * read_phy_attr_table - read the phy attribute table and save it.
137 * @pm8001_ha: our hba card information
138 */
139static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
140{
141 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
142 pm8001_ha->phy_attr_table.phystart1_16[0] =
143 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
144 pm8001_ha->phy_attr_table.phystart1_16[1] =
145 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
146 pm8001_ha->phy_attr_table.phystart1_16[2] =
147 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
148 pm8001_ha->phy_attr_table.phystart1_16[3] =
149 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
150 pm8001_ha->phy_attr_table.phystart1_16[4] =
151 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
152 pm8001_ha->phy_attr_table.phystart1_16[5] =
153 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
154 pm8001_ha->phy_attr_table.phystart1_16[6] =
155 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
156 pm8001_ha->phy_attr_table.phystart1_16[7] =
157 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
158 pm8001_ha->phy_attr_table.phystart1_16[8] =
159 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
160 pm8001_ha->phy_attr_table.phystart1_16[9] =
161 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
162 pm8001_ha->phy_attr_table.phystart1_16[10] =
163 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
164 pm8001_ha->phy_attr_table.phystart1_16[11] =
165 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
166 pm8001_ha->phy_attr_table.phystart1_16[12] =
167 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
168 pm8001_ha->phy_attr_table.phystart1_16[13] =
169 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
170 pm8001_ha->phy_attr_table.phystart1_16[14] =
171 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
172 pm8001_ha->phy_attr_table.phystart1_16[15] =
173 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
174
175 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
176 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
177 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
178 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
179 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
180 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
181 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
182 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
183 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
184 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
185 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
186 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
187 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
188 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
189 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
190 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
191 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
192 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
193 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
194 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
195 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
196 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
197 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
198 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
199 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
200 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
201 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
202 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
203 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
204 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
205 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
206 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
207
208}
209
210/**
211 * read_inbnd_queue_table - read the inbound queue table and save it.
212 * @pm8001_ha: our hba card information
213 */
214static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
215{
216 int i;
217 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
218 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
219 u32 offset = i * 0x20;
220 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
221 get_pci_bar_index(pm8001_mr32(address,
222 (offset + IB_PIPCI_BAR)));
223 pm8001_ha->inbnd_q_tbl[i].pi_offset =
224 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
225 }
226}
227
228/**
229 * read_outbnd_queue_table - read the outbound queue table and save it.
230 * @pm8001_ha: our hba card information
231 */
232static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
233{
234 int i;
235 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
236 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
237 u32 offset = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(address,
240 (offset + OB_CIPCI_BAR)));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
243 }
244}
245
246/**
247 * init_default_table_values - init the default table.
248 * @pm8001_ha: our hba card information
249 */
250static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
251{
252 int i;
253 u32 offsetib, offsetob;
254 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
255 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
256
257 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
258 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
259 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
260 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
261 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
262 PM8001_EVENT_LOG_SIZE;
263 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
264 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
265 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
266 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
267 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
268 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
269 PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
272
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]273 /* Disable end to end CRC checking */
274 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
275
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]276 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
277 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]278 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]279 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
280 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
281 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
282 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
283 pm8001_ha->inbnd_q_tbl[i].base_virt =
284 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
285 pm8001_ha->inbnd_q_tbl[i].total_length =
286 pm8001_ha->memoryMap.region[IB + i].total_len;
287 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
288 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
289 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
290 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
291 pm8001_ha->inbnd_q_tbl[i].ci_virt =
292 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
293 offsetib = i * 0x20;
294 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
295 get_pci_bar_index(pm8001_mr32(addressib,
296 (offsetib + 0x14)));
297 pm8001_ha->inbnd_q_tbl[i].pi_offset =
298 pm8001_mr32(addressib, (offsetib + 0x18));
299 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
300 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
301 }
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]304 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]305 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
306 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
307 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
308 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
309 pm8001_ha->outbnd_q_tbl[i].base_virt =
310 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
311 pm8001_ha->outbnd_q_tbl[i].total_length =
312 pm8001_ha->memoryMap.region[OB + i].total_len;
313 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
314 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
315 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
316 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
317 /* interrupt vector based on oq */
318 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
319 pm8001_ha->outbnd_q_tbl[i].pi_virt =
320 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
321 offsetob = i * 0x24;
322 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
323 get_pci_bar_index(pm8001_mr32(addressob,
324 offsetob + 0x14));
325 pm8001_ha->outbnd_q_tbl[i].ci_offset =
326 pm8001_mr32(addressob, (offsetob + 0x18));
327 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
328 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
329 }
330}
331
332/**
333 * update_main_config_table - update the main default table to the HBA.
334 * @pm8001_ha: our hba card information
335 */
336static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
337{
338 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
339 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
340 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
341 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
342 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
343 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
344 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
345 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
346 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
347 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
348 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
349 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
350 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
351 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
352 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
353 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
354 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
355 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
356 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
357 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
358 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]359 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
360 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]361
362 /* SPCv specific */
363 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
364 /* Set GPIOLED to 0x2 for LED indicator */
365 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
366 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
367 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
368
369 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
370 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
371 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
372 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
373}
374
375/**
376 * update_inbnd_queue_table - update the inbound queue table to the HBA.
377 * @pm8001_ha: our hba card information
378 */
379static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
380 int number)
381{
382 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
383 u16 offset = number * 0x20;
384 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
385 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
386 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
387 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
388 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
389 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
390 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
391 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
392 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
393 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
394}
395
396/**
397 * update_outbnd_queue_table - update the outbound queue table to the HBA.
398 * @pm8001_ha: our hba card information
399 */
400static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
401 int number)
402{
403 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
404 u16 offset = number * 0x24;
405 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
406 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
407 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
408 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
409 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
410 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
411 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
412 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
413 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
414 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
415 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
416 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
417}
418
419/**
420 * mpi_init_check - check firmware initialization status.
421 * @pm8001_ha: our hba card information
422 */
423static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
424{
425 u32 max_wait_count;
426 u32 value;
427 u32 gst_len_mpistate;
428
429 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
430 table is updated */
431 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
432 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]433 if (IS_SPCV_12G(pm8001_ha->pdev)) {
434 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
435 } else {
436 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
437 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]438 do {
439 udelay(1);
440 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
441 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
442 } while ((value != 0) && (--max_wait_count));
443
444 if (!max_wait_count)
445 return -1;
446 /* check the MPI-State for initialization upto 100ms*/
447 max_wait_count = 100 * 1000;/* 100 msec */
448 do {
449 udelay(1);
450 gst_len_mpistate =
451 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
452 GST_GSTLEN_MPIS_OFFSET);
453 } while ((GST_MPI_STATE_INIT !=
454 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
455 if (!max_wait_count)
456 return -1;
457
458 /* check MPI Initialization error */
459 gst_len_mpistate = gst_len_mpistate >> 16;
460 if (0x0000 != gst_len_mpistate)
461 return -1;
462
463 return 0;
464}
465
466/**
467 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
468 * @pm8001_ha: our hba card information
469 */
470static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
471{
472 u32 value;
473 u32 max_wait_count;
474 u32 max_wait_time;
475 int ret = 0;
476
477 /* reset / PCIe ready */
478 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
479 do {
480 udelay(1);
481 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
482 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
483
484 /* check ila status */
485 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
486 do {
487 udelay(1);
488 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
489 } while (((value & SCRATCH_PAD_ILA_READY) !=
490 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
491 if (!max_wait_count)
492 ret = -1;
493 else {
494 PM8001_MSG_DBG(pm8001_ha,
495 pm8001_printk(" ila ready status in %d millisec\n",
496 (max_wait_time - max_wait_count)));
497 }
498
499 /* check RAAE status */
500 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
501 do {
502 udelay(1);
503 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
504 } while (((value & SCRATCH_PAD_RAAE_READY) !=
505 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
506 if (!max_wait_count)
507 ret = -1;
508 else {
509 PM8001_MSG_DBG(pm8001_ha,
510 pm8001_printk(" raae ready status in %d millisec\n",
511 (max_wait_time - max_wait_count)));
512 }
513
514 /* check iop0 status */
515 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
516 do {
517 udelay(1);
518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
519 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
520 (--max_wait_count));
521 if (!max_wait_count)
522 ret = -1;
523 else {
524 PM8001_MSG_DBG(pm8001_ha,
525 pm8001_printk(" iop0 ready status in %d millisec\n",
526 (max_wait_time - max_wait_count)));
527 }
528
529 /* check iop1 status only for 16 port controllers */
530 if ((pm8001_ha->chip_id != chip_8008) &&
531 (pm8001_ha->chip_id != chip_8009)) {
532 /* 200 milli sec */
533 max_wait_time = max_wait_count = 200 * 1000;
534 do {
535 udelay(1);
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
537 } while (((value & SCRATCH_PAD_IOP1_READY) !=
538 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
539 if (!max_wait_count)
540 ret = -1;
541 else {
542 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
543 "iop1 ready status in %d millisec\n",
544 (max_wait_time - max_wait_count)));
545 }
546 }
547
548 return ret;
549}
550
551static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
552{
553 void __iomem *base_addr;
554 u32 value;
555 u32 offset;
556 u32 pcibar;
557 u32 pcilogic;
558
559 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
560 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
561
562 PM8001_INIT_DBG(pm8001_ha,
563 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
564 offset, value));
565 pcilogic = (value & 0xFC000000) >> 26;
566 pcibar = get_pci_bar_index(pcilogic);
567 PM8001_INIT_DBG(pm8001_ha,
568 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
569 pm8001_ha->main_cfg_tbl_addr = base_addr =
570 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
571 pm8001_ha->general_stat_tbl_addr =
572 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
573 0xFFFFFF);
574 pm8001_ha->inbnd_q_tbl_addr =
575 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
576 0xFFFFFF);
577 pm8001_ha->outbnd_q_tbl_addr =
578 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
579 0xFFFFFF);
580 pm8001_ha->ivt_tbl_addr =
581 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
582 0xFFFFFF);
583 pm8001_ha->pspa_q_tbl_addr =
584 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
585 0xFFFFFF);
586
587 PM8001_INIT_DBG(pm8001_ha,
588 pm8001_printk("GST OFFSET 0x%x\n",
589 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
590 PM8001_INIT_DBG(pm8001_ha,
591 pm8001_printk("INBND OFFSET 0x%x\n",
592 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
593 PM8001_INIT_DBG(pm8001_ha,
594 pm8001_printk("OBND OFFSET 0x%x\n",
595 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
596 PM8001_INIT_DBG(pm8001_ha,
597 pm8001_printk("IVT OFFSET 0x%x\n",
598 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
599 PM8001_INIT_DBG(pm8001_ha,
600 pm8001_printk("PSPA OFFSET 0x%x\n",
601 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
602 PM8001_INIT_DBG(pm8001_ha,
603 pm8001_printk("addr - main cfg %p general status %p\n",
604 pm8001_ha->main_cfg_tbl_addr,
605 pm8001_ha->general_stat_tbl_addr));
606 PM8001_INIT_DBG(pm8001_ha,
607 pm8001_printk("addr - inbnd %p obnd %p\n",
608 pm8001_ha->inbnd_q_tbl_addr,
609 pm8001_ha->outbnd_q_tbl_addr));
610 PM8001_INIT_DBG(pm8001_ha,
611 pm8001_printk("addr - pspa %p ivt %p\n",
612 pm8001_ha->pspa_q_tbl_addr,
613 pm8001_ha->ivt_tbl_addr));
614}
615
616/**
617 * pm80xx_set_thermal_config - support the thermal configuration
618 * @pm8001_ha: our hba card information.
619 */
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]620int
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]621pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
622{
623 struct set_ctrl_cfg_req payload;
624 struct inbound_queue_table *circularQ;
625 int rc;
626 u32 tag;
627 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
628
629 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
630 rc = pm8001_tag_alloc(pm8001_ha, &tag);
631 if (rc)
632 return -1;
633
634 circularQ = &pm8001_ha->inbnd_q_tbl[0];
635 payload.tag = cpu_to_le32(tag);
636 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
637 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
638 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
639
640 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
641 return rc;
642
643}
644
645/**
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]646* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
647* Timer configuration page
648* @pm8001_ha: our hba card information.
649*/
650static int
651pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
652{
653 struct set_ctrl_cfg_req payload;
654 struct inbound_queue_table *circularQ;
655 SASProtocolTimerConfig_t SASConfigPage;
656 int rc;
657 u32 tag;
658 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
659
660 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
661 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
662
663 rc = pm8001_tag_alloc(pm8001_ha, &tag);
664
665 if (rc)
666 return -1;
667
668 circularQ = &pm8001_ha->inbnd_q_tbl[0];
669 payload.tag = cpu_to_le32(tag);
670
671 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
672 SASConfigPage.MST_MSI = 3 << 15;
673 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
674 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
675 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
676 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
677
678 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
679 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
680
681
682 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
683 SAS_OPNRJT_RTRY_INTVL;
684 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
685 | SAS_COPNRJT_RTRY_TMO;
686 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
687 | SAS_COPNRJT_RTRY_THR;
688 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
689
690 PM8001_INIT_DBG(pm8001_ha,
691 pm8001_printk("SASConfigPage.pageCode "
692 "0x%08x\n", SASConfigPage.pageCode));
693 PM8001_INIT_DBG(pm8001_ha,
694 pm8001_printk("SASConfigPage.MST_MSI "
695 " 0x%08x\n", SASConfigPage.MST_MSI));
696 PM8001_INIT_DBG(pm8001_ha,
697 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
698 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
699 PM8001_INIT_DBG(pm8001_ha,
700 pm8001_printk("SASConfigPage.STP_FRM_TMO "
701 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
702 PM8001_INIT_DBG(pm8001_ha,
703 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
704 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
705 PM8001_INIT_DBG(pm8001_ha,
706 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
707 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
708 PM8001_INIT_DBG(pm8001_ha,
709 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
710 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
711 PM8001_INIT_DBG(pm8001_ha,
712 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
713 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
714 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
715 " 0x%08x\n", SASConfigPage.MAX_AIP));
716
717 memcpy(&payload.cfg_pg, &SASConfigPage,
718 sizeof(SASProtocolTimerConfig_t));
719
720 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
721
722 return rc;
723}
724
725/**
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]726 * pm80xx_get_encrypt_info - Check for encryption
727 * @pm8001_ha: our hba card information.
728 */
729static int
730pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
731{
732 u32 scratch3_value;
733 int ret;
734
735 /* Read encryption status from SCRATCH PAD 3 */
736 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
737
738 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
739 SCRATCH_PAD3_ENC_READY) {
740 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
741 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
742 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
743 SCRATCH_PAD3_SMF_ENABLED)
744 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
745 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
746 SCRATCH_PAD3_SMA_ENABLED)
747 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
748 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
749 SCRATCH_PAD3_SMB_ENABLED)
750 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
751 pm8001_ha->encrypt_info.status = 0;
752 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
753 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
754 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
755 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
756 pm8001_ha->encrypt_info.sec_mode,
757 pm8001_ha->encrypt_info.status));
758 ret = 0;
759 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
760 SCRATCH_PAD3_ENC_DISABLED) {
761 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
762 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
763 scratch3_value));
764 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
765 pm8001_ha->encrypt_info.cipher_mode = 0;
766 pm8001_ha->encrypt_info.sec_mode = 0;
767 return 0;
768 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
769 SCRATCH_PAD3_ENC_DIS_ERR) {
770 pm8001_ha->encrypt_info.status =
771 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
772 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
773 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
774 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
775 SCRATCH_PAD3_SMF_ENABLED)
776 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
777 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
778 SCRATCH_PAD3_SMA_ENABLED)
779 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
780 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
781 SCRATCH_PAD3_SMB_ENABLED)
782 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
783 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
784 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
785 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
786 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
787 pm8001_ha->encrypt_info.sec_mode,
788 pm8001_ha->encrypt_info.status));
789 ret = -1;
790 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
791 SCRATCH_PAD3_ENC_ENA_ERR) {
792
793 pm8001_ha->encrypt_info.status =
794 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
795 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
796 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
797 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
798 SCRATCH_PAD3_SMF_ENABLED)
799 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
800 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
801 SCRATCH_PAD3_SMA_ENABLED)
802 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
803 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
804 SCRATCH_PAD3_SMB_ENABLED)
805 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
806
807 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
808 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
809 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
810 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
811 pm8001_ha->encrypt_info.sec_mode,
812 pm8001_ha->encrypt_info.status));
813 ret = -1;
814 }
815 return ret;
816}
817
818/**
819 * pm80xx_encrypt_update - update flash with encryption informtion
820 * @pm8001_ha: our hba card information.
821 */
822static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
823{
824 struct kek_mgmt_req payload;
825 struct inbound_queue_table *circularQ;
826 int rc;
827 u32 tag;
828 u32 opc = OPC_INB_KEK_MANAGEMENT;
829
830 memset(&payload, 0, sizeof(struct kek_mgmt_req));
831 rc = pm8001_tag_alloc(pm8001_ha, &tag);
832 if (rc)
833 return -1;
834
835 circularQ = &pm8001_ha->inbnd_q_tbl[0];
836 payload.tag = cpu_to_le32(tag);
837 /* Currently only one key is used. New KEK index is 1.
838 * Current KEK index is 1. Store KEK to NVRAM is 1.
839 */
840 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
841 KEK_MGMT_SUBOP_KEYCARDUPDATE);
842
843 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
844
845 return rc;
846}
847
848/**
849 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
850 * @pm8001_ha: our hba card information
851 */
852static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
853{
854 int ret;
855 u8 i = 0;
856
857 /* check the firmware status */
858 if (-1 == check_fw_ready(pm8001_ha)) {
859 PM8001_FAIL_DBG(pm8001_ha,
860 pm8001_printk("Firmware is not ready!\n"));
861 return -EBUSY;
862 }
863
864 /* Initialize pci space address eg: mpi offset */
865 init_pci_device_addresses(pm8001_ha);
866 init_default_table_values(pm8001_ha);
867 read_main_config_table(pm8001_ha);
868 read_general_status_table(pm8001_ha);
869 read_inbnd_queue_table(pm8001_ha);
870 read_outbnd_queue_table(pm8001_ha);
871 read_phy_attr_table(pm8001_ha);
872
873 /* update main config table ,inbound table and outbound table */
874 update_main_config_table(pm8001_ha);
875 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
876 update_inbnd_queue_table(pm8001_ha, i);
877 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
878 update_outbnd_queue_table(pm8001_ha, i);
879
880 /* notify firmware update finished and check initialization status */
881 if (0 == mpi_init_check(pm8001_ha)) {
882 PM8001_INIT_DBG(pm8001_ha,
883 pm8001_printk("MPI initialize successful!\n"));
884 } else
885 return -EBUSY;
886
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]887 /* send SAS protocol timer configuration page to FW */
888 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]889
890 /* Check for encryption */
891 if (pm8001_ha->chip->encrypt) {
892 PM8001_INIT_DBG(pm8001_ha,
893 pm8001_printk("Checking for encryption\n"));
894 ret = pm80xx_get_encrypt_info(pm8001_ha);
895 if (ret == -1) {
896 PM8001_INIT_DBG(pm8001_ha,
897 pm8001_printk("Encryption error !!\n"));
898 if (pm8001_ha->encrypt_info.status == 0x81) {
899 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
900 "Encryption enabled with error."
901 "Saving encryption key to flash\n"));
902 pm80xx_encrypt_update(pm8001_ha);
903 }
904 }
905 }
906 return 0;
907}
908
909static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
910{
911 u32 max_wait_count;
912 u32 value;
913 u32 gst_len_mpistate;
914 init_pci_device_addresses(pm8001_ha);
915 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
916 table is stop */
917 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
918
919 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]920 if (IS_SPCV_12G(pm8001_ha->pdev)) {
921 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
922 } else {
923 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
924 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]925 do {
926 udelay(1);
927 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
928 value &= SPCv_MSGU_CFG_TABLE_RESET;
929 } while ((value != 0) && (--max_wait_count));
930
931 if (!max_wait_count) {
932 PM8001_FAIL_DBG(pm8001_ha,
933 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
934 return -1;
935 }
936
937 /* check the MPI-State for termination in progress */
938 /* wait until Inbound DoorBell Clear Register toggled */
939 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
940 do {
941 udelay(1);
942 gst_len_mpistate =
943 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
944 GST_GSTLEN_MPIS_OFFSET);
945 if (GST_MPI_STATE_UNINIT ==
946 (gst_len_mpistate & GST_MPI_STATE_MASK))
947 break;
948 } while (--max_wait_count);
949 if (!max_wait_count) {
950 PM8001_FAIL_DBG(pm8001_ha,
951 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
952 gst_len_mpistate & GST_MPI_STATE_MASK));
953 return -1;
954 }
955
956 return 0;
957}
958
959/**
960 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
961 * the FW register status to the originated status.
962 * @pm8001_ha: our hba card information
963 */
964
965static int
966pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
967{
968 u32 regval;
969 u32 bootloader_state;
970
971 /* Check if MPI is in ready state to reset */
972 if (mpi_uninit_check(pm8001_ha) != 0) {
973 PM8001_FAIL_DBG(pm8001_ha,
974 pm8001_printk("MPI state is not ready\n"));
975 return -1;
976 }
977
978 /* checked for reset register normal state; 0x0 */
979 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
980 PM8001_INIT_DBG(pm8001_ha,
981 pm8001_printk("reset register before write : 0x%x\n", regval));
982
983 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
984 mdelay(500);
985
986 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
987 PM8001_INIT_DBG(pm8001_ha,
988 pm8001_printk("reset register after write 0x%x\n", regval));
989
990 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
991 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
992 PM8001_MSG_DBG(pm8001_ha,
993 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
994 regval));
995 } else {
996 PM8001_MSG_DBG(pm8001_ha,
997 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
998 regval));
999
1000 /* check bootloader is successfully executed or in HDA mode */
1001 bootloader_state =
1002 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1003 SCRATCH_PAD1_BOOTSTATE_MASK;
1004
1005 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1006 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1007 "Bootloader state - HDA mode SEEPROM\n"));
1008 } else if (bootloader_state ==
1009 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1010 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1011 "Bootloader state - HDA mode Bootstrap Pin\n"));
1012 } else if (bootloader_state ==
1013 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1014 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1015 "Bootloader state - HDA mode soft reset\n"));
1016 } else if (bootloader_state ==
1017 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1018 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1019 "Bootloader state-HDA mode critical error\n"));
1020 }
1021 return -EBUSY;
1022 }
1023
1024 /* check the firmware status after reset */
1025 if (-1 == check_fw_ready(pm8001_ha)) {
1026 PM8001_FAIL_DBG(pm8001_ha,
1027 pm8001_printk("Firmware is not ready!\n"));
1028 return -EBUSY;
1029 }
1030 PM8001_INIT_DBG(pm8001_ha,
1031 pm8001_printk("SPCv soft reset Complete\n"));
1032 return 0;
1033}
1034
1035static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1036{
1037 u32 i;
1038
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("chip reset start\n"));
1041
1042 /* do SPCv chip reset. */
1043 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1044 PM8001_INIT_DBG(pm8001_ha,
1045 pm8001_printk("SPC soft reset Complete\n"));
1046
1047 /* Check this ..whether delay is required or no */
1048 /* delay 10 usec */
1049 udelay(10);
1050
1051 /* wait for 20 msec until the firmware gets reloaded */
1052 i = 20;
1053 do {
1054 mdelay(1);
1055 } while ((--i) != 0);
1056
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("chip reset finished\n"));
1059}
1060
1061/**
1062 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1063 * @pm8001_ha: our hba card information
1064 */
1065static void
1066pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1067{
1068 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1069 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1070}
1071
1072/**
1073 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1074 * @pm8001_ha: our hba card information
1075 */
1076static void
1077pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1078{
1079 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1080}
1081
1082/**
1083 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1084 * @pm8001_ha: our hba card information
1085 */
1086static void
1087pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1088{
1089#ifdef PM8001_USE_MSIX
1090 u32 mask;
1091 mask = (u32)(1 << vec);
1092
1093 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1094 return;
1095#endif
1096 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1097
1098}
1099
1100/**
1101 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1102 * @pm8001_ha: our hba card information
1103 */
1104static void
1105pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1106{
1107#ifdef PM8001_USE_MSIX
1108 u32 mask;
1109 if (vec == 0xFF)
1110 mask = 0xFFFFFFFF;
1111 else
1112 mask = (u32)(1 << vec);
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1114 return;
1115#endif
1116 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1117}
1118
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1119static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1120 struct pm8001_device *pm8001_ha_dev)
1121{
1122 int res;
1123 u32 ccb_tag;
1124 struct pm8001_ccb_info *ccb;
1125 struct sas_task *task = NULL;
1126 struct task_abort_req task_abort;
1127 struct inbound_queue_table *circularQ;
1128 u32 opc = OPC_INB_SATA_ABORT;
1129 int ret;
1130
1131 if (!pm8001_ha_dev) {
1132 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1133 return;
1134 }
1135
1136 task = sas_alloc_slow_task(GFP_ATOMIC);
1137
1138 if (!task) {
1139 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1140 "allocate task\n"));
1141 return;
1142 }
1143
1144 task->task_done = pm8001_task_done;
1145
1146 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1147 if (res)
1148 return;
1149
1150 ccb = &pm8001_ha->ccb_info[ccb_tag];
1151 ccb->device = pm8001_ha_dev;
1152 ccb->ccb_tag = ccb_tag;
1153 ccb->task = task;
1154
1155 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1156
1157 memset(&task_abort, 0, sizeof(task_abort));
1158 task_abort.abort_all = cpu_to_le32(1);
1159 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1160 task_abort.tag = cpu_to_le32(ccb_tag);
1161
1162 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1163
1164}
1165
1166static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1167 struct pm8001_device *pm8001_ha_dev)
1168{
1169 struct sata_start_req sata_cmd;
1170 int res;
1171 u32 ccb_tag;
1172 struct pm8001_ccb_info *ccb;
1173 struct sas_task *task = NULL;
1174 struct host_to_dev_fis fis;
1175 struct domain_device *dev;
1176 struct inbound_queue_table *circularQ;
1177 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1178
1179 task = sas_alloc_slow_task(GFP_ATOMIC);
1180
1181 if (!task) {
1182 PM8001_FAIL_DBG(pm8001_ha,
1183 pm8001_printk("cannot allocate task !!!\n"));
1184 return;
1185 }
1186 task->task_done = pm8001_task_done;
1187
1188 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1189 if (res) {
1190 PM8001_FAIL_DBG(pm8001_ha,
1191 pm8001_printk("cannot allocate tag !!!\n"));
1192 return;
1193 }
1194
1195 /* allocate domain device by ourselves as libsas
1196 * is not going to provide any
1197 */
1198 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1199 if (!dev) {
1200 PM8001_FAIL_DBG(pm8001_ha,
1201 pm8001_printk("Domain device cannot be allocated\n"));
1202 sas_free_task(task);
1203 return;
1204 } else {
1205 task->dev = dev;
1206 task->dev->lldd_dev = pm8001_ha_dev;
1207 }
1208
1209 ccb = &pm8001_ha->ccb_info[ccb_tag];
1210 ccb->device = pm8001_ha_dev;
1211 ccb->ccb_tag = ccb_tag;
1212 ccb->task = task;
1213 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1214 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1215
1216 memset(&sata_cmd, 0, sizeof(sata_cmd));
1217 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1218
1219 /* construct read log FIS */
1220 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1221 fis.fis_type = 0x27;
1222 fis.flags = 0x80;
1223 fis.command = ATA_CMD_READ_LOG_EXT;
1224 fis.lbal = 0x10;
1225 fis.sector_count = 0x1;
1226
1227 sata_cmd.tag = cpu_to_le32(ccb_tag);
1228 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1229 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1230 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1231
1232 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1233
1234}
1235
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1236/**
1237 * mpi_ssp_completion- process the event that FW response to the SSP request.
1238 * @pm8001_ha: our hba card information
1239 * @piomb: the message contents of this outbound message.
1240 *
1241 * When FW has completed a ssp request for example a IO request, after it has
1242 * filled the SG data with the data, it will trigger this event represent
1243 * that he has finished the job,please check the coresponding buffer.
1244 * So we will tell the caller who maybe waiting the result to tell upper layer
1245 * that the task has been finished.
1246 */
1247static void
1248mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1249{
1250 struct sas_task *t;
1251 struct pm8001_ccb_info *ccb;
1252 unsigned long flags;
1253 u32 status;
1254 u32 param;
1255 u32 tag;
1256 struct ssp_completion_resp *psspPayload;
1257 struct task_status_struct *ts;
1258 struct ssp_response_iu *iu;
1259 struct pm8001_device *pm8001_dev;
1260 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1261 status = le32_to_cpu(psspPayload->status);
1262 tag = le32_to_cpu(psspPayload->tag);
1263 ccb = &pm8001_ha->ccb_info[tag];
1264 if ((status == IO_ABORTED) && ccb->open_retry) {
1265 /* Being completed by another */
1266 ccb->open_retry = 0;
1267 return;
1268 }
1269 pm8001_dev = ccb->device;
1270 param = le32_to_cpu(psspPayload->param);
1271 t = ccb->task;
1272
1273 if (status && status != IO_UNDERFLOW)
1274 PM8001_FAIL_DBG(pm8001_ha,
1275 pm8001_printk("sas IO status 0x%x\n", status));
1276 if (unlikely(!t || !t->lldd_task || !t->dev))
1277 return;
1278 ts = &t->task_status;
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame^]1279 /* Print sas address of IO failed device */
1280 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1281 (status != IO_UNDERFLOW))
1282 PM8001_FAIL_DBG(pm8001_ha,
1283 pm8001_printk("SAS Address of IO Failure Drive"
1284 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1285
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1286 switch (status) {
1287 case IO_SUCCESS:
1288 PM8001_IO_DBG(pm8001_ha,
1289 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1290 param));
1291 if (param == 0) {
1292 ts->resp = SAS_TASK_COMPLETE;
1293 ts->stat = SAM_STAT_GOOD;
1294 } else {
1295 ts->resp = SAS_TASK_COMPLETE;
1296 ts->stat = SAS_PROTO_RESPONSE;
1297 ts->residual = param;
1298 iu = &psspPayload->ssp_resp_iu;
1299 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1300 }
1301 if (pm8001_dev)
1302 pm8001_dev->running_req--;
1303 break;
1304 case IO_ABORTED:
1305 PM8001_IO_DBG(pm8001_ha,
1306 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1307 ts->resp = SAS_TASK_COMPLETE;
1308 ts->stat = SAS_ABORTED_TASK;
1309 break;
1310 case IO_UNDERFLOW:
1311 /* SSP Completion with error */
1312 PM8001_IO_DBG(pm8001_ha,
1313 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1314 param));
1315 ts->resp = SAS_TASK_COMPLETE;
1316 ts->stat = SAS_DATA_UNDERRUN;
1317 ts->residual = param;
1318 if (pm8001_dev)
1319 pm8001_dev->running_req--;
1320 break;
1321 case IO_NO_DEVICE:
1322 PM8001_IO_DBG(pm8001_ha,
1323 pm8001_printk("IO_NO_DEVICE\n"));
1324 ts->resp = SAS_TASK_UNDELIVERED;
1325 ts->stat = SAS_PHY_DOWN;
1326 break;
1327 case IO_XFER_ERROR_BREAK:
1328 PM8001_IO_DBG(pm8001_ha,
1329 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1330 ts->resp = SAS_TASK_COMPLETE;
1331 ts->stat = SAS_OPEN_REJECT;
1332 /* Force the midlayer to retry */
1333 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1334 break;
1335 case IO_XFER_ERROR_PHY_NOT_READY:
1336 PM8001_IO_DBG(pm8001_ha,
1337 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1338 ts->resp = SAS_TASK_COMPLETE;
1339 ts->stat = SAS_OPEN_REJECT;
1340 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1341 break;
1342 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1343 PM8001_IO_DBG(pm8001_ha,
1344 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1345 ts->resp = SAS_TASK_COMPLETE;
1346 ts->stat = SAS_OPEN_REJECT;
1347 ts->open_rej_reason = SAS_OREJ_EPROTO;
1348 break;
1349 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1350 PM8001_IO_DBG(pm8001_ha,
1351 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1352 ts->resp = SAS_TASK_COMPLETE;
1353 ts->stat = SAS_OPEN_REJECT;
1354 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1355 break;
1356 case IO_OPEN_CNX_ERROR_BREAK:
1357 PM8001_IO_DBG(pm8001_ha,
1358 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1359 ts->resp = SAS_TASK_COMPLETE;
1360 ts->stat = SAS_OPEN_REJECT;
1361 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1362 break;
1363 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1364 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1365 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1366 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1367 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1368 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1369 PM8001_IO_DBG(pm8001_ha,
1370 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1371 ts->resp = SAS_TASK_COMPLETE;
1372 ts->stat = SAS_OPEN_REJECT;
1373 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1374 if (!t->uldd_task)
1375 pm8001_handle_event(pm8001_ha,
1376 pm8001_dev,
1377 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1378 break;
1379 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1380 PM8001_IO_DBG(pm8001_ha,
1381 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1382 ts->resp = SAS_TASK_COMPLETE;
1383 ts->stat = SAS_OPEN_REJECT;
1384 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1385 break;
1386 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1387 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1388 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1389 ts->resp = SAS_TASK_COMPLETE;
1390 ts->stat = SAS_OPEN_REJECT;
1391 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1392 break;
1393 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1394 PM8001_IO_DBG(pm8001_ha,
1395 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1396 ts->resp = SAS_TASK_UNDELIVERED;
1397 ts->stat = SAS_OPEN_REJECT;
1398 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1399 break;
1400 case IO_XFER_ERROR_NAK_RECEIVED:
1401 PM8001_IO_DBG(pm8001_ha,
1402 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1403 ts->resp = SAS_TASK_COMPLETE;
1404 ts->stat = SAS_OPEN_REJECT;
1405 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1406 break;
1407 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1408 PM8001_IO_DBG(pm8001_ha,
1409 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1410 ts->resp = SAS_TASK_COMPLETE;
1411 ts->stat = SAS_NAK_R_ERR;
1412 break;
1413 case IO_XFER_ERROR_DMA:
1414 PM8001_IO_DBG(pm8001_ha,
1415 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1416 ts->resp = SAS_TASK_COMPLETE;
1417 ts->stat = SAS_OPEN_REJECT;
1418 break;
1419 case IO_XFER_OPEN_RETRY_TIMEOUT:
1420 PM8001_IO_DBG(pm8001_ha,
1421 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1422 ts->resp = SAS_TASK_COMPLETE;
1423 ts->stat = SAS_OPEN_REJECT;
1424 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1425 break;
1426 case IO_XFER_ERROR_OFFSET_MISMATCH:
1427 PM8001_IO_DBG(pm8001_ha,
1428 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1429 ts->resp = SAS_TASK_COMPLETE;
1430 ts->stat = SAS_OPEN_REJECT;
1431 break;
1432 case IO_PORT_IN_RESET:
1433 PM8001_IO_DBG(pm8001_ha,
1434 pm8001_printk("IO_PORT_IN_RESET\n"));
1435 ts->resp = SAS_TASK_COMPLETE;
1436 ts->stat = SAS_OPEN_REJECT;
1437 break;
1438 case IO_DS_NON_OPERATIONAL:
1439 PM8001_IO_DBG(pm8001_ha,
1440 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1441 ts->resp = SAS_TASK_COMPLETE;
1442 ts->stat = SAS_OPEN_REJECT;
1443 if (!t->uldd_task)
1444 pm8001_handle_event(pm8001_ha,
1445 pm8001_dev,
1446 IO_DS_NON_OPERATIONAL);
1447 break;
1448 case IO_DS_IN_RECOVERY:
1449 PM8001_IO_DBG(pm8001_ha,
1450 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1451 ts->resp = SAS_TASK_COMPLETE;
1452 ts->stat = SAS_OPEN_REJECT;
1453 break;
1454 case IO_TM_TAG_NOT_FOUND:
1455 PM8001_IO_DBG(pm8001_ha,
1456 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1457 ts->resp = SAS_TASK_COMPLETE;
1458 ts->stat = SAS_OPEN_REJECT;
1459 break;
1460 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1461 PM8001_IO_DBG(pm8001_ha,
1462 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1463 ts->resp = SAS_TASK_COMPLETE;
1464 ts->stat = SAS_OPEN_REJECT;
1465 break;
1466 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1467 PM8001_IO_DBG(pm8001_ha,
1468 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1469 ts->resp = SAS_TASK_COMPLETE;
1470 ts->stat = SAS_OPEN_REJECT;
1471 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1472 break;
1473 default:
1474 PM8001_IO_DBG(pm8001_ha,
1475 pm8001_printk("Unknown status 0x%x\n", status));
1476 /* not allowed case. Therefore, return failed status */
1477 ts->resp = SAS_TASK_COMPLETE;
1478 ts->stat = SAS_OPEN_REJECT;
1479 break;
1480 }
1481 PM8001_IO_DBG(pm8001_ha,
1482 pm8001_printk("scsi_status = 0x%x\n ",
1483 psspPayload->ssp_resp_iu.status));
1484 spin_lock_irqsave(&t->task_state_lock, flags);
1485 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1486 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1487 t->task_state_flags |= SAS_TASK_STATE_DONE;
1488 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1489 spin_unlock_irqrestore(&t->task_state_lock, flags);
1490 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1491 "task 0x%p done with io_status 0x%x resp 0x%x "
1492 "stat 0x%x but aborted by upper layer!\n",
1493 t, status, ts->resp, ts->stat));
1494 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1495 } else {
1496 spin_unlock_irqrestore(&t->task_state_lock, flags);
1497 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1498 mb();/* in order to force CPU ordering */
1499 t->task_done(t);
1500 }
1501}
1502
1503/*See the comments for mpi_ssp_completion */
1504static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1505{
1506 struct sas_task *t;
1507 unsigned long flags;
1508 struct task_status_struct *ts;
1509 struct pm8001_ccb_info *ccb;
1510 struct pm8001_device *pm8001_dev;
1511 struct ssp_event_resp *psspPayload =
1512 (struct ssp_event_resp *)(piomb + 4);
1513 u32 event = le32_to_cpu(psspPayload->event);
1514 u32 tag = le32_to_cpu(psspPayload->tag);
1515 u32 port_id = le32_to_cpu(psspPayload->port_id);
1516
1517 ccb = &pm8001_ha->ccb_info[tag];
1518 t = ccb->task;
1519 pm8001_dev = ccb->device;
1520 if (event)
1521 PM8001_FAIL_DBG(pm8001_ha,
1522 pm8001_printk("sas IO status 0x%x\n", event));
1523 if (unlikely(!t || !t->lldd_task || !t->dev))
1524 return;
1525 ts = &t->task_status;
1526 PM8001_IO_DBG(pm8001_ha,
1527 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1528 port_id, tag, event));
1529 switch (event) {
1530 case IO_OVERFLOW:
1531 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1532 ts->resp = SAS_TASK_COMPLETE;
1533 ts->stat = SAS_DATA_OVERRUN;
1534 ts->residual = 0;
1535 if (pm8001_dev)
1536 pm8001_dev->running_req--;
1537 break;
1538 case IO_XFER_ERROR_BREAK:
1539 PM8001_IO_DBG(pm8001_ha,
1540 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1541 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1542 return;
1543 case IO_XFER_ERROR_PHY_NOT_READY:
1544 PM8001_IO_DBG(pm8001_ha,
1545 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1546 ts->resp = SAS_TASK_COMPLETE;
1547 ts->stat = SAS_OPEN_REJECT;
1548 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1549 break;
1550 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1551 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1552 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1553 ts->resp = SAS_TASK_COMPLETE;
1554 ts->stat = SAS_OPEN_REJECT;
1555 ts->open_rej_reason = SAS_OREJ_EPROTO;
1556 break;
1557 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1558 PM8001_IO_DBG(pm8001_ha,
1559 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1560 ts->resp = SAS_TASK_COMPLETE;
1561 ts->stat = SAS_OPEN_REJECT;
1562 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1563 break;
1564 case IO_OPEN_CNX_ERROR_BREAK:
1565 PM8001_IO_DBG(pm8001_ha,
1566 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1567 ts->resp = SAS_TASK_COMPLETE;
1568 ts->stat = SAS_OPEN_REJECT;
1569 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1570 break;
1571 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1572 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1573 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1574 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1575 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1576 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1577 PM8001_IO_DBG(pm8001_ha,
1578 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1579 ts->resp = SAS_TASK_COMPLETE;
1580 ts->stat = SAS_OPEN_REJECT;
1581 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1582 if (!t->uldd_task)
1583 pm8001_handle_event(pm8001_ha,
1584 pm8001_dev,
1585 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1586 break;
1587 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1588 PM8001_IO_DBG(pm8001_ha,
1589 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1590 ts->resp = SAS_TASK_COMPLETE;
1591 ts->stat = SAS_OPEN_REJECT;
1592 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1593 break;
1594 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1595 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1596 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1597 ts->resp = SAS_TASK_COMPLETE;
1598 ts->stat = SAS_OPEN_REJECT;
1599 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1600 break;
1601 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1602 PM8001_IO_DBG(pm8001_ha,
1603 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1604 ts->resp = SAS_TASK_COMPLETE;
1605 ts->stat = SAS_OPEN_REJECT;
1606 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1607 break;
1608 case IO_XFER_ERROR_NAK_RECEIVED:
1609 PM8001_IO_DBG(pm8001_ha,
1610 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1611 ts->resp = SAS_TASK_COMPLETE;
1612 ts->stat = SAS_OPEN_REJECT;
1613 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1614 break;
1615 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1616 PM8001_IO_DBG(pm8001_ha,
1617 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1618 ts->resp = SAS_TASK_COMPLETE;
1619 ts->stat = SAS_NAK_R_ERR;
1620 break;
1621 case IO_XFER_OPEN_RETRY_TIMEOUT:
1622 PM8001_IO_DBG(pm8001_ha,
1623 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1624 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1625 return;
1626 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1627 PM8001_IO_DBG(pm8001_ha,
1628 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1629 ts->resp = SAS_TASK_COMPLETE;
1630 ts->stat = SAS_DATA_OVERRUN;
1631 break;
1632 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1633 PM8001_IO_DBG(pm8001_ha,
1634 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1635 ts->resp = SAS_TASK_COMPLETE;
1636 ts->stat = SAS_DATA_OVERRUN;
1637 break;
1638 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1639 PM8001_IO_DBG(pm8001_ha,
1640 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1641 ts->resp = SAS_TASK_COMPLETE;
1642 ts->stat = SAS_DATA_OVERRUN;
1643 break;
1644 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1645 PM8001_IO_DBG(pm8001_ha,
1646 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1647 ts->resp = SAS_TASK_COMPLETE;
1648 ts->stat = SAS_DATA_OVERRUN;
1649 break;
1650 case IO_XFER_ERROR_OFFSET_MISMATCH:
1651 PM8001_IO_DBG(pm8001_ha,
1652 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1653 ts->resp = SAS_TASK_COMPLETE;
1654 ts->stat = SAS_DATA_OVERRUN;
1655 break;
1656 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1657 PM8001_IO_DBG(pm8001_ha,
1658 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1659 ts->resp = SAS_TASK_COMPLETE;
1660 ts->stat = SAS_DATA_OVERRUN;
1661 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1662 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1663 PM8001_IO_DBG(pm8001_ha,
1664 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1665 /* TBC: used default set values */
1666 ts->resp = SAS_TASK_COMPLETE;
1667 ts->stat = SAS_DATA_OVERRUN;
1668 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1669 case IO_XFER_CMD_FRAME_ISSUED:
1670 PM8001_IO_DBG(pm8001_ha,
1671 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1672 return;
1673 default:
1674 PM8001_IO_DBG(pm8001_ha,
1675 pm8001_printk("Unknown status 0x%x\n", event));
1676 /* not allowed case. Therefore, return failed status */
1677 ts->resp = SAS_TASK_COMPLETE;
1678 ts->stat = SAS_DATA_OVERRUN;
1679 break;
1680 }
1681 spin_lock_irqsave(&t->task_state_lock, flags);
1682 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1683 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1684 t->task_state_flags |= SAS_TASK_STATE_DONE;
1685 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1686 spin_unlock_irqrestore(&t->task_state_lock, flags);
1687 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1688 "task 0x%p done with event 0x%x resp 0x%x "
1689 "stat 0x%x but aborted by upper layer!\n",
1690 t, event, ts->resp, ts->stat));
1691 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1692 } else {
1693 spin_unlock_irqrestore(&t->task_state_lock, flags);
1694 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1695 mb();/* in order to force CPU ordering */
1696 t->task_done(t);
1697 }
1698}
1699
1700/*See the comments for mpi_ssp_completion */
1701static void
1702mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1703{
1704 struct sas_task *t;
1705 struct pm8001_ccb_info *ccb;
1706 u32 param;
1707 u32 status;
1708 u32 tag;
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame^]1709 int i, j;
1710 u8 sata_addr_low[4];
1711 u32 temp_sata_addr_low, temp_sata_addr_hi;
1712 u8 sata_addr_hi[4];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1713 struct sata_completion_resp *psataPayload;
1714 struct task_status_struct *ts;
1715 struct ata_task_resp *resp ;
1716 u32 *sata_resp;
1717 struct pm8001_device *pm8001_dev;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1718 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1719
1720 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1721 status = le32_to_cpu(psataPayload->status);
1722 tag = le32_to_cpu(psataPayload->tag);
1723
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1724 if (!tag) {
1725 PM8001_FAIL_DBG(pm8001_ha,
1726 pm8001_printk("tag null\n"));
1727 return;
1728 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1729 ccb = &pm8001_ha->ccb_info[tag];
1730 param = le32_to_cpu(psataPayload->param);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1731 if (ccb) {
1732 t = ccb->task;
1733 pm8001_dev = ccb->device;
1734 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1735 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1736 pm8001_printk("ccb null\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1737 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1738 }
1739
1740 if (t) {
1741 if (t->dev && (t->dev->lldd_dev))
1742 pm8001_dev = t->dev->lldd_dev;
1743 } else {
1744 PM8001_FAIL_DBG(pm8001_ha,
1745 pm8001_printk("task null\n"));
1746 return;
1747 }
1748
1749 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1750 && unlikely(!t || !t->lldd_task || !t->dev)) {
1751 PM8001_FAIL_DBG(pm8001_ha,
1752 pm8001_printk("task or dev null\n"));
1753 return;
1754 }
1755
1756 ts = &t->task_status;
1757 if (!ts) {
1758 PM8001_FAIL_DBG(pm8001_ha,
1759 pm8001_printk("ts null\n"));
1760 return;
1761 }
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame^]1762 /* Print sas address of IO failed device */
1763 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1764 (status != IO_UNDERFLOW)) {
1765 if (!((t->dev->parent) &&
1766 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
1767 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
1768 sata_addr_low[i] = pm8001_ha->sas_addr[j];
1769 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
1770 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
1771 memcpy(&temp_sata_addr_low, sata_addr_low,
1772 sizeof(sata_addr_low));
1773 memcpy(&temp_sata_addr_hi, sata_addr_hi,
1774 sizeof(sata_addr_hi));
1775 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
1776 |((temp_sata_addr_hi << 8) &
1777 0xff0000) |
1778 ((temp_sata_addr_hi >> 8)
1779 & 0xff00) |
1780 ((temp_sata_addr_hi << 24) &
1781 0xff000000));
1782 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
1783 & 0xff) |
1784 ((temp_sata_addr_low << 8)
1785 & 0xff0000) |
1786 ((temp_sata_addr_low >> 8)
1787 & 0xff00) |
1788 ((temp_sata_addr_low << 24)
1789 & 0xff000000)) +
1790 pm8001_dev->attached_phy +
1791 0x10);
1792 PM8001_FAIL_DBG(pm8001_ha,
1793 pm8001_printk("SAS Address of IO Failure Drive:"
1794 "%08x%08x", temp_sata_addr_hi,
1795 temp_sata_addr_low));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1796
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame^]1797 } else {
1798 PM8001_FAIL_DBG(pm8001_ha,
1799 pm8001_printk("SAS Address of IO Failure Drive:"
1800 "%016llx", SAS_ADDR(t->dev->sas_addr)));
1801 }
1802 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1803 switch (status) {
1804 case IO_SUCCESS:
1805 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1806 if (param == 0) {
1807 ts->resp = SAS_TASK_COMPLETE;
1808 ts->stat = SAM_STAT_GOOD;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1809 /* check if response is for SEND READ LOG */
1810 if (pm8001_dev &&
1811 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
1812 /* set new bit for abort_all */
1813 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
1814 /* clear bit for read log */
1815 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
1816 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
1817 /* Free the tag */
1818 pm8001_tag_free(pm8001_ha, tag);
1819 sas_free_task(t);
1820 return;
1821 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1822 } else {
1823 u8 len;
1824 ts->resp = SAS_TASK_COMPLETE;
1825 ts->stat = SAS_PROTO_RESPONSE;
1826 ts->residual = param;
1827 PM8001_IO_DBG(pm8001_ha,
1828 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1829 param));
1830 sata_resp = &psataPayload->sata_resp[0];
1831 resp = (struct ata_task_resp *)ts->buf;
1832 if (t->ata_task.dma_xfer == 0 &&
1833 t->data_dir == PCI_DMA_FROMDEVICE) {
1834 len = sizeof(struct pio_setup_fis);
1835 PM8001_IO_DBG(pm8001_ha,
1836 pm8001_printk("PIO read len = %d\n", len));
1837 } else if (t->ata_task.use_ncq) {
1838 len = sizeof(struct set_dev_bits_fis);
1839 PM8001_IO_DBG(pm8001_ha,
1840 pm8001_printk("FPDMA len = %d\n", len));
1841 } else {
1842 len = sizeof(struct dev_to_host_fis);
1843 PM8001_IO_DBG(pm8001_ha,
1844 pm8001_printk("other len = %d\n", len));
1845 }
1846 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1847 resp->frame_len = len;
1848 memcpy(&resp->ending_fis[0], sata_resp, len);
1849 ts->buf_valid_size = sizeof(*resp);
1850 } else
1851 PM8001_IO_DBG(pm8001_ha,
1852 pm8001_printk("response to large\n"));
1853 }
1854 if (pm8001_dev)
1855 pm8001_dev->running_req--;
1856 break;
1857 case IO_ABORTED:
1858 PM8001_IO_DBG(pm8001_ha,
1859 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1860 ts->resp = SAS_TASK_COMPLETE;
1861 ts->stat = SAS_ABORTED_TASK;
1862 if (pm8001_dev)
1863 pm8001_dev->running_req--;
1864 break;
1865 /* following cases are to do cases */
1866 case IO_UNDERFLOW:
1867 /* SATA Completion with error */
1868 PM8001_IO_DBG(pm8001_ha,
1869 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1870 ts->resp = SAS_TASK_COMPLETE;
1871 ts->stat = SAS_DATA_UNDERRUN;
1872 ts->residual = param;
1873 if (pm8001_dev)
1874 pm8001_dev->running_req--;
1875 break;
1876 case IO_NO_DEVICE:
1877 PM8001_IO_DBG(pm8001_ha,
1878 pm8001_printk("IO_NO_DEVICE\n"));
1879 ts->resp = SAS_TASK_UNDELIVERED;
1880 ts->stat = SAS_PHY_DOWN;
1881 break;
1882 case IO_XFER_ERROR_BREAK:
1883 PM8001_IO_DBG(pm8001_ha,
1884 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1885 ts->resp = SAS_TASK_COMPLETE;
1886 ts->stat = SAS_INTERRUPTED;
1887 break;
1888 case IO_XFER_ERROR_PHY_NOT_READY:
1889 PM8001_IO_DBG(pm8001_ha,
1890 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1891 ts->resp = SAS_TASK_COMPLETE;
1892 ts->stat = SAS_OPEN_REJECT;
1893 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1894 break;
1895 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1896 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1897 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1898 ts->resp = SAS_TASK_COMPLETE;
1899 ts->stat = SAS_OPEN_REJECT;
1900 ts->open_rej_reason = SAS_OREJ_EPROTO;
1901 break;
1902 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1903 PM8001_IO_DBG(pm8001_ha,
1904 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1905 ts->resp = SAS_TASK_COMPLETE;
1906 ts->stat = SAS_OPEN_REJECT;
1907 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1908 break;
1909 case IO_OPEN_CNX_ERROR_BREAK:
1910 PM8001_IO_DBG(pm8001_ha,
1911 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1912 ts->resp = SAS_TASK_COMPLETE;
1913 ts->stat = SAS_OPEN_REJECT;
1914 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1915 break;
1916 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1917 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1918 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1919 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1920 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1921 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1922 PM8001_IO_DBG(pm8001_ha,
1923 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1924 ts->resp = SAS_TASK_COMPLETE;
1925 ts->stat = SAS_DEV_NO_RESPONSE;
1926 if (!t->uldd_task) {
1927 pm8001_handle_event(pm8001_ha,
1928 pm8001_dev,
1929 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1930 ts->resp = SAS_TASK_UNDELIVERED;
1931 ts->stat = SAS_QUEUE_FULL;
1932 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1933 mb();/*in order to force CPU ordering*/
1934 spin_unlock_irq(&pm8001_ha->lock);
1935 t->task_done(t);
1936 spin_lock_irq(&pm8001_ha->lock);
1937 return;
1938 }
1939 break;
1940 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1941 PM8001_IO_DBG(pm8001_ha,
1942 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1943 ts->resp = SAS_TASK_UNDELIVERED;
1944 ts->stat = SAS_OPEN_REJECT;
1945 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1946 if (!t->uldd_task) {
1947 pm8001_handle_event(pm8001_ha,
1948 pm8001_dev,
1949 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1950 ts->resp = SAS_TASK_UNDELIVERED;
1951 ts->stat = SAS_QUEUE_FULL;
1952 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1953 mb();/*ditto*/
1954 spin_unlock_irq(&pm8001_ha->lock);
1955 t->task_done(t);
1956 spin_lock_irq(&pm8001_ha->lock);
1957 return;
1958 }
1959 break;
1960 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1961 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1962 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1963 ts->resp = SAS_TASK_COMPLETE;
1964 ts->stat = SAS_OPEN_REJECT;
1965 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1966 break;
1967 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1968 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1969 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1970 ts->resp = SAS_TASK_COMPLETE;
1971 ts->stat = SAS_DEV_NO_RESPONSE;
1972 if (!t->uldd_task) {
1973 pm8001_handle_event(pm8001_ha,
1974 pm8001_dev,
1975 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1976 ts->resp = SAS_TASK_UNDELIVERED;
1977 ts->stat = SAS_QUEUE_FULL;
1978 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1979 mb();/* ditto*/
1980 spin_unlock_irq(&pm8001_ha->lock);
1981 t->task_done(t);
1982 spin_lock_irq(&pm8001_ha->lock);
1983 return;
1984 }
1985 break;
1986 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1987 PM8001_IO_DBG(pm8001_ha,
1988 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1989 ts->resp = SAS_TASK_COMPLETE;
1990 ts->stat = SAS_OPEN_REJECT;
1991 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1992 break;
1993 case IO_XFER_ERROR_NAK_RECEIVED:
1994 PM8001_IO_DBG(pm8001_ha,
1995 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1996 ts->resp = SAS_TASK_COMPLETE;
1997 ts->stat = SAS_NAK_R_ERR;
1998 break;
1999 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2000 PM8001_IO_DBG(pm8001_ha,
2001 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2002 ts->resp = SAS_TASK_COMPLETE;
2003 ts->stat = SAS_NAK_R_ERR;
2004 break;
2005 case IO_XFER_ERROR_DMA:
2006 PM8001_IO_DBG(pm8001_ha,
2007 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2008 ts->resp = SAS_TASK_COMPLETE;
2009 ts->stat = SAS_ABORTED_TASK;
2010 break;
2011 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2012 PM8001_IO_DBG(pm8001_ha,
2013 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2014 ts->resp = SAS_TASK_UNDELIVERED;
2015 ts->stat = SAS_DEV_NO_RESPONSE;
2016 break;
2017 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2018 PM8001_IO_DBG(pm8001_ha,
2019 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2020 ts->resp = SAS_TASK_COMPLETE;
2021 ts->stat = SAS_DATA_UNDERRUN;
2022 break;
2023 case IO_XFER_OPEN_RETRY_TIMEOUT:
2024 PM8001_IO_DBG(pm8001_ha,
2025 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2026 ts->resp = SAS_TASK_COMPLETE;
2027 ts->stat = SAS_OPEN_TO;
2028 break;
2029 case IO_PORT_IN_RESET:
2030 PM8001_IO_DBG(pm8001_ha,
2031 pm8001_printk("IO_PORT_IN_RESET\n"));
2032 ts->resp = SAS_TASK_COMPLETE;
2033 ts->stat = SAS_DEV_NO_RESPONSE;
2034 break;
2035 case IO_DS_NON_OPERATIONAL:
2036 PM8001_IO_DBG(pm8001_ha,
2037 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2038 ts->resp = SAS_TASK_COMPLETE;
2039 ts->stat = SAS_DEV_NO_RESPONSE;
2040 if (!t->uldd_task) {
2041 pm8001_handle_event(pm8001_ha, pm8001_dev,
2042 IO_DS_NON_OPERATIONAL);
2043 ts->resp = SAS_TASK_UNDELIVERED;
2044 ts->stat = SAS_QUEUE_FULL;
2045 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2046 mb();/*ditto*/
2047 spin_unlock_irq(&pm8001_ha->lock);
2048 t->task_done(t);
2049 spin_lock_irq(&pm8001_ha->lock);
2050 return;
2051 }
2052 break;
2053 case IO_DS_IN_RECOVERY:
2054 PM8001_IO_DBG(pm8001_ha,
2055 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2056 ts->resp = SAS_TASK_COMPLETE;
2057 ts->stat = SAS_DEV_NO_RESPONSE;
2058 break;
2059 case IO_DS_IN_ERROR:
2060 PM8001_IO_DBG(pm8001_ha,
2061 pm8001_printk("IO_DS_IN_ERROR\n"));
2062 ts->resp = SAS_TASK_COMPLETE;
2063 ts->stat = SAS_DEV_NO_RESPONSE;
2064 if (!t->uldd_task) {
2065 pm8001_handle_event(pm8001_ha, pm8001_dev,
2066 IO_DS_IN_ERROR);
2067 ts->resp = SAS_TASK_UNDELIVERED;
2068 ts->stat = SAS_QUEUE_FULL;
2069 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2070 mb();/*ditto*/
2071 spin_unlock_irq(&pm8001_ha->lock);
2072 t->task_done(t);
2073 spin_lock_irq(&pm8001_ha->lock);
2074 return;
2075 }
2076 break;
2077 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2078 PM8001_IO_DBG(pm8001_ha,
2079 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2080 ts->resp = SAS_TASK_COMPLETE;
2081 ts->stat = SAS_OPEN_REJECT;
2082 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2083 default:
2084 PM8001_IO_DBG(pm8001_ha,
2085 pm8001_printk("Unknown status 0x%x\n", status));
2086 /* not allowed case. Therefore, return failed status */
2087 ts->resp = SAS_TASK_COMPLETE;
2088 ts->stat = SAS_DEV_NO_RESPONSE;
2089 break;
2090 }
2091 spin_lock_irqsave(&t->task_state_lock, flags);
2092 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2093 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2094 t->task_state_flags |= SAS_TASK_STATE_DONE;
2095 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2096 spin_unlock_irqrestore(&t->task_state_lock, flags);
2097 PM8001_FAIL_DBG(pm8001_ha,
2098 pm8001_printk("task 0x%p done with io_status 0x%x"
2099 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2100 t, status, ts->resp, ts->stat));
2101 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2102 } else if (t->uldd_task) {
2103 spin_unlock_irqrestore(&t->task_state_lock, flags);
2104 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2105 mb();/* ditto */
2106 spin_unlock_irq(&pm8001_ha->lock);
2107 t->task_done(t);
2108 spin_lock_irq(&pm8001_ha->lock);
2109 } else if (!t->uldd_task) {
2110 spin_unlock_irqrestore(&t->task_state_lock, flags);
2111 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2112 mb();/*ditto*/
2113 spin_unlock_irq(&pm8001_ha->lock);
2114 t->task_done(t);
2115 spin_lock_irq(&pm8001_ha->lock);
2116 }
2117}
2118
2119/*See the comments for mpi_ssp_completion */
2120static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2121{
2122 struct sas_task *t;
2123 struct task_status_struct *ts;
2124 struct pm8001_ccb_info *ccb;
2125 struct pm8001_device *pm8001_dev;
2126 struct sata_event_resp *psataPayload =
2127 (struct sata_event_resp *)(piomb + 4);
2128 u32 event = le32_to_cpu(psataPayload->event);
2129 u32 tag = le32_to_cpu(psataPayload->tag);
2130 u32 port_id = le32_to_cpu(psataPayload->port_id);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2131 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2132 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2133
2134 ccb = &pm8001_ha->ccb_info[tag];
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2135
2136 if (ccb) {
2137 t = ccb->task;
2138 pm8001_dev = ccb->device;
2139 } else {
2140 PM8001_FAIL_DBG(pm8001_ha,
2141 pm8001_printk("No CCB !!!. returning\n"));
2142 return;
2143 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2144 if (event)
2145 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2146 pm8001_printk("SATA EVENT 0x%x\n", event));
2147
2148 /* Check if this is NCQ error */
2149 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2150 /* find device using device id */
2151 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2152 /* send read log extension */
2153 if (pm8001_dev)
2154 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2155 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2156 }
2157
2158 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2159 PM8001_FAIL_DBG(pm8001_ha,
2160 pm8001_printk("task or dev null\n"));
2161 return;
2162 }
2163
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2164 ts = &t->task_status;
2165 PM8001_IO_DBG(pm8001_ha,
2166 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2167 port_id, tag, event));
2168 switch (event) {
2169 case IO_OVERFLOW:
2170 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2171 ts->resp = SAS_TASK_COMPLETE;
2172 ts->stat = SAS_DATA_OVERRUN;
2173 ts->residual = 0;
2174 if (pm8001_dev)
2175 pm8001_dev->running_req--;
2176 break;
2177 case IO_XFER_ERROR_BREAK:
2178 PM8001_IO_DBG(pm8001_ha,
2179 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2180 ts->resp = SAS_TASK_COMPLETE;
2181 ts->stat = SAS_INTERRUPTED;
2182 break;
2183 case IO_XFER_ERROR_PHY_NOT_READY:
2184 PM8001_IO_DBG(pm8001_ha,
2185 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2186 ts->resp = SAS_TASK_COMPLETE;
2187 ts->stat = SAS_OPEN_REJECT;
2188 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2189 break;
2190 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2191 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2192 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2193 ts->resp = SAS_TASK_COMPLETE;
2194 ts->stat = SAS_OPEN_REJECT;
2195 ts->open_rej_reason = SAS_OREJ_EPROTO;
2196 break;
2197 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2198 PM8001_IO_DBG(pm8001_ha,
2199 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2200 ts->resp = SAS_TASK_COMPLETE;
2201 ts->stat = SAS_OPEN_REJECT;
2202 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2203 break;
2204 case IO_OPEN_CNX_ERROR_BREAK:
2205 PM8001_IO_DBG(pm8001_ha,
2206 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2207 ts->resp = SAS_TASK_COMPLETE;
2208 ts->stat = SAS_OPEN_REJECT;
2209 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2210 break;
2211 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2212 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2213 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2214 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2215 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2216 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2217 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2218 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2219 ts->resp = SAS_TASK_UNDELIVERED;
2220 ts->stat = SAS_DEV_NO_RESPONSE;
2221 if (!t->uldd_task) {
2222 pm8001_handle_event(pm8001_ha,
2223 pm8001_dev,
2224 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2225 ts->resp = SAS_TASK_COMPLETE;
2226 ts->stat = SAS_QUEUE_FULL;
2227 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2228 mb();/*ditto*/
2229 spin_unlock_irq(&pm8001_ha->lock);
2230 t->task_done(t);
2231 spin_lock_irq(&pm8001_ha->lock);
2232 return;
2233 }
2234 break;
2235 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2236 PM8001_IO_DBG(pm8001_ha,
2237 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2238 ts->resp = SAS_TASK_UNDELIVERED;
2239 ts->stat = SAS_OPEN_REJECT;
2240 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2241 break;
2242 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2243 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2244 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2245 ts->resp = SAS_TASK_COMPLETE;
2246 ts->stat = SAS_OPEN_REJECT;
2247 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2248 break;
2249 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2250 PM8001_IO_DBG(pm8001_ha,
2251 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2252 ts->resp = SAS_TASK_COMPLETE;
2253 ts->stat = SAS_OPEN_REJECT;
2254 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2255 break;
2256 case IO_XFER_ERROR_NAK_RECEIVED:
2257 PM8001_IO_DBG(pm8001_ha,
2258 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2259 ts->resp = SAS_TASK_COMPLETE;
2260 ts->stat = SAS_NAK_R_ERR;
2261 break;
2262 case IO_XFER_ERROR_PEER_ABORTED:
2263 PM8001_IO_DBG(pm8001_ha,
2264 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2265 ts->resp = SAS_TASK_COMPLETE;
2266 ts->stat = SAS_NAK_R_ERR;
2267 break;
2268 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2269 PM8001_IO_DBG(pm8001_ha,
2270 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2271 ts->resp = SAS_TASK_COMPLETE;
2272 ts->stat = SAS_DATA_UNDERRUN;
2273 break;
2274 case IO_XFER_OPEN_RETRY_TIMEOUT:
2275 PM8001_IO_DBG(pm8001_ha,
2276 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2277 ts->resp = SAS_TASK_COMPLETE;
2278 ts->stat = SAS_OPEN_TO;
2279 break;
2280 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2281 PM8001_IO_DBG(pm8001_ha,
2282 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2283 ts->resp = SAS_TASK_COMPLETE;
2284 ts->stat = SAS_OPEN_TO;
2285 break;
2286 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2287 PM8001_IO_DBG(pm8001_ha,
2288 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2289 ts->resp = SAS_TASK_COMPLETE;
2290 ts->stat = SAS_OPEN_TO;
2291 break;
2292 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2293 PM8001_IO_DBG(pm8001_ha,
2294 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2295 ts->resp = SAS_TASK_COMPLETE;
2296 ts->stat = SAS_OPEN_TO;
2297 break;
2298 case IO_XFER_ERROR_OFFSET_MISMATCH:
2299 PM8001_IO_DBG(pm8001_ha,
2300 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2301 ts->resp = SAS_TASK_COMPLETE;
2302 ts->stat = SAS_OPEN_TO;
2303 break;
2304 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2305 PM8001_IO_DBG(pm8001_ha,
2306 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2307 ts->resp = SAS_TASK_COMPLETE;
2308 ts->stat = SAS_OPEN_TO;
2309 break;
2310 case IO_XFER_CMD_FRAME_ISSUED:
2311 PM8001_IO_DBG(pm8001_ha,
2312 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2313 break;
2314 case IO_XFER_PIO_SETUP_ERROR:
2315 PM8001_IO_DBG(pm8001_ha,
2316 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2317 ts->resp = SAS_TASK_COMPLETE;
2318 ts->stat = SAS_OPEN_TO;
2319 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2320 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2321 PM8001_FAIL_DBG(pm8001_ha,
2322 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2323 /* TBC: used default set values */
2324 ts->resp = SAS_TASK_COMPLETE;
2325 ts->stat = SAS_OPEN_TO;
2326 break;
2327 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2328 PM8001_FAIL_DBG(pm8001_ha,
2329 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2330 /* TBC: used default set values */
2331 ts->resp = SAS_TASK_COMPLETE;
2332 ts->stat = SAS_OPEN_TO;
2333 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2334 default:
2335 PM8001_IO_DBG(pm8001_ha,
2336 pm8001_printk("Unknown status 0x%x\n", event));
2337 /* not allowed case. Therefore, return failed status */
2338 ts->resp = SAS_TASK_COMPLETE;
2339 ts->stat = SAS_OPEN_TO;
2340 break;
2341 }
2342 spin_lock_irqsave(&t->task_state_lock, flags);
2343 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2344 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2345 t->task_state_flags |= SAS_TASK_STATE_DONE;
2346 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2347 spin_unlock_irqrestore(&t->task_state_lock, flags);
2348 PM8001_FAIL_DBG(pm8001_ha,
2349 pm8001_printk("task 0x%p done with io_status 0x%x"
2350 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2351 t, event, ts->resp, ts->stat));
2352 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2353 } else if (t->uldd_task) {
2354 spin_unlock_irqrestore(&t->task_state_lock, flags);
2355 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2356 mb();/* ditto */
2357 spin_unlock_irq(&pm8001_ha->lock);
2358 t->task_done(t);
2359 spin_lock_irq(&pm8001_ha->lock);
2360 } else if (!t->uldd_task) {
2361 spin_unlock_irqrestore(&t->task_state_lock, flags);
2362 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2363 mb();/*ditto*/
2364 spin_unlock_irq(&pm8001_ha->lock);
2365 t->task_done(t);
2366 spin_lock_irq(&pm8001_ha->lock);
2367 }
2368}
2369
2370/*See the comments for mpi_ssp_completion */
2371static void
2372mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2373{
2374 u32 param, i;
2375 struct sas_task *t;
2376 struct pm8001_ccb_info *ccb;
2377 unsigned long flags;
2378 u32 status;
2379 u32 tag;
2380 struct smp_completion_resp *psmpPayload;
2381 struct task_status_struct *ts;
2382 struct pm8001_device *pm8001_dev;
2383 char *pdma_respaddr = NULL;
2384
2385 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2386 status = le32_to_cpu(psmpPayload->status);
2387 tag = le32_to_cpu(psmpPayload->tag);
2388
2389 ccb = &pm8001_ha->ccb_info[tag];
2390 param = le32_to_cpu(psmpPayload->param);
2391 t = ccb->task;
2392 ts = &t->task_status;
2393 pm8001_dev = ccb->device;
2394 if (status)
2395 PM8001_FAIL_DBG(pm8001_ha,
2396 pm8001_printk("smp IO status 0x%x\n", status));
2397 if (unlikely(!t || !t->lldd_task || !t->dev))
2398 return;
2399
2400 switch (status) {
2401
2402 case IO_SUCCESS:
2403 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2404 ts->resp = SAS_TASK_COMPLETE;
2405 ts->stat = SAM_STAT_GOOD;
2406 if (pm8001_dev)
2407 pm8001_dev->running_req--;
2408 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2409 PM8001_IO_DBG(pm8001_ha,
2410 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2411 param));
2412 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2413 ((u64)sg_dma_address
2414 (&t->smp_task.smp_resp))));
2415 for (i = 0; i < param; i++) {
2416 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2417 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2418 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2419 i, *(pdma_respaddr+i),
2420 psmpPayload->_r_a[i]));
2421 }
2422 }
2423 break;
2424 case IO_ABORTED:
2425 PM8001_IO_DBG(pm8001_ha,
2426 pm8001_printk("IO_ABORTED IOMB\n"));
2427 ts->resp = SAS_TASK_COMPLETE;
2428 ts->stat = SAS_ABORTED_TASK;
2429 if (pm8001_dev)
2430 pm8001_dev->running_req--;
2431 break;
2432 case IO_OVERFLOW:
2433 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2434 ts->resp = SAS_TASK_COMPLETE;
2435 ts->stat = SAS_DATA_OVERRUN;
2436 ts->residual = 0;
2437 if (pm8001_dev)
2438 pm8001_dev->running_req--;
2439 break;
2440 case IO_NO_DEVICE:
2441 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2442 ts->resp = SAS_TASK_COMPLETE;
2443 ts->stat = SAS_PHY_DOWN;
2444 break;
2445 case IO_ERROR_HW_TIMEOUT:
2446 PM8001_IO_DBG(pm8001_ha,
2447 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2448 ts->resp = SAS_TASK_COMPLETE;
2449 ts->stat = SAM_STAT_BUSY;
2450 break;
2451 case IO_XFER_ERROR_BREAK:
2452 PM8001_IO_DBG(pm8001_ha,
2453 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2454 ts->resp = SAS_TASK_COMPLETE;
2455 ts->stat = SAM_STAT_BUSY;
2456 break;
2457 case IO_XFER_ERROR_PHY_NOT_READY:
2458 PM8001_IO_DBG(pm8001_ha,
2459 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2460 ts->resp = SAS_TASK_COMPLETE;
2461 ts->stat = SAM_STAT_BUSY;
2462 break;
2463 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2464 PM8001_IO_DBG(pm8001_ha,
2465 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2466 ts->resp = SAS_TASK_COMPLETE;
2467 ts->stat = SAS_OPEN_REJECT;
2468 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2469 break;
2470 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2471 PM8001_IO_DBG(pm8001_ha,
2472 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2473 ts->resp = SAS_TASK_COMPLETE;
2474 ts->stat = SAS_OPEN_REJECT;
2475 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2476 break;
2477 case IO_OPEN_CNX_ERROR_BREAK:
2478 PM8001_IO_DBG(pm8001_ha,
2479 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2480 ts->resp = SAS_TASK_COMPLETE;
2481 ts->stat = SAS_OPEN_REJECT;
2482 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2483 break;
2484 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2485 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2486 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2487 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2488 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2489 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2490 PM8001_IO_DBG(pm8001_ha,
2491 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2492 ts->resp = SAS_TASK_COMPLETE;
2493 ts->stat = SAS_OPEN_REJECT;
2494 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2495 pm8001_handle_event(pm8001_ha,
2496 pm8001_dev,
2497 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2498 break;
2499 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2500 PM8001_IO_DBG(pm8001_ha,
2501 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2502 ts->resp = SAS_TASK_COMPLETE;
2503 ts->stat = SAS_OPEN_REJECT;
2504 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2505 break;
2506 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2507 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2508 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2509 ts->resp = SAS_TASK_COMPLETE;
2510 ts->stat = SAS_OPEN_REJECT;
2511 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2512 break;
2513 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2514 PM8001_IO_DBG(pm8001_ha,
2515 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2516 ts->resp = SAS_TASK_COMPLETE;
2517 ts->stat = SAS_OPEN_REJECT;
2518 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2519 break;
2520 case IO_XFER_ERROR_RX_FRAME:
2521 PM8001_IO_DBG(pm8001_ha,
2522 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2523 ts->resp = SAS_TASK_COMPLETE;
2524 ts->stat = SAS_DEV_NO_RESPONSE;
2525 break;
2526 case IO_XFER_OPEN_RETRY_TIMEOUT:
2527 PM8001_IO_DBG(pm8001_ha,
2528 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2529 ts->resp = SAS_TASK_COMPLETE;
2530 ts->stat = SAS_OPEN_REJECT;
2531 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2532 break;
2533 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2534 PM8001_IO_DBG(pm8001_ha,
2535 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_QUEUE_FULL;
2538 break;
2539 case IO_PORT_IN_RESET:
2540 PM8001_IO_DBG(pm8001_ha,
2541 pm8001_printk("IO_PORT_IN_RESET\n"));
2542 ts->resp = SAS_TASK_COMPLETE;
2543 ts->stat = SAS_OPEN_REJECT;
2544 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2545 break;
2546 case IO_DS_NON_OPERATIONAL:
2547 PM8001_IO_DBG(pm8001_ha,
2548 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2549 ts->resp = SAS_TASK_COMPLETE;
2550 ts->stat = SAS_DEV_NO_RESPONSE;
2551 break;
2552 case IO_DS_IN_RECOVERY:
2553 PM8001_IO_DBG(pm8001_ha,
2554 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2555 ts->resp = SAS_TASK_COMPLETE;
2556 ts->stat = SAS_OPEN_REJECT;
2557 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2558 break;
2559 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2560 PM8001_IO_DBG(pm8001_ha,
2561 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2562 ts->resp = SAS_TASK_COMPLETE;
2563 ts->stat = SAS_OPEN_REJECT;
2564 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2565 break;
2566 default:
2567 PM8001_IO_DBG(pm8001_ha,
2568 pm8001_printk("Unknown status 0x%x\n", status));
2569 ts->resp = SAS_TASK_COMPLETE;
2570 ts->stat = SAS_DEV_NO_RESPONSE;
2571 /* not allowed case. Therefore, return failed status */
2572 break;
2573 }
2574 spin_lock_irqsave(&t->task_state_lock, flags);
2575 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2576 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2577 t->task_state_flags |= SAS_TASK_STATE_DONE;
2578 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2579 spin_unlock_irqrestore(&t->task_state_lock, flags);
2580 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2581 "task 0x%p done with io_status 0x%x resp 0x%x"
2582 "stat 0x%x but aborted by upper layer!\n",
2583 t, status, ts->resp, ts->stat));
2584 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2585 } else {
2586 spin_unlock_irqrestore(&t->task_state_lock, flags);
2587 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2588 mb();/* in order to force CPU ordering */
2589 t->task_done(t);
2590 }
2591}
2592
2593/**
2594 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2595 * @pm8001_ha: our hba card information
2596 * @Qnum: the outbound queue message number.
2597 * @SEA: source of event to ack
2598 * @port_id: port id.
2599 * @phyId: phy id.
2600 * @param0: parameter 0.
2601 * @param1: parameter 1.
2602 */
2603static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2604 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2605{
2606 struct hw_event_ack_req payload;
2607 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2608
2609 struct inbound_queue_table *circularQ;
2610
2611 memset((u8 *)&payload, 0, sizeof(payload));
2612 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2613 payload.tag = cpu_to_le32(1);
2614 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2615 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2616 payload.param0 = cpu_to_le32(param0);
2617 payload.param1 = cpu_to_le32(param1);
2618 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2619}
2620
2621static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2622 u32 phyId, u32 phy_op);
2623
2624/**
2625 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2626 * @pm8001_ha: our hba card information
2627 * @piomb: IO message buffer
2628 */
2629static void
2630hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2631{
2632 struct hw_event_resp *pPayload =
2633 (struct hw_event_resp *)(piomb + 4);
2634 u32 lr_status_evt_portid =
2635 le32_to_cpu(pPayload->lr_status_evt_portid);
2636 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2637
2638 u8 link_rate =
2639 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2640 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2641 u8 phy_id =
2642 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2643 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2644
2645 struct pm8001_port *port = &pm8001_ha->port[port_id];
2646 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2647 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2648 unsigned long flags;
2649 u8 deviceType = pPayload->sas_identify.dev_type;
2650 port->port_state = portstate;
2651 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2652 "portid:%d; phyid:%d; linkrate:%d; "
2653 "portstate:%x; devicetype:%x\n",
2654 port_id, phy_id, link_rate, portstate, deviceType));
2655
2656 switch (deviceType) {
2657 case SAS_PHY_UNUSED:
2658 PM8001_MSG_DBG(pm8001_ha,
2659 pm8001_printk("device type no device.\n"));
2660 break;
2661 case SAS_END_DEVICE:
2662 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2663 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2664 PHY_NOTIFY_ENABLE_SPINUP);
2665 port->port_attached = 1;
2666 pm8001_get_lrate_mode(phy, link_rate);
2667 break;
2668 case SAS_EDGE_EXPANDER_DEVICE:
2669 PM8001_MSG_DBG(pm8001_ha,
2670 pm8001_printk("expander device.\n"));
2671 port->port_attached = 1;
2672 pm8001_get_lrate_mode(phy, link_rate);
2673 break;
2674 case SAS_FANOUT_EXPANDER_DEVICE:
2675 PM8001_MSG_DBG(pm8001_ha,
2676 pm8001_printk("fanout expander device.\n"));
2677 port->port_attached = 1;
2678 pm8001_get_lrate_mode(phy, link_rate);
2679 break;
2680 default:
2681 PM8001_MSG_DBG(pm8001_ha,
2682 pm8001_printk("unknown device type(%x)\n", deviceType));
2683 break;
2684 }
2685 phy->phy_type |= PORT_TYPE_SAS;
2686 phy->identify.device_type = deviceType;
2687 phy->phy_attached = 1;
2688 if (phy->identify.device_type == SAS_END_DEVICE)
2689 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2690 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2691 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2692 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2693 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2694 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2695 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2696 sizeof(struct sas_identify_frame)-4);
2697 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2698 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2699 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2700 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2701 mdelay(200);/*delay a moment to wait disk to spinup*/
2702 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2703}
2704
2705/**
2706 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2707 * @pm8001_ha: our hba card information
2708 * @piomb: IO message buffer
2709 */
2710static void
2711hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2712{
2713 struct hw_event_resp *pPayload =
2714 (struct hw_event_resp *)(piomb + 4);
2715 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2716 u32 lr_status_evt_portid =
2717 le32_to_cpu(pPayload->lr_status_evt_portid);
2718 u8 link_rate =
2719 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2720 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2721 u8 phy_id =
2722 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2723
2724 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2725
2726 struct pm8001_port *port = &pm8001_ha->port[port_id];
2727 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2728 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2729 unsigned long flags;
2730 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2731 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2732 port_id, phy_id, link_rate, portstate));
2733
2734 port->port_state = portstate;
2735 port->port_attached = 1;
2736 pm8001_get_lrate_mode(phy, link_rate);
2737 phy->phy_type |= PORT_TYPE_SATA;
2738 phy->phy_attached = 1;
2739 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2740 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2741 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2742 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2743 sizeof(struct dev_to_host_fis));
2744 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2745 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]2746 phy->identify.device_type = SAS_SATA_DEV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2747 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2748 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2749 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2750}
2751
2752/**
2753 * hw_event_phy_down -we should notify the libsas the phy is down.
2754 * @pm8001_ha: our hba card information
2755 * @piomb: IO message buffer
2756 */
2757static void
2758hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2759{
2760 struct hw_event_resp *pPayload =
2761 (struct hw_event_resp *)(piomb + 4);
2762
2763 u32 lr_status_evt_portid =
2764 le32_to_cpu(pPayload->lr_status_evt_portid);
2765 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2766 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2767 u8 phy_id =
2768 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2769 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2770
2771 struct pm8001_port *port = &pm8001_ha->port[port_id];
2772 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2773 port->port_state = portstate;
2774 phy->phy_type = 0;
2775 phy->identify.device_type = 0;
2776 phy->phy_attached = 0;
2777 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2778 switch (portstate) {
2779 case PORT_VALID:
2780 break;
2781 case PORT_INVALID:
2782 PM8001_MSG_DBG(pm8001_ha,
2783 pm8001_printk(" PortInvalid portID %d\n", port_id));
2784 PM8001_MSG_DBG(pm8001_ha,
2785 pm8001_printk(" Last phy Down and port invalid\n"));
2786 port->port_attached = 0;
2787 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2788 port_id, phy_id, 0, 0);
2789 break;
2790 case PORT_IN_RESET:
2791 PM8001_MSG_DBG(pm8001_ha,
2792 pm8001_printk(" Port In Reset portID %d\n", port_id));
2793 break;
2794 case PORT_NOT_ESTABLISHED:
2795 PM8001_MSG_DBG(pm8001_ha,
2796 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2797 port->port_attached = 0;
2798 break;
2799 case PORT_LOSTCOMM:
2800 PM8001_MSG_DBG(pm8001_ha,
2801 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2802 PM8001_MSG_DBG(pm8001_ha,
2803 pm8001_printk(" Last phy Down and port invalid\n"));
2804 port->port_attached = 0;
2805 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2806 port_id, phy_id, 0, 0);
2807 break;
2808 default:
2809 port->port_attached = 0;
2810 PM8001_MSG_DBG(pm8001_ha,
2811 pm8001_printk(" phy Down and(default) = 0x%x\n",
2812 portstate));
2813 break;
2814
2815 }
2816}
2817
2818static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2819{
2820 struct phy_start_resp *pPayload =
2821 (struct phy_start_resp *)(piomb + 4);
2822 u32 status =
2823 le32_to_cpu(pPayload->status);
2824 u32 phy_id =
2825 le32_to_cpu(pPayload->phyid);
2826 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2827
2828 PM8001_INIT_DBG(pm8001_ha,
2829 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2830 status, phy_id));
2831 if (status == 0) {
2832 phy->phy_state = 1;
2833 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2834 complete(phy->enable_completion);
2835 }
2836 return 0;
2837
2838}
2839
2840/**
2841 * mpi_thermal_hw_event -The hw event has come.
2842 * @pm8001_ha: our hba card information
2843 * @piomb: IO message buffer
2844 */
2845static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2846{
2847 struct thermal_hw_event *pPayload =
2848 (struct thermal_hw_event *)(piomb + 4);
2849
2850 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2851 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2852
2853 if (thermal_event & 0x40) {
2854 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2855 "Thermal Event: Local high temperature violated!\n"));
2856 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2857 "Thermal Event: Measured local high temperature %d\n",
2858 ((rht_lht & 0xFF00) >> 8)));
2859 }
2860 if (thermal_event & 0x10) {
2861 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2862 "Thermal Event: Remote high temperature violated!\n"));
2863 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2864 "Thermal Event: Measured remote high temperature %d\n",
2865 ((rht_lht & 0xFF000000) >> 24)));
2866 }
2867 return 0;
2868}
2869
2870/**
2871 * mpi_hw_event -The hw event has come.
2872 * @pm8001_ha: our hba card information
2873 * @piomb: IO message buffer
2874 */
2875static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2876{
2877 unsigned long flags;
2878 struct hw_event_resp *pPayload =
2879 (struct hw_event_resp *)(piomb + 4);
2880 u32 lr_status_evt_portid =
2881 le32_to_cpu(pPayload->lr_status_evt_portid);
2882 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2883 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2884 u8 phy_id =
2885 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2886 u16 eventType =
2887 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2888 u8 status =
2889 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2890
2891 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2892 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2893 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2894 PM8001_MSG_DBG(pm8001_ha,
2895 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2896 port_id, phy_id, eventType, status));
2897
2898 switch (eventType) {
2899
2900 case HW_EVENT_SAS_PHY_UP:
2901 PM8001_MSG_DBG(pm8001_ha,
2902 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2903 hw_event_sas_phy_up(pm8001_ha, piomb);
2904 break;
2905 case HW_EVENT_SATA_PHY_UP:
2906 PM8001_MSG_DBG(pm8001_ha,
2907 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2908 hw_event_sata_phy_up(pm8001_ha, piomb);
2909 break;
2910 case HW_EVENT_SATA_SPINUP_HOLD:
2911 PM8001_MSG_DBG(pm8001_ha,
2912 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2913 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2914 break;
2915 case HW_EVENT_PHY_DOWN:
2916 PM8001_MSG_DBG(pm8001_ha,
2917 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2918 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2919 phy->phy_attached = 0;
2920 phy->phy_state = 0;
2921 hw_event_phy_down(pm8001_ha, piomb);
2922 break;
2923 case HW_EVENT_PORT_INVALID:
2924 PM8001_MSG_DBG(pm8001_ha,
2925 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2926 sas_phy_disconnected(sas_phy);
2927 phy->phy_attached = 0;
2928 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2929 break;
2930 /* the broadcast change primitive received, tell the LIBSAS this event
2931 to revalidate the sas domain*/
2932 case HW_EVENT_BROADCAST_CHANGE:
2933 PM8001_MSG_DBG(pm8001_ha,
2934 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2935 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2936 port_id, phy_id, 1, 0);
2937 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2938 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2939 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2940 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2941 break;
2942 case HW_EVENT_PHY_ERROR:
2943 PM8001_MSG_DBG(pm8001_ha,
2944 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2945 sas_phy_disconnected(&phy->sas_phy);
2946 phy->phy_attached = 0;
2947 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2948 break;
2949 case HW_EVENT_BROADCAST_EXP:
2950 PM8001_MSG_DBG(pm8001_ha,
2951 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2952 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2953 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2954 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2955 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2956 break;
2957 case HW_EVENT_LINK_ERR_INVALID_DWORD:
2958 PM8001_MSG_DBG(pm8001_ha,
2959 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2960 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2961 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2962 sas_phy_disconnected(sas_phy);
2963 phy->phy_attached = 0;
2964 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2965 break;
2966 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2967 PM8001_MSG_DBG(pm8001_ha,
2968 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2969 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2970 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2971 port_id, phy_id, 0, 0);
2972 sas_phy_disconnected(sas_phy);
2973 phy->phy_attached = 0;
2974 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2975 break;
2976 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2977 PM8001_MSG_DBG(pm8001_ha,
2978 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
2979 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2980 HW_EVENT_LINK_ERR_CODE_VIOLATION,
2981 port_id, phy_id, 0, 0);
2982 sas_phy_disconnected(sas_phy);
2983 phy->phy_attached = 0;
2984 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2985 break;
2986 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
2987 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2988 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
2989 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2990 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
2991 port_id, phy_id, 0, 0);
2992 sas_phy_disconnected(sas_phy);
2993 phy->phy_attached = 0;
2994 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2995 break;
2996 case HW_EVENT_MALFUNCTION:
2997 PM8001_MSG_DBG(pm8001_ha,
2998 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
2999 break;
3000 case HW_EVENT_BROADCAST_SES:
3001 PM8001_MSG_DBG(pm8001_ha,
3002 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3003 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3004 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3005 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3006 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3007 break;
3008 case HW_EVENT_INBOUND_CRC_ERROR:
3009 PM8001_MSG_DBG(pm8001_ha,
3010 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3011 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3012 HW_EVENT_INBOUND_CRC_ERROR,
3013 port_id, phy_id, 0, 0);
3014 break;
3015 case HW_EVENT_HARD_RESET_RECEIVED:
3016 PM8001_MSG_DBG(pm8001_ha,
3017 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3018 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3019 break;
3020 case HW_EVENT_ID_FRAME_TIMEOUT:
3021 PM8001_MSG_DBG(pm8001_ha,
3022 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3023 sas_phy_disconnected(sas_phy);
3024 phy->phy_attached = 0;
3025 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3026 break;
3027 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3028 PM8001_MSG_DBG(pm8001_ha,
3029 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3030 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3031 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3032 port_id, phy_id, 0, 0);
3033 sas_phy_disconnected(sas_phy);
3034 phy->phy_attached = 0;
3035 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3036 break;
3037 case HW_EVENT_PORT_RESET_TIMER_TMO:
3038 PM8001_MSG_DBG(pm8001_ha,
3039 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3040 sas_phy_disconnected(sas_phy);
3041 phy->phy_attached = 0;
3042 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3043 break;
3044 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3045 PM8001_MSG_DBG(pm8001_ha,
3046 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]3047 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3048 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3049 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3050 sas_phy_disconnected(sas_phy);
3051 phy->phy_attached = 0;
3052 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3053 break;
3054 case HW_EVENT_PORT_RECOVER:
3055 PM8001_MSG_DBG(pm8001_ha,
3056 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3057 break;
3058 case HW_EVENT_PORT_RESET_COMPLETE:
3059 PM8001_MSG_DBG(pm8001_ha,
3060 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3061 break;
3062 case EVENT_BROADCAST_ASYNCH_EVENT:
3063 PM8001_MSG_DBG(pm8001_ha,
3064 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3065 break;
3066 default:
3067 PM8001_MSG_DBG(pm8001_ha,
3068 pm8001_printk("Unknown event type 0x%x\n", eventType));
3069 break;
3070 }
3071 return 0;
3072}
3073
3074/**
3075 * mpi_phy_stop_resp - SPCv specific
3076 * @pm8001_ha: our hba card information
3077 * @piomb: IO message buffer
3078 */
3079static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3080{
3081 struct phy_stop_resp *pPayload =
3082 (struct phy_stop_resp *)(piomb + 4);
3083 u32 status =
3084 le32_to_cpu(pPayload->status);
3085 u32 phyid =
3086 le32_to_cpu(pPayload->phyid);
3087 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3088 PM8001_MSG_DBG(pm8001_ha,
3089 pm8001_printk("phy:0x%x status:0x%x\n",
3090 phyid, status));
3091 if (status == 0)
3092 phy->phy_state = 0;
3093 return 0;
3094}
3095
3096/**
3097 * mpi_set_controller_config_resp - SPCv specific
3098 * @pm8001_ha: our hba card information
3099 * @piomb: IO message buffer
3100 */
3101static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3102 void *piomb)
3103{
3104 struct set_ctrl_cfg_resp *pPayload =
3105 (struct set_ctrl_cfg_resp *)(piomb + 4);
3106 u32 status = le32_to_cpu(pPayload->status);
3107 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3108
3109 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3110 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3111 status, err_qlfr_pgcd));
3112
3113 return 0;
3114}
3115
3116/**
3117 * mpi_get_controller_config_resp - SPCv specific
3118 * @pm8001_ha: our hba card information
3119 * @piomb: IO message buffer
3120 */
3121static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3122 void *piomb)
3123{
3124 PM8001_MSG_DBG(pm8001_ha,
3125 pm8001_printk(" pm80xx_addition_functionality\n"));
3126
3127 return 0;
3128}
3129
3130/**
3131 * mpi_get_phy_profile_resp - SPCv specific
3132 * @pm8001_ha: our hba card information
3133 * @piomb: IO message buffer
3134 */
3135static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3136 void *piomb)
3137{
3138 PM8001_MSG_DBG(pm8001_ha,
3139 pm8001_printk(" pm80xx_addition_functionality\n"));
3140
3141 return 0;
3142}
3143
3144/**
3145 * mpi_flash_op_ext_resp - SPCv specific
3146 * @pm8001_ha: our hba card information
3147 * @piomb: IO message buffer
3148 */
3149static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3150{
3151 PM8001_MSG_DBG(pm8001_ha,
3152 pm8001_printk(" pm80xx_addition_functionality\n"));
3153
3154 return 0;
3155}
3156
3157/**
3158 * mpi_set_phy_profile_resp - SPCv specific
3159 * @pm8001_ha: our hba card information
3160 * @piomb: IO message buffer
3161 */
3162static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3163 void *piomb)
3164{
3165 PM8001_MSG_DBG(pm8001_ha,
3166 pm8001_printk(" pm80xx_addition_functionality\n"));
3167
3168 return 0;
3169}
3170
3171/**
3172 * mpi_kek_management_resp - SPCv specific
3173 * @pm8001_ha: our hba card information
3174 * @piomb: IO message buffer
3175 */
3176static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3177 void *piomb)
3178{
3179 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3180
3181 u32 status = le32_to_cpu(pPayload->status);
3182 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3183 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3184
3185 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3186 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3187 status, kidx_new_curr_ksop, err_qlfr));
3188
3189 return 0;
3190}
3191
3192/**
3193 * mpi_dek_management_resp - SPCv specific
3194 * @pm8001_ha: our hba card information
3195 * @piomb: IO message buffer
3196 */
3197static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3198 void *piomb)
3199{
3200 PM8001_MSG_DBG(pm8001_ha,
3201 pm8001_printk(" pm80xx_addition_functionality\n"));
3202
3203 return 0;
3204}
3205
3206/**
3207 * ssp_coalesced_comp_resp - SPCv specific
3208 * @pm8001_ha: our hba card information
3209 * @piomb: IO message buffer
3210 */
3211static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3212 void *piomb)
3213{
3214 PM8001_MSG_DBG(pm8001_ha,
3215 pm8001_printk(" pm80xx_addition_functionality\n"));
3216
3217 return 0;
3218}
3219
3220/**
3221 * process_one_iomb - process one outbound Queue memory block
3222 * @pm8001_ha: our hba card information
3223 * @piomb: IO message buffer
3224 */
3225static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3226{
3227 __le32 pHeader = *(__le32 *)piomb;
3228 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3229
3230 switch (opc) {
3231 case OPC_OUB_ECHO:
3232 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3233 break;
3234 case OPC_OUB_HW_EVENT:
3235 PM8001_MSG_DBG(pm8001_ha,
3236 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3237 mpi_hw_event(pm8001_ha, piomb);
3238 break;
3239 case OPC_OUB_THERM_HW_EVENT:
3240 PM8001_MSG_DBG(pm8001_ha,
3241 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3242 mpi_thermal_hw_event(pm8001_ha, piomb);
3243 break;
3244 case OPC_OUB_SSP_COMP:
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3247 mpi_ssp_completion(pm8001_ha, piomb);
3248 break;
3249 case OPC_OUB_SMP_COMP:
3250 PM8001_MSG_DBG(pm8001_ha,
3251 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3252 mpi_smp_completion(pm8001_ha, piomb);
3253 break;
3254 case OPC_OUB_LOCAL_PHY_CNTRL:
3255 PM8001_MSG_DBG(pm8001_ha,
3256 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3257 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3258 break;
3259 case OPC_OUB_DEV_REGIST:
3260 PM8001_MSG_DBG(pm8001_ha,
3261 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3262 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3263 break;
3264 case OPC_OUB_DEREG_DEV:
3265 PM8001_MSG_DBG(pm8001_ha,
Masanari Iida8b513d02013-05-21 23:13:12 +0900[diff] [blame]3266 pm8001_printk("unregister the device\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3267 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3268 break;
3269 case OPC_OUB_GET_DEV_HANDLE:
3270 PM8001_MSG_DBG(pm8001_ha,
3271 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3272 break;
3273 case OPC_OUB_SATA_COMP:
3274 PM8001_MSG_DBG(pm8001_ha,
3275 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3276 mpi_sata_completion(pm8001_ha, piomb);
3277 break;
3278 case OPC_OUB_SATA_EVENT:
3279 PM8001_MSG_DBG(pm8001_ha,
3280 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3281 mpi_sata_event(pm8001_ha, piomb);
3282 break;
3283 case OPC_OUB_SSP_EVENT:
3284 PM8001_MSG_DBG(pm8001_ha,
3285 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3286 mpi_ssp_event(pm8001_ha, piomb);
3287 break;
3288 case OPC_OUB_DEV_HANDLE_ARRIV:
3289 PM8001_MSG_DBG(pm8001_ha,
3290 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3291 /*This is for target*/
3292 break;
3293 case OPC_OUB_SSP_RECV_EVENT:
3294 PM8001_MSG_DBG(pm8001_ha,
3295 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3296 /*This is for target*/
3297 break;
3298 case OPC_OUB_FW_FLASH_UPDATE:
3299 PM8001_MSG_DBG(pm8001_ha,
3300 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3301 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3302 break;
3303 case OPC_OUB_GPIO_RESPONSE:
3304 PM8001_MSG_DBG(pm8001_ha,
3305 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3306 break;
3307 case OPC_OUB_GPIO_EVENT:
3308 PM8001_MSG_DBG(pm8001_ha,
3309 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3310 break;
3311 case OPC_OUB_GENERAL_EVENT:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3314 pm8001_mpi_general_event(pm8001_ha, piomb);
3315 break;
3316 case OPC_OUB_SSP_ABORT_RSP:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3319 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3320 break;
3321 case OPC_OUB_SATA_ABORT_RSP:
3322 PM8001_MSG_DBG(pm8001_ha,
3323 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3324 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3325 break;
3326 case OPC_OUB_SAS_DIAG_MODE_START_END:
3327 PM8001_MSG_DBG(pm8001_ha,
3328 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3329 break;
3330 case OPC_OUB_SAS_DIAG_EXECUTE:
3331 PM8001_MSG_DBG(pm8001_ha,
3332 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3333 break;
3334 case OPC_OUB_GET_TIME_STAMP:
3335 PM8001_MSG_DBG(pm8001_ha,
3336 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3337 break;
3338 case OPC_OUB_SAS_HW_EVENT_ACK:
3339 PM8001_MSG_DBG(pm8001_ha,
3340 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3341 break;
3342 case OPC_OUB_PORT_CONTROL:
3343 PM8001_MSG_DBG(pm8001_ha,
3344 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3345 break;
3346 case OPC_OUB_SMP_ABORT_RSP:
3347 PM8001_MSG_DBG(pm8001_ha,
3348 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3349 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3350 break;
3351 case OPC_OUB_GET_NVMD_DATA:
3352 PM8001_MSG_DBG(pm8001_ha,
3353 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3354 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3355 break;
3356 case OPC_OUB_SET_NVMD_DATA:
3357 PM8001_MSG_DBG(pm8001_ha,
3358 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3359 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3360 break;
3361 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3362 PM8001_MSG_DBG(pm8001_ha,
3363 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3364 break;
3365 case OPC_OUB_SET_DEVICE_STATE:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3368 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3369 break;
3370 case OPC_OUB_GET_DEVICE_STATE:
3371 PM8001_MSG_DBG(pm8001_ha,
3372 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3373 break;
3374 case OPC_OUB_SET_DEV_INFO:
3375 PM8001_MSG_DBG(pm8001_ha,
3376 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3377 break;
3378 /* spcv specifc commands */
3379 case OPC_OUB_PHY_START_RESP:
3380 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3381 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3382 mpi_phy_start_resp(pm8001_ha, piomb);
3383 break;
3384 case OPC_OUB_PHY_STOP_RESP:
3385 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3386 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3387 mpi_phy_stop_resp(pm8001_ha, piomb);
3388 break;
3389 case OPC_OUB_SET_CONTROLLER_CONFIG:
3390 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3391 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3392 mpi_set_controller_config_resp(pm8001_ha, piomb);
3393 break;
3394 case OPC_OUB_GET_CONTROLLER_CONFIG:
3395 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3396 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3397 mpi_get_controller_config_resp(pm8001_ha, piomb);
3398 break;
3399 case OPC_OUB_GET_PHY_PROFILE:
3400 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3401 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3402 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3403 break;
3404 case OPC_OUB_FLASH_OP_EXT:
3405 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3406 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3407 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3408 break;
3409 case OPC_OUB_SET_PHY_PROFILE:
3410 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3411 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3412 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3413 break;
3414 case OPC_OUB_KEK_MANAGEMENT_RESP:
3415 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3416 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3417 mpi_kek_management_resp(pm8001_ha, piomb);
3418 break;
3419 case OPC_OUB_DEK_MANAGEMENT_RESP:
3420 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3421 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3422 mpi_dek_management_resp(pm8001_ha, piomb);
3423 break;
3424 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3425 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3426 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3427 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3428 break;
3429 default:
3430 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3431 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3432 break;
3433 }
3434}
3435
3436static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3437{
3438 struct outbound_queue_table *circularQ;
3439 void *pMsg1 = NULL;
3440 u8 uninitialized_var(bc);
3441 u32 ret = MPI_IO_STATUS_FAIL;
3442 unsigned long flags;
3443
3444 spin_lock_irqsave(&pm8001_ha->lock, flags);
3445 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3446 do {
3447 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3448 if (MPI_IO_STATUS_SUCCESS == ret) {
3449 /* process the outbound message */
3450 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3451 /* free the message from the outbound circular buffer */
3452 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3453 circularQ, bc);
3454 }
3455 if (MPI_IO_STATUS_BUSY == ret) {
3456 /* Update the producer index from SPC */
3457 circularQ->producer_index =
3458 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3459 if (le32_to_cpu(circularQ->producer_index) ==
3460 circularQ->consumer_idx)
3461 /* OQ is empty */
3462 break;
3463 }
3464 } while (1);
3465 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3466 return ret;
3467}
3468
3469/* PCI_DMA_... to our direction translation. */
3470static const u8 data_dir_flags[] = {
3471 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3472 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3473 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3474 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3475};
3476
3477static void build_smp_cmd(u32 deviceID, __le32 hTag,
3478 struct smp_req *psmp_cmd, int mode, int length)
3479{
3480 psmp_cmd->tag = hTag;
3481 psmp_cmd->device_id = cpu_to_le32(deviceID);
3482 if (mode == SMP_DIRECT) {
3483 length = length - 4; /* subtract crc */
3484 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3485 } else {
3486 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3487 }
3488}
3489
3490/**
3491 * pm8001_chip_smp_req - send a SMP task to FW
3492 * @pm8001_ha: our hba card information.
3493 * @ccb: the ccb information this request used.
3494 */
3495static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3496 struct pm8001_ccb_info *ccb)
3497{
3498 int elem, rc;
3499 struct sas_task *task = ccb->task;
3500 struct domain_device *dev = task->dev;
3501 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3502 struct scatterlist *sg_req, *sg_resp;
3503 u32 req_len, resp_len;
3504 struct smp_req smp_cmd;
3505 u32 opc;
3506 struct inbound_queue_table *circularQ;
3507 char *preq_dma_addr = NULL;
3508 __le64 tmp_addr;
3509 u32 i, length;
3510
3511 memset(&smp_cmd, 0, sizeof(smp_cmd));
3512 /*
3513 * DMA-map SMP request, response buffers
3514 */
3515 sg_req = &task->smp_task.smp_req;
3516 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3517 if (!elem)
3518 return -ENOMEM;
3519 req_len = sg_dma_len(sg_req);
3520
3521 sg_resp = &task->smp_task.smp_resp;
3522 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3523 if (!elem) {
3524 rc = -ENOMEM;
3525 goto err_out;
3526 }
3527 resp_len = sg_dma_len(sg_resp);
3528 /* must be in dwords */
3529 if ((req_len & 0x3) || (resp_len & 0x3)) {
3530 rc = -EINVAL;
3531 goto err_out_2;
3532 }
3533
3534 opc = OPC_INB_SMP_REQUEST;
3535 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3536 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3537
3538 length = sg_req->length;
3539 PM8001_IO_DBG(pm8001_ha,
3540 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3541 if (!(length - 8))
3542 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3543 else
3544 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3545
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3546
3547 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3548 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3549
3550 /* INDIRECT MODE command settings. Use DMA */
3551 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3552 PM8001_IO_DBG(pm8001_ha,
3553 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3554 /* for SPCv indirect mode. Place the top 4 bytes of
3555 * SMP Request header here. */
3556 for (i = 0; i < 4; i++)
3557 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3558 /* exclude top 4 bytes for SMP req header */
3559 smp_cmd.long_smp_req.long_req_addr =
3560 cpu_to_le64((u64)sg_dma_address
Anand Kumar Santhanamcb993e52013-09-17 14:37:14 +0530[diff] [blame]3561 (&task->smp_task.smp_req) + 4);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3562 /* exclude 4 bytes for SMP req header and CRC */
3563 smp_cmd.long_smp_req.long_req_size =
3564 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3565 smp_cmd.long_smp_req.long_resp_addr =
3566 cpu_to_le64((u64)sg_dma_address
3567 (&task->smp_task.smp_resp));
3568 smp_cmd.long_smp_req.long_resp_size =
3569 cpu_to_le32((u32)sg_dma_len
3570 (&task->smp_task.smp_resp)-4);
3571 } else { /* DIRECT MODE */
3572 smp_cmd.long_smp_req.long_req_addr =
3573 cpu_to_le64((u64)sg_dma_address
3574 (&task->smp_task.smp_req));
3575 smp_cmd.long_smp_req.long_req_size =
3576 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3577 smp_cmd.long_smp_req.long_resp_addr =
3578 cpu_to_le64((u64)sg_dma_address
3579 (&task->smp_task.smp_resp));
3580 smp_cmd.long_smp_req.long_resp_size =
3581 cpu_to_le32
3582 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3583 }
3584 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3585 PM8001_IO_DBG(pm8001_ha,
3586 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3587 for (i = 0; i < length; i++)
3588 if (i < 16) {
3589 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3590 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3591 "Byte[%d]:%x (DMA data:%x)\n",
3592 i, smp_cmd.smp_req16[i],
3593 *(preq_dma_addr)));
3594 } else {
3595 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3596 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3597 "Byte[%d]:%x (DMA data:%x)\n",
3598 i, smp_cmd.smp_req[i],
3599 *(preq_dma_addr)));
3600 }
3601 }
3602
3603 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3604 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3605 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3606 return 0;
3607
3608err_out_2:
3609 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3610 PCI_DMA_FROMDEVICE);
3611err_out:
3612 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3613 PCI_DMA_TODEVICE);
3614 return rc;
3615}
3616
3617static int check_enc_sas_cmd(struct sas_task *task)
3618{
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3619 u8 cmd = task->ssp_task.cmd->cmnd[0];
3620
3621 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3622 return 1;
3623 else
3624 return 0;
3625}
3626
3627static int check_enc_sat_cmd(struct sas_task *task)
3628{
3629 int ret = 0;
3630 switch (task->ata_task.fis.command) {
3631 case ATA_CMD_FPDMA_READ:
3632 case ATA_CMD_READ_EXT:
3633 case ATA_CMD_READ:
3634 case ATA_CMD_FPDMA_WRITE:
3635 case ATA_CMD_WRITE_EXT:
3636 case ATA_CMD_WRITE:
3637 case ATA_CMD_PIO_READ:
3638 case ATA_CMD_PIO_READ_EXT:
3639 case ATA_CMD_PIO_WRITE:
3640 case ATA_CMD_PIO_WRITE_EXT:
3641 ret = 1;
3642 break;
3643 default:
3644 ret = 0;
3645 break;
3646 }
3647 return ret;
3648}
3649
3650/**
3651 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3652 * @pm8001_ha: our hba card information.
3653 * @ccb: the ccb information this request used.
3654 */
3655static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3656 struct pm8001_ccb_info *ccb)
3657{
3658 struct sas_task *task = ccb->task;
3659 struct domain_device *dev = task->dev;
3660 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3661 struct ssp_ini_io_start_req ssp_cmd;
3662 u32 tag = ccb->ccb_tag;
3663 int ret;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3664 u64 phys_addr, start_addr, end_addr;
3665 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3666 struct inbound_queue_table *circularQ;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3667 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3668 u32 opc = OPC_INB_SSPINIIOSTART;
3669 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3670 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3671 /* data address domain added for spcv; set to 0 by host,
3672 * used internally by controller
3673 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3674 */
3675 ssp_cmd.dad_dir_m_tlr =
3676 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3677 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3678 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3679 ssp_cmd.tag = cpu_to_le32(tag);
3680 if (task->ssp_task.enable_first_burst)
3681 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3682 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3683 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3684 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3685 task->ssp_task.cmd->cmd_len);
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3686 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3687 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3688
3689 /* Check if encryption is set */
3690 if (pm8001_ha->chip->encrypt &&
3691 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3692 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3693 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3694 task->ssp_task.cmd->cmnd[0]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3695 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3696 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3697 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3698 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3699
3700 /* fill in PRD (scatter/gather) table, if any */
3701 if (task->num_scatter > 1) {
3702 pm8001_chip_make_sg(task->scatter,
3703 ccb->n_elem, ccb->buf_prd);
3704 phys_addr = ccb->ccb_dma_handle +
3705 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3706 ssp_cmd.enc_addr_low =
3707 cpu_to_le32(lower_32_bits(phys_addr));
3708 ssp_cmd.enc_addr_high =
3709 cpu_to_le32(upper_32_bits(phys_addr));
3710 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3711 } else if (task->num_scatter == 1) {
3712 u64 dma_addr = sg_dma_address(task->scatter);
3713 ssp_cmd.enc_addr_low =
3714 cpu_to_le32(lower_32_bits(dma_addr));
3715 ssp_cmd.enc_addr_high =
3716 cpu_to_le32(upper_32_bits(dma_addr));
3717 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3718 ssp_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3719 /* Check 4G Boundary */
3720 start_addr = cpu_to_le64(dma_addr);
3721 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3722 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3723 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3724 if (end_addr_high != ssp_cmd.enc_addr_high) {
3725 PM8001_FAIL_DBG(pm8001_ha,
3726 pm8001_printk("The sg list address "
3727 "start_addr=0x%016llx data_len=0x%x "
3728 "end_addr_high=0x%08x end_addr_low="
3729 "0x%08x has crossed 4G boundary\n",
3730 start_addr, ssp_cmd.enc_len,
3731 end_addr_high, end_addr_low));
3732 pm8001_chip_make_sg(task->scatter, 1,
3733 ccb->buf_prd);
3734 phys_addr = ccb->ccb_dma_handle +
3735 offsetof(struct pm8001_ccb_info,
3736 buf_prd[0]);
3737 ssp_cmd.enc_addr_low =
3738 cpu_to_le32(lower_32_bits(phys_addr));
3739 ssp_cmd.enc_addr_high =
3740 cpu_to_le32(upper_32_bits(phys_addr));
3741 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3742 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3743 } else if (task->num_scatter == 0) {
3744 ssp_cmd.enc_addr_low = 0;
3745 ssp_cmd.enc_addr_high = 0;
3746 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3747 ssp_cmd.enc_esgl = 0;
3748 }
3749 /* XTS mode. All other fields are 0 */
3750 ssp_cmd.key_cmode = 0x6 << 4;
3751 /* set tweak values. Should be the start lba */
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3752 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3753 (task->ssp_task.cmd->cmnd[3] << 16) |
3754 (task->ssp_task.cmd->cmnd[4] << 8) |
3755 (task->ssp_task.cmd->cmnd[5]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3756 } else {
3757 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3758 "Sending Normal SAS command 0x%x inb q %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3759 task->ssp_task.cmd->cmnd[0], q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3760 /* fill in PRD (scatter/gather) table, if any */
3761 if (task->num_scatter > 1) {
3762 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3763 ccb->buf_prd);
3764 phys_addr = ccb->ccb_dma_handle +
3765 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3766 ssp_cmd.addr_low =
3767 cpu_to_le32(lower_32_bits(phys_addr));
3768 ssp_cmd.addr_high =
3769 cpu_to_le32(upper_32_bits(phys_addr));
3770 ssp_cmd.esgl = cpu_to_le32(1<<31);
3771 } else if (task->num_scatter == 1) {
3772 u64 dma_addr = sg_dma_address(task->scatter);
3773 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3774 ssp_cmd.addr_high =
3775 cpu_to_le32(upper_32_bits(dma_addr));
3776 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3777 ssp_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3778 /* Check 4G Boundary */
3779 start_addr = cpu_to_le64(dma_addr);
3780 end_addr = (start_addr + ssp_cmd.len) - 1;
3781 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3782 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3783 if (end_addr_high != ssp_cmd.addr_high) {
3784 PM8001_FAIL_DBG(pm8001_ha,
3785 pm8001_printk("The sg list address "
3786 "start_addr=0x%016llx data_len=0x%x "
3787 "end_addr_high=0x%08x end_addr_low="
3788 "0x%08x has crossed 4G boundary\n",
3789 start_addr, ssp_cmd.len,
3790 end_addr_high, end_addr_low));
3791 pm8001_chip_make_sg(task->scatter, 1,
3792 ccb->buf_prd);
3793 phys_addr = ccb->ccb_dma_handle +
3794 offsetof(struct pm8001_ccb_info,
3795 buf_prd[0]);
3796 ssp_cmd.addr_low =
3797 cpu_to_le32(lower_32_bits(phys_addr));
3798 ssp_cmd.addr_high =
3799 cpu_to_le32(upper_32_bits(phys_addr));
3800 ssp_cmd.esgl = cpu_to_le32(1<<31);
3801 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3802 } else if (task->num_scatter == 0) {
3803 ssp_cmd.addr_low = 0;
3804 ssp_cmd.addr_high = 0;
3805 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3806 ssp_cmd.esgl = 0;
3807 }
3808 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3809 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
3810 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3811 &ssp_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3812 return ret;
3813}
3814
3815static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3816 struct pm8001_ccb_info *ccb)
3817{
3818 struct sas_task *task = ccb->task;
3819 struct domain_device *dev = task->dev;
3820 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3821 u32 tag = ccb->ccb_tag;
3822 int ret;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3823 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3824 struct sata_start_req sata_cmd;
3825 u32 hdr_tag, ncg_tag = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3826 u64 phys_addr, start_addr, end_addr;
3827 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3828 u32 ATAP = 0x0;
3829 u32 dir;
3830 struct inbound_queue_table *circularQ;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3831 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3832 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3833 memset(&sata_cmd, 0, sizeof(sata_cmd));
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3834 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3835 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3836
3837 if (task->data_dir == PCI_DMA_NONE) {
3838 ATAP = 0x04; /* no data*/
3839 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3840 } else if (likely(!task->ata_task.device_control_reg_update)) {
3841 if (task->ata_task.dma_xfer) {
3842 ATAP = 0x06; /* DMA */
3843 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3844 } else {
3845 ATAP = 0x05; /* PIO*/
3846 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3847 }
3848 if (task->ata_task.use_ncq &&
3849 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3850 ATAP = 0x07; /* FPDMA */
3851 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3852 }
3853 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3854 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
3855 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3856 ncg_tag = hdr_tag;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3857 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3858 dir = data_dir_flags[task->data_dir] << 8;
3859 sata_cmd.tag = cpu_to_le32(tag);
3860 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3861 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3862
3863 sata_cmd.sata_fis = task->ata_task.fis;
3864 if (likely(!task->ata_task.device_control_reg_update))
3865 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3866 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3867
3868 /* Check if encryption is set */
3869 if (pm8001_ha->chip->encrypt &&
3870 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3871 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3872 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3873 sata_cmd.sata_fis.command));
3874 opc = OPC_INB_SATA_DIF_ENC_IO;
3875
3876 /* set encryption bit */
3877 sata_cmd.ncqtag_atap_dir_m_dad =
3878 cpu_to_le32(((ncg_tag & 0xff)<<16)|
3879 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3880 /* dad (bit 0-1) is 0 */
3881 /* fill in PRD (scatter/gather) table, if any */
3882 if (task->num_scatter > 1) {
3883 pm8001_chip_make_sg(task->scatter,
3884 ccb->n_elem, ccb->buf_prd);
3885 phys_addr = ccb->ccb_dma_handle +
3886 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3887 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3888 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3889 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3890 } else if (task->num_scatter == 1) {
3891 u64 dma_addr = sg_dma_address(task->scatter);
3892 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3893 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3894 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3895 sata_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3896 /* Check 4G Boundary */
3897 start_addr = cpu_to_le64(dma_addr);
3898 end_addr = (start_addr + sata_cmd.enc_len) - 1;
3899 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3900 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3901 if (end_addr_high != sata_cmd.enc_addr_high) {
3902 PM8001_FAIL_DBG(pm8001_ha,
3903 pm8001_printk("The sg list address "
3904 "start_addr=0x%016llx data_len=0x%x "
3905 "end_addr_high=0x%08x end_addr_low"
3906 "=0x%08x has crossed 4G boundary\n",
3907 start_addr, sata_cmd.enc_len,
3908 end_addr_high, end_addr_low));
3909 pm8001_chip_make_sg(task->scatter, 1,
3910 ccb->buf_prd);
3911 phys_addr = ccb->ccb_dma_handle +
3912 offsetof(struct pm8001_ccb_info,
3913 buf_prd[0]);
3914 sata_cmd.enc_addr_low =
3915 lower_32_bits(phys_addr);
3916 sata_cmd.enc_addr_high =
3917 upper_32_bits(phys_addr);
3918 sata_cmd.enc_esgl =
3919 cpu_to_le32(1 << 31);
3920 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3921 } else if (task->num_scatter == 0) {
3922 sata_cmd.enc_addr_low = 0;
3923 sata_cmd.enc_addr_high = 0;
3924 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3925 sata_cmd.enc_esgl = 0;
3926 }
3927 /* XTS mode. All other fields are 0 */
3928 sata_cmd.key_index_mode = 0x6 << 4;
3929 /* set tweak values. Should be the start lba */
3930 sata_cmd.twk_val0 =
3931 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3932 (sata_cmd.sata_fis.lbah << 16) |
3933 (sata_cmd.sata_fis.lbam << 8) |
3934 (sata_cmd.sata_fis.lbal));
3935 sata_cmd.twk_val1 =
3936 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3937 (sata_cmd.sata_fis.lbam_exp));
3938 } else {
3939 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3940 "Sending Normal SATA command 0x%x inb %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3941 sata_cmd.sata_fis.command, q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3942 /* dad (bit 0-1) is 0 */
3943 sata_cmd.ncqtag_atap_dir_m_dad =
3944 cpu_to_le32(((ncg_tag & 0xff)<<16) |
3945 ((ATAP & 0x3f) << 10) | dir);
3946
3947 /* fill in PRD (scatter/gather) table, if any */
3948 if (task->num_scatter > 1) {
3949 pm8001_chip_make_sg(task->scatter,
3950 ccb->n_elem, ccb->buf_prd);
3951 phys_addr = ccb->ccb_dma_handle +
3952 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3953 sata_cmd.addr_low = lower_32_bits(phys_addr);
3954 sata_cmd.addr_high = upper_32_bits(phys_addr);
3955 sata_cmd.esgl = cpu_to_le32(1 << 31);
3956 } else if (task->num_scatter == 1) {
3957 u64 dma_addr = sg_dma_address(task->scatter);
3958 sata_cmd.addr_low = lower_32_bits(dma_addr);
3959 sata_cmd.addr_high = upper_32_bits(dma_addr);
3960 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3961 sata_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]3962 /* Check 4G Boundary */
3963 start_addr = cpu_to_le64(dma_addr);
3964 end_addr = (start_addr + sata_cmd.len) - 1;
3965 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3966 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3967 if (end_addr_high != sata_cmd.addr_high) {
3968 PM8001_FAIL_DBG(pm8001_ha,
3969 pm8001_printk("The sg list address "
3970 "start_addr=0x%016llx data_len=0x%x"
3971 "end_addr_high=0x%08x end_addr_low="
3972 "0x%08x has crossed 4G boundary\n",
3973 start_addr, sata_cmd.len,
3974 end_addr_high, end_addr_low));
3975 pm8001_chip_make_sg(task->scatter, 1,
3976 ccb->buf_prd);
3977 phys_addr = ccb->ccb_dma_handle +
3978 offsetof(struct pm8001_ccb_info,
3979 buf_prd[0]);
3980 sata_cmd.addr_low =
3981 lower_32_bits(phys_addr);
3982 sata_cmd.addr_high =
3983 upper_32_bits(phys_addr);
3984 sata_cmd.esgl = cpu_to_le32(1 << 31);
3985 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3986 } else if (task->num_scatter == 0) {
3987 sata_cmd.addr_low = 0;
3988 sata_cmd.addr_high = 0;
3989 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3990 sata_cmd.esgl = 0;
3991 }
3992 /* scsi cdb */
3993 sata_cmd.atapi_scsi_cdb[0] =
3994 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
3995 (task->ata_task.atapi_packet[1] << 8) |
3996 (task->ata_task.atapi_packet[2] << 16) |
3997 (task->ata_task.atapi_packet[3] << 24)));
3998 sata_cmd.atapi_scsi_cdb[1] =
3999 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4000 (task->ata_task.atapi_packet[5] << 8) |
4001 (task->ata_task.atapi_packet[6] << 16) |
4002 (task->ata_task.atapi_packet[7] << 24)));
4003 sata_cmd.atapi_scsi_cdb[2] =
4004 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4005 (task->ata_task.atapi_packet[9] << 8) |
4006 (task->ata_task.atapi_packet[10] << 16) |
4007 (task->ata_task.atapi_packet[11] << 24)));
4008 sata_cmd.atapi_scsi_cdb[3] =
4009 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4010 (task->ata_task.atapi_packet[13] << 8) |
4011 (task->ata_task.atapi_packet[14] << 16) |
4012 (task->ata_task.atapi_packet[15] << 24)));
4013 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4014
4015 /* Check for read log for failed drive and return */
4016 if (sata_cmd.sata_fis.command == 0x2f) {
4017 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4018 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4019 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4020 struct task_status_struct *ts;
4021
4022 pm8001_ha_dev->id &= 0xDFFFFFFF;
4023 ts = &task->task_status;
4024
4025 spin_lock_irqsave(&task->task_state_lock, flags);
4026 ts->resp = SAS_TASK_COMPLETE;
4027 ts->stat = SAM_STAT_GOOD;
4028 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4029 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4030 task->task_state_flags |= SAS_TASK_STATE_DONE;
4031 if (unlikely((task->task_state_flags &
4032 SAS_TASK_STATE_ABORTED))) {
4033 spin_unlock_irqrestore(&task->task_state_lock,
4034 flags);
4035 PM8001_FAIL_DBG(pm8001_ha,
4036 pm8001_printk("task 0x%p resp 0x%x "
4037 " stat 0x%x but aborted by upper layer "
4038 "\n", task, ts->resp, ts->stat));
4039 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4040 return 0;
4041 } else if (task->uldd_task) {
4042 spin_unlock_irqrestore(&task->task_state_lock,
4043 flags);
4044 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4045 mb();/* ditto */
4046 spin_unlock_irq(&pm8001_ha->lock);
4047 task->task_done(task);
4048 spin_lock_irq(&pm8001_ha->lock);
4049 return 0;
4050 } else if (!task->uldd_task) {
4051 spin_unlock_irqrestore(&task->task_state_lock,
4052 flags);
4053 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4054 mb();/*ditto*/
4055 spin_unlock_irq(&pm8001_ha->lock);
4056 task->task_done(task);
4057 spin_lock_irq(&pm8001_ha->lock);
4058 return 0;
4059 }
4060 }
4061 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4062 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4063 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4064 &sata_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4065 return ret;
4066}
4067
4068/**
4069 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4070 * @pm8001_ha: our hba card information.
4071 * @num: the inbound queue number
4072 * @phy_id: the phy id which we wanted to start up.
4073 */
4074static int
4075pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4076{
4077 struct phy_start_req payload;
4078 struct inbound_queue_table *circularQ;
4079 int ret;
4080 u32 tag = 0x01;
4081 u32 opcode = OPC_INB_PHYSTART;
4082 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4083 memset(&payload, 0, sizeof(payload));
4084 payload.tag = cpu_to_le32(tag);
4085
4086 PM8001_INIT_DBG(pm8001_ha,
4087 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4088 /*
4089 ** [0:7] PHY Identifier
4090 ** [8:11] link rate 1.5G, 3G, 6G
4091 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4092 ** [14] 0b disable spin up hold; 1b enable spin up hold
4093 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4094 */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]4095 if (!IS_SPCV_12G(pm8001_ha->pdev))
4096 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4097 LINKMODE_AUTO | LINKRATE_15 |
4098 LINKRATE_30 | LINKRATE_60 | phy_id);
4099 else
4100 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4101 LINKMODE_AUTO | LINKRATE_15 |
4102 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4103 phy_id);
4104
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4105 /* SSC Disable and SAS Analog ST configuration */
4106 /**
4107 payload.ase_sh_lm_slr_phyid =
4108 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4109 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4110 phy_id);
4111 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4112 **/
4113
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4114 payload.sas_identify.dev_type = SAS_END_DEVICE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4115 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4116 memcpy(payload.sas_identify.sas_addr,
4117 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4118 payload.sas_identify.phy_id = phy_id;
4119 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4120 return ret;
4121}
4122
4123/**
4124 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4125 * @pm8001_ha: our hba card information.
4126 * @num: the inbound queue number
4127 * @phy_id: the phy id which we wanted to start up.
4128 */
4129static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4130 u8 phy_id)
4131{
4132 struct phy_stop_req payload;
4133 struct inbound_queue_table *circularQ;
4134 int ret;
4135 u32 tag = 0x01;
4136 u32 opcode = OPC_INB_PHYSTOP;
4137 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4138 memset(&payload, 0, sizeof(payload));
4139 payload.tag = cpu_to_le32(tag);
4140 payload.phy_id = cpu_to_le32(phy_id);
4141 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4142 return ret;
4143}
4144
4145/**
4146 * see comments on pm8001_mpi_reg_resp.
4147 */
4148static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4149 struct pm8001_device *pm8001_dev, u32 flag)
4150{
4151 struct reg_dev_req payload;
4152 u32 opc;
4153 u32 stp_sspsmp_sata = 0x4;
4154 struct inbound_queue_table *circularQ;
4155 u32 linkrate, phy_id;
4156 int rc, tag = 0xdeadbeef;
4157 struct pm8001_ccb_info *ccb;
4158 u8 retryFlag = 0x1;
4159 u16 firstBurstSize = 0;
4160 u16 ITNT = 2000;
4161 struct domain_device *dev = pm8001_dev->sas_device;
4162 struct domain_device *parent_dev = dev->parent;
4163 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4164
4165 memset(&payload, 0, sizeof(payload));
4166 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4167 if (rc)
4168 return rc;
4169 ccb = &pm8001_ha->ccb_info[tag];
4170 ccb->device = pm8001_dev;
4171 ccb->ccb_tag = tag;
4172 payload.tag = cpu_to_le32(tag);
4173
4174 if (flag == 1) {
4175 stp_sspsmp_sata = 0x02; /*direct attached sata */
4176 } else {
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4177 if (pm8001_dev->dev_type == SAS_SATA_DEV)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4178 stp_sspsmp_sata = 0x00; /* stp*/
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4179 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4180 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4181 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4182 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4183 }
4184 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4185 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4186 else
4187 phy_id = pm8001_dev->attached_phy;
4188
4189 opc = OPC_INB_REG_DEV;
4190
4191 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4192 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4193
4194 payload.phyid_portid =
4195 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4196 ((phy_id & 0xFF) << 8));
4197
4198 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4199 ((linkrate & 0x0F) << 24) |
4200 ((stp_sspsmp_sata & 0x03) << 28));
4201 payload.firstburstsize_ITNexustimeout =
4202 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4203
4204 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4205 SAS_ADDR_SIZE);
4206
4207 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4208
4209 return rc;
4210}
4211
4212/**
4213 * pm80xx_chip_phy_ctl_req - support the local phy operation
4214 * @pm8001_ha: our hba card information.
4215 * @num: the inbound queue number
4216 * @phy_id: the phy id which we wanted to operate
4217 * @phy_op:
4218 */
4219static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4220 u32 phyId, u32 phy_op)
4221{
4222 struct local_phy_ctl_req payload;
4223 struct inbound_queue_table *circularQ;
4224 int ret;
4225 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4226 memset(&payload, 0, sizeof(payload));
4227 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4228 payload.tag = cpu_to_le32(1);
4229 payload.phyop_phyid =
4230 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4231 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4232 return ret;
4233}
4234
4235static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4236{
4237 u32 value;
4238#ifdef PM8001_USE_MSIX
4239 return 1;
4240#endif
4241 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4242 if (value)
4243 return 1;
4244 return 0;
4245
4246}
4247
4248/**
4249 * pm8001_chip_isr - PM8001 isr handler.
4250 * @pm8001_ha: our hba card information.
4251 * @irq: irq number.
4252 * @stat: stat.
4253 */
4254static irqreturn_t
4255pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4256{
4257 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4258 process_oq(pm8001_ha, vec);
4259 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4260 return IRQ_HANDLED;
4261}
4262
4263const struct pm8001_dispatch pm8001_80xx_dispatch = {
4264 .name = "pmc80xx",
4265 .chip_init = pm80xx_chip_init,
4266 .chip_soft_rst = pm80xx_chip_soft_rst,
4267 .chip_rst = pm80xx_hw_chip_rst,
4268 .chip_iounmap = pm8001_chip_iounmap,
4269 .isr = pm80xx_chip_isr,
4270 .is_our_interupt = pm80xx_chip_is_our_interupt,
4271 .isr_process_oq = process_oq,
4272 .interrupt_enable = pm80xx_chip_interrupt_enable,
4273 .interrupt_disable = pm80xx_chip_interrupt_disable,
4274 .make_prd = pm8001_chip_make_sg,
4275 .smp_req = pm80xx_chip_smp_req,
4276 .ssp_io_req = pm80xx_chip_ssp_io_req,
4277 .sata_req = pm80xx_chip_sata_req,
4278 .phy_start_req = pm80xx_chip_phy_start_req,
4279 .phy_stop_req = pm80xx_chip_phy_stop_req,
4280 .reg_dev_req = pm80xx_chip_reg_dev_req,
4281 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4282 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4283 .task_abort = pm8001_chip_abort_task,
4284 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4285 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4286 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4287 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4288 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4289};