blob: d55c6b240a30db3b5dc1c075f642b4deec6bbbf1 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Stephen Warrena7db2c12011-10-25 02:01:28 +00002/dts-v1/;
3
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05304#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06005#include "tegra20.dtsi"
Stephen Warrena7db2c12011-10-25 02:01:28 +00006
7/ {
8 model = "Compulab TrimSlice board";
9 compatible = "compulab,trimslice", "nvidia,tegra20";
10
Stephen Warren553c0a22013-12-09 14:43:59 -070011 aliases {
12 rtc0 = "/i2c@7000c500/rtc@56";
13 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080014 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070015 };
16
Jon Hunterf5bbb322016-02-09 13:51:59 +000017 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060021 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060022 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000023 };
24
Stephen Warren58ecb232013-11-25 17:53:16 -070025 host1x@50000000 {
26 hdmi@54280000 {
Thierry Redingdced3e32012-09-20 10:39:20 +020027 status = "okay";
28
29 vdd-supply = <&hdmi_vdd_reg>;
30 pll-supply = <&hdmi_pll_reg>;
31
32 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070033 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 GPIO_ACTIVE_HIGH>;
Thierry Redingdced3e32012-09-20 10:39:20 +020035 };
36 };
37
Stephen Warren58ecb232013-11-25 17:53:16 -070038 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060039 pinctrl-names = "default";
40 pinctrl-0 = <&state_default>;
41
42 state_default: pinmux {
43 ata {
44 nvidia,pins = "ata";
45 nvidia,function = "ide";
46 };
47 atb {
48 nvidia,pins = "atb", "gma";
49 nvidia,function = "sdio4";
50 };
51 atc {
52 nvidia,pins = "atc", "gmb";
53 nvidia,function = "nand";
54 };
55 atd {
56 nvidia,pins = "atd", "ate", "gme", "pta";
57 nvidia,function = "gmi";
58 };
59 cdev1 {
60 nvidia,pins = "cdev1";
61 nvidia,function = "plla_out";
62 };
63 cdev2 {
64 nvidia,pins = "cdev2";
65 nvidia,function = "pllp_out4";
66 };
67 crtp {
68 nvidia,pins = "crtp";
69 nvidia,function = "crt";
70 };
71 csus {
72 nvidia,pins = "csus";
73 nvidia,function = "vi_sensor_clk";
74 };
75 dap1 {
76 nvidia,pins = "dap1";
77 nvidia,function = "dap1";
78 };
79 dap2 {
80 nvidia,pins = "dap2";
81 nvidia,function = "dap2";
82 };
83 dap3 {
84 nvidia,pins = "dap3";
85 nvidia,function = "dap3";
86 };
87 dap4 {
88 nvidia,pins = "dap4";
89 nvidia,function = "dap4";
90 };
91 ddc {
92 nvidia,pins = "ddc";
93 nvidia,function = "i2c2";
94 };
95 dta {
96 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
97 nvidia,function = "vi";
98 };
99 dtf {
100 nvidia,pins = "dtf";
101 nvidia,function = "i2c3";
102 };
103 gmc {
104 nvidia,pins = "gmc", "gmd";
105 nvidia,function = "sflash";
106 };
107 gpu {
108 nvidia,pins = "gpu";
109 nvidia,function = "uarta";
110 };
111 gpu7 {
112 nvidia,pins = "gpu7";
113 nvidia,function = "rtck";
114 };
115 gpv {
116 nvidia,pins = "gpv", "slxa", "slxk";
117 nvidia,function = "pcie";
118 };
119 hdint {
120 nvidia,pins = "hdint";
121 nvidia,function = "hdmi";
122 };
123 i2cp {
124 nvidia,pins = "i2cp";
125 nvidia,function = "i2cp";
126 };
127 irrx {
128 nvidia,pins = "irrx", "irtx";
129 nvidia,function = "uartb";
130 };
131 kbca {
132 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
133 "kbce", "kbcf";
134 nvidia,function = "kbc";
135 };
136 lcsn {
137 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
138 "ld3", "ld4", "ld5", "ld6", "ld7",
139 "ld8", "ld9", "ld10", "ld11", "ld12",
140 "ld13", "ld14", "ld15", "ld16", "ld17",
141 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
142 "lhs", "lm0", "lm1", "lpp", "lpw0",
143 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
144 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
145 "lvs";
146 nvidia,function = "displaya";
147 };
148 owc {
149 nvidia,pins = "owc", "uac";
150 nvidia,function = "rsvd2";
151 };
152 pmc {
153 nvidia,pins = "pmc";
154 nvidia,function = "pwr_on";
155 };
156 rm {
157 nvidia,pins = "rm";
158 nvidia,function = "i2c1";
159 };
160 sdb {
161 nvidia,pins = "sdb", "sdc", "sdd";
162 nvidia,function = "pwm";
163 };
164 sdio1 {
165 nvidia,pins = "sdio1";
166 nvidia,function = "sdio1";
167 };
168 slxc {
169 nvidia,pins = "slxc", "slxd";
170 nvidia,function = "sdio3";
171 };
172 spdi {
173 nvidia,pins = "spdi", "spdo";
174 nvidia,function = "spdif";
175 };
176 spia {
177 nvidia,pins = "spia", "spib", "spic";
178 nvidia,function = "spi2";
179 };
180 spid {
181 nvidia,pins = "spid", "spie", "spif";
182 nvidia,function = "spi1";
183 };
184 spig {
185 nvidia,pins = "spig", "spih";
186 nvidia,function = "spi2_alt";
187 };
188 uaa {
189 nvidia,pins = "uaa", "uab", "uda";
190 nvidia,function = "ulpi";
191 };
192 uad {
193 nvidia,pins = "uad";
194 nvidia,function = "irda";
195 };
196 uca {
197 nvidia,pins = "uca", "ucb";
198 nvidia,function = "uartc";
199 };
200 conf_ata {
201 nvidia,pins = "ata", "atc", "atd", "ate",
202 "crtp", "dap2", "dap3", "dap4", "dta",
203 "dtb", "dtc", "dtd", "dte", "gmb",
204 "gme", "i2cp", "pta", "slxc", "slxd",
205 "spdi", "spdo", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600208 };
209 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600210 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
211 "gma", "gmc", "gmd", "gpu", "gpu7",
212 "gpv", "sdio1", "slxa", "slxk", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600215 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600216 conf_ck32 {
217 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
218 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600220 };
Stephen Warren563da212012-04-13 16:35:20 -0600221 conf_csus {
222 nvidia,pins = "csus", "spia", "spib",
223 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530224 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600226 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600227 conf_ddc {
228 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530229 nvidia,pull = <TEGRA_PIN_PULL_UP>;
230 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600231 };
232 conf_hdint {
233 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
234 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
235 "lvp0", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530236 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600237 };
238 conf_irrx {
239 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
240 "kbcc", "kbcd", "kbce", "kbcf", "owc",
241 "spic", "spie", "spig", "spih", "uaa",
242 "uab", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530243 nvidia,pull = <TEGRA_PIN_PULL_UP>;
244 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600245 };
246 conf_lc {
247 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530248 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600249 };
250 conf_ld0 {
251 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
252 "ld5", "ld6", "ld7", "ld8", "ld9",
253 "ld10", "ld11", "ld12", "ld13", "ld14",
254 "ld15", "ld16", "ld17", "ldi", "lhp0",
255 "lhp1", "lhp2", "lhs", "lm0", "lpp",
256 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
257 "lvs", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600259 };
260 conf_ld17_0 {
261 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
262 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530263 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600264 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700265 conf_spif {
266 nvidia,pins = "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530267 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
268 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700269 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600270 };
271 };
272
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600273 i2s@70002800 {
274 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600275 };
276
277 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600278 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600279 };
280
Thierry Redingdced3e32012-09-20 10:39:20 +0200281 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600282 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200283 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000284 };
285
Stephen Warrenfea221e2012-11-12 12:51:22 -0700286 spi@7000c380 {
287 status = "okay";
288 spi-max-frequency = <48000000>;
289 spi-flash@0 {
290 compatible = "winbond,w25q80bl";
291 reg = <0>;
292 spi-max-frequency = <48000000>;
293 };
294 };
295
Thierry Redingdced3e32012-09-20 10:39:20 +0200296 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600297 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200298 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000299 };
300
301 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600302 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000303 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600304
Stephen Warren22bfe102012-04-27 13:24:03 -0600305 codec: codec@1a {
306 compatible = "ti,tlv320aic23";
307 reg = <0x1a>;
308 };
309
Stephen Warren081cc0a2012-04-27 09:22:44 -0600310 rtc@56 {
311 compatible = "emmicro,em3027";
312 reg = <0x56>;
313 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000314 };
315
Stephen Warren58ecb232013-11-25 17:53:16 -0700316 pmc@7000e400 {
Joseph Lo47d2d632013-08-12 17:40:07 +0800317 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800318 nvidia,cpu-pwr-good-time = <5000>;
319 nvidia,cpu-pwr-off-time = <5000>;
320 nvidia,core-pwr-good-time = <3845 3845>;
321 nvidia,core-pwr-off-time = <3875>;
322 nvidia,sys-clock-req-active-high;
323 };
324
Rob Herring508d6902017-03-21 21:03:06 -0500325 pcie@80003000 {
Thierry Reding1798efd2013-08-09 16:49:23 +0200326 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200327
328 avdd-pex-supply = <&pci_vdd_reg>;
329 vdd-pex-supply = <&pci_vdd_reg>;
330 avdd-pex-pll-supply = <&pci_vdd_reg>;
331 avdd-plle-supply = <&pci_vdd_reg>;
332 vddio-pex-clk-supply = <&pci_clk_reg>;
333
Thierry Reding1798efd2013-08-09 16:49:23 +0200334 pci@1,0 {
335 status = "okay";
336 };
337 };
338
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600339 usb@c5000000 {
340 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700341 };
342
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530343 usb-phy@c5000000 {
344 status = "okay";
345 vbus-supply = <&vbus_reg>;
346 };
347
Stephen Warrenc04abb32012-05-11 17:03:26 -0600348 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600349 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700350 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
351 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530352 };
353
354 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530355 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700356 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
357 GPIO_ACTIVE_LOW>;
Stephen Warren31c1ec92011-11-21 14:44:10 -0700358 };
359
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600360 usb@c5008000 {
361 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700362 };
363
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530364 usb-phy@c5008000 {
365 status = "okay";
366 };
367
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600368 sdhci@c8000000 {
369 status = "okay";
Rask Ingemann Lambertsena3e48632017-01-22 22:17:48 +0100370 broken-cd;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200371 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700372 };
373
Stephen Warrena7db2c12011-10-25 02:01:28 +0000374 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600375 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700376 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
377 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200378 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000379 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600380
Joseph Lo7021d122013-04-03 19:31:27 +0800381 clocks {
382 compatible = "simple-bus";
383 #address-cells = <1>;
384 #size-cells = <0>;
385
Stephen Warren58ecb232013-11-25 17:53:16 -0700386 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800387 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200388 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800389 #clock-cells = <0>;
390 clock-frequency = <32768>;
391 };
392 };
393
Joseph Lo5741a252013-04-03 19:31:48 +0800394 gpio-keys {
395 compatible = "gpio-keys";
396
397 power {
398 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700399 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530400 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000401 wakeup-source;
Joseph Lo5741a252013-04-03 19:31:48 +0800402 };
403 };
404
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700405 poweroff {
406 compatible = "gpio-poweroff";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700407 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700408 };
409
Thierry Redingdced3e32012-09-20 10:39:20 +0200410 regulators {
411 compatible = "simple-bus";
412 #address-cells = <1>;
413 #size-cells = <0>;
414
415 hdmi_vdd_reg: regulator@0 {
416 compatible = "regulator-fixed";
417 reg = <0>;
418 regulator-name = "avdd_hdmi";
419 regulator-min-microvolt = <3300000>;
420 regulator-max-microvolt = <3300000>;
421 regulator-always-on;
422 };
423
424 hdmi_pll_reg: regulator@1 {
425 compatible = "regulator-fixed";
426 reg = <1>;
427 regulator-name = "avdd_hdmi_pll";
428 regulator-min-microvolt = <1800000>;
429 regulator-max-microvolt = <1800000>;
430 regulator-always-on;
431 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530432
433 vbus_reg: regulator@2 {
434 compatible = "regulator-fixed";
435 reg = <2>;
436 regulator-name = "usb1_vbus";
437 regulator-min-microvolt = <5000000>;
438 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600439 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600440 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600441 regulator-always-on;
442 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530443 };
Thierry Reding1798efd2013-08-09 16:49:23 +0200444
445 pci_clk_reg: regulator@3 {
446 compatible = "regulator-fixed";
447 reg = <3>;
448 regulator-name = "pci_clk";
449 regulator-min-microvolt = <3300000>;
450 regulator-max-microvolt = <3300000>;
451 regulator-always-on;
452 };
453
454 pci_vdd_reg: regulator@4 {
455 compatible = "regulator-fixed";
456 reg = <4>;
457 regulator-name = "pci_vdd";
458 regulator-min-microvolt = <1050000>;
459 regulator-max-microvolt = <1050000>;
460 regulator-always-on;
461 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200462 };
463
Stephen Warrenc04abb32012-05-11 17:03:26 -0600464 sound {
465 compatible = "nvidia,tegra-audio-trimslice";
466 nvidia,i2s-controller = <&tegra_i2s1>;
467 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600468
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300469 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
470 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
471 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600472 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600473 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000474};