blob: 51b3a44fc0633fb554f440b17c24d042be82d3dd [file] [log] [blame]
Stephen Warrena7db2c12011-10-25 02:01:28 +00001/dts-v1/;
2
Stephen Warrena7db2c12011-10-25 02:01:28 +00003/include/ "tegra20.dtsi"
4
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000011 };
12
Thierry Redingdced3e32012-09-20 10:39:20 +020013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc", "gmb";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gme", "pta";
44 nvidia,function = "gmi";
45 };
46 cdev1 {
47 nvidia,pins = "cdev1";
48 nvidia,function = "plla_out";
49 };
50 cdev2 {
51 nvidia,pins = "cdev2";
52 nvidia,function = "pllp_out4";
53 };
54 crtp {
55 nvidia,pins = "crtp";
56 nvidia,function = "crt";
57 };
58 csus {
59 nvidia,pins = "csus";
60 nvidia,function = "vi_sensor_clk";
61 };
62 dap1 {
63 nvidia,pins = "dap1";
64 nvidia,function = "dap1";
65 };
66 dap2 {
67 nvidia,pins = "dap2";
68 nvidia,function = "dap2";
69 };
70 dap3 {
71 nvidia,pins = "dap3";
72 nvidia,function = "dap3";
73 };
74 dap4 {
75 nvidia,pins = "dap4";
76 nvidia,function = "dap4";
77 };
78 ddc {
79 nvidia,pins = "ddc";
80 nvidia,function = "i2c2";
81 };
82 dta {
83 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
84 nvidia,function = "vi";
85 };
86 dtf {
87 nvidia,pins = "dtf";
88 nvidia,function = "i2c3";
89 };
90 gmc {
91 nvidia,pins = "gmc", "gmd";
92 nvidia,function = "sflash";
93 };
94 gpu {
95 nvidia,pins = "gpu";
96 nvidia,function = "uarta";
97 };
98 gpu7 {
99 nvidia,pins = "gpu7";
100 nvidia,function = "rtck";
101 };
102 gpv {
103 nvidia,pins = "gpv", "slxa", "slxk";
104 nvidia,function = "pcie";
105 };
106 hdint {
107 nvidia,pins = "hdint";
108 nvidia,function = "hdmi";
109 };
110 i2cp {
111 nvidia,pins = "i2cp";
112 nvidia,function = "i2cp";
113 };
114 irrx {
115 nvidia,pins = "irrx", "irtx";
116 nvidia,function = "uartb";
117 };
118 kbca {
119 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
120 "kbce", "kbcf";
121 nvidia,function = "kbc";
122 };
123 lcsn {
124 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
125 "ld3", "ld4", "ld5", "ld6", "ld7",
126 "ld8", "ld9", "ld10", "ld11", "ld12",
127 "ld13", "ld14", "ld15", "ld16", "ld17",
128 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
129 "lhs", "lm0", "lm1", "lpp", "lpw0",
130 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
131 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
132 "lvs";
133 nvidia,function = "displaya";
134 };
135 owc {
136 nvidia,pins = "owc", "uac";
137 nvidia,function = "rsvd2";
138 };
139 pmc {
140 nvidia,pins = "pmc";
141 nvidia,function = "pwr_on";
142 };
143 rm {
144 nvidia,pins = "rm";
145 nvidia,function = "i2c1";
146 };
147 sdb {
148 nvidia,pins = "sdb", "sdc", "sdd";
149 nvidia,function = "pwm";
150 };
151 sdio1 {
152 nvidia,pins = "sdio1";
153 nvidia,function = "sdio1";
154 };
155 slxc {
156 nvidia,pins = "slxc", "slxd";
157 nvidia,function = "sdio3";
158 };
159 spdi {
160 nvidia,pins = "spdi", "spdo";
161 nvidia,function = "spdif";
162 };
163 spia {
164 nvidia,pins = "spia", "spib", "spic";
165 nvidia,function = "spi2";
166 };
167 spid {
168 nvidia,pins = "spid", "spie", "spif";
169 nvidia,function = "spi1";
170 };
171 spig {
172 nvidia,pins = "spig", "spih";
173 nvidia,function = "spi2_alt";
174 };
175 uaa {
176 nvidia,pins = "uaa", "uab", "uda";
177 nvidia,function = "ulpi";
178 };
179 uad {
180 nvidia,pins = "uad";
181 nvidia,function = "irda";
182 };
183 uca {
184 nvidia,pins = "uca", "ucb";
185 nvidia,function = "uartc";
186 };
187 conf_ata {
188 nvidia,pins = "ata", "atc", "atd", "ate",
189 "crtp", "dap2", "dap3", "dap4", "dta",
190 "dtb", "dtc", "dtd", "dte", "gmb",
191 "gme", "i2cp", "pta", "slxc", "slxd",
192 "spdi", "spdo", "uda";
193 nvidia,pull = <0>;
194 nvidia,tristate = <1>;
195 };
196 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600197 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
198 "gma", "gmc", "gmd", "gpu", "gpu7",
199 "gpv", "sdio1", "slxa", "slxk", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600200 nvidia,pull = <0>;
201 nvidia,tristate = <0>;
202 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600203 conf_ck32 {
204 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
205 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
206 nvidia,pull = <0>;
207 };
Stephen Warren563da212012-04-13 16:35:20 -0600208 conf_csus {
209 nvidia,pins = "csus", "spia", "spib",
210 "spid", "spif";
211 nvidia,pull = <1>;
212 nvidia,tristate = <1>;
213 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600214 conf_ddc {
215 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
216 nvidia,pull = <2>;
217 nvidia,tristate = <0>;
218 };
219 conf_hdint {
220 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
221 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "pmc";
223 nvidia,tristate = <1>;
224 };
225 conf_irrx {
226 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
227 "kbcc", "kbcd", "kbce", "kbcf", "owc",
228 "spic", "spie", "spig", "spih", "uaa",
229 "uab", "uad", "uca", "ucb";
230 nvidia,pull = <2>;
231 nvidia,tristate = <1>;
232 };
233 conf_lc {
234 nvidia,pins = "lc", "ls";
235 nvidia,pull = <2>;
236 };
237 conf_ld0 {
238 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
239 "ld5", "ld6", "ld7", "ld8", "ld9",
240 "ld10", "ld11", "ld12", "ld13", "ld14",
241 "ld15", "ld16", "ld17", "ldi", "lhp0",
242 "lhp1", "lhp2", "lhs", "lm0", "lpp",
243 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
244 "lvs", "sdb";
245 nvidia,tristate = <0>;
246 };
247 conf_ld17_0 {
248 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
249 "ld23_22";
250 nvidia,pull = <1>;
251 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700252 conf_spif {
253 nvidia,pins = "spif";
254 nvidia,pull = <1>;
255 nvidia,tristate = <0>;
256 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600257 };
258 };
259
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600260 i2s@70002800 {
261 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600262 };
263
264 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600265 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600266 };
267
Thierry Redingdced3e32012-09-20 10:39:20 +0200268 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600269 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200270 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000271 };
272
Stephen Warrenfea221e2012-11-12 12:51:22 -0700273 spi@7000c380 {
274 status = "okay";
275 spi-max-frequency = <48000000>;
276 spi-flash@0 {
277 compatible = "winbond,w25q80bl";
278 reg = <0>;
279 spi-max-frequency = <48000000>;
280 };
281 };
282
Thierry Redingdced3e32012-09-20 10:39:20 +0200283 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600284 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200285 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000286 };
287
288 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600289 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000290 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600291
Stephen Warren22bfe102012-04-27 13:24:03 -0600292 codec: codec@1a {
293 compatible = "ti,tlv320aic23";
294 reg = <0x1a>;
295 };
296
Stephen Warren081cc0a2012-04-27 09:22:44 -0600297 rtc@56 {
298 compatible = "emmicro,em3027";
299 reg = <0x56>;
300 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000301 };
302
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600303 usb@c5000000 {
304 status = "okay";
Stephen Warren01ad8062012-07-25 14:02:44 -0600305 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
Stephen Warren88950f3b2011-11-21 14:44:09 -0700306 };
307
Stephen Warrenc04abb32012-05-11 17:03:26 -0600308 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600309 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600310 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
Stephen Warren31c1ec92011-11-21 14:44:10 -0700311 };
312
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600313 usb@c5008000 {
314 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700315 };
316
Venu Byravarasu40e8b3a2013-01-24 15:46:46 +0530317 usb-phy@c5004400 {
318 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
319 };
320
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600321 sdhci@c8000000 {
322 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200323 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700324 };
325
Stephen Warrena7db2c12011-10-25 02:01:28 +0000326 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600327 status = "okay";
Joseph Lo908ab932013-02-22 11:23:39 +0800328 cd-gpios = <&gpio 121 1>; /* gpio PP1 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600329 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200330 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000331 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600332
Joseph Lo7021d122013-04-03 19:31:27 +0800333 clocks {
334 compatible = "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 clk32k_in: clock {
339 compatible = "fixed-clock";
340 reg=<0>;
341 #clock-cells = <0>;
342 clock-frequency = <32768>;
343 };
344 };
345
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700346 poweroff {
347 compatible = "gpio-poweroff";
348 gpios = <&gpio 191 1>; /* gpio PX7, active low */
349 };
350
Thierry Redingdced3e32012-09-20 10:39:20 +0200351 regulators {
352 compatible = "simple-bus";
353 #address-cells = <1>;
354 #size-cells = <0>;
355
356 hdmi_vdd_reg: regulator@0 {
357 compatible = "regulator-fixed";
358 reg = <0>;
359 regulator-name = "avdd_hdmi";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-always-on;
363 };
364
365 hdmi_pll_reg: regulator@1 {
366 compatible = "regulator-fixed";
367 reg = <1>;
368 regulator-name = "avdd_hdmi_pll";
369 regulator-min-microvolt = <1800000>;
370 regulator-max-microvolt = <1800000>;
371 regulator-always-on;
372 };
373 };
374
Stephen Warrenc04abb32012-05-11 17:03:26 -0600375 sound {
376 compatible = "nvidia,tegra-audio-trimslice";
377 nvidia,i2s-controller = <&tegra_i2s1>;
378 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600379
380 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
381 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600382 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000383};