blob: 5b3be4c67be8ae0c628f4501754e37620eaaa98c [file] [log] [blame]
Florian Fainellib560a582014-02-13 16:08:45 -08001/*
2 * Broadcom BCM7xxx internal transceivers support.
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/phy.h>
14#include <linux/delay.h>
Arun Parameswarana1cba562015-10-06 12:25:48 -070015#include "bcm-phy-lib.h"
Florian Fainellib560a582014-02-13 16:08:45 -080016#include <linux/bitops.h>
17#include <linux/brcmphy.h>
Florian Fainellib8f9a022014-08-22 18:55:45 -070018#include <linux/mdio.h>
Florian Fainellib560a582014-02-13 16:08:45 -080019
20/* Broadcom BCM7xxx internal PHY registers */
Florian Fainellib560a582014-02-13 16:08:45 -080021
22/* 40nm only register definitions */
23#define MII_BCM7XXX_100TX_AUX_CTL 0x10
24#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
25#define MII_BCM7XXX_100TX_DISC 0x14
26#define MII_BCM7XXX_AUX_MODE 0x1d
Florian Fainelli3ccc3052016-02-06 13:09:36 -080027#define MII_BCM7XXX_64CLK_MDIO BIT(12)
Florian Fainellib560a582014-02-13 16:08:45 -080028#define MII_BCM7XXX_TEST 0x1f
29#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
30
Florian Fainellia3622f22014-03-24 16:36:47 -070031/* 28nm only register definitions */
32#define MISC_ADDR(base, channel) base, channel
33
34#define DSP_TAP10 MISC_ADDR(0x0a, 0)
35#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
36#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
37#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
38
39#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
40#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
Florian Fainellia4906312014-11-11 14:55:13 -080041#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
Florian Fainellia3622f22014-03-24 16:36:47 -070042#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
43#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
Florian Fainellia4906312014-11-11 14:55:13 -080044#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
45#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
Florian Fainellia3622f22014-03-24 16:36:47 -070046#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
47
Florian Fainelli9c41f2b2014-11-11 14:55:12 -080048static void r_rc_cal_reset(struct phy_device *phydev)
49{
50 /* Reset R_CAL/RC_CAL Engine */
Arun Parameswarana1cba562015-10-06 12:25:48 -070051 bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
Florian Fainelli9c41f2b2014-11-11 14:55:12 -080052
53 /* Disable Reset R_AL/RC_CAL Engine */
Arun Parameswarana1cba562015-10-06 12:25:48 -070054 bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
Florian Fainelli9c41f2b2014-11-11 14:55:12 -080055}
56
Florian Fainelli2a9df742014-11-11 14:55:11 -080057static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
Florian Fainellib560a582014-02-13 16:08:45 -080058{
Florian Fainellib560a582014-02-13 16:08:45 -080059 /* Increase VCO range to prevent unlocking problem of PLL at low
60 * temp
61 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070062 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
Florian Fainellib560a582014-02-13 16:08:45 -080063
64 /* Change Ki to 011 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070065 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
Florian Fainellib560a582014-02-13 16:08:45 -080066
67 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
68 * to 111
69 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070070 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
Florian Fainellib560a582014-02-13 16:08:45 -080071
72 /* Adjust bias current trim by -3 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070073 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
Florian Fainellib560a582014-02-13 16:08:45 -080074
75 /* Switch to CORE_BASE1E */
Arun Parameswaran9200c272015-10-06 12:25:50 -070076 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
Florian Fainellib560a582014-02-13 16:08:45 -080077
Florian Fainelli9c41f2b2014-11-11 14:55:12 -080078 r_rc_cal_reset(phydev);
Florian Fainellib560a582014-02-13 16:08:45 -080079
Florian Fainelli99185422014-03-24 16:36:48 -070080 /* write AFE_RXCONFIG_0 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070081 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
Florian Fainelli99185422014-03-24 16:36:48 -070082
83 /* write AFE_RXCONFIG_1 */
Arun Parameswarana1cba562015-10-06 12:25:48 -070084 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
Florian Fainelli99185422014-03-24 16:36:48 -070085
86 /* write AFE_RX_LP_COUNTER */
Arun Parameswarana1cba562015-10-06 12:25:48 -070087 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
Florian Fainelli99185422014-03-24 16:36:48 -070088
89 /* write AFE_HPF_TRIM_OTHERS */
Arun Parameswarana1cba562015-10-06 12:25:48 -070090 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
Florian Fainelli99185422014-03-24 16:36:48 -070091
92 /* write AFTE_TX_CONFIG */
Arun Parameswarana1cba562015-10-06 12:25:48 -070093 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
Florian Fainelli99185422014-03-24 16:36:48 -070094
Florian Fainellib560a582014-02-13 16:08:45 -080095 return 0;
96}
97
Florian Fainellia4906312014-11-11 14:55:13 -080098static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
99{
100 /* AFE_RXCONFIG_0 */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700101 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
Florian Fainellia4906312014-11-11 14:55:13 -0800102
103 /* AFE_RXCONFIG_1 */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700104 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
Florian Fainellia4906312014-11-11 14:55:13 -0800105
106 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700107 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
Florian Fainellia4906312014-11-11 14:55:13 -0800108
109 /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700110 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
Florian Fainellia4906312014-11-11 14:55:13 -0800111
Florian Fainelli6da82532015-06-08 11:05:20 -0700112 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700113 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
Florian Fainellia4906312014-11-11 14:55:13 -0800114
115 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700116 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
Florian Fainellia4906312014-11-11 14:55:13 -0800117
118 /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700119 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
Florian Fainellia4906312014-11-11 14:55:13 -0800120
121 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
122 * offset for HT=0 code
123 */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700124 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
Florian Fainellia4906312014-11-11 14:55:13 -0800125
126 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
Arun Parameswaran9200c272015-10-06 12:25:50 -0700127 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
Florian Fainellia4906312014-11-11 14:55:13 -0800128
129 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700130 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
Florian Fainellia4906312014-11-11 14:55:13 -0800131
132 /* Reset R_CAL/RC_CAL engine */
133 r_rc_cal_reset(phydev);
134
135 return 0;
136}
137
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800138static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
139{
140 /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700141 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800142
Florian Fainelli6da82532015-06-08 11:05:20 -0700143 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700144 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
Florian Fainelli6da82532015-06-08 11:05:20 -0700145
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800146 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700147 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800148
149 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
150 * offset for HT=0 code
151 */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700152 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800153
154 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
Arun Parameswaran9200c272015-10-06 12:25:50 -0700155 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800156
157 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700158 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800159
160 /* Reset R_CAL/RC_CAL engine */
161 r_rc_cal_reset(phydev);
162
163 return 0;
164}
165
Florian Fainellib560a582014-02-13 16:08:45 -0800166static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
167{
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700168 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
169 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
Florian Fainellidb888162016-11-22 11:40:57 -0800170 u8 count;
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700171 int ret = 0;
Florian Fainellib560a582014-02-13 16:08:45 -0800172
Florian Fainelli6ec259c2014-11-11 14:55:10 -0800173 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
Andrew Lunn84eff6d2016-01-06 20:11:10 +0100174 phydev_name(phydev), phydev->drv->name, rev, patch);
Florian Fainellib560a582014-02-13 16:08:45 -0800175
Florian Fainelli8e346e12015-06-26 10:39:04 -0700176 /* Dummy read to a register to workaround an issue upon reset where the
177 * internal inverter may not allow the first MDIO transaction to pass
178 * the MDIO management controller and make us return 0xffff for such
179 * reads.
180 */
181 phy_read(phydev, MII_BMSR);
182
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700183 switch (rev) {
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700184 case 0xb0:
Florian Fainelli2a9df742014-11-11 14:55:11 -0800185 ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700186 break;
Florian Fainellia4906312014-11-11 14:55:13 -0800187 case 0xd0:
188 ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
189 break;
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800190 case 0xe0:
191 case 0xf0:
Florian Fainelli60efff02014-12-03 09:57:00 -0800192 /* Rev G0 introduces a roll over */
193 case 0x10:
Florian Fainelli0c2fdc22014-11-11 14:55:14 -0800194 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
195 break;
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700196 default:
Florian Fainellid8ebfed2014-09-19 13:07:56 -0700197 break;
198 }
199
Florian Fainelli9df54dd2014-08-22 18:55:41 -0700200 if (ret)
201 return ret;
202
Florian Fainellidb888162016-11-22 11:40:57 -0800203 ret = bcm_phy_downshift_get(phydev, &count);
204 if (ret)
205 return ret;
206
207 /* Only enable EEE if Wirespeed/downshift is disabled */
208 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
Florian Fainellib8f9a022014-08-22 18:55:45 -0700209 if (ret)
210 return ret;
211
Arun Parameswarana1cba562015-10-06 12:25:48 -0700212 return bcm_phy_enable_apd(phydev, true);
Florian Fainellib560a582014-02-13 16:08:45 -0800213}
214
Florian Fainelli4fd14e02014-08-14 16:52:52 -0700215static int bcm7xxx_28nm_resume(struct phy_device *phydev)
216{
217 int ret;
218
219 /* Re-apply workarounds coming out suspend/resume */
220 ret = bcm7xxx_28nm_config_init(phydev);
221 if (ret)
222 return ret;
223
224 /* 28nm Gigabit PHYs come out of reset without any half-duplex
225 * or "hub" compliant advertised mode, fix that. This does not
226 * cause any problems with the PHY library since genphy_config_aneg()
227 * gracefully handles auto-negotiated and forced modes.
228 */
229 return genphy_config_aneg(phydev);
230}
231
Florian Fainellib560a582014-02-13 16:08:45 -0800232static int phy_set_clr_bits(struct phy_device *dev, int location,
233 int set_mask, int clr_mask)
234{
235 int v, ret;
236
237 v = phy_read(dev, location);
238 if (v < 0)
239 return v;
240
241 v &= ~clr_mask;
242 v |= set_mask;
243
244 ret = phy_write(dev, location, v);
245 if (ret < 0)
246 return ret;
247
248 return v;
249}
250
251static int bcm7xxx_config_init(struct phy_device *phydev)
252{
253 int ret;
254
255 /* Enable 64 clock MDIO */
Florian Fainelli3ccc3052016-02-06 13:09:36 -0800256 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
Florian Fainellib560a582014-02-13 16:08:45 -0800257 phy_read(phydev, MII_BCM7XXX_AUX_MODE);
258
Florian Fainellib560a582014-02-13 16:08:45 -0800259 /* set shadow mode 2 */
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
261 MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
262 if (ret < 0)
263 return ret;
264
265 /* set iddq_clkbias */
266 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
267 udelay(10);
268
269 /* reset iddq_clkbias */
270 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
271
272 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
273
274 /* reset shadow mode 2 */
Florian Fainelli50d89982016-02-06 12:58:48 -0800275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
Florian Fainellib560a582014-02-13 16:08:45 -0800276 if (ret < 0)
277 return ret;
278
279 return 0;
280}
281
282/* Workaround for putting the PHY in IDDQ mode, required
Florian Fainelli82c084f2014-08-14 16:52:53 -0700283 * for all BCM7XXX 40nm and 65nm PHYs
Florian Fainellib560a582014-02-13 16:08:45 -0800284 */
285static int bcm7xxx_suspend(struct phy_device *phydev)
286{
287 int ret;
288 const struct bcm7xxx_regs {
289 int reg;
290 u16 value;
291 } bcm7xxx_suspend_cfg[] = {
292 { MII_BCM7XXX_TEST, 0x008b },
293 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
294 { MII_BCM7XXX_100TX_DISC, 0x7000 },
295 { MII_BCM7XXX_TEST, 0x000f },
296 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
297 { MII_BCM7XXX_TEST, 0x000b },
298 };
299 unsigned int i;
300
301 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
302 ret = phy_write(phydev,
303 bcm7xxx_suspend_cfg[i].reg,
304 bcm7xxx_suspend_cfg[i].value);
305 if (ret)
306 return ret;
307 }
308
309 return 0;
310}
311
Florian Fainellidb888162016-11-22 11:40:57 -0800312static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
313 struct ethtool_tunable *tuna,
314 void *data)
315{
316 switch (tuna->id) {
317 case ETHTOOL_PHY_DOWNSHIFT:
318 return bcm_phy_downshift_get(phydev, (u8 *)data);
319 default:
320 return -EOPNOTSUPP;
321 }
322}
323
324static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
325 struct ethtool_tunable *tuna,
326 const void *data)
327{
328 u8 count = *(u8 *)data;
329 int ret;
330
331 switch (tuna->id) {
332 case ETHTOOL_PHY_DOWNSHIFT:
333 ret = bcm_phy_downshift_set(phydev, count);
334 break;
335 default:
336 return -EOPNOTSUPP;
337 }
338
339 if (ret)
340 return ret;
341
342 /* Disable EEE advertisment since this prevents the PHY
343 * from successfully linking up, trigger auto-negotiation restart
344 * to let the MAC decide what to do.
345 */
346 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
347 if (ret)
348 return ret;
349
350 return genphy_restart_aneg(phydev);
351}
352
Florian Fainelli153df3c2014-08-26 13:15:24 -0700353#define BCM7XXX_28NM_GPHY(_oui, _name) \
354{ \
355 .phy_id = (_oui), \
356 .phy_id_mask = 0xfffffff0, \
357 .name = _name, \
358 .features = PHY_GBIT_FEATURES | \
359 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
360 .flags = PHY_IS_INTERNAL, \
Florian Fainelli2a9df742014-11-11 14:55:11 -0800361 .config_init = bcm7xxx_28nm_config_init, \
Florian Fainelli153df3c2014-08-26 13:15:24 -0700362 .config_aneg = genphy_config_aneg, \
363 .read_status = genphy_read_status, \
364 .resume = bcm7xxx_28nm_resume, \
Florian Fainellidb888162016-11-22 11:40:57 -0800365 .get_tunable = bcm7xxx_28nm_get_tunable, \
366 .set_tunable = bcm7xxx_28nm_set_tunable, \
Florian Fainelli153df3c2014-08-26 13:15:24 -0700367}
368
Florian Fainelli3125c082016-02-06 13:09:37 -0800369#define BCM7XXX_40NM_EPHY(_oui, _name) \
370{ \
371 .phy_id = (_oui), \
372 .phy_id_mask = 0xfffffff0, \
373 .name = _name, \
374 .features = PHY_BASIC_FEATURES | \
375 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
376 .flags = PHY_IS_INTERNAL, \
377 .config_init = bcm7xxx_config_init, \
378 .config_aneg = genphy_config_aneg, \
379 .read_status = genphy_read_status, \
380 .suspend = bcm7xxx_suspend, \
381 .resume = bcm7xxx_config_init, \
382}
383
Florian Fainellib560a582014-02-13 16:08:45 -0800384static struct phy_driver bcm7xxx_driver[] = {
Florian Fainelli430ad682014-08-26 13:15:27 -0700385 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
386 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
Florian Fainelli153df3c2014-08-26 13:15:24 -0700387 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
388 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
Florian Fainelli59e33c22015-03-09 15:44:13 -0700389 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
Florian Fainelli153df3c2014-08-26 13:15:24 -0700390 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
Jaedon Shin4cef1912016-03-25 12:46:54 +0900391 BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
392 BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
Florian Fainelli3125c082016-02-06 13:09:37 -0800393 BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
394 BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
395 BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
David S. Millerb6333532016-02-23 00:09:14 -0500396};
Florian Fainellib560a582014-02-13 16:08:45 -0800397
398static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
Florian Fainelli430ad682014-08-26 13:15:27 -0700399 { PHY_ID_BCM7250, 0xfffffff0, },
400 { PHY_ID_BCM7364, 0xfffffff0, },
Florian Fainellib560a582014-02-13 16:08:45 -0800401 { PHY_ID_BCM7366, 0xfffffff0, },
Jaedon Shin4cef1912016-03-25 12:46:54 +0900402 { PHY_ID_BCM7346, 0xfffffff0, },
403 { PHY_ID_BCM7362, 0xfffffff0, },
Petri Gyntherd068b022014-10-01 11:58:02 -0700404 { PHY_ID_BCM7425, 0xfffffff0, },
405 { PHY_ID_BCM7429, 0xfffffff0, },
Florian Fainellib560a582014-02-13 16:08:45 -0800406 { PHY_ID_BCM7439, 0xfffffff0, },
Florian Fainelli9458cea2015-11-24 15:30:21 -0800407 { PHY_ID_BCM7435, 0xfffffff0, },
Florian Fainellib560a582014-02-13 16:08:45 -0800408 { PHY_ID_BCM7445, 0xfffffff0, },
Florian Fainellib560a582014-02-13 16:08:45 -0800409 { }
410};
411
Johan Hovold50fd7152014-11-11 19:45:59 +0100412module_phy_driver(bcm7xxx_driver);
Florian Fainellib560a582014-02-13 16:08:45 -0800413
414MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
415
416MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
417MODULE_LICENSE("GPL");
418MODULE_AUTHOR("Broadcom Corporation");