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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +02002/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra30-apalis.dtsi"
6
7/ {
8 model = "Toradex Apalis T30 on Apalis Evaluation Board";
Marcel Ziswiler70451b52018-08-31 18:38:07 +02009 compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30",
10 "nvidia,tegra30";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020011
12 aliases {
13 rtc0 = "/i2c@7000c000/rtc@68";
Marcel Ziswilerb4cfc772018-08-31 18:38:13 +020014 rtc1 = "/i2c@7000d000/pmic@2d";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020015 rtc2 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080016 serial0 = &uarta;
17 serial1 = &uartb;
18 serial2 = &uartc;
19 serial3 = &uartd;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020020 };
21
Jon Hunterf5bbb322016-02-09 13:51:59 +000022 chosen {
23 stdout-path = "serial0:115200n8";
24 };
25
Rob Herring508d6902017-03-21 21:03:06 -050026 pcie@3000 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020027 pci@1,0 {
28 status = "okay";
29 };
30
31 pci@2,0 {
32 status = "okay";
33 };
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020034 };
35
36 host1x@50000000 {
37 dc@54200000 {
38 rgb {
39 status = "okay";
40 nvidia,panel = <&panel>;
41 };
42 };
Marcel Ziswiler4eb7e5e2018-08-31 18:37:53 +020043
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020044 hdmi@54280000 {
45 status = "okay";
Marcel Ziswiler32980cb2018-08-31 18:37:50 +020046 hdmi-supply = <&reg_5v0>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020047 };
48 };
49
Marcel Ziswilere0734522018-08-31 18:37:51 +020050 /* Apalis UART1 */
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020051 serial@70006000 {
52 status = "okay";
53 };
54
Marcel Ziswilere0734522018-08-31 18:37:51 +020055 /* Apalis UART2 */
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020056 serial@70006040 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020057 status = "okay";
58 };
59
Marcel Ziswilere0734522018-08-31 18:37:51 +020060 /* Apalis UART3 */
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020061 serial@70006200 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020062 status = "okay";
63 };
64
Marcel Ziswilere0734522018-08-31 18:37:51 +020065 /* Apalis UART4 */
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020066 serial@70006300 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020067 status = "okay";
68 };
69
70 pwm@7000a000 {
71 status = "okay";
72 };
73
74 /*
75 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
76 * board)
77 */
78 i2c@7000c000 {
79 status = "okay";
Marcel Ziswiler1c3389e2018-02-10 02:36:36 +010080 clock-frequency = <400000>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020081
82 pcie-switch@58 {
83 compatible = "plx,pex8605";
84 reg = <0x58>;
85 };
86
87 /* M41T0M6 real time clock on carrier board */
88 rtc@68 {
Marcel Ziswiler29a62752018-02-10 02:36:37 +010089 compatible = "st,m41t0";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +020090 reg = <0x68>;
91 };
92 };
93
94 /* GEN2_I2C: unused */
95
96 /*
97 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
98 * carrier board)
99 */
Marcel Ziswiler95bcc022018-08-31 18:37:52 +0200100 i2c@7000c500 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200101 status = "okay";
102 clock-frequency = <400000>;
103 };
104
105 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
Marcel Ziswiler46717602018-08-31 18:38:12 +0200106 i2c@7000c700 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200107 status = "okay";
108 };
109
110 /* SPI1: Apalis SPI1 */
111 spi@7000d400 {
112 status = "okay";
113 spi-max-frequency = <25000000>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200114 };
115
116 /* SPI5: Apalis SPI2 */
117 spi@7000dc00 {
118 status = "okay";
119 spi-max-frequency = <25000000>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200120 };
121
Marcel Ziswiler005a00d2018-08-31 18:37:55 +0200122 /* Apalis SD1 */
Thierry Reding32c096c2020-06-11 19:21:17 +0200123 mmc@78000000 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200124 status = "okay";
125 bus-width = <4>;
126 /* SD1_CD# */
127 cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
128 no-1-8-v;
129 };
130
Marcel Ziswiler005a00d2018-08-31 18:37:55 +0200131 /* Apalis MMC1 */
Thierry Reding32c096c2020-06-11 19:21:17 +0200132 mmc@78000400 {
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200133 status = "okay";
134 bus-width = <8>;
135 /* MMC1_CD# */
136 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
137 no-1-8-v;
138 };
139
140 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
141 usb@7d000000 {
142 status = "okay";
Marcel Ziswiler8bf0d6b2018-08-31 18:37:56 +0200143 dr_mode = "otg";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200144 };
145
146 usb-phy@7d000000 {
147 status = "okay";
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200148 vbus-supply = <&reg_usbo1_vbus>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200149 };
150
151 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
152 usb@7d004000 {
153 status = "okay";
154 };
155
156 usb-phy@7d004000 {
157 status = "okay";
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200158 vbus-supply = <&reg_usbh_vbus>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200159 };
160
161 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
162 usb@7d008000 {
163 status = "okay";
164 };
165
166 usb-phy@7d008000 {
167 status = "okay";
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200168 vbus-supply = <&reg_usbh_vbus>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200169 };
170
171 backlight: backlight {
172 compatible = "pwm-backlight";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200173 brightness-levels = <255 231 223 207 191 159 127 0>;
174 default-brightness-level = <6>;
175 /* BKL1_ON */
176 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marcel Ziswiler32980cb2018-08-31 18:37:50 +0200177 power-supply = <&reg_3v3>;
Marcel Ziswiler654b7132018-08-31 18:37:57 +0200178 pwms = <&pwm 0 5000000>; /* BKL1_PWM */
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200179 };
180
181 gpio-keys {
182 compatible = "gpio-keys";
183
Marcel Ziswiler21db15d2015-08-28 14:42:36 +0200184 wakeup {
185 label = "WAKE1_MICO";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200186 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
Marcel Ziswiler21db15d2015-08-28 14:42:36 +0200187 linux,code = <KEY_WAKEUP>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200188 debounce-interval = <10>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000189 wakeup-source;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200190 };
191 };
192
193 panel: panel {
194 /*
195 * edt,et057090dhu: EDT 5.7" LCD TFT
196 * edt,et070080dh6: EDT 7.0" LCD TFT
197 */
Rob Herring7860c872020-01-17 17:08:55 -0600198 compatible = "edt,et057090dhu";
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200199 backlight = <&backlight>;
Marcel Ziswiler32980cb2018-08-31 18:37:50 +0200200 power-supply = <&reg_3v3>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200201 };
202
Marcel Ziswiler32980cb2018-08-31 18:37:50 +0200203 reg_3v3: regulator-3v3 {
204 compatible = "regulator-fixed";
205 regulator-name = "3.3V_SW";
206 regulator-min-microvolt = <3300000>;
207 regulator-max-microvolt = <3300000>;
208 };
209
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200210 reg_5v0: regulator-5v0 {
211 compatible = "regulator-fixed";
212 regulator-name = "5V_SW";
213 regulator-min-microvolt = <5000000>;
214 regulator-max-microvolt = <5000000>;
215 };
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200216
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200217 /* USBO1_EN */
218 reg_usbo1_vbus: regulator-usbo1-vbus {
219 compatible = "regulator-fixed";
220 regulator-name = "VCC_USBO1";
221 regulator-min-microvolt = <5000000>;
222 regulator-max-microvolt = <5000000>;
223 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
224 enable-active-high;
225 vin-supply = <&reg_5v0>;
226 };
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200227
Marcel Ziswilerf98439c2018-08-31 18:37:49 +0200228 /* USBH_EN */
229 reg_usbh_vbus: regulator-usbh-vbus {
230 compatible = "regulator-fixed";
231 regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
232 regulator-min-microvolt = <5000000>;
233 regulator-max-microvolt = <5000000>;
234 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
235 enable-active-high;
236 vin-supply = <&reg_5v0>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200237 };
238};
Marcel Ziswilerda250012018-08-31 18:38:11 +0200239
240&gpio {
241 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
242 pex-perst-n {
243 gpio-hog;
244 gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
245 output-high;
246 line-name = "PEX_PERST_N";
247 };
248};